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PDP Training (Alexander)

Agenda
1.Explanation of Layout and Function of Circuit Board 2.Operation Explanation per Board
2-1 Drive Description on SMPS 2-2 Operation Explanation of Driving Circuit 2-3 Logic-Main Board 2-4 Scaler Board

1. Explanation of Layout & Function of Circuit Board


[PDP Mod ule Pic ture ]
Y buffer "Upper"

SM PS
Y- MAIN X- MAIN

Lo g ic - Main

Y buffer "Lo wer"

E- buffer

F- buffer

G- buffer

COF x 7

[ Function Description by board - 1 ]


.SMPS(Switching Mode Power Supply) : It is the supplier to provide voltage and current to work the drive voltage and panel in each board.

.X-MAIN BOARD : It makes the drive wave form by switching FETs to Timing Controlle coming from logic-board and supplies X electrode of panel with the drive wave form via connector.

.Y-MAIN BOARD : It makes the drive wave form by switching FETs to Timing Controller coming from the logic-board and provides Y electrode of panel with the drive wave form via Scan Driver IC on Y buffer board in order.

.LOGIC MAIN BOARD : It process image signal and performs buffering of the logic-main board (to create XY drive signal and output) and the address driver output signal. Then it supplies the output signal to the address driver IC(COF Module).

[ Function Description by board - 2 ]


.LOGIC BUFFER(E,F,G) : It delivers the data signal and control signal to the COF.

.Y-BUFFER (Upper,Lower) : It is the board to impress the scan waveform on the Y board and consist of 2 boards (upper board and lower board). 8 Y-buffers are fixed at the scan driver (STV7617 of STC corp. : 64 or 65 Output).

.AC Noise Filter : It has functions to remove noise(low frequency) coming from AC LINE and prevent surge. It gives serious effects on the safety regulations (EMC, EMI) according to AC filter.

.COF(Chip on Flexible) : It impress the Va pulse to the address electrode in the address section and forms the address discharge by electric potential difference with scanning pulse to be dismissed by the Y electrode. It is made in the form of COF and one COF consists of 4 Data Drive IC (STV7610A :96 Output), otherwise single scan is made of 7 COF.

CELL STRUCTURE OF PDP


Bus electrode Front panel

Dielectric MgO layer Barrier ITO electrode Phosphors

Address Electrode

Back panel

Electro Arrangement of SD PDP


A1 Y1 X Y2 X A2 A3 A4 A5 A6 A7

Y4 8 0 X

Re fe r e n c e
- A1 ,A2 , , , : Add r e s s Ele c tr od e - Y1 ,Y2 , , , : S c an & S us ta in Ele c tr od e - X : Com m o n & S us ta in Ele c tr od e

ADDRESS OPERATION

In order to display picture, select the cells.

SUSTAIN OPERATION

Display cells through strong Sustain discharge.

1 SUB-FIELD IMAGE PROCESS (ADS)

Reset

Address

Sustain

Function Sustain Erase Wall Charge Set Issue Operation margin Contrast Short Time

Function Select On Cell Issue High Speed Low Voltage Low Failure

Function Discharge On Cell Issue High Efficiency Low Voltage ERC Performance

FRAME STRUCTURE (ADS)


SF1 scan line
1 2 .. ... 480

SF2

SF3

SF4

SF5

SF6

SF7

SF8 sub-field address

1T 2T 4T 8T 16T

32T

64T

128T

sustain

1TV field (time)


Reset Period Address Period Sustain Period

D X Y1 Y2 Yn

1 Picture Structure by 8 sub-field

SF1 scan line


1 2 .. ... 480

SF2

SF3

SF4

SF5

SF6

SF7

SF8 sub-field address

1T 2T 4T 8T 16T

32T

64T

128T

sustain

1TV field (time)

2. Explanation of Operation per Boards


[Whole Bloc k Diagra m]
Y- Ma in B'd

Lo g ic B'd

Dis p la y Da ta DRAM Drive r Timing Ro w Drive r

X- Ma in B'd

PDP Panel
852 X 4 80 Pixe ls 853 X 3 X 480 Ce lls X- Puls e Ge ne ra to r

Inp ut Da ta Pro c e s s o r

Da ta Co ntro lle r

Drive r Timing Co ntro lle r Clo c k : S can Timing

Y- Puls e Ge ne ra to r Co lumn Drive r Po we r B'd

Clo c k : 27MHz

Clo c k : 60MHz

20MHz 40MHz

Po we r S up p ly

LVDS
Dig ita l B'd Ana lo g B'd Aud io Pro c e s s o r Vid e o S /W Co mb Filte r Tune r

Ima g e Enha nc e r Ima g e S c a le rr Mic o m AD Co nve rte rr

De inte rla c e r Vid e o De c o d e r TMDS Re c e ive rr

AC Po we r S o urc e 220V

1 Picture Structure by 8 sub-field


[ Wiring Diagram Schematic]

CN805 (10 P)

CN805 (10 P)

Y- Ma in

S MPS CN806) CN812 (5P) CN802 CN803 (10 P) (11 P)

CN804 (9P)

CN804 (9P)

CN801 (10 P)

X- Ma in

LA03 (31 P) CN201 CN201 CN401

CN803 (10 P)

Log ic
CN402

CN101 CN403

CN101

CN806)

EF1

FE1 FG1 CN101 CN102 CN103

GF1 AC Inle t

CN111 CN601

CN802

CN801

Digital

Ana log

PIN CONFIGURATION
[ S c a le r : Ana log
CN101(Co ntro l) NO 1 2 3 4 5 6 7 8 9 10 11 12 PIN Name GND S CL1 S DA1 GND S AFT GND MUTE GND MAFT GND ANAL_CVBS GND CN102(Vid e o /S ync ) NO 1 2 3 4 5 6 7 8 9 10 11 12 PIN Name ANAL_YCOMB GND ANAL_CCOMB GND ANAL_Y2 GND ANAL_PB2 GND ANAL_PR2 GND ANAL_H ANAL_V

Dgita l ]
CN103(Vid e o /S ync ) NO 1 2 3 4 5 6 7 8 9 10 11 12 PIN Name ANAL_YCOMB GND ANAL_CCOMB GND ANAL_Y2 GND ANAL_PB2 GND ANAL_PR2 GND ANAL_H ANAL_V NO 1 2 3 4 5 6 7 8 9 10 11 12 13 14

[ S c a le r Dgita l
PIN Name GND GND Tx Out0- / Rx In0Tx Out0+ / Rx In0+ GND GND Tx Out1- / Rx In1Tx Out1+ / Rx In1+ GND GND Tx Out2- / Rx In2Tx Out2+ / Rx In2+ GND GND

Log ic (CN601) ]
NO 17 18 19 20 21 22 23 24 25 26 27 28 29 31 PIN Name GND GND Tx Out0- / Rx In0Tx Out0- / Rx In0GND GND GND GND RES ET_MN GND IIC S CL2 GND IIC S DA2 GND GND 16 Tx CLK Out+ / Rx CLK In+

15 Tx CLK Out- / Rx CLK In- 30

PIN CONFIGURATION
[ S MPS
CN801(An a lo g Tu) NO 1 2 3 4 5 6 7 8 9 10 Po we r GND A33V GND GND AMP12V AMP12V GND D12V GND D6V

Ana log / Digital / Log ic ]


CN802(Dig ita l Tu) NO 1 2 3 4 5 6 7 8 9 10 11 Po we r THEM_D S TD_5V GND PS _ON N. C. GND GND D3.3V D3.3V GND D6V 1 2 3 4 5 6 7 8 9 10 CN803(Lo g ic ) NO Po we r D3.3V D3.3V GND GND D5V GND IC2 IC2 PS _ON GND NO 1 2 3 4 5 6 7 8 9

[ S MPS
CN804(X- Ma in) Po we r D5V VG GND GND VE GND GND VS VS NO 1 2 3 4 5 6 7 8 9 10

X,Y- Ma in / Buffe r ]
CN805(Y- Ma in) Po we r D5V VG GND Vs c a n GND Vs e t GND GND VS VS CN806/ 812(Buffe r) NO 1 2 3 4 5 Po we r Va Va N. C. GND GND

[ FAN B+:For VMB]


CN807/ 811(FAN) NO 1 2 5 Po we r 12V GND Fa n_D

2-1. Drive Description on SMPS


[ S MPS Blo c k Dia g ra m]
HOT
AC input 90 V2 6 4V
EMI FILT ER

COLD

Vs (+ 8 5V)
DC/DC Converter
DC/DC Con ve r te r

3 8 5Vd c b u s Bo o s t PFC S tag e Vs _S witc hing S tag e

Vs et (+ 9 5V) Ve (+ 11 0 V)

NOIS E FILTER

Retur n PWM c o ntrol S tag e Va_S witc hing S tag e Aux ilia ry S tag e
Vcc
DC/DC Con ve r te r

Vs c an (+ 78 V)

Va(+ 7 9 V) Retur n

PWM c o ntrol S tag e VT (+ 3 3V 0 .03 A) 1 2V(+ 12 V 0.7A)

S tand_By

5V V_dig ital Cho ppe r REG

A1 2 V(+ 1 2V) D5 V (+ 5V)) Retur n MAG- AMP D3 .3 V (+ 3 .3 V) Vg (+ 15 V) 1 2 V Amp(+ 12 v) A6 V(+ 6V) PWM c o ntrol D6 V(+ 6V) V_analo g S witc hing S tag e Reg .

PS - ON/Relay S ignal

Vs Log ic _ON Ac tive_High

COLD

HOT

S tag e

COLD

Operation Description on SMPS


1. Overview SMPS used in PDP 42" developed into the compact-sized with high efficiency. The asymmetrical half bridge and the flyback converter are applied into all output. To comply with the harmonic restrictions, it takes the power factor improvementcircuit, which converts AC into the high DC and uses as the input of another converter controller.

2. Input controller SMPS works in whole section of AC 90~264V. It is possible to start in the AC 90 and can restart with new input voltage, even in interruption of electric power. STD_5V comes out when AC is impressed

3. Output Controller Given SMPS have 15 output voltages. The following shows the specification of output voltage and output current in case of their successive drive.

Operation Description on SMPS


Name VS VA VS CAN VS ET VE VG D12V Vo ltag e + 75V ~ 1 00V + 65V ~ 8 0V + 65V ~ 1 00V + 80V ~ 1 00V + 100V ~ 120V + 15V + 12V Curre n t(Max .) Us ing in P DP Driving 4.5 A 0.6 A 0.1 A 0.1 A 0.1 A 1.5 A 0.1 A Driving Vo ltag e o f F e t S us tain Vo ltag e Addres s Vo ltag e A6V D5V D3.3V + 6V + 5V + 3 .3V 0 .1A 1 .0A 4 .5A 1 .7A 0 .003A 0 .6A S tandby fo r Re mo te Co ntro l Amp Vo ltag e o f Audio IC Driving Vo ltag e o f Lo g ic Name A12V D6V Vo ltag e + 1 2V + 6V Curre n t(Max .) Us ing in P DP Driving 0 .3 A 0 .1A

12VAMP + 1 2V VT S T D_5V + 3 3V + 5V

3-1. Overvoltage protection It has circuit to maintain normal voltage, additionally with circuit for sensing overvoltage, so it means any overvoltage does not give impacts on other output controller. SMPS prevents overvoltage in the latch mode. VS(85V) works protection function more than 100V, over 94V for VA(75V), over 8.2V for D6V, over 4.7V for D3.3V

Operation Description on SMPS


3-2. Short circuit and overvoltage protection It forms definition that in the short circuit of output controller the output impedance is lower than 300mohm. If the VS output have a short circuit in case of given SMPS, SMPS stops its working. Even in the case of short circuit between main output and STD_5V, SMPS does not break down. When the short circuit is removed, it restarts.

4. Detail Description AC-DC Converter It converts AC into DC by using the power factor improvementcircuit. This converter was designated to control the high frequency noise, with the function to improve the power factor. This part becomes input controller of another constant-voltage.

[ P F C Drive F ET (S P W4 7 N6 0) Dra in P u ls e ]

[ P F C Drive F ET (S P W4 7 N6 0) Ga te P u ls e ]

Operation Description on SMPS


Auxiliary Power It is the part to supply power of mycom for remote control. When the power is on, it will work, which means that MICOM is on standby. This output part is stand_by voltage. When the power-on signal from remote control impress, it works main power panel of SMPS via stand_by voltage.

Configuration of VS output Major part of PDF SMPS outputs 85V 5A. It takes asymmetrical half bridge converter and connects 2 converters with 85V output in parallel, which increases efficiency than one 85V converter, on the other hand, decreases its size.

[ D i vi ng FET(2SK r 2372) D ai n Pul s e& r ent w r Cur ave. ]

[ Driving FET (2 S K2 3 72 ) Ga te P uls e ]

Operation Description on SMPS


- PWM Part It uses PWM part of ML4824, but there are some points to take cautions. As this part is synchronized with the PFC part, PWM wave in the current mode drive is induced via the current sensor resistance or current transformer, and shows the current flowing in the output controller.

DC-DC Converter : Input of VSCAN, VSET and VE belongs to the VS part

[ VS ET Puls e ]

[ VE Puls e ]

[ Vs c an Puls e ]

Operation Description on SMPS


Output (VA,Multi Outputs) Pulse

[ Va Ma in P uls e ]

[ Multi Outputs Ma in P uls e ]

Trouble shooting on SMPS


Po we r ON Che c k c o rd c o nne c tio n OK

NG S TB_5V

Chec k the IC2,D2 8

OK

PFC

Chec k the IC1,Q1 ,Q2

OK NG

OK

PFC

Chec k the IC35

NG PFC

Chec k the IC7

Trouble shooting on SMPS

NG

VS

Che c k the Q6 ,Q8

OK

Vs c an VE,Vs e t OK

Che c k the IC16 , IC17 , IC18

Che c k the Othe r boa rd ( Ima ge Board or Drive r Board ) or Ca ble .

2-2. Operation Explanation of Driving Circuit


1. Overview of Driver Circuit 1) Definition of Driver Circuit The driver circuit division drives the panel with the proper wave form (high voltage pulse) to develop image on the outside terminal division (X electrode group, Y electrode group, Address electrode). High voltage switching pulse is made by MOSFET combination.

2) Working Principle of Driver Circuit To develop image on the PDP, the voltage should be impressed into the X, Y and ADDRESS electrodes (which are component of each pictorial element) under the proper conditions. The driver wave form which is currently applied to is ADS (Address & Display Separate: Driving method to work by dividing address and constant-current section ) Based on this method, the discharge to be done in the pictorial element of PDP can be divided into 3 types as follows.

Address Discharge: to form the wall voltage within pictorial element by providing lighting pictorial element with information(impressing data voltage) : It is the discharge produced by difference between the positive electric potential of address electrode (normally, Va impressed voltage of 70~75V +Positive Wall charge) and negative electric potential of Y electrode (GND level impression+ Negative Wall charge).

Operation Description on Driving Board


Constant-current Discharge: It is the display section to form discharge voluntarily with the help of wall voltage formed by address discharge. (It makes optical power to create image) : It is the Self Sustaining Discharge made by combining the electric potential of coherent pulse, normally 160-170Volt, which alternates the X electrode with Y electrode in the sustain section, with the wall voltage according to the pictorial element condition changed by if the former discharge exists or not. That is to say, it works according to Memory characteristic (it means that former working condition defines the current condition) as the basic feature of AC PDP.

If the wall voltage formerly exists in the pictorial element(i.e., the pictorial element is on), the discharge makes forms again because the voltage higher than one of the discharging starting time is impressed by combination of the wall voltage and of the next impressed constant-current. While if the wall voltage does not exist in the pictorial element (i.e., the pictorial element is off), the discharge does not form because the voltage could not reach to the level of the discharging starting time, only with constant-current.

Operation Description on Driving Board


Erasing discharge: To selectively perform the address discharge for respective pixel, pixels of all panels must be on same conditions (same wall charge state and space charge state). Therefore the erasing discharge zone is important factor to obtain driving margins. There are various methods such as application of log waveform but the wall voltage control method by the Ramp Waveform is now widely applied. : The purpose of intialization (Erasing) discharge is to make wall voltage within the the whole of Pixels. In other words, the erasing discharge must make difference between wall voltages uniform depending on whether or not the sustain discharge exists in the previous state. Namely it must remove the wall voltage formed by the sustain discharge and supply ions or elements by causing discharge for removing the wall voltage. In the other words, To remove the wall voltage, limit the time when polarity of the wall voltage is reversely charged by causing discharge or prevent polarity form being reversely charged by supplying appropriate quantity of ions or elements through forming weak discharge [low voltage of erasing]. There are two types of the weak discharge [low voltage]as known so far. 1) Log Waveform adopted by the F-company 2) Weak erasing discharge by the Ramp Waveform largely adopted by Matsushita company, etc. Outside applied voltage is adjusted depending on difference of wall voltage within Pixel, since discharge is formed when the sumof the existing wall voltage remained and the voltage on a rising waveform exceed the driving beginning voltage, by slowly applying the rising slope of the erased waveform for these two methods. In addition, weak discharge is formed since the strength of applied voltage is small.

Operation Description on Driving Board


3) Essential factors for driving board operation - Supplied from power board and the optimum value may somewhat differ from the below cases.

Vs

: 85V

- Sustain - Y Rising Ramp - Ve bias

Vset : 60V ~ 70V Ve : 110V

Vscan : 70V ~ 80V - Scan bias Vdd : 3.3V Vcc : 15V Logic Signal : Supplied from logic board : Gate signal of each FET - Logic signal buffer IC - FET Gate drive IC

Driving Waveform Specification Arrangement


Y ris ing Ra mp Y falling Ra mp Y s us tain P uls e

Y s c an P uls e X s us tain P uls e

Addre s s P uls e

A 2. . . . . 1, X Y 2. . . . 1,

A es s (=D a) El ect r ode ddr at Com on & Sus t ai n El ect r ode m Scan & Sus t ai n El ect r ode

V s V et s V can s

85V 95V 85V

V e V a

110V 79V

Explanation of Function per Pulse


Y Rising Ramp Pulse Outside voltage of about 390V~400V is applied to the Y electrode in the Y Rising Ramp zone, and weak discharge begins if respective gap voltage equals to the discharge beginning voltage. Negative Wall charges accumulate on the Y electrode and the Positive Wall charges on the X electrode in the whole while weak discharge is maintained.

Y Falling Ramp Pulse Most of Negative Wall charges accumulated on the Y electrode by the X bias of about 200V are used to remove Positive Wall charges in the Y Falling Ramp zone, and most of Positive charges accumulated on the (0V) Rising Ramp zone toward the address electrode are maintained, having distribution of wall charges beneficial for the subsequent address discharge.

Explanation of Function per Pulse


Y Scan Pulse Y scan pulse is called as injection pulse, and selects the Y electrode one by one (Line-at-a-time). In this case, Vscan is called as Scan bias. For the electrode line with the Vscan voltage applied, voltage of about 70 Volt (Vscan) is applied, and voltage of 0 Volt(GN0) is applied. However, since Negative Wall charges accumulate on the Y electrode by the application of Ramp pulse and Positive Wall charges accumulate on the address electrode, voltage of more than the discharge beginning voltage is applied to the cell where address pulse(70V~75V) is allotted and thus address discharge occurs. Address time of the PDP is very long since both scan pulse and data pulse must be applied in line at a time.

1st Sustain Pulse The Sustain Pulse always begins from the Y electrode, it is because Positive Wall charges are formed on the Y electrode if address discharge occurs. The wall charges formed by the address discharge are less than those for the sustain discharge, and thus the strength of the initial discharge is weak. Sustain discharge usually become stable after 5~6 times of discharge depending on structure of electrode and environment. Therefore, the initial long sustain pulse is intended to form the initial discharge stable and form the wall charges much as possible as.

Trouble shooting on Driving Board


1. Y buffer
- To check whether there is failure of the Y Main, firstly check normal operation of the Y buffer. - After separating both the Y Main and the Y buffer connector, - Check forward voltage drop of 0.4V ~ 0.5V by diode check between OUTL and OUTH. - In addition, resistance between both ends is also more than several k .

OUT L

OUT H

O TL U O TH U

O TL U

O TH U

Trouble shooting on Driving Board


2. Y Main - After connecting both the Y Main and the Y buffer, check that output of one of OUT1~8 of the Y buffer is done as follows in application of power
O T1 U O T2 U

Y m t check 1EA of Scan pul s e i s out put ou us

O T3 U O T4 U O T6 U O T5 U

Trouble shooting on Driving Board


3. X Main - Check output of the TPOUT on the X board is done as follows in application of power

TPOU T

2-3. Operation Explanation of Logic Board


[ Lo g ic Blo c k Dia g ra m]
Im age Si gnal V St art s Si gnal Logi c Pow er 3. 3V 5V ,

LA 03 IIC (SCL, SD ) A V s t art s U 2004 27M z H LV DS SW 2001


Im age Si gnal 8 bi t pe r DATA R. G B . 1 bi t pe r H V SYN , C

CN 803 28. 636M z X H 2002 O SC CY 2305 U 2003 EPC2 U 2011 EPC2 U 2007 EPC2 U 2006 64M SD M RA U 2014

X 2000 60M z H 64M CY 2305 U 2002 SD M RA U 2013 R ESET SPS10- M EM A C SI M OY EM R CO TR N OLLER U 2000 Ci r cui t X CO TRO N L X CO TR N OL CN 101

EP20K 400EBC652- 1 Y CO TR N OL Y CO TRO N L CN 201 28BV 256K U 2001 IIC V CC(3. 3V ) GD N I I C(SCL, SDA ) CN 2002 CN 401
A 101~106 DRV A 201~206 DRV A 301~306 DRV CLK BLK POL, STB , ,

FPG A FR T_X ON Y U 2005

8 bi t per D TA R G. B A . 1 bi t per H V SY , NC 1 bi t per D TA , TSC, PO SEN SD SC A _EN L, , A, LK _nR ESET

40M z H X 2001

CLK Y(20M z), SV N _X H _SY C nRESET

A 401~406 DRV CLK BLK POL, STB , ,

CN 402

A 501~506 DRV A 601~606 DRV A 701~706 DRV CLK BLK POL, STB , ,

CN 403

e-buff er

f-buff er

g-buff er

Definition of Name and Terms on Logic Board

LOGIC BOARD M O D E L OP T ION S /W S T AT US


ON

REMARKS
Ex te rnal : 2,4 On Inte rnal : 3 On

4 2" S D
OFF 1 2 3 4

N o. LV connect or DS

I t em LED for operat i on check I 2C connect or 256K Y connect or X connect or CN 401(E- addres s buf fer connect or) CN 402(F- addres s buf fer connect or) CN 403(G addres s buf fer] connect or) Power connect or Power fus e O ON S/ W PTI

Expl anat i on Connect or for recei vi ng R B, H V D TA , D G , , A EN CLK encoded i n t he LV from i m DS age board. LED t o s how t hat Sync, cl ock i s nor m l y i nput i nt o t he l ogi c board al Connect or connect i ng t he K Scan Board t hat checks and adj us t s 256K dat a ey Eeprom t o s ave t abl e, A t abl e, dri vi ng w PC avef orm t i m ng and ot her opt i on, et c i Connect or t o out put cont r ol s i gnal of t he Y dri vi ng board Connect or t o out put cont r ol s i gnal of t he X dri vi ng board Connect or t o out put addres s dat a, cont r ol s i gnal t o t he E-buf fer board Cnnec t or t o out put addres s dat a, cont r ol s i gnal t o t he F-buf fer board Connect or t o out put addres s dat a, cont r ol s i gnal t o t he G -buf fer board Connect or t o recei ve power 95V t o t he l ogi c board ] Fus e at t ac hed t o power [5V t o t he l ogi c board ] I nner / O er cut -off S/ W ut

Explanation of Logic Board


Logic board is composed of a logic main board that generates and outputs the address driver output signal and the XY driving signal by processing image signal, and a buffer board that buffers the address driver output signal and delivers it to the address driver IC (COF Module).

Logi c Board

Funct i on
- Pr oces s es I m age s i gnal (WL, er r or di s per s i on, A / PC) - O put s i m ut age s i gnal as addr es s dr i ver cont r ol s i gnal , dat a s i gnal buf fer boar d - O put s t he X dr i vi ng boar d cont r ol s i gnal ut Y

R ar ks em

Logi c M n ai

E Buf fer boar d

- D i ver s dat a s i gnal and cont r ol s i gnal t o t he el r i ght / r i ght CO F - D i ver s dat a s i gnal and cont r ol s i gnal t o t he el m ddl e/ l ow CO i er F - D i ver s dat a s i gnal and cont r ol s i gnal t o t he el Ri ght / Low CO er F

Buf fer Boar d

F Buf fer boadr

G Buf fer boar d

2-4. Explanation of Scaler(Image Board) Operation


DIGIT AL BO RD I C & SI G A BLOCK D A RA A NL I G M
CR STA Y L TO LO I C G D S90C385 Z86129 M 2 7 V 1 6 0 A A G Si gnal N LO D G TA Si gnal I I L FR SM OM PS CLOCK Si gnal

K 4S643232E SN I K 4S643232E FLI 2200

V PC3230

CVBS

20. 25M K 4S641632E K 4S643232E A 500 SI K 4S643232E SD 6000 A BA 7657 V PC3230 20. 25M 14. 3181M K 4S643232E M 160 27V

Y/ C

Y/ Pb/ Pr/ H/ V

A 9883 D FR OM CO TR N OL PCB 6M Si I 161A

74H C4052

DVI L/ R R/ G/ B/ H V / D- SU L/ R B

S- VH Y/ C S

DVI , D- SU L/ R B S- VH L/ R S

RS- 232

DVI

DVI SOU D N

D- SU B

D- SU B Sound

S- VI DEO

S- VI DEO VI DEO Sound /

Explanation of Scaler(Image Board) Operation


ANALOG BO RD I C & SI G A BLOCK D A RA A NL I G M
CN8 01
FR SM OM PS CR STA Y L A A G SI G A N LO NL D G TA SI G A I I L NL CLOCK SI G A NL

18. 432M

Y/ C CN1 01

U 64083 PD

20M

SU W B OOPER CVBS CVBS DVI , D- SU L/ R B Y/ Pb/ Pr/ H/ V S- VH L/ R S


CX 2151 A 4M M SP3451

L/ R CN1 02

S- CV BS
TEA 6425

Y/ Pb/ Pr
BA 7657 TA 1101

M CV - BS
TU ER 2 N TU ER 1 N

CN1 03 VI DEO- C VBS Y/ Pb/ Pr 1 Y/ Pb/ Pr 2

VODEO

COM EN PON T1

COM EN SOU D PON T1 N

COM EN PON T2

COM EN SOU D PON T2 N

SOU D OU T N TPU

RF IN T PU

Sub-woof er Out put

Factory Data per each Mode


1. UPD 64083 (COMB FILTER)
I TEM V PG I N A A V PI N A V Y PFP Y PFG TV V deo/ S- V de o/ Com / i i ponent 1, 2(SD ) 4 16 3 9 Com ponent 1, 2(H ) D 4 16 3 9 PC 4 16 3 9 DI V 4 16 3 9

2. VPC 3230(M) : Main VCD


I TEM CO TRA N ST BRI G TN H ESS PEA I N K G CO I N R G LU A D Y M ELA H PLL SPEED Y V CO TRA U N ST Y V BRI G TN U H ESS Y V SA U TCB Y V SA U TCR Y V TI N U T SA RA O TU TI N TI N T TV V deo/ S- V de o/ Com / i i ponent 1, 2(SD ) 43 47 5 0 255 1 29 68 42 42 3 2000 32 Com ponent 1, 2(H ) D 43 47 5 0 255 1 29 68 42 42 3 2000 32 PC 43 47 5 0 255 1 29 68 42 42 3 2000 32 DI V 43 47 5 0 255 1 29 68 42 42 3 2000 32

Factory Data per each Mode


3. VPC 3230(S) : SUB VCD
I TEM PI P CON A TR ST PI P BRI G TN H ESS Y V CON A U TR ST Y V BRI G TN U H ESS LU A D Y M ELA H POSI TI ON V POSI TI ON TV V deo/ S-V deo/ Com / i i ponent 1, 2(SD ) 43 47 29 68 255 0 0 Com ponent 1, 2(H ) D 43 47 29 68 255 0 0 PC 43 47 29 68 255 0 0 DI V 43 47 29 68 255 0 0

4. FLI 2200 (De-Interlacer)


I TEM Y CLA P M C CLA P M YD Y ELA CD Y ELA M O D OTI N ETECT TV V deo/ S-V deo/ Com / i i ponent 1, 2(SD ) 64 512 4 11 48 Com ponent 1, 2(H ) D 64 512 4 11 48 PC 64 512 4 11 48 DI V 64 512 4 11 48

Factory Data per each Mode


5. ASI500
I TEM
R CO TR ST N A G CO TR ST N A B CO TR ST N A R BR G TN I H ESS G BR G TN I H ESS B BR G TN I H ESS TEX A A T LPH TEX TH T RESHO LD FI LTER M L FI LTER M R FI LTER FR FI LTER M C FI LTER U C FI LTER LC FI LTER Y SS PA R G MA AM G G MA AM B G MA AM H PO TI O SI N V PO TI O SI N H SI ZE V SI ZE O ER N B V SCA O ER N G V SCA O ER N R V SCA

(SCALER MAIN / OSD)


TV V deo/ S- V de o/ Com / i i ponent 1, 2(SD ) Com ponent 1, 2(H ) D
32 32 32 0 0 0 1 7 0 0 0 16 0 0 0 32 32 32 0 0 0 0 63 63 63

PC

DI V

Factory Data per each Mode


6. ASI500
I TEM PI P R CON T PI P G CON T PI P B CON T PI P R BRI G T H PI P G BRI G T H PI P B BRI G T H PI P FI LTER LC PI P FI LTER M L PI P FI LTER M R PI P FI LTER U C

(SCALER PIP)
TV V deo/ S-V deo/ Com / i i ponent 1, 2(SD ) Com ponent 1, 2(H ) D 32 32 32 0 0 0 0 0 0 0 PC DI V

8. CXA2151HD (COMPONENT MUX)


I TEM G IN A -SEL CR G I N A CB G I N A Y G IN A TV V deo/ S- V de o/ Com / i i ponent 1, 2(SD ) 1 7 7 7 Com ponent 1, 2(H ) D 1 7 7 7 PC 1 7 7 7 DI V 1 7 7 7

Factory Data per each Mode


7. DNIe (Picture Enhancer)
I TEM BR G T OFFSET I H CO TRA OFFSET N N SCA M X R LE A N SCA M N R LE I D G I N CO E A R D G I N CLI P E A CE U PPER CE CU FF TO CE G I N A W Y TH TE RE R CTL SY C M D N OE PA SEL TT RED CO PEN N SA BLU CO PEN E N SA W GIN TE A RA V ZE ST SI RA H ZE ST SI SH R OFFSET AP TV V deo/ S- V de o/ Com / i i ponent 1, 2(SD ) Com ponent 1, 2(H ) D 0 0 52 18 3 60 240 64 48 230 2 1 0 616 616 58 1023 895 0 PC DI V

Factory Data per each Mode


9. AD 9883 (AD Converter)
I TEM R G IN A G G IN A B G IN A R, CR O FFSET G YO , FFSET B, CB O FFSET A o Col or ut TV V deo/ S- V de o/ Com / i i ponent 1, 2(SD ) 142 142 142 60 48 64 Com ponent 1, 2(H ) D 142 142 142 60 48 64 PC 142 142 142 54 54 54 DI V 142 142 142 60 48 64

10. Logic (PDP Driver)


I TEM RD V RI E GD V RI E BD V RI E R CU FF TO G CU FF TO B CU FF TO G MA AM G SET TS ERD M D OE RA D M N I SE NO O D FF FI LTER I A PC A SET PC A V LU PC A E A V V S CTI E PO A V H S CTI E PO V N PO SY C S H N PO SY C S V N WD SY C I TH H N WD SY C I TH TV V deo/ S- V de o/ Com / i i ponent 1, 2(SD ) 140 130 120 0 0 0 Com ponent 1, 2(H ) D 140 130 120 0 0 0 1 0 2 0 1 1 0 127 12 19 3 32 2 12 PC 140 130 120 0 0 0 DI V 140 130 120 0 0 0

Factory Data per each Mode


11. TP LOG-ASI : Test Pattern LOGIC/SCALER
I TEM LOG PA TTERN LOG H G LEV I H EL LOG LOWLEV EL A COLOR R SI BA TV V deo/ S- V de o/ Com / i i ponent 1, 2(SD ) Com ponent 1, 2(H ) D 0 255 0 0 PC DI V

12. Option
I TEM PI X SH FT I SH FT TEST I PI X N M U BER SH FT LI N I E SH FT TI M I E COU TRY N TEM PRO P TECT SN D O I EM SN TH G I ROU H V D M TE I EO U I RC A FN LA G A E NUG CU M STO ER TU ER N TV V deo/ S- V de o/ Com / i i ponent 1, 2(SD) Com ponent 1, 2(H D) 0 0 2 1 4 0 0 0 0 10 0 0 0 0
0 : OFF 1: ON 1 : TH OU H R G 0 : N TH OU H OT R G U t : 100m ec ni s 0 : for cus t om er 0 : Engl i s h 0 : CE 0: 1 TU ER N 1 : for m l i t ar y i 2 : Spani s h

PC

DI V
0 : OFF 0 : m nut e i

Rem k ar
1 : ON 1 : s econd

N ber of s hi ft ed Li nes hori zont al l y um N ber of s hi ft ed Li nes vert i cal l y um Ti m fi xed at SH FT TEST e I 0 : dom t i c es 1: U SA 2 : Japan

1 : Fr ench 1: VB M 1: 2 TU ER N

Signal Waveform at AV(Audio & Visual) Board


Input Signal : 8-Color Bar 8-

A A G BOA I C103(TEA N LO RD 6425D PI N I D -CV ) 6(V EO BS)

A A G BOA CN N LO RD 102 PI N 12(3D _OU _Y T)

AA N LOG BO R CN A D 102 PI N 10(3D _C_O T) U

D G TA BO R I C101(V I I L AD PC3230D C5) PI N 57(V PC_V N SY C)

Signal Waveform at AV(Audio & Visual) Board


Input Signal : 8-Color Bar

D G TA BOA D I C101(V I I L R PC3230D -C5) PI N 56(V PC_H N SY C)

D G TA BOA D I C101(V I I L R PC3230D -C5) PI N 28(V PC_CLK )

D G TA BOA D I C104(FLI 2200) PI N I I L R 91(FLI _V N SY C)

D G TA BOA D I C104(FLI 2200) PI N I I L R 92(FLI _H N SY C)

* Dimensions in mm

Signal Waveform at AV(Audio & Visual) Board


Input Signal : 8-Color Bar

D G TA BO R I C104(FLI 2200) PI N I I L AD 90(FLI _D E)

D G TA BO R I C104(FLI 2200) PI N I I L AD 117(FLI _CLK )

D G TA BO RD RW I I L A 507(A 500 OU T) PI N N N ) SI TPU 2(M _I _V

D G TA BO RD RW I I L A 507(A 500 OU T) PI N N N ) SI TPU 1(M _I _H

Signal Waveform at AV(Audio & Visual) Board


Input Signal : 8-Color Bar

D G TA BOA D R 507(A 500 O TPU PI N N N I I L R W SI U T) 4(M _I _CLK )

D G TA BOA D I C601(SN O TPU PI N U SY C) I I L R I U T) 9(O T_V N

D G TA BOA I C601(SN O TPU PI N I I L RD I U T) 10(O T_H N U SY C)

D G TA BOA I C601(SN O TPU PI N I I L RD I U T) 8(OU E) T_D

Signal Waveform at AV(Audio & Visual) Board


Input Signal : 8-Color Bar

D G TA BOA D I C601(SN O TPU PI N I I L R I U T) 12(O T_CLK U )

AA N LOG BOA D I C101(CX 2151 O TPU PI N R A U T) 27(COM ) P_Y

A A G BOA I C101(CX 2151 O TPU PI N N LO RD A U T) 26(COM P_PB)

A A G BOA I C101(CX 2151 O TPU PI N N LO RD A U T) 25(COM P_PR)

Signal Waveform at AV(Audio & Visual) Board


Input Signal : 8-Color Bar

AA N LOG BOA D I C101(CX 2151 O TPU PI N R A U T) 23(COM ) P_V

AA N LOG BOA D I C101(CX 2151 O TPU PI N R A U T) 22(COM ) P_H

D G TA BOA I C705(A 9883 O TPU PI N I I L RD D U T) 64(A _SU ) SI B_V

D G TA BOA I C705(A 9883 O TPU PI N I I L RD D U T) 66(A _SU ) SI B_H

Signal Waveform at AV(Audio & Visual) Board


Input Signal : 8-Color Bar

D G TA BOA D I C705(A 9883 O TPU PI N I I L R D U T) 65(A _SU SI B_SO ) G

D G TA BOA D I C705(A 9883 O TPU PI N I I L R D U T) 67(A _SU SI B_CLK )

D G TA BOA D I C702(SI I 169CT O TPU PI N I I L R U T) 47(D I _V N V SY C)

D G TA BOA D I C702(SI I 169CT O TPU PI N I I L R U T) 48(D I _H N V SY C)

Signal Waveform at AV(Audio & Visual) Board


Input Signal : 8-Color Bar

D G TA BO R I C702(SI I 169CT OU T) PI N I I L AD TPU 46(D I _D V E)

D G TA BO R I C702(SI I 169CT OU T) PI N I I L AD TPU 44(D I _CLK V )

Trouble Shooting for PDP Set


Tur n on t he s et Pr ot ect i on or LED N m or al N O LED pr obl em s Rem ove al l Connect or s f r om SM PS(except A ) and V Che ck t he pr ot ect i on or vol t age s N O Change SM PS N O Change XM n - ai N O OK Connect XM n - ai OK Connect YM n - ai OK Connect A ddres s Buf fer Change YM n - ai OK Che ck PS_O ( 0V: SM CN N PS 802 pi n4) & (SM 802 pi n2) N LED Che ck s t and_by 5V PS CN O Rem ove N O Connect or s f r om Am t N l os o V t age s ol on t he SM PS? OK N V t age s O ol Change SM PS Y es Change t he dam aged Board OK Che ck t he K ey-Pad Rem ove al l Connect or s N O f r om SM and Che ck t he PS vol t age s on A Boards V N O Onl y V or V cannot be m ur e d s a eas Che ck V N ) S_O (3V CN 803(SM pi n2) PS N O Change Logi c Change SM PS OK Change Di gi t al N O OK Che ck ot her Boards

Change A ddres s Buf fer

Che ck V t age s ol on t he SM PS (V , V Ve, V et . . ) s a, s OK Che ck t he dam aged com pone nt s on X Y-M n & , ai A ddres s Board

N O

X Y-M n, A es s , ai ddr Buf fer s and Che ck t he vol t age s on SM agai n PS

N Dam O aged Com pone nt s Che ck t he Fus es on X Y-M n Boards , ai (F4003, F5003) OK Change Y M n - ai N O Change X M n - ai N O N O Change t he dam aged Board

I can s ee s om V deo e i ex) TV V de o or et c I nput s our ce , i Che ck whe t her al ways N V deo o i about al l A i nput s V

Change A og nal Change Che ck t he N O LV cabl e DS N O Change Logi c

N can' t s ee O, any V deo i

Di gi t al

Comparison with New Models


Project
Design

Alexander (V2)

Mozart (V3)

Nelson (V3)

Brightness Contrast ratio Tuner Audio out Sound Speaker Video input S-Video input Component Input Side Input DVI Power Consumption Etc.

700cd/m2 1200:1 2Tuner 10W x 2 Dolby Virtual Not Included 1Rear 1Rear 2Rear 1Rear 330W -

1000cd/m2 3000:1 2Tuner 15W x 2 SRS Tru Surround XT Included 2Rear 1Rear 2Rear CVBS, S-Video 1Rear 330W Touch Pad, Melody

1000cd/m2 3000:1 1Tuner 15W x 2 SRS Tru Surround XT Not Included 1Rear 1Rear 1Rear 1Rear 330W -

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