How does microprocessor differentiate between data and instruction and code?

As soon as p is turned on it begins execution of code in the memory sequentially - Both opcode and data are in binary numbers, so how to differentiate? - The p interprets the first byte it fetches as opcode and second as data - Eg. We tell the processor that our program begins at 2000h. The first code it fetches is 3Eh, when it decodes it knows that it is a 2 byte instruction, hence the second code i.e. 32h is a data byte. If we enter 06h instead of 32h then it will load 06 in the accumulator instead of 32 -

One byte instructions

TASK Copy contents of accumulator in register C Complement each bit in the accumulator OPCODE MOV OPERAND C,A BINARY CODE 0100 1111 HEX CODE 4FH

CMA

0010 1111

2FH

As soon as p decodes this it understands that it is a 1 byte instruction

Tw o b y t e i n s t r u c t i o n s
TASK Load an 8 bit data byte in the accumulator Load an 8 bit data byte in register B OPCODE MVI OPERAND A,32H BINARY CODE 0011 1110 0011 0010 0000 0110 1111 0010 HEX CODE 3E(first byte) 32(second byte) 06 F2

MVI

B,F2H

2 memory locations required

As soon as p decodes this it understands that it is a 2 byte instruction

Three byte instructions

TASK Load of contents of memory location 2050H into A Transfer the program sequence to memory location 2085H OPCODE LDA OPERAND 2050H BINARY CODE 0011 1010 0101 0000 0010 0000 1100 0011 1000 0101 0010 0000 HEX CODE 3A(first byte) 50(second byte) 20(third byte) C3 85 20

JMP

2085H

As soon as p decodes this it understands that it is a 3 byte instruction

C L A S S I F I C AT I O N O F INSTRUCTION SET
1.Data transfer(copy) instructions 2.Arithmetic instructions 3.Logical instructions 4. Branching instructions 5.Machine control instructions

Data transfer instructions

Definition : Copies data from source to destination, retaining the contents in the source. Note:
NOTATIONS M r rp rs rd addr MEANING Memory location pointed by HL register pair 8 bit register 16 bit register pair Source register Destination register 8 bit/16 bit address

The various data transfer instructions are MOV rd,rs MVI rd,data(8bit) MVI M, data (8 bit) MOV M ,rs MOV rd, M LXI rp , data (16 bit) STA, addr( 16 bit) LDA addr (16 bit) SHLD addr(16 bit) LHLD addr (16 bit) STAX, rp LDAX rp XCHG

Instruction MVI r,8 bit data    

Description Loads specified register with 8 bit data Addressing mode : Immediate No. of bytes: 2 bytes Example: MVI C,30H

Example details C 30H

MVI M,8 bit data

 Loads 8 bit data into a memory location whose address is specified by contents of HL register pair  Addressing mode : Register indirect  No. of bytes: 2 bytes  Example: MVI M,90H  Content of source register is copied into the destination register  Addressing mode : Register  No. of bytes: 1 bytes  Example: MOV E,A

assume H = 30H L = 50H [3050] 90H

MOV rd , rs

A = 15H E 15H

MOV M , rs

 Contents of source register is copied into the assume HL = 2055 memory location whose address is specified by C = 25H HL register pair [2055] 25H  Addressing mode : register indirect  No. of bytes: 1 bytes  Example: MOV M,C

Instruction MOV rd,M

Description

Example details

 Contents in the memory location specified by Assume HL = 2055 HL register pair are copied to the destination Contents of memory location 2055 = 30H register rd  Addressing mode : Register indirect B 30H  No. of bytes: 1 byte  Example: MOV B,M  Loads 16 bit data into the register pair B specified C  Addressing mode : immediate  No. of bytes: 3 bytes Only higher order register is mentioned  Example: LXI B,6051H 60H 51H

LXI rp,16 bit data

LDA addr

 It loads the content specified by the memory Assume [3500H] = 54H location into the accumulator A 54H  Addressing mode : direct  No. of bytes: 3 bytes  Example: LDA 3500H  Contents of accumulator are copied to the A = 54H specified memory location (3800)  Addressing mode : direct  No. of bytes: 3 bytes  Example: STA 3800H

STA addr

54H

Instruction LDAX rp

Description

Example details

 Instruction copies content of memory location Assume whose address is specified by register pair in the DE = [4515H] = FFH accumulator only BC or DE register pair is used  Addressing mode : Immediate A FFH  No. of bytes: 1 byte  Example: LDAX D  Copies the content of accumulator in the Assume A = 10H memory location specified by register pair BC = 4324H  Addressing mode : register indirect [4324]  No. of bytes: 1 byte  Example: STAX B  Copies the content from the memory(address specified) into register L and content of next memory location in register H  Addressing mode : direct  No. of bytes: 3 bytes  Example: LHLD 2500H  Copies the contents of the L register in the memory(address specified) and contents of H register in the next memory location  Addressing mode : direct  No. of bytes: 3 bytes  Example: SHLD 2500H Assume [2500] = 35H [2501] = 60H H 60H L 35H Assume L = 30H H = 55H [2500] = 30H [2501] = 55H

STAX rp

10H

LHLD addr

SHLD addr

Instruction XCHG

Description

Example details

 Exchange contents of H with D Assume HL = 2060H register and L with E register DE = 3055H  Addressing mode : register H = 30H L = 55H  No. of bytes: 1 byte D = 20H E = 60H  Example: XCHG

MOV rd , rs
MOV rd,rs this is the one byte instruction use to transfer the the contents of source register to destination register. Operation : rd <----rs It is one byte instruction Register addressing mode No flag is affected eg. MOV E,B MOV D,A etc

MVI rd, data (8 bit)

MVI rd,data (8 bit) The eight bit data is copied immidiatly in to the destination register. Operation : rd <---- 8 bit data 2 byte instruction Immidiate addressing mode No flags are affected Eg : MVI A ,40 MVI C, CD

MVI M data (8 bit)

MVI M ,data (8 bit) This instruction copies the the 8 bit data immidiatly to the memory location of which the address is given by HL register. Operation: M <--- 8bit data Two byte instruction Indirect addressing mode No flags are affected eg. MVI M 4D, MVIM ,D0

MOV rd, M
MOV rd, M This instruction copy the content of memory location of which address is given by HL register pair. Operation: rd <---- M One byte instruction Indirect adrressing mode. No flags are affected. eg. MOV C,M MOV E , M

LXI rp , data (16 bit)

LXI rp , data (16 bit) This instruction copy the 16 bit data immidiatly into the register pair specified in the instruction.The register pair may be BC , DE , HL etc. Operation : rp <--- 16 bit data 3 byte instruction Immidiate addressing mode No flags are affected. eg. LXIH 49D1 , LXID 3O7A etc.

STA , addr (16 bit)

This instruction will copy th contents of accumulator to the address specified in the instruction. Operation : addr <--- A 3 bye instruction Direct addressing mode No flag affected eg. STA 40FO STA 3000.

LDA , addr(16)
This instruction copy the content of the memory location specified in the instruction ,in to acuumulator. Operation : A <----addr 3 byte instruction Direct addressing mode No flag affected Eg . LDA 4800 LDA 27F7

SHLD , addr
This insruction copy the content of H and L register to the memory address given in the instruction such that contents of H will copy to higher address and contents of L will copy to lower address. Operation : (addr) <---L and (addr+1) <---H 3 byte instruction Direct addressing mode. No flag affected. Eg . SHLD 3000 SHLD 30FF

LHLD , addr
This insruction copy the conents of memory address, given in the instruction to H and L register such that lower address contents will copy in L and higher address contents will copy to H register. Operation : L <---- addr and H <--- addr + 1 3 byte instruction Direct addressing mode. No flag affected Eg . LHLD 3000 LHLD 93FF

STAX rp
this instruction will copy the contents of accumulator to the memory address give by the register pair in the instruction. Operation : rp <-----A 1 byte instruction. Register indirect addrssing mode. No flags are affected. Eg . STAX B STAX D .

LDAX rp
This instruction will copy the contents of memory address given by the register pair in the instruction in to accumulator. Operation : A <---rp 1 byte instruction. Register indirect addressing mode. No flag affected. Eg . LDAX D LDAX B.

XCHG
This instruction will exchange the contents of HL and DE register pair . Operation : H <----> D and L <----> E 1 byte instruction Register addressing mode. No flag affected.

ARITHMETIC GROUP
This group contains the instructions which are responsible for arithmatical operation such as addition ,substraction, increament or decreament the data in the register. This group consist of following instruction ADD r ADD M ADI data (8 bit) ADC r ADC M ACI data (8) DAD rp

ADD r
This instruction add the content of register specified in instruction with contents of accumulator.Result will be stored in the accumulator. Operation : A <----- A + r . 1 Byte instruction. Register addressing mode All flags are affected. Eg . ADD B ,ADD C ADDM etc

ADD M
This instruction will add the data of memory(memory address in HL REG.) with the data in accumulator . Operation : A <--- A + M 1 Byte instruction. Indirect addressing mode. All flags are affected. Eg . ADDM

ADI data (8 bit)

This insruction add the 8 bit data given in the instruction with the accumulator.result will be stored in the accumulator. Operation : A <---- A + data 8 bit. 2 byte instruction. Immidiate addressing mode. All flags are affected. Eg . ADI 5D , ADI F9.

ADC r
This instruction add the conents of register along with carry with register A. Result is stored in A. Operation : A <--- A + r + CY 1byte instruction. Register addressing mode. All flags are affected. Eg . ADC B ADCH

ADC M
This instruction add the data in A with memory along with carry flag.result will be stored in A. Operation : A <---- A + M + CY 1 byte instruction Indirect addressing mode. All flags are affected. Eg . ADC M

ACI data (8 bit)

This instruction add the 8 bit data along with carry with A .Result will be stored in A . Operation : A <------ A + data (8 bit) + CY. 2 byte instruction. Immidiate addressing mode. All flags are affected. Eg . ACI 87 ACI F3

DAD rp
This instruction add the 16 bit data in the register pair with the 16 bit data in HL register. Result is stored in HL pair. Operation : HL <---- HL + rp. 1 byte instruction. Register addressing mode. Only carry flag is affected. Eg .DAD B , DAD D

SUBSTRACTION

SUB r SUB M SUI data (8 bit) SBB r SBB M SBI data (8 bit)

SUB r
This instruction substracts the data in register from accumulator.Result is stored in accumulator. Operation : A <--- A r 1 byte instruction. Register addressing mode. All flags are affected. Eg . SUB B SUB D

SUB M
This instruction substracts the contents of memory (address given by HL) from accumulator.Result is stored in accumulator, Operation : A <---- A - M. 1 byte instruction. Indirect addressing mode. All flags are affected. Eg . SUBM

SUI data (8 bit)

This instruction substracts the 8 bit data immidiatly from A .Result is stored in accumulator. Operation : A <----- A- data (8 bit). 2 byte instruction. Immidiate addressing mode. All flags are affected. Eg . SUI 7A SUI 40

SBB r
This instruction substracts the data in the register from A along with carry .Result is stored in A. Operation : A<----- A r - CY. one byte instruction. register addrssing mode All flags are affected. Eg . SBB D SBB C .

SBBM
This instruction will substracts the contents of memory (address given by HL ) from A along with carry flag. Operation : A <----- A M- CY. 1 byte instruction. Indirect addressing mode. All flags are affected. Eg .SBB M

SBI data (8 bit)

This instruction immidiatly substracts the 8 bit data from A along with carry. Result is stored in A . Operation : A <----- A data (8 bit) CY. 2 byte instruction. Immidiate adressing mode. All flags are affected. Eg . SBI 74 SBI 3B

DECIMAL ADJUST ACCUMULATOR (DAA)

This instruction adjust the result in accumulator to valid BCD. This instruction add the no. 06 to MSB or LSB if it is greator than 9 or auxillary carry and carry flag is set. I byte instruction. All flags are affected.

INCREMENT AND DECREMENT INSTRUCTION

INR r INR M INX rp DCR r DCR M DCX rp

INR r

Increments the conents of specified register by one. Operation : r <--- r + 1. 1 byte instruction. Register addressing. All flags except carry are affected. Eg . INR D INR B

DCR r
Decrements the contents of register by one Operation : r <---- r + 1 One byte instruction. Register addressing mode. All flags except carry are affected.

INX rp
This instruction increaments the contents of register pair by one. Operation : rp <---- rp + 1. 1 byte instruction. Register addrssing mode. All flags are affected. Eg .INX B INX H INX SP

INR M
This instruction will increment the content of memory location (address given by HL) by one. Operation : M <----- M+ 1. 1 Byte instruction. Indirect addressing mode. All flags are affected. Eg . INR M

DCX rp
This instruction decrement the content of the specified register pair by one. Operation : rp <------ rp 1 1 byte instruction Register addressing mode. All flagsd are affected. Eg . DCX B DCX H.

DCR M
This instruction decrements the content of memory location (address given by HL )by one. Operation : M<---- M - 1 1 byte instruction. Indirect addressing mode. All flags are affected. Eg . DCR M

LOGIC GROUP
These instructions perform the logical operation on the oprand. The various logical instructions are AND , OR , XOR , NOT etc. The instructions are ANA r ANA M XRA r XRA M XRI data (8 bit)

ORA r ORA M ORI data (8 bit) CMP r CMP M CPI data(8 bit) STC CMC CMA

ANAr
This instruction AND the contents of specified register with accumulator. Operation : A <---- A ^ r. 1 byte instruction. Register addressing mode. All flags are affected. ANA B ANA H

ANA M
This instruction AND the content of memory locationwith the content with acccumulator. Operation : A<---- A ^ M. 1 byte instruction. Indirect addressing mode. All flags are affected. Eg . ANA M

ANI data (8bit)

This instruction AND the 8 bit data immidiatly with accumulator. Operation : A <----- A ^ data (8 bit) 2 byte instruction Immidiate addressing mode. All flags are affected. Eg ANI 4D ANI 5B

XRA r
This instruction logically XOR the contents with the contents in accumulator. Operation : A <------ A xor r. 1 byte instruction. Register addressing mode. All flags are affected with CY and AC zero Eg . XRA B XRA H

XRA M
This instruction logically XOR the content of memory (address given by HL ) with the contents of accumulator. Operation : A <---- A xor M. 1 Byte instruction. Indirected addressing mode. All flags are affected with CY and AC zero. Eg . XRAM

XRI data (8 bit)

This instruction logically XORS the 8 bit data with contents of accumulator. Operation : A <----- A XOR data (8 bit) . 2 byte instruction. Immidiate addressing mode. All flags are affected with CY and AC zero. Eg .XRI D5 XRI 59

ORA r
This instruction logically OR the contents of register with the contents of accumulator. Operation : A <----- A U r. 1 byte instruction. Register addrssing mode. All flags are affected with CY and AC zero. Eg . ORA B ORA D

ORA M
this instruction logically or the content of memory (address given by hl)with the contents of accumulator. operation : A <---- A U M. 1 byte instruction. indirect addressing mode. all flags are affected with ACand CY zero. eg . ORA M

ORI data (8 bit)

This instruction logically or the 8 bit data with contents of accumulator. Operation : A <----- A U data (8 bit). 2 byte instruction. Immidiate addressing mode. All flags are affected with AC and CY zero Eg . ORI 4D ORI C6

CMP r
This instruction compares the contents of register with the contents of accumulator .result is not stored anywhere only flags are affected.the comparison is carried by substraction process. Operation : A- r. 1 byte instruction. Register addressing mode. Flags are affected as 1. if A=r then Z=1 2.If A> r then CY=0 and Z=0 3.If A< r then CY =1 and Z=0

CMP M
Compare the contents of A with memory. Operation : A- M 1 byte instruction Indirect addressing mode Flags affected as : If A< M Then CY= 1 Z=0 If A > M Then CY = O Z=O If A= M Then CY= O Z= 1

CPI data (8)

This instruction compares the 8 bit data with A Operation : A data 2 byte instruction. Immidiate addressing mode. Flags affected as if A< data then CY=1 Z=0 If A > data then CY= 0 Z= 0 If A = data then CY= 0 Z=1