On Oct 13, 2011, at 6:26 PM, a.

pastoral wrote:4 BITS GRAY TO BINARY CONVERTER

ENTITY GRAY_BINARY IS PORT( G: IN STD_LOGIC_VECTOR(3 DOWNTO 0); B: INOUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END GRAY_BINARY; ARCHITECTURE BEHAVIORAL OF GRAY_BINARY IS BEGIN B(3)<= G(3); B(2)<= B(3) XOR G(2); B(1)<= B(2) XOR G(1); B(0)<= B(1) XOR G(0); END BEHAVIORAL; 1 TO 4 DE-MULTIPLEXER A demultiplexer is a circuit that receives information on a single line and transmits this information on one of 2 ^ N ouput lines.The selection of specific output lines is controlled by the value of N selection lines.The single input variable din as a path to all 4 outputs but the input information is directed to only one of the output lines.

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY DEMUX1_4 IS PORT ( D_IN: IN STD_LOGIC; SEL: IN STD_LOGIC_VECTOR (1 DOWNTO 0); D_OUT: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)); END DEMUX1_4; ARCHITECTURE DEMUX1_4_ARCH OF DEMUX1_4 IS BEGIN PROCESS(D_IN,SEL) BEGIN D_OUT<="0000"; CASE SEL IS WHEN "00" => D_OUT(0)<=D_IN; WHEN "01" => D_OUT(1)<=D_IN; WHEN "10" => D_OUT(2)<=D_IN; WHEN OTHERS => D_OUT(3)<=D_IN; END CASE; END PROCESS; END DEMUX1_4_ARCH; VERILOG CODE FOR 1 TO 4 DEMUX module demux(din, s, dout); input din; input [1:0] s; output [3:0] dout; reg [3:0] dout; always @ (din or s) case(s) 2b00: dout(0)=din; 2b01: dout(1)=din; 2b10: dout(2)=din; 2b11: dout(3)=din;

endcase endmodule

H) N-BIT COMPARATOR Comparator is a special combinational circuit designed primarily to compare the relative magnitude of 2 binary numbers.It receives 2 N bit numbers A and B as inputs and the outputs are A>B,A=B and A

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY COMPARATOR IS GENERIC (N: INTEGER := 3); PORT( A,B: IN STD_LOGIC_VECTOR(N DOWNTO 0); ALB,AGB,AEB: OUT STD_LOGIC); END COMPARATOR; ARCHITECTURE COMPARATOR_ARC OF COMPARATOR IS BEGIN PROCESS(A,B) BEGIN ALB<=0; AGB<=0; AEB<=0; IF A=B THEN AEB<=1; ELSIF A>B THEN AGB<=1; ELSE ALB<=1; END IF; END PROCESS; END COMPARATOR_ARC;

VERILOG CODE FOR 4 BIT COMPARATOR module compare(a, b, aeqb, agtb, altb) input [3:0] a, b; output aeqb, agtb, altb; reg aeqb, agtb, altb; always @ (a or b) if (a=b) aeqb=1b1; else if (a>b) agtb=1b1; else (a endmodule

3. WRITE A HDL CODE TO DESCRIBE THE FUNCTIONS OF A FULL ADDER USING THREE MODELING STYLES. A) STRUCTURAL MODELING VHDL CODE FOR THE IMPLEMENTATION OF HALF ADDER ENTITY HALFADDER IS PORT ( A, B : IN STD_LOGIC; S, C : OUT STD_LOGIC); --SUM& CARRY END HALFADDER; ARCHITECTURE BEHAVIORAL OF HALFADDER IS BEGIN S <= A XOR B; C<= A AND B; END BEHAVIORAL; VHDL CODE FOR FULL ADDER USING COMPONENT INSTANTIATION METHOD. ENTITY FULLADDER IS PORT ( AIN : IN STD_LOGIC; BIN : IN STD_LOGIC; CIN : IN STD_LOGIC; COUT : OUT STD_LOGIC; SUM : OUT STD_LOGIC); END FULLADDER; ARCHITECTURE BEHAVIORAL OF FULLADDER IS COMPONENT HALFADDER PORT ( A : IN STD_LOGIC; B: IN STD_LOGIC; S: OUT STD_LOGIC; C: OUT STD_LOGIC); END COMPONENT; SIGNAL TEMP1,TEMP2, TEMP3: STD_LOGIC; BEGIN L1: HALFADDER PORT MAP( AIN, BIN,TEMP1,TEMP2); L2: HALFADDER PORT MAP( TEMP1,CIN,SUM,TEMP3); COUT <= TEMP2 OR TEMP3; END BEHAVIORAL; B) DATAFLOW MODELING ARCHITECTURE DATAFLOW OF FULLADDER IS BEGIN SUM<= AIN XOR BIN XOR CIN; COUT<= (AIN AND BIN) OR (BIN AND CIN) OR (CIN AND AIN); END DATAFLOW; C) BEHAVIORAL MODELING ARCHITECTURE BEHAVIOR OF FULLADDER IS BEGIN PROCESS(AIN,BIN,CIN) BEGIN SUM<= AIN XOR BIN XOR CIN; COUT<= (AIN AND BIN) OR (BIN AND CIN) OR (CIN AND AIN); END PROCESS; END BEHAVIOR;

4. Write a model for 32 - bit or 4-bit ALU using the schematic diagram shown below (example only)

y y y

ALU should use combinational logic to calculate an output based on the fout bit op-code input. ALU should pass the result to the out bus when enable line is high and tri-state the out bus when the enable line is low. ALU should decode the 4 bit op-code according to the given in example below.

Opcode 1 2 3 4 5 6 7 8

ALU Operation A+B AB A Compliment A*B A AND B A OR B A NAND B A XOR B

-- THIS ALU IS A COMBINATIONAL LOGIC TO CALCULATE AN OUTPUT BASED ON THE THREE BIT OP-CODE INPUT. -- ALU PASSES THE RESULT TO THE OUTPUT BUS WHEN ENABLE LINE IS LOW.

ENTITY ALU IS PORT ( A : IN STD_LOGIC_VECTOR(3 DOWNTO 0); B : IN STD_LOGIC_VECTOR(3 DOWNTO 0); OPCODE : IN STD_LOGIC_VECTOR(2 DOWNTO 0); ENB : IN STD_LOGIC; OUTPUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); OUTPUT1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END ALU; ARCHITECTURE BEHAVIORAL OF ALU IS BEGIN PROCESS(A,B,OPCODE,ENB) BEGIN IF ENB= '1' THEN CASE OPCODE IS WHEN "000" => OUTPUT<= A+B; WHEN "001" => OUTPUT<= A-B; WHEN "010" => OUTPUT<= NOT A; WHEN "011" => OUTPUT1<= A*B; WHEN "100" => OUTPUT<= A AND B; WHEN "101" => OUTPUT<= A OR B; WHEN "110" => OUTPUT<= A NAND B; WHEN OTHERS =>OUTPUT<= A XOR B; END CASE;

ELSE OUTPUT <= (OTHERS =>'Z'); END IF; END PROCESS; END BEHAVIORAL;

SEQUENTIAL CIRCUITS 5. DEVELOP THE HDL CODE FOR THE FOLLOWING FLIP-FLOPS. SR flip-flop: A SR flip - flop is the simplest possible memory element. The SR flip flop has two inputs Set and Reset. The SR flip-flop is a basic building block for other flip-flops. D flip-flop: This is a flip - flop with a delay (D) equal to exactly equal to one cycle of the clock. The defect with SR FF is the indeterminate output when the data inputs at S and R are 1. In order to avoid this the input to R is through an inverter from S so that the input to R is always the complement of S and never same. The S input is redesignated as D. JK flip-flop: The JK flip flop is called a universal flip flop because the other flip flops like D, SR, T can be derived from it. The racing or race around condition takes place in a JK FF when J=1 and K=1 and clock=1. T flip-flop: T stands for toggling. It is obtained from JK FF by tying both the inputs J and K.

A) SR FLIP-FLOP ENTITY SRFF IS PORT ( S,R,CLK: IN BIT; Q: BUFFER STD_LOGIC ):=0; END SRFF; ARCHITECTURE S_R_FF_ARCH OF SRFF IS BEGIN PROCESS(CLK) BEGIN IF CLK='1' AND CLK'EVENT THEN IF(S='0' AND R='0')THEN Q<=Q; ELSIF(S='0' AND R='1')THEN Q<='0'; ELSIF(S='1' AND R='0')THEN Q<='1'; ELSIF (S='1' AND R='1')THEN Q<='Z'; END IF; END IF; END PROCESS; END S_R_FF_ARCH; B) D FLIP-FLOP LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY DFF IS PORT (CLK: IN STD_LOGIC; D: IN STD_LOGIC; Q: OUT STD_LOGIC);

END DFF; ARCHITECTURE D_FF_ARCH OF DFF IS BEGIN PROCESS(CLK) BEGIN IF(CLK'EVENT AND CLK='1')THEN Q<=D; END IF; END PROCESS; END D_FF_ARCH;

C) T FLIP-FLOP ENTITY TF IS PORT ( CLK,RST,T : IN STD_LOGIC; Q:OUT STD_LOGIC; QB:OUT STD_LOGIC); END TF; ARCHITECTURE BEHAVIORAL OF TF IS SIGNAL TEMP:STD_LOGIC; BEGIN PROCESS(CLK,RST) BEGIN IF(RST='1')THEN TEMP<='0'; ELSIF(CLK='1' AND CLK'EVENT)THEN IF(T='1')THEN TEMP<=NOT TEMP; END IF; END IF; END PROCESS; Q<=TEMP; QB<=NOT TEMP; END BEHAVIORAL;

D) JK FLIP-FLOP ENTITY JKFF IS PORT ( CLK,RST,J,K : IN STD_LOGIC; Q: OUT STD_LOGIC; QB : OUT STD_LOGIC); END JKFF; ARCHITECTURE BEHAVIORAL OF JKFF IS SIGNAL TEMP :STD_LOGIC; BEGIN PROCESS(CLK,RST) VARIABLE JK:STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN IF(RST='1')THEN FF<='0'; ELSIF(CLK='1' AND CLK'EVENT)THEN JK:=J & K; CASE JK IS WHEN "01"=>TEMP<='0'; WHEN "10"=>TEMP<='1'; WHEN "11"=>TEMP<=NOT TEMP; WHEN OTHERS=>TEMP<=TEMP; END CASE; END IF; END PROCESS; Q<=TEMP; QB<=NOT TEMP; END BEHAVIORAL;

6. DESIGN 4-BIT BINARY, BCD COUNTERS AND ANY SEQUENCE COUNTERS. A) 4-BIT BINARY UP COUNTER ENTITY BINCOUNT IS PORT ( CLK,RST : IN STD_LOGIC; BINCOUNT: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END BINCOUNT; ARCHITECTURE BEHAVIORAL OF BINCOUNT IS SIGNAL BINCOUNT1:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN PROCESS(CLK,RST) BEGIN IF(RST='1')THEN BINCOUNT1<=(OTHERS=>'0'); ELSIF(CLK='1' AND CLK'EVENT)THEN IF(BINCOUNT1="1111")THEN BINCOUNT1<="0000"; ELSE BINCOUNT1<=BINCOUNT1+1; END IF; END IF; END PROCESS; BINCOUNT<=BINCOUNT1; END BEHAVIORAL;

B) 4-BIT BINARY DOWN COUNTER ENTITY BINDOWN IS PORT ( CLK,RST : IN STD_LOGIC; BINCOUNT: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END BINDOWN; ARCHITECTURE BEHAVIORAL OF BINDOWN IS SIGNAL BINCOUNT1:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN PROCESS(CLK,RST) BEGIN IF(RST='1')THEN BINCOUNT1<=(OTHERS=>'0'); ELSIF(CLK='1' AND CLK'EVENT)THEN IF(BINCOUNT1="0000")THEN BINCOUNT1<="1111"; ELSE BINCOUNT1<=BINCOUNT1-1; END IF; END IF; END PROCESS; BINCOUNT<=BINCOUNT1; END BEHAVIORAL;

C) 4-BIT BCD UP COUNTER ENTITY BCDCOUNT IS PORT ( CLK,RST : IN STD_LOGIC; BCDCOUNT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END BCDCOUNT; ARCHITECTURE BEHAVIORAL OF BCDCOUNT IS SIGNAL BCDCOUNT1:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN PROCESS(CLK,RST) BEGIN IF(RST='1')THEN BCDCOUNT1<=(OTHERS=>'0'); ELSIF(CLK='1' AND CLK'EVENT)THEN IF(BCDCOUNT1="1001")THEN BCDCOUNT1<="0000"; ELSE BCDCOUNT1<=BCDCOUNT1+1; END IF; END IF; END PROCESS; BCDCOUNT<=BCDCOUNT1; END BEHAVIORAL;

C) 4-BIT BCD DOWN COUNTER ENTITY BCDDOWN IS PORT ( CLK,RST : IN STD_LOGIC; BCDCOUNT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END BCDDOWN; ARCHITECTURE BEHAVIORAL OF BCDDOWN IS SIGNAL BCDCOUNT1:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN

PROCESS(CLK,RST) BEGIN IF(RST='1')THEN BCDCOUNT1<=(OTHERS=>'0'); ELSIF(CLK='1' AND CLK'EVENT)THEN IF(BCDCOUNT1="0000")THEN BCDCOUNT1<="1001"; ELSE BCDCOUNT1<=BCDCOUNT1-1; END IF; END IF; END PROCESS; BCDCOUNT<=BCDCOUNT1; END BEHAVIORAL;

INTERFACING PROGRAMS EXP1. INTERFACE SEVEN-SEGMENT LED TO DISPLAY BCD COUNT STARTING FROM 0 TO 9. THERE SHOULD BE A DELAY OF 1 SEC BETWEEN EACH COUNT.

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY SEG7 IS PORT ( CLK : IN STD_LOGIC; A: OUT STD_LOGIC; DOUT : OUT STD_LOGIC_VECTOR (0 TO 6)); END SEG7; ARCHITECTURE BEHAVIORAL OF SEG7 IS SIGNAL CLK_DIV:STD_LOGIC_VECTOR(22 DOWNTO 0); SIGNAL CLKD:STD_LOGIC; TYPE SEG7 IS ARRAY (0 TO 9)OF STD_LOGIC_VECTOR(6 DOWNTO 0); CONSTANT SEG_VALUE: SEG7:=("1111110","0110000","1101101", "1111001", "0110011","1011011","1011111", "1110000","1111111","1110011"); BEGIN PROCESS(CLK) BEGIN IF RISING_EDGE (CLK)THEN CLK_DIV<=CLK_DIV+'1'; END IF; CLKD<=CLK_DIV(21); END PROCESS; PROCESS(CLKD) VARIABLE Y: INTEGER RANGE 0 TO 9; BEGIN

IF RISING_EDGE(CLKD) THEN DOUT<=SEG_VALUE(Y); Y:=Y+1; IF Y>9 THEN Y:=0; END IF; END IF; END PROCESS; A<='1'; END BEHAVIORAL;

EXP2: VHDL CODE FOR STEPPER MOTOR TO CONTROL THE SPEED AND DIRECTION. ENTITY STEPPER_MOTOR IS PORT ( D_OUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); ENB : IN STD_LOGIC; CLK : IN STD_LOGIC); END STEPPER_MOTOR; ARCHITECTURE BEHAVIORAL OF STEPPER_MOTOR IS SIGNAL CLK_DIV:STD_LOGIC_VECTOR(12 DOWNTO 0); SIGNAL CLKD:STD_LOGIC; SIGNAL STEP:STD_LOGIC_VECTOR(3 DOWNTO 0):="1000"; BEGIN PROCESS(CLK) BEGIN IF RISING_EDGE(CLK) THEN CLK_DIV<=CLK_DIV+1; END IF; CLKD<=CLK_DIV(12); END PROCESS; PROCESS(CLKD) BEGIN IF RISING_EDGE(CLKD) THEN IF ENB='1' THEN

STEP<=STEP(0) & STEP(3 DOWNTO 1); ELSIF ENB='0' THEN STEP<=STEP(2 DOWNTO 0) & STEP(3); END IF; END IF; END PROCESS; D_OUT<=STEP; END BEHAVIORAL;

EXP3: INTERFACE LCD 16 X 2 TO DISPLAY FOLLOWING MESSAGE SHASHI. LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY LCD_INTERFACE IS PORT ( DATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); REG_SEL : OUT STD_LOGIC; RD_WR : OUT STD_LOGIC; EN : OUT STD_LOGIC; CLK : IN STD_LOGIC); END LCD_INTERFACE; ARCHITECTURE BEHAVIORAL OF LCD_INTERFACE IS SIGNAL CLK_DIV:STD_LOGIC_VECTOR(21 DOWNTO 0); SIGNAL CLKD:STD_LOGIC; BEGIN PROCESS(CLK) BEGIN IF RISING_EDGE(CLK) THEN CLK_DIV<=CLK_DIV+1; END IF; CLKD<=CLK_DIV(21); EN<=CLK_DIV(21); END PROCESS; PROCESS(CLKD) VARIABLE A: INTEGER RANGE 0 TO 6; TYPE LCD_TYPE IS ARRAY(NATURAL RANGE<>) OF STD_LOGIC_VECTOR(7 DOWNTO 0); CONSTANT LCD_DATA: LCD_TYPE(0 TO 6):=("00111000","00000001","00001110","00000010", "01000111","01001100","01011111",01000010,01000001,01001100);

BEGIN RD_WR<='0'; IF RISING_EDGE(CLKD) THEN IF A<4 THEN REG_SEL<='0'; DATA<=LCD_DATA(A); ELSE REG_SEL<='1'; DATA<=LCD_DATA(A); END IF; A:=A+1; END IF;

END PROCESS; END BEHAVIORAL;

EXP4. INTERFACE KEYPAD AND SEVEN-SEGMENT DISPLAY, WHEN THE KEY IS PRESSED THE CORRESPONDING KEY NUMBER SHOULD BE DISPLAYED USING FPGA KIT. LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY KEYPAD IS PORT ( KEYROW : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); KEYCOL :IN STD_LOGIC_VECTOR(3 DOWNTO 0); A:OUT STD_LOGIC; CLK : IN STD_LOGIC; LED_OUT : OUT STD_LOGIC_VECTOR(0 TO 6)); END KEYPAD; ARCHITECTURE BEHAVIORAL OF KEYPAD IS SIGNAL KEY_VAL:INTEGER RANGE 0 TO 15; SIGNAL KEY_HIT:STD_LOGIC; SIGNAL KEY_SCAN:STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL CLK_DIV:STD_LOGIC_VECTOR(6 DOWNTO 0); SIGNAL CLKD:STD_LOGIC; BEGIN PROCESS(KEYCOL) BEGIN CASE KEYCOL IS WHEN "1110"=>KEY_HIT<='1'; WHEN "1101"=>KEY_HIT<='1'; WHEN "1011"=>KEY_HIT<='1'; WHEN "0111"=>KEY_HIT<='1'; WHEN OTHERS=>KEY_HIT<='0'; END CASE; END PROCESS; PROCESS(KEY_HIT)

BEGIN IF RISING_EDGE(KEY_HIT) THEN IF (KEY_SCAN="1110" AND KEYCOL="1110") THEN KEY_VAL<=0; ELSIF ELSIF ELSIF ELSIF ELSIF ELSIF ELSIF ELSIF ELSIF ELSIF ELSIF ELSIF ELSIF ELSIF ELSIF (KEY_SCAN="1110" AND KEYCOL="1101") THEN KEY_VAL<=1; (KEY_SCAN="1110" AND KEYCOL="1011") THEN KEY_VAL<=2; (KEY_SCAN="1110" AND KEYCOL="0111") THEN KEY_VAL<=3; (KEY_SCAN="1101" AND KEYCOL="1110") THEN KEY_VAL<=4; (KEY_SCAN="1101" AND KEYCOL="1101") THEN KEY_VAL<=5; (KEY_SCAN="1101" AND KEYCOL="1011") THEN KEY_VAL<=6; (KEY_SCAN="1101" AND KEYCOL="0111") THEN KEY_VAL<=7; (KEY_SCAN="1011" AND KEYCOL="1110") THEN KEY_VAL<=8; (KEY_SCAN="1011" AND KEYCOL="1101") THEN KEY_VAL<=9; (KEY_SCAN="1011" AND KEYCOL="1011") THEN KEY_VAL<=10; (KEY_SCAN="1011" AND KEYCOL="0111") THEN KEY_VAL<=11; (KEY_SCAN="0111" AND KEYCOL="1110") THEN KEY_VAL<=12; (KEY_SCAN="0111" AND KEYCOL="1101") THEN KEY_VAL<=13; (KEY_SCAN="0111" AND KEYCOL="1011") THEN KEY_VAL<=14; (KEY_SCAN="0111" AND KEYCOL="0111") THEN KEY_VAL<=15;

END IF; END IF; END PROCESS; PROCESS(CLK) BEGIN IF RISING_EDGE(CLK) THEN CLK_DIV<=CLK_DIV+1; END IF; CLKD<=CLK_DIV(6); END PROCESS; PROCESS(CLKD) BEGIN IF RISING_EDGE(CLKD) THEN IF KEY_SCAN="1110" THEN KEY_SCAN<="1101"; ELSIF KEY_SCAN="1101" THEN KEY_SCAN<="1011"; ELSIF KEY_SCAN="1011" THEN KEY_SCAN<="0111"; ELSIF KEY_SCAN="0111" THEN KEY_SCAN<="1110"; ELSE KEY_SCAN<="1110"; END IF; END IF; KEYROW<=KEY_SCAN; END PROCESS; PROCESS(KEY_VAL) TYPE SEG7 IS ARRAY(0 TO 15) OF STD_LOGIC_VECTOR(6 DOWNTO 0); CONSTANT SEG_VAL:SEG7:=("1111110","0110000","1101101","1111001", "1111111","1110011","1110111","0011111", "1001110","0111101","1001111","1000111"); "0110011","1011011","1011111","1110000",

BEGIN LED_OUT<=SEG_VAL(KEY_VAL); END PROCESS; A<='1'; END BEHAVIORAL;

EXP5. VHDL CODE FOR ELEVATOR FUNCTIONS USING FPGA KIT. ENTITY ELEVATOR IS PORT ( KEYROW : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); KEYCOL :IN STD_LOGIC_VECTOR(3 DOWNTO 0); A:OUT STD_LOGIC; CLK : IN STD_LOGIC; LED_OUT : OUT STD_LOGIC_VECTOR(0 TO 6)); END ELEVATOR; ARCHITECTURE BEHAVIORAL OF ELEVATOR IS SIGNAL KEY_VAL,CUR_FLR:INTEGER RANGE 0 TO 15; SIGNAL KEY_HIT:STD_LOGIC; SIGNAL KEY_SCAN:STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL CLK_DIV:STD_LOGIC_VECTOR(22 DOWNTO 0); SIGNAL CLKD,FLR_CLK:STD_LOGIC; BEGIN PROCESS(KEYCOL) BEGIN CASE KEYCOL IS WHEN "1110"=>KEY_HIT<='1'; WHEN "1101"=>KEY_HIT<='1'; WHEN "1011"=>KEY_HIT<='1'; WHEN "0111"=>KEY_HIT<='1'; WHEN OTHERS=>KEY_HIT<='0'; END CASE; END PROCESS; PROCESS(KEY_HIT) BEGIN IF RISING_EDGE(KEY_HIT) THEN IF (KEY_SCAN="1110" AND KEYCOL="1110") THEN KEY_VAL<=0; ELSIF ELSIF ELSIF ELSIF ELSIF ELSIF ELSIF ELSIF ELSIF ELSIF ELSIF ELSIF ELSIF ELSIF ELSIF END IF; END IF; END PROCESS; PROCESS(CLK) BEGIN IF RISING_EDGE(CLK) THEN CLK_DIV<=CLK_DIV+1; END IF; CLKD<=CLK_DIV(6); FLR_CLK<=CLK_DIV(22); END PROCESS; (KEY_SCAN="1110" AND KEYCOL="1101") THEN KEY_VAL<=1; (KEY_SCAN="1110" AND KEYCOL="1011") THEN KEY_VAL<=2; (KEY_SCAN="1110" AND KEYCOL="0111") THEN KEY_VAL<=3; (KEY_SCAN="1101" AND KEYCOL="1110") THEN KEY_VAL<=4; (KEY_SCAN="1101" AND KEYCOL="1101") THEN KEY_VAL<=5; (KEY_SCAN="1101" AND KEYCOL="1011") THEN KEY_VAL<=6; (KEY_SCAN="1101" AND KEYCOL="0111") THEN KEY_VAL<=7; (KEY_SCAN="1011" AND KEYCOL="1110") THEN KEY_VAL<=8; (KEY_SCAN="1011" AND KEYCOL="1101") THEN KEY_VAL<=9; (KEY_SCAN="1011" AND KEYCOL="1011") THEN KEY_VAL<=10; (KEY_SCAN="1011" AND KEYCOL="0111") THEN KEY_VAL<=11; (KEY_SCAN="0111" AND KEYCOL="1110") THEN KEY_VAL<=12; (KEY_SCAN="0111" AND KEYCOL="1101") THEN KEY_VAL<=13; (KEY_SCAN="0111" AND KEYCOL="1011") THEN KEY_VAL<=14; (KEY_SCAN="0111" AND KEYCOL="0111") THEN KEY_VAL<=15;

PROCESS(CLKD) BEGIN IF RISING_EDGE(CLKD) THEN IF KEY_SCAN="1110" THEN KEY_SCAN<="1101"; ELSIF KEY_SCAN="1101" THEN KEY_SCAN<="1011"; ELSIF KEY_SCAN="1011" THEN KEY_SCAN<="0111"; ELSIF KEY_SCAN="0111" THEN KEY_SCAN<="1110"; ELSE KEY_SCAN<="1110"; END IF; END IF; KEYROW<=KEY_SCAN; END PROCESS; PROCESS(FLR_CLK) BEGIN IF RISING_EDGE(FLR_CLK) THEN IF(NOT(KEY_VAL=CUR_FLR)) THEN IF(KEY_VAL>CUR_FLR) THEN CUR_FLR<=CUR_FLR+1; ELSE CUR_FLR<=CUR_FLR-1; END IF; END IF; END IF; END PROCESS; PROCESS(KEY_VAL) TYPE SEG7 IS ARRAY(0 TO 15) OF STD_LOGIC_VECTOR(6 DOWNTO 0); CONSTANT SEG_VAL:SEG7:=("1111110","0110000","1101101","1111001", "0110011","1011011","1011111","1110000", "1111111","1110011","1110111","0011111", "1001110","0111101","1001111","1000111"); BEGIN LED_OUT<=SEG_VAL(CUR_FLR); A<='1'; END PROCESS; END BEHAVIORAL;