Al-albayt University

Advanced Computer Architecture

Asynchronous Data Transfer

Presented by: Motasem Smadi
Fall 2011

Asynchronous Data Transfer

There are two types of data transfer :
Synchronous Data Transfer
All data transfers occur simultaneously during the occurrence of a clock pulse Registers in the interface share a common clock with CPU registers

Asynchronous Data Transfer

Internal timing in each unit (CPU and Interface) is independent Each unit uses its own private clock for internal registers

Asynchronous Data Transfer Methods

There are two asynchronous data transfer methods
Strobe control
A strobe control is supplied by one unit to indicate the other unit when the transfer has to occur

Handshaking
A control signal is accompanied with each data being transmitted to indicate the presence of data The receiving unit responds with another control signal to acknowledge receipt of the data

STROBE CONTROL
Employs a single control line to time each transfer. The strobe may be activated by either the source or the destination unit.
Da ta b us S o urc e unit S tro b e (a ) Blo c k d ia g ra m De s tina tio n unit S o urc e unit Da ta b us S tro b e (a ) Blo c k d ia g ra m De s tina tio n unit

Da ta

Va lid d a ta

Da ta

Va lid d a ta

S tro b e (b ) Tim ing d ia g ra m

S tro b e (b ) Tim ing d ia g ra m

1- Source-initiated strobe

2- Destination-initiated strobe

Disadvantage of strobe method

Strobe methods
Source-Initiated The source unit that initiates the transfer has no way of knowing whether the destination unit has actually received data Destination-Initiated The destination unit that initiates the transfer no way of knowing whether the source has actually placed the data on the bus

To solve this problem, the HANDSHAKE method introduces a second control signal to provide a Reply to the unit that initiates the transfer

Handshake: 1- Source-initiated
Da ta b us S o urc e un it Da ta va lid Da ta a c c e p te d (a ) Blo c k d ia g ra m De s tin a tio n un it

Allows arbitrary delays from

one state to the next unit to Permits each transferrespond at its own data rate

Da ta

Va lid d a ta

The rate of transfer is unit determined by the slower

Da ta va lid

Da ta a c c e p te d (b ) Tim ing d ia g ra m

S o urc e un it Pla c e d a ta o n b us Ena b le d a ta va lid .

De s tin a tio n unit

Ac c e p t d a ta fro m b u s Ena b le d a ta a c c e p te d

Dis a b le d a ta va lid In va lid a te d a ta o n b us

Dis a b le d a ta a c c e p te d Re a d y to a c c e p t d a ta (in itia l s ta te ) (c ) S e q ue n c e o f e ve nts

Handshake: 2- Destination-initiated
Da ta b us

a high  Handshaking providesreliability degree of flexibility and because the successful completion of a data transfer relies on active participation by both units

S o urc e unit

Da ta va lid Re a d y fo r d a ta (a ) Blo c k d ia g ra m

De s tina tio n unit

Re a d y fo r d a ta

one unit is faulty,  If not be completed .data transfer will

Da ta va lid

Can be detected by means of a timeout mechanism.

: If  Timeout not the return handshake signal does respond within a given time period, the unit assumes that an error has occurred

Va lid d a ta Da ta b us (b ) Timing d ia g ra m

S o urc e unit

De s tina tio n unit Re a d y to a c c e p t d a ta . Ena b le re a d y fo r d a ta

Pla c e d a ta o n b us Ena b le d a ta va lid .

Dis a b le d a ta va lid Inva lid a te d a ta o n b us (initia l s ta te )

Ac c e p t d a ta fro m b us Dis a b le re d a y fo r d a ta

(c ) S e q ue nc e o f e ve nts

ASYNCHRONOUS SERIAL TRANSFER

Four Different Types of Transfer :- Asynchronous serial transfer Synchronous serial transfer Asynchronous parallel transfer Synchronous parallel transfer

Asynchronous Serial Transfer

Employs special bits which are inserted at both ends of the character code Each character consists of three parts; Start bit; Data bits; Stop bits.
1 Start 1 0 0 0 1 0 1 Stop bits

Character bits

A character can be detected by the receiver from the knowledge of 4 rules; - When data are not being sent, the line is kept in the 1-state (idle state) - The initiation of a character transmission is detected by a Start Bit , which is always a 0 - The character bits always follow the Start Bit - After the last character , a Stop Bit is detected when the line returns to the 1-state for at least 1 bit time The receiver knows in advance the transfer rate of the bits and the number of information bits to expect

UNIVERSAL ASYNCHRONOUS RECEIVER-TRANSMITTER - UART A typical asynchronous communication interface available as an IC

Transmitter Register

- Accepts a data byte(from CPU) through the data bus - Transferred to a shift register for serial transmission Receiver - Receives serial information into another shift register - Complete data byte is sent to the receiver register Status Register Bits - Used for I/O flags and for recording errors Control Register Bits - Define baud rate, no. of bits in each character, whether to generate and check parity, and no. of stop bits

References
 Mano. M. Morris, Computer System Architecture/ M.
Morris Mano-- 3rd Edition.