UNIT 1:

Switches, Lights, and Multiplexers

PART II

Design a 4 bits wide 2-to-1 Multiplexer

Code Verilog
module mux4b(m,x,y,s);
input [3:0]x,y;
input s;
output [3:0]m;
mux1b u0(m[0],x[0],y[0],s);
mux1b u1(m[1],x[1],y[1],s);
mux1b u2(m[2],x[2],y[2],s);
mux1b u3(m[3],x[3],y[3],s);
endmodule
module mux1b(m,x,y,s);
input s,x,y;
output m;
assign m=(x&~s)|(y&s);
endmodule

Code testbend
module mux4b_tb;
reg [3:0]x,y;
reg s;
wire [3:0]m;
mux4b u4(m,x,y,s);
initial begin
#5 x=4'b0000;
forever #5 x=x+1'b1;
end
initial begin
#5 y=4'b0000;
forever #5 y=y+1'b1;
end
initial begin
#5 s=1'b0;
forever #5 s=s+1'b1;
end
initial begin
$monitor ($time,"\t x=%b \t y=%b \t s=%b \t m=%b",x,y,s,m);

end
initial begin
#100 $stop;
end
endmodule
PART III

Design a 3-to-1 Mutiplexer:

s1
s0
u
v
w

00
01

10

Code Verilog
module mux3to1(m,x,y,z,s);
input
x,y,z;
input
[1:0]s;
output m;
reg
m;
always@(*) begin
case (s)
2'b00: m=x;
2'b01: m=y;
2'b10: m=z;
2'b11: m=z;
endcase
end
endmodule
module mux3to1_2b(m,x,y,z,s);
input
[1:0]x,y,z,s;
output [1:0]m;
mux3to1 u0(m[0],x[0],y[0],z[0],s);
mux3to1 u1(m[1],x[1],y[1],z[1],s);
endmodule

Code testbend
module mux3to1_2b_tb;
reg
[1:0]x,y,z,s;
wire [1:0]m;
mux3to1_2b u4(m,x,y,z,s);
initial begin
x=2'b00;

forever #5 x=x+1'b1;
end
initial begin
y=2'b01;
forever #5 y=y+1'b1;
end
initial begin
z=2'b10;
forever #5 z=z+1'b1;
end
initial begin
s=2'b00;
forever #5 s=x+1'b1;
end
initial begin
$monitor ($time,"\t X=%b\tY=%b\tZ=%b\tS=%b\tM=%b",x,y,z,s,m);
#150 $stop;
end
endmodule
PART IV

Design a seven-segment decoder.

Display d, E, 1 and blank characters on

7-segment display.

Code Verilog
module dec7seg(s,c);
input
[1:0]c;
output [6:0]s;
reg
[6:0]s;
always@(*) begin
case (c)
2'b00: s=7'b0100001;
2'b01: s=7'b0000110;
2'b10: s=7'b1001111;
2'b11: s=7'b1111111;
default: s=7'bxxxxxxx;
endcase
end

endmodule

Code testbend
module dec7seg_tb;
reg
[1:0]c;
wire [6:0]s;
dec7seg u0(s,c);
initial begin
c=2'b00;
forever #10 c=c+1'b1;
end
initial begin
$monitor ($time,"\tC=%b\tS=%b",c,s);
#50 $stop;
end
endmodule
PART V
Design a mux and 7-segment decoder that can be display dE1 word on three 7-segment
(HEX2, HEX1,HEX0) display and it can be able to rotate this word in a circular fashion.

Code Verilog
// Decoder 7 segment
module dec7seg(s,c);
input
[1:0]c;
output [6:0]s;
reg
[6:0]s;
always@(*) begin
case (c)
2'b00: s=7'b0100001;
2'b01: s=7'b0000110;
2'b10: s=7'b1001111;
2'b11: s=7'b1111111;
default: s=7'bxxxxxxx;

endcase
end
endmodule
// 3 inputs 2 bits multiplexer
module mux3to1(m,x,y,z,s);
input
x,y,z;
input
[1:0]s;
output m;
reg
m;
always@(*) begin
case (s)
2'b00: m=x;
2'b01: m=y;
2'b10: m=z;
2'b11: m=z;
endcase
end
endmodule
module mux3to1_2b(m,x,y,z,s);
input
[1:0]x,y,z,s;
output [1:0]m;
mux3to1 u9(m[0],x[0],y[0],z[0],s);
mux3to1 u10(m[1],x[1],y[1],z[1],s);
endmodule
// Mux and 7 segment decoder
module mux3seg7(h0,h1,h2,sw01,sw23,sw45,sw89);
input
[1:0]sw01,sw23,sw45,sw89;
output [6:0]h0,h1,h2;
wire
[1:0]m0,m1,m2;
mux3to1_2b u0(m0,sw01,sw23,sw45,sw89);
mux3to1_2b u1(m1,sw45,sw01,sw23,sw89);
mux3to1_2b u2(m2,sw23,sw45,sw01,sw89);
dec7seg
u4(h0,m0);
dec7seg
u5(h1,m1);
dec7seg
u6(h2,m2);
endmodule

Code testbend
module mux3seg7_tb;
reg
[1:0]sw01,sw23,sw45,sw89;
wire
[6:0]h0,h1,h2;
mux3seg7
u11(h0,h1,h2,sw01,sw23,sw45,sw89);
initial begin
sw01=2'b10;
sw23=2'b01;
sw45=2'b00;
end
initial begin
sw89=2'b00;
forever #10 sw89=sw89+1'b1;

end
initial begin
$monitor ($time," \t SW01=%b SW23=%b SW45=%b SW89=%b \n \t\t\t H0=%b H1=
%b H2=%b",sw01,sw23,sw45,sw89,h0,h1,h2);
#200 $stop;
end
endmodule

UNIT 2:
NUMBERS AND DISPLAYS

Code Verilog
// Full Adder 4 bits
module fa1b(a,b,ci,s,co);
input
a,b,ci;
output s,co;
assign s=a^b^ci;
assign co=(a&b&~ci)|(a&ci);
endmodule
module fa4b(a,b,ci,s,co);
input
[3:0]a,b;
input
ci;
output [3:0]s;
output co;
wire
co1,co2,co3;
fa1b fa0(a[0],b[0],ci,s[0],co1);
fa1b fa1(a[1],b[1],co1,s[1],co2);
fa1b fa2(a[2],b[2],co2,s[2],co3);
fa1b fa3(a[3],b[3],co3,s[3],co);
endmodule
// Binary to LED 7 segment
module bcd2seg2(v,h1,h0);
input
[3:0]v;
output [6:0]h1,h0;
reg
[6:0]h1,h0;

wire
[3:0]t;
assign t=v-4'b1010;
always@(v)
if (v<4'b1010) begin
h1=7'b1111111;
case(v)
4'b0000: h0=7'b1000000; // 0
4'b0001: h0=7'b1111001; // 1
4'b0010: h0=7'b0100100; // 2
4'b0011: h0=7'b0110000; // 3
4'b0100: h0=7'b0011001; // 4
4'b0101: h0=7'b0010010; // 5
4'b0110: h0=7'b0000010; // 6
4'b0111: h0=7'b1111000; // 7
4'b1000: h0=7'b0000000; // 8
4'b1001: h0=7'b0010000; // 9
default h0=7'bxxxxxxx;
endcase
end
else begin
h1=7'b1111001;
case(t)
4'b0000: h0=7'b1000000; // 10
4'b0001: h0=7'b1111001; // 11
4'b0010: h0=7'b0100100; // 12
4'b0011: h0=7'b0110000; // 13
4'b0100: h0=7'b0011001; // 14
4'b0101: h0=7'b0010010; // 15
4'b0110: h0=7'b0000010; // x16
default h0=7'bxxxxxxx;
endcase
end
endmodule
// Mux 2 to 1 7 bits
module mux1b(s,x,y,m);
input
s,x,y;
output m;
assign m=(~s&x)|(s&y);
endmodule
module mux7b(s,x,y,m);
input
[6:0]x,y;
input
s;
output [6:0]m;
mux1b
m0(s,x[6],y[6],m[6]);
mux1b
m1(s,x[5],y[5],m[5]);
mux1b
m2(s,x[4],y[4],m[4]);
mux1b
m3(s,x[3],y[3],m[3]);
mux1b
m4(s,x[2],y[2],m[2]);
mux1b
m5(s,x[1],y[1],m[1]);
mux1b
m6(s,x[0],y[0],m[0]);

endmodule
//Bin to DEC 2 bits input
module bin2dec(i,o);
input
[1:0]i;
output reg
[6:0]o;
always@(i)
case(i)
2'b00: o=7'b0000010;
2'b01: o=7'b1111000;
2'b10: o=7'b0000000;
2'b11: o=7'b0011000;
endcase
endmodule
// Adder 2 BCD numbers
module add2bcd(ci,a,b,h1,h0);
input
[3:0]a,b;
input
ci;
output [6:0]h1,h0;
wire
[3:0]s;
wire
co;
wire
[6:0]m0,m1,m2;
wire
[6:0]m3;
assign m3=7'b1111001;
fa4b
u0(a,b,ci,s,co);
bin2dec u1(s[1:0],m2);
bcd2seg2
u2(s,m1,m0);
mux7b
u3(co,m0,m2,h0);
mux7b
u4(co,m1,m3,h1);
endmodule
// Adder 2 BCD numbers 9+9+1=19
module add2bcd2(ci,a,b,h1,h0);
input
[3:0]a,b;
input
ci;
output reg
[6:0]h1,h0;
wire
[6:0]t1,t0;
add2bcd
u5(ci,a,b,t1,t0);
always@(*) begin
if
((a>4'b1001)|(b>4'b1001)) begin
h0=7'b1111110;
h1=7'b1111110;
end
else begin
h1=t1;
h0=t0;
end
end
endmodule

Code testbend
module add2bcd2_tb;
reg
[3:0]a,b;
reg
ci;
wire [6:0]h1,h0;
add2bcd2
tb(ci,a,b,h1,h0);
initial begin
a=4'b0000;
forever #5
a=a+1'b1;
end
initial begin
b=4'b1010;
forever #5 b=b+1'b1;
end
initial begin
ci=1'b0;
forever #20 ci=~ci;
end
initial $monitor ($time,"\t ci=%b \t a=%b \t b=%b \t h1=%b \t h0=%b \n",ci,a,b,h1,h0);
initial #300 $stop;
endmodule
UNIT 3:
LATCHES, FLIP-FLOPS, AND REGISTERS
PART I - RS LATCH

Code Verilog
module rsl(q,clk,r,s);
input
output q;
wire
and
and
nor
nor
assign q=qa;
endmodule

Code testbend
module rsl_tb;

clk,r,s;
rg,sg,qa,qb;
u0(rg,r,clk);
u1(sg,s,clk);
u2(qa,rg,qb);
u3(qb,sg,qa);

reg
clk,r,s;
wire
q;
rsl
tb(q,clk,r,s);
initial begin
clk=0;r=0;s=0;
#5 clk=1;r=0;s=0;
#5 clk=0;r=0;s=1;
#5 clk=1;r=0;s=1;
#5 clk=0;r=1;s=0;
#5 clk=1;r=1;s=0;
#5 clk=0;r=1;s=1;
#5 clk=1;r=1;s=1;
#5 clk=0;r=0;s=0;
end
initial $monitor($time," RS=%b%b CLK=%b Q=%b",r,s,clk,q);
endmodule
PART II - D LATCH

Code Verilog
module D_latch(q,clk,d);
input
clk,d;
output q;
wire
sg,rg,qa,qb,r;
not
u0(r,d);
nand
u1(sg,d,clk);
nand
u2(rg,r,clk);
nand
u3(qa,sg,qb);
nand
u4(qb,rg,qa);
assign q=qa;
endmodule

Code testbend
module D_latch_tb;
reg
clk,d;
wire
q;
D_latch tb(q,clk,d);
initial begin
clk=0;
forever #5 clk=~clk;

end
initial begin
d=0;
forever #10 d=~d;
end
initial begin
$monitor($time," CLK=%b D=%b Q=%b",clk,d,q);
#100 $stop;
end
endmodule
PART III
MASTER-SLAVE D FLIP-FLOP

Code Verilog
module D_ff(q,qb,clk,d);
input
clk,d;
output q,qb;
wire
qm,qs,c;
not
n0(c,clk);
D_latch m(qm,c,d);
D_latch s(qs,clk,qm);
not
n1(qb,qs);
assign q=qs;
endmodule
module D_latch(q,clk,d);
input
clk,d;
output q;
wire
sg,rg,qa,qb,r;
not
u0(r,d);
nand
u1(sg,d,clk);
nand
u2(rg,r,clk);
nand
u3(qa,sg,qb);
nand
u4(qb,rg,qa);
assign q=qa;
endmodule

Code testbend
module D_ff_tb;
reg
clk,d;
wire
q,qb;
D_ff
tb(q,qb,clk,d);
initial begin
clk=0;
forever #5 clk=~clk;

end
initial begin
d=0;
forever #10 d=~d;
end
initial begin
$monitor($time," CLK=%b D=%b Q=%b Qb=%b",clk,d,q,qb);
#100 $stop;
end
endmodule

PART IV
D LATCH - FLIPLOP

Code Verilog
module D_l(qa,d,clk);
input
d,clk;
output reg
qa;
always@(*)
if(clk)
qa=d;
endmodule
module D_ff1(qb,d,clk);
input
d,clk;
output reg
qb;
always@(posedge clk)
qb<=d;
endmodule
module D_ff2(qc,d,clk);
input
d,clk;
output reg
qc;
always@(negedge clk)

qc<=d;
endmodule
module D_lf(qa,qb,qc,qab,qbb,qcb,d,clk);
input
d,clk;
output qa,qb,qc,qab,qbb,qcb;
wire
q1,q2,q3;
D_l
u0(q1,d,clk);
D_ff1
u1(q2,d,clk);
D_ff2
u2(q3,d,clk);
assign qa=q1;
assign qb=q2;
assign qc=q3;
not
u3(qab,q1);
not
u4(qbb,q2);
not
u5(qcb,q3);
endmodule

Code testbend
module D_lff_tb;
reg
clk,d;
wire
[2:0]q1,q2;
D_lff
tb(q1,q2,d,clk);
initial begin
clk=0;
forever #20 clk=~clk;
end
initial begin
d=0;
forever #4 d=~d;
end
initial begin
$monitor($time," CLK=%b D=%b Qa=%b Qb=%b Qc=%b",clk,d,q1[0],q1[1],q1[2]);
#200 $stop;
end
endmodule

PART V REGISTER

Code Verilog
module bin4seg1(b,h);
input
[3:0]b;
output reg
[6:0]h;
always@(*) begin
case(b)
4'b0000: h=7'b1000000;
4'b0001: h=7'b1111001;
4'b0010: h=7'b0100100;
4'b0011: h=7'b0110000;
4'b0100: h=7'b0011001;
4'b0101: h=7'b0010010;
4'b0110: h=7'b0000010;
4'b0111: h=7'b1111000;
4'b1000: h=7'b0000000;
4'b1001: h=7'b0010000;
4'b1010: h=7'b1001000;
4'b1011: h=7'b0000011;
4'b1100: h=7'b1000110;
4'b1101: h=7'b0100001;
4'b1110: h=7'b0000110;
4'b1111: h=7'b0001110;
endcase
end
endmodule
module D_ff(q,d,clk);
input
d,clk;
output reg
q;
always@(posedge clk)
q<=d;
endmodule
module rega(a03,a47,s03,s47,clk);
input
clk;
input
[3:0]s03,s47;

output [3:0]a03,a47;
D_ff
u0(a03[0],s03[0],clk);
D_ff
u1(a03[1],s03[1],clk);
D_ff
u2(a03[2],s03[2],clk);
D_ff
u3(a03[3],s03[3],clk);
D_ff
u4(a47[0],s47[0],clk);
D_ff
u5(a47[1],s47[1],clk);
D_ff
u6(a47[2],s47[2],clk);
D_ff
u7(a47[3],s47[3],clk);
endmodule
module bin8seg4(ha0,ha1,hb0,hb1,clk,s03,s47);
input
clk;
input
[3:0]s03,s47;
output [6:0]ha0,ha1,hb0,hb1;
wire
[3:0]a03,a47,b03,b47;
assign b03=s03;
assign b47=s47;
rega
r0(a03,a47,s03,s47,clk);
bin4seg1
b0(a03,ha0);
bin4seg1
b1(a47,ha1);
bin4seg1
b2(b03,hb0);
bin4seg1
b3(b47,hb1);
endmodule

Code testbend
module bin8seg4_tb;
reg
clk;
reg
[3:0]s03,s47;
wire
[6:0]ha0,ha1,hb0,hb1;
bin8seg4
tb(ha0,ha1,hb0,hb1,clk,s03,s47);
initial begin
clk=0;
forever #3 clk=~clk;
end
initial begin
s03=4'b0000;
forever #8 s03=s03+1;
end
initial begin
s47=4'b0001;
forever #8 s47=s47+1;
end
initial begin
$monitor($time," CLK=%b SW03=%b SW47=%b B0=%b B1=%b A0=%b A1=%b
",clk,s03,s47,hb0,hb1,ha0,ha1);
#120 $stop;
end
endmodule

UNIT 4:

COUNTERS
PART I
Counter 16 bit su dung T-FF

Code Verilog
module counter16b(q,clk,en,clr);
input
clk,en,clr;
output [15:0]q;
wire
[14:0]ten;
tffwre t0(q[0],en,clk,clr);
tffwre t1(q[1],ten[0],clk,clr);
tffwre t2(q[2],ten[1],clk,clr);
tffwre t3(q[3],ten[2],clk,clr);
tffwre t4(q[4],ten[3],clk,clr);
tffwre t5(q[5],ten[4],clk,clr);
tffwre t6(q[6],ten[5],clk,clr);
tffwre t7(q[7],ten[6],clk,clr);
tffwre t8(q[8],ten[7],clk,clr);
tffwre t9(q[9],ten[8],clk,clr);

tffwre
tffwre
tffwre
tffwre
tffwre
tffwre
and
and
and
and
and
and
and
and
and
and
and
and
and
and
and
endmodule

t10(q[10],ten[9],clk,clr);
t11(q[11],ten[10],clk,clr);
t12(q[12],ten[11],clk,clr);
t13(q[13],ten[12],clk,clr);
t14(q[14],ten[13],clk,clr);
t15(q[15],ten[14],clk,clr);
a0(ten[0],en,q[0]);
a1(ten[1],ten[0],q[1]);
a2(ten[2],ten[1],q[2]);
a3(ten[3],ten[2],q[3]);
a4(ten[4],ten[3],q[4]);
a5(ten[5],ten[4],q[5]);
a6(ten[6],ten[5],q[6]);
a7(ten[7],ten[6],q[7]);
a8(ten[8],ten[7],q[8]);
a9(ten[9],ten[8],q[9]);
a10(ten[10],ten[9],q[10]);
a11(ten[11],ten[10],q[11]);
a12(ten[12],ten[11],q[12]);
a13(ten[13],ten[12],q[13]);
a14(ten[14],ten[13],q[14]);

module tffwre(q,t,clk,clr);
input
t,clk,clr;
output reg
q;
always@(posedge clk or negedge clr)
if(clr==0) q<=0;
else if (t==1) q<=~q;
endmodule

Code testbend
module counter16b_tb;
reg
clk,en,clr;
wire
[15:0]q;
counter16b
tb(q,clk,en,clr);
initial begin
clk=0;
forever #5 clk=~clk;
end
initial begin
en=0;
#10 en=1;
end
initial begin
clr=0;
#25 clr=1;
#45 clr=0;
#60 clr=1;
end
initial begin
$monitor($time," CLK=%b EN=%b CLR=%b

Q=%b",clk,en,clr,q);

#900 $stop;
end
endmodule
Use

KEY0 as the clock input. Use SW0 as aresetn input, SW1 as enable
input. Use 7-segment HEX3-0 to display result of counter.

module counter16bseg4(h0,h1,h2,h3,q,clk,en,clr);
input
clk,en,clr;
output
[6:0]h0,h1,h2,h3;
output
[15:0]q;
reg
[3:0]dig1,dig2,dig3,dig4;
counter16b
c0(q,clk,en,clr);
bin7seg (h0,h1,h2,h3,q);
//bin7seg
b0(q[3:0],h0);
//bin7seg
b1(q[7:4],h1);
//bin7seg
b2(q[11:8],h2);
//bin7seg
b3(q[15:12],h3);
endmodule
module counter16b(q,clk,en,clr);
input
clk,en,clr;
output [15:0]q;
wire
[14:0]ten;
tffwre t0(q[0],en,clk,clr);
tffwre t1(q[1],ten[0],clk,clr);
tffwre t2(q[2],ten[1],clk,clr);
tffwre t3(q[3],ten[2],clk,clr);

tffwre
tffwre
tffwre
tffwre
tffwre
tffwre
tffwre
tffwre
tffwre
tffwre
tffwre
tffwre
and
and
and
and
and
and
and
and
and
and
and
and
and
and
and
endmodule

t4(q[4],ten[3],clk,clr);
t5(q[5],ten[4],clk,clr);
t6(q[6],ten[5],clk,clr);
t7(q[7],ten[6],clk,clr);
t8(q[8],ten[7],clk,clr);
t9(q[9],ten[8],clk,clr);
t10(q[10],ten[9],clk,clr);
t11(q[11],ten[10],clk,clr);
t12(q[12],ten[11],clk,clr);
t13(q[13],ten[12],clk,clr);
t14(q[14],ten[13],clk,clr);
t15(q[15],ten[14],clk,clr);
a0(ten[0],en,q[0]);
a1(ten[1],ten[0],q[1]);
a2(ten[2],ten[1],q[2]);
a3(ten[3],ten[2],q[3]);
a4(ten[4],ten[3],q[4]);
a5(ten[5],ten[4],q[5]);
a6(ten[6],ten[5],q[6]);
a7(ten[7],ten[6],q[7]);
a8(ten[8],ten[7],q[8]);
a9(ten[9],ten[8],q[9]);
a10(ten[10],ten[9],q[10]);
a11(ten[11],ten[10],q[11]);
a12(ten[12],ten[11],q[12]);
a13(ten[13],ten[12],q[13]);
a14(ten[14],ten[13],q[14]);

module tffwre(q,t,clk,clr);
input
t,clk,clr;
output reg
q;
always@(posedge clk or negedge clr)
if(clr==0) q<=0;
else if (t==1) q<=~q;
endmodule
module bin7seg(h0,h1,h2,h3,s1);
input [15:0]s1;
//input
[3:0]b;
output [6:0]h0,h1,h2,h3;
reg
[6:0]h0,h1,h2,h3;
wire [15:0]s1;
reg
[15:0]tam;
wire [3:0]dig1,dig2,dig3,dig4;
//j=s;
assign tam= s1;
assign dig1 =tam[3:0];
assign dig2 =tam[7:4];
assign dig3 =tam[11:8];

assign dig4 =tam[15:12];

always@(dig1)
begin
if (dig1 < 4'b1010)
case(dig1)
4'b0000: h0=7'b1000000;
4'b0001: h0=7'b1111001;
4'b0010: h0=7'b0100100;
4'b0011: h0=7'b0110000;
4'b0100: h0=7'b0011001;
4'b0101: h0=7'b0010010;
4'b0110: h0=7'b0000010;
4'b0111: h0=7'b1111000;
4'b1000: h0=7'b0000000;
4'b1001: h0=7'b0010000;
endcase
else begin
h0=7'b1000000;
tam[3:0]=4'b0000;
tam[7:4]=tam[7:4]+1;
end
end
always@(dig2)
begin
if (dig2<4'b1010)
case(dig2)
4'b0000: h1=7'b1000000;
4'b0001: h1=7'b1111001;
4'b0010: h1=7'b0100100;
4'b0011: h1=7'b0110000;
4'b0100: h1=7'b0011001;
4'b0101: h1=7'b0010010;
4'b0110: h1=7'b0000010;
4'b0111: h1=7'b1111000;
4'b1000: h1=7'b0000000;
4'b1001: h1=7'b0010000;
endcase
else begin
h1=7'b1000000;
tam[7:4]=0;
tam[11:8]=tam[11:8]+1;
end
end
always@(dig3)
begin
if (dig3<4'b1010)
case(dig3)

4'b0000: h2=7'b1000000;
4'b0001: h2=7'b1111001;
4'b0010: h2=7'b0100100;
4'b0011: h2=7'b0110000;
4'b0100: h2=7'b0011001;
4'b0101: h2=7'b0010010;
4'b0110: h2=7'b0000010;
4'b0111: h2=7'b1111000;
4'b1000: h2=7'b0000000;
4'b1001: h2=7'b0010000;
endcase
else
begin
h2=7'b1000000;
tam[11:8]=0;
tam[15:12]=tam[15:12]+1;
end
end
always@(dig4)
begin
if (dig4<4'b1010)
case(dig4)
4'b0000: h3=7'b1000000;
4'b0001: h3=7'b1111001;
4'b0010: h3=7'b0100100;
4'b0011: h3=7'b0110000;
4'b0100: h3=7'b0011001;
4'b0101: h3=7'b0010010;
4'b0110: h3=7'b0000010;
4'b0111: h3=7'b1111000;
4'b1000: h3=7'b0000000;
4'b1001: h3=7'b0010000;
endcase
else begin
h3=7'b1000000;
tam[15:12]=0;
end
end
endmodule

Kieu behaviour
module counterqq1seg4(h0,h1,h2,h3,q,clk,en,re);
input
clk,en,re;
output
[6:0]h0,h1,h2,h3;
output
[15:0]q;
counterqq1
c0(q,clk,en,re);
bin7seg
b0(q[3:0],h0);
bin7seg
b1(q[7:4],h1);

bin7seg
bin7seg
endmodule

b2(q[11:8],h2);
b3(q[15:12],h3);

module counterqq1(q,clk,en,re);
input
clk,en,re;
output reg
[15:0]q;
always@(posedge clk) begin
if (re==1) q=0;
else if(en==0) q=0;
else q=q+1;
end
endmodule
module bin7seg(b,h);
input
[3:0]b;
output [6:0]h;
reg
[6:0]h;
always@(b)
case(b)
4'b0000: h=7'b1000000;
4'b0001: h=7'b1111001;
4'b0010: h=7'b0100100;
4'b0011: h=7'b0110000;
4'b0100: h=7'b0011001;
4'b0101: h=7'b0010010;
4'b0110: h=7'b0000010;
4'b0111: h=7'b1111000;
4'b1000: h=7'b0000000;
4'b1001: h=7'b0010000;
4'b1010: h=7'b1001000;
4'b1011: h=7'b0000011;
4'b1100: h=7'b1000110;
4'b1101: h=7'b0100001;
4'b1110: h=7'b0000110;
4'b1111: h=7'b0001110;
endcase
endmodule

Code Testbend
module counterqq1seg4_tb;
reg
clk,en,re;
wire
[6:0]h0,h1,h2,h3;
wire
[15:0]q;
counterqq1seg4 tb(h0,h1,h2,h3,q,clk,en,re);
initial begin
clk=1;
forever #5 clk=~clk;
end

initial begin
en=0;
#10 en=1;
end
initial begin
re=0;
#25 re=1;
#45 re=0;
end
initial begin
$monitor($time," CLK=%b EN=%b RE=%b Q=%d H3=%b H2=%b H1=%b H0=
%b ",clk,en,re,q,h3,h2,h1,h0);
#3000 $stop;
end
endmodule

PART III

module counterwde(q,clk);
input
clk;
output [3:0]q;
wire
d1s;
delay1s u0(d1s,clk);
counterqq1
u1(q,d1s,clk);
endmodule
module counterqq1(q,t,clk);
input
clk,t;
output reg
[3:0]q;
always@(posedge clk) begin
if (t==1)
if (q<9)
q = q+4'b1;
else
q = 4'b0;
end
endmodule
module delay1s(d1s,clk);
input
clk;
output reg
d1s;
reg
[7:0]temp;

always@(posedge clk) begin

if (temp<49) begin
temp = temp+8'b1;
d1s = 1'b0;
end
else begin
d1s = 1'b1;
temp = 8'b0;
end
end
endmodule

Code Testbend
module counterwde_tb;
reg
clk;
wire
[3:0]q;
counterwde
tb(q,clk);
initial begin
clk = 1'b1;
forever #1 clk=~clk;
end
initial begin
$monitor($time," CLK=%b Q=%h ",clk,q);
#300 $stop;
end
endmodule

PART IV

module ar7seg(h0,h1,h2,h3,p0,p1,p2,p3,clk,re);
input
clk,re;
output [6:0]h0,h1,h2,h3;
output [1:0]p0,p1,p2,p3;
ar_dE1 a0(p0,p1,p2,p3,clk,re);
char7seg
a1(h0,p0);
char7seg
a2(h1,p1);
char7seg
a3(h2,p2);

char7seg
endmodule

a4(h3,p3);

module ar_dE1(p0,p1,p2,p3,clk,re);
input
clk,re;
output [1:0]p0,p1,p2,p3;
wire
d1s;
delay1s u0(d1s,clk);
cqq1
u1(p3,d1s,clk,re);
add1
u2(p2,p3);
add2
u3(p1,p3);
add3
u4(p0,p3);
endmodule
module cqq1(q,t,clk,re);
input
clk,t,re;
output reg
[1:0]q;
always@(posedge clk or negedge re) begin
if (re==0)
q=2'b0;
else if (q<2'b11)
q = q+2'b1;
else
q = 2'b0;
end
endmodule
module delay1s(d1s,clk);
input
clk;
output reg
d1s;
reg
[7:0]temp;
always@(posedge clk) begin
if (temp<49) begin
temp = temp+8'b1;
d1s = 1'b0;
end
else begin
d1s = 1'b1;
temp = 8'b0;
end
end
endmodule
module add1(y,x);
input
[1:0]x;
output reg
[1:0]y;
always@(x)
y = x + 2'b01;
endmodule
module add2(y,x);
input

[1:0]x;

output reg
[1:0]y;
always@(x)
y = x + 2'b10;
endmodule
module add3(y,x);
input
[1:0]x;
output reg
[1:0]y;
always@(x)
y = x + 2'b11;
endmodule
module char7seg(h,p);
input
[1:0]p;
output reg
[6:0]h;
always@(p) begin
case(p)
2'b00: h=7'b0100001;
2'b01: h=7'b0000110;
2'b10: h=7'b1001111;
2'b11: h=7'b1111111;
endcase
end
endmodule

Code Testbend
module ar7seg_tb;
reg
clk,re;
wire
[6:0]h0,h1,h2,h3;
wire
[1:0]p0,p1,p2,p3;
ar7seg tb(h0,h1,h2,h3,p0,p1,p2,p3,clk,re);
initial begin
clk = 1'b1;
forever #1 clk = ~clk;
end
initial begin
re = 1'b1;
#15 re = 1'b0;
#35 re = 1'b1;
end
initial begin
$monitor($time," CLK=%b RE=%b P3=%b P2=%b P1=%b P0=%b H3=%b H2=%b
H1=%b H0=%b",clk,re,p3,p2,p1,p0,h3,h2,h1,h0);
#120 $stop;
end
endmodule

UNIT 5:
CLOCK AND TIMER
PART I

module c999wre(h2,h1,h0,b2,b1,b0,clk,re);
input
clk,re;
output [6:0]h2,h1,h0;
output [3:0]b2,b1,b0;
wire
d1s;
delay1s c0(d1s,clk);
c999
c1(b0,b1,b2,clk,re,d1s);
bcd7seg
c2(b2,h2);
bcd7seg
c3(b1,h1);
bcd7seg
c4(b0,h0);
endmodule
module c999(b0,b1,b2,clk,re,t);
input
clk,re,t;
output reg
[3:0]b0,b1,b2;
always@(posedge clk or negedge re) begin
if (re==0) begin
b0=0;
b1=0;
b2=0;
end
else if (t==1)
if(b0<9)
b0 = b0+4'b1;
else if (b1<9) begin
b1 = b1+4'b1;
b0 = 0;
end

else if (b2<9) begin

b2 = b2+4'b1;
b1 = 0;
b0 = 0;
end
else begin
b0 = 0;
b1 = 0;
b2 = 0;
end
end
endmodule
module delay1s(d1s,clk);
input
clk;
output reg
d1s;
reg
[7:0]temp;
always@(posedge clk) begin
if (temp<49) begin
temp = temp+8'b1;
d1s = 1'b0;
end
else begin
d1s = 1'b1;
temp = 8'b0;
end
end
endmodule
module bcd7seg(b,h);
input
[3:0]b;
output [6:0]h;
reg
[6:0]h;
always@(b)
case(b)
4'b0000: h=7'b1000000;
4'b0001: h=7'b1111001;
4'b0010: h=7'b0100100;
4'b0011: h=7'b0110000;
4'b0100: h=7'b0011001;
4'b0101: h=7'b0010010;
4'b0110: h=7'b0000010;
4'b0111: h=7'b1111000;
4'b1000: h=7'b0000000;
4'b1001: h=7'b0010000;
4'b1010: h=7'b1001000;
4'b1011: h=7'b0000011;
4'b1100: h=7'b1000110;
4'b1101: h=7'b0100001;
4'b1110: h=7'b0000110;
4'b1111: h=7'b0001110;

endcase
endmodule

Code Testbend
module counter999_tb;
reg
clk;
wire [3:0]b0,b1,b2;
counter999
tb(b0,b1,b2,clk);
initial begin
clk=1;
forever #1 clk=~clk;
end
initial begin
re=0;
#50 re=1;
#80 re=0;
end
initial begin
$monitor($time," CLK=%b B2=%d B1=%d B0=%d",clk,b2,b1,b0);
#500 $stop;
end
endmodule

Cng tr c xung Clock

module addsub
(
input [7:0] dataa,
input [7:0] datab,
input add_sub, // if this is 1, add; else subtract
input clk,
output reg [8:0] result
);
always @ (posedge clk)
begin
if (add_sub)
result <= dataa + datab;
else
result <= dataa - datab;
end
endmodule

Following is the Verilog code for a logical shifter.

module lshift (di, sel, so);
input [7:0] di;
input [1:0] sel;
output [7:0] so;
reg [7:0] so;

always @(di or sel)

begin
case (sel)
2b00 : so = di;
2b01 : so = di << 1;
2b10 : so = di << 2;
default : so = di << 3;
endcase
end
endmodule

Following is the Verilog code for an unsigned 8-bit adder with carry in.
module adder(a, b, ci, sum);
input [7:0] a;
input [7:0] b;
input
ci;
output [7:0] sum;
assign sum = a + b + ci;
endmodule

Following is the Verilog code for an unsigned 8-bit adder with carry out.
module adder(a, b, sum, co);
input [7:0] a;
input [7:0] b;
output [7:0] sum;
output
co;
wire [8:0] tmp;
assign tmp = a + b;
assign sum = tmp [7:0];
assign co = tmp [8];
endmodule

Following is the Verilog code for an unsigned 8-bit adder with carry in and carry out.
module adder(a, b, ci, sum, co);
input
ci;
input [7:0] a;
input [7:0] b;
output [7:0] sum;
output
co;
wire [8:0] tmp;
assign tmp = a + b + ci;
assign sum = tmp [7:0];
assign co = tmp [8];
endmodule

Following is the Verilog code for an unsigned 8-bit adder/subtractor.

module addsub(a, b, oper, res);
input
oper;
input [7:0] a;
input [7:0] b;
output [7:0] res;
reg [7:0] res;
always @(a or b or oper)
begin
if (oper == 1b0)
res = a + b;
else
res = a - b;
end
endmodule

Following is the Verilog code for an unsigned 8-bit greater or equal comparator.
module compar(a, b, cmp);
input [7:0] a;
input [7:0] b;
output
cmp;
assign cmp = (a >= b) ? 1b1 : 1b0;
endmodule

Following is the Verilog code for an unsigned 8x4-bit multiplier.

module compar(a, b, res);
input [7:0] a;
input [3:0] b;
output [11:0] res;
assign res = a * b;
endmodule

Following is the Verilog code for a 4-to-1 1-bit MUX using an If statement.
module mux (a, b, c, d, s, o);
input
a,b,c,d;
input [1:0] s;
output
o;
reg
o;
always @(a or b or c or d or s)
begin
if (s == 2b00)
o = a;

else if (s == 2b01)
o = b;
else if (s == 2b10)
o = c;
else
o = d;
end
endmodule

Following is the Verilog Code for a 4-to-1 1-bit MUX using a Case statement.
module mux (a, b, c, d, s, o);
input
a, b, c, d;
input [1:0] s;
output
o;
reg
o;
always @(a or b or c or d or s)
begin
case (s)
2b00 : o = a;
2b01 : o = b;
2b10 : o = c;
default : o = d;
endcase
end
endmodule

Following is the Verilog code for a 4-bit unsigned up/down counter with an asynchronous
clear.
module counter (clk, clr, up_down, q);
input
clk, clr, up_down;
output [3:0] q;
reg [3:0] tmp;
always @(posedge clk or posedge clr)
begin
if (clr)
tmp <= 4b0000;
else if (up_down)
tmp <= tmp + 1b1;
else
tmp <= tmp - 1b1;
end
assign q = tmp;
endmodule

Following is the Verilog code for a 4-bit unsigned up counter with asynchronous clear.
module counter (clk, clr, q);
input
clk, clr;
output [3:0] q;
reg [3:0] tmp;
always @(posedge clk or posedge clr)
begin

if (clr)
tmp <= 4b0000;
else
tmp <= tmp + 1b1;
end
assign q = tmp;
endmodule

Following is the Verilog code for a 4-bit unsigned down counter with synchronous
set.
module counter (clk, s, q);
input
clk, s;
output [3:0] q;
reg [3:0] tmp;
always @(posedge clk)
begin
if (s)
tmp <= 4b1111;
else
tmp <= tmp - 1b1;
end
assign q = tmp;
endmodule

Following is the Verilog code for a 4-bit unsigned up counter with an asynchronous load
from the primary input.
module counter (clk, load, d, q);
input
clk, load;
input [3:0] d;
output [3:0] q;
reg [3:0] tmp;
always @(posedge clk or posedge load)
begin
if (load)
tmp <= d;
else
tmp <= tmp + 1b1;
end
assign q = tmp;
endmodule

Following is the Verilog code for a 4-bit unsigned up counter with a synchronous load with
a constant.
module counter (clk, sload, q);
input
clk, sload;
output [3:0] q;
reg [3:0] tmp;
always @(posedge clk)
begin
if (sload)
tmp <= 4b1010;
else

tmp <= tmp + 1b1;

end
assign q = tmp;
endmodule

Following is the Verilog code for a 4-bit unsigned up counter with an asynchronous clear
and a clock enable.
module counter (clk, clr, ce, q);
input
clk, clr, ce;
output [3:0] q;
reg [3:0] tmp;
always @(posedge clk or posedge clr)
begin
if (clr)
tmp <= 4b0000;
else if (ce)
tmp <= tmp + 1b1;
end
assign q = tmp;
endmodule

Following is the Verilog code for a 4-bit unsigned up/down counter with an asynchronous
clear.
module counter (clk, clr, up_down, q);
input
clk, clr, up_down;
output [3:0] q;
reg [3:0] tmp;
always @(posedge clk or posedge clr)
begin
if (clr)
tmp <= 4b0000;
else if (up_down)
tmp <= tmp + 1b1;
else
tmp <= tmp - 1b1;
end
assign q = tmp;
endmodule

Following is the Verilog code for a 4-bit signed up counter with an asynchronous reset.
module counter (clk, clr, q);
input
clk, clr;
output signed [3:0] q;
reg signed [3:0] tmp;
always @ (posedge clk or posedge clr)
begin
if (clr)
tmp <= 4b0000;
else
tmp <= tmp + 1b1;
end
assign q = tmp;
endmodule

Following is the Verilog code for a 4-bit signed up counter with an asynchronous reset and
a modulo maximum.
module counter (clk, clr, q);
parameter MAX_SQRT = 4, MAX = (MAX_SQRT*MAX_SQRT);
input
clk, clr;
output [MAX_SQRT-1:0] q;
reg [MAX_SQRT-1:0] cnt;
always @ (posedge clk or posedge clr)
begin
if (clr)
cnt <= 0;
else
cnt <= (cnt + 1) %MAX;
end
assign q = cnt;
endmodule

Following is the Verilog code for a 4-bit unsigned up accumulator with an asynchronous
clear.
module accum (clk, clr, d, q);
input
clk, clr;
input [3:0] d;
output [3:0] q;
reg [3:0] tmp;
always @(posedge clk or posedge clr)
begin
if (clr)
tmp <= 4b0000;
else
tmp <= tmp + d;
end
assign q = tmp;
endmodule

Following is the Verilog code for an 8-bit shift-left register with a positive-edge clock, serial
in and serial out.
module shift (clk, si, so);
input
clk,si;
output
so;
reg [7:0] tmp;
always @(posedge clk)
begin
tmp <= tmp << 1;
tmp[0] <= si;
end
assign so = tmp[7];
endmodule

module add_carry_signed_2001 (
input signed [2:0] A,
input signed [2:0] B,
input carry_in,
output signed [3:0] Sum
);

assign Sum = A + B + carry_in;

endmodule // add_carry_signed_2001