1.

2. (a)
# cycle ID EX MEM EX (1)/2/3 1/2 1 MEM (1/2)/3 (1)/2 1

EXID 1 1 2 1 1 2 MEMID 1 1 2 1 1 2 1 1 2 EXEX 1 1 2 1 1 2 F F 2 D F 2 D 1 cycle ahead 3 X D 4 M X 3 X F 5 W M 4 M D W 5 W X M W F 6 7 6 7 F F F 2 D stall 2 D stall 2 D 3 X F 3 X stall 3 X 3 cycle ahead 4 M 5 6 7 W 7 M 7 X 8 W 8 M 9 W 8 W Non-causal D X M 4 M F 4 M 5 W D 5 W F D X 6 6 F F 2 D stall 2 D 3 X F 3 X 4 M D 4 M F 5 W X 5 W D X M W M 6 W 7 8 6 7

2 cycle ahead

MEMEX 1 1 2 1 1 2 EXMEM 1 1 2 MEMMEM 1 1 2 F 2 D 1 cycle ahead 3 X F 4 M D 5 W X M W 6 7 F 2 D 1 cycle ahead 3 X F 4 M D 5 W X M W 6 7 F F 2 D stall 2 D 3 X F 3 X 4 M D 4 M F 5 W X 5 W D X M W M 6 W 7 8 6 7

2 cycle ahead

(b) LOOP:

lw $t0,-4($s0) sw $t0, 996($s0) addi $s0,$s0,-4 bne $s0,$zero,LOOP

lw sw data hazard (MEM to MEM) addi bne data hazard (EX to ID) bne control hazard

(c) 4-stage 1 lw sw addi bne

next iteration

2 D F

3 X/M stall

4 W D F

5 X/M D F

6 W X/M stall

W D X/M F W D

lw 1 iteration 7 cycles 100 iterations 700 cycles 5-stage 1 lw sw addi bne F 2 D F 3 X stall 4 M stall 5 W D F X D F M X stall W M stall W D 6 7 8 9

10

11

12

X F

M D

W X

next iteration

lw 1 iteration 9 cycles 100 iterations 900 cycles

(d) LOOP:

lw $t0,-4($s0) lw $t1,-8($s0) lw $t2,-12($s0) lw $t3,-16($s0) sw $t0,996($s0) sw $t1,992($s0) sw $t2,988($s0) sw $t3,984($s0) addi $s0,$s0,-16 bne $s0,$zero,LOOP

5-stage 1 lw lw lw lw sw sw sw sw addi bne

next iteration

2 D F

3 X D F

4 M X D F

5 W M X D F

6 W M X D F

10

11

12

13 14 15 16

W M X D F W M X D F W M X D F W M X D F W M X W M W D X F M D W X

stall stall

lw 1 iteration 13 cycles 25 iterations 325 cycles

(e) LOOP:

lw $t0,-4($s0) lw $t1,-8($s0) lw $t2,-12($s0) lw $t3,-16($s0) addi $s0,$s0,-16 sw $t0,996($s0) sw $t1,992($s0) sw $t2,1004($s0) bne $s0,$zero,LOOP sw $t3,1000($s0)

$s0 write back delay slot

5-stage 1 lw lw lw lw addi sw sw sw bne sw

next iteration

2 D F

3 X D F

4 M X D F

5 W M X D F

6 W M X D F

10

11

12

13 14

W M X D F W M X D F W M X D F W M X D F W M X D F W M X D W M W X M

lw

drawback: loop code section interruptcompiler code

(f) 4-stage 1 lw sw addi bne

next iteration

2 D F

3 X/M D F

4 W X/M D F

5 W X/M stall

W D X/M F W D

lw 1 iteration 6 cycles 100 iterations 600 cycles 5-stage 1 lw sw addi bne F 2 D F 3 X D F 4 M X D F 5 W M X stall W M D W X F M D 6 7 8

W X

next iteration

lw 1 iteration 6 cycles 100 iterations 600 cycles

(g) 4-stage if (EX-MEM/WB.RegWrite // WB stage Reg and EX-MEM/WB.MemtoReg // WB stage Reg MEM (lw ) and (EX-MEM/WB.RegisterRd 0) // WB stage Destination Reg $zero and ID/EX-MEM.MemWrite // EX-MEM stage (sw ) and (EX-MEM/WB.RegisterRd = ID/EX-MEM.RegisterRt))// WB stage lw Destination
Reg EX-MEM stage sw Source Reg

if (EX-MEM/WB.RegWrite // WB stage Reg and (EX-MEM/WB.MemtoReg=0) // WB stage Reg ALU (addi ) and (EX-MEM/WB.RegisterRd 0) // WB stage Destination Reg $zero and IF/ID.branch // EX-MEM stage (bne ) and (EX-MEM/WB.RegisterRd = IF/ID.RegisterRs))// WB stage addi Destination
Reg ID stage bne Source Reg

5-stage if (MEM/WB.RegWrite // WB stage Reg and MEM/WB.MemtoReg // WB stage Reg MEM (lw ) and (MEM/WB.RegisterRd 0) // WB stage Destination Reg $zero and EX/MEM.MemWrite // MEM stage (sw ) and (MEM/WB.RegisterRd = EX/MEM.RegisterRd))// WB stage lw Destination Reg
MEM stage sw Source Reg

if (EX/MEM.RegWrite // MEM stage Reg (addi ) and (EX/MEM.RegisterRd0) // MEM stage Reg (addi ) Destination
Reg $zero

and IF/ID.Branch // ID stage branch (bne) and (EX/MEM.RegisterRd = IF/ID.RegsterRs)) // MEM stage addi Destination Reg
ID stage bne Source Reg

(h) LOOP:

lw $t0,-4($s0) addi $s0,$s0,-4 sw$t0,996($s0) bne $s0,$zero,LOOP 1 2 D F 3 X/M D F 4 W X/M D F W X/M D stall W X/M F W D 5 6 7

4-stage lw addi sw bne

next iteration

lw 5-stage 1 lw addi sw bne F 2 D F 3 X D F 4 M X D F 5 W M X D stall 6

W M X F W M D W X

next iteration

lw

4-stage if( EX-MEM/WB.RegWrite // WB stage Reg and (EX-MEM/WB.MemtoReg=0) // WB stage Reg ALU (addi ) and(EX-MEM/WB.RegisterRd0) // WB stage Destination Reg $zero and ID/EX-MEM.MemWrite // EX stage (sw ) and (EX-MEM/WB.RegisterRd = ID/EX-MEM.RegisterRt))// WB stage addi
Destination Reg EX-MEM stage sw Source Reg

5-stage if( MEM/WB.RegWrite // WB stage Reg and MEM/WB.MemtoReg // WB stage Reg MEM (lw ) and(MEM/WB.RegisterRd0) // WB stage Destination Reg $zero and ID/EX.MemWrite
// EX stage (sw )

and (MEM/WB.RegisterRd = ID/EX.RegisterRt))

// WB stage lw Destination Reg EX stage sw Source Reg

if (EX/MEM.RegWrite // MEM stage Reg (addi ) and (EX/MEM.RegisterRd0) // MEM stage Reg (addi )
Destination Reg $zero

and ID/EX.MemWrite // EX stage (sw ) and (EX/MEM.RegisterRd = ID/EX.RegsterRs)) // MEM stage addi
Destination Reg EX stage sw Base Reg ( RegisterRs Base Reg )

if (EX/MEM.RegWrite // MEM stage Reg (addi ) and (EX/MEM.RegisterRd0) // MEM stage Reg (addi )
Destination Reg $zero

and IF/ID.Branch // ID stage branch (bne) and (EX/MEM.RegisterRd = IF/ID.RegsterRs))// MEM stage addi Destination
Reg ID stage bne Source Reg

3. (a)

0 1 mux

RegDst control signal

( forwarding control signal forwarding data path ) If ( (EX/MEM.MemWrite) // MEM stage (sw ) and (MEM/WB.MemToReg) // WB stage MEM and (MEM/WB.RegWrite) // Reg and(EX/MEM.RegisterRd = MEM/WB.RegisterRd)// WB stage lw Destination Reg
MEM stage sw Source Reg

and (MEM/WB.RegisterRd0) ) Forwardgreen=1 else Forwardgreen=0

// WB stage Reg $zero //forwarding 1data MEM

//forwarding 0 pipeline

( EX/MEM.RegisterRd RegisterRt RegDst 0) ( sw Source Register RegisterRt) ( lw Destination Register RegisterRt)

4. block size 32 (= 25) bytes. 16KByte cache 16K/32 = 512 (= 29) blocks. 2-way set associative 512/2 = 256 (= 28) sets. 36-bit address 5 bits block offset8 bits index 23 bits tag. cache organization

5. 40-bit virtual address=>virtual memory 1TB page 16KB 1TB/16KB= 67,108,864 ( = 226) page page page table entry entry physical page number 4 control bits physical page number bits 32-bit physical address=>physical memory 4GB page 16KB physical page number=4GB/16KB= 262,144 ( = 218) 18 bits physical page number page table 67108864 entry entry 18+4=22 bits page table =67,108,864*22(bits)= 1,476,395,008(bits)= 184,549,376(bytes)=176(MB)