FPGA应用举例

七段译码器
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;
CASE D IS
ENTITY seven_v IS WHEN 0 => S<="1111110"; --0
PORT( D : IN WHEN 1 =>RANGE
INTEGER S<="0000110";
0 TO 9; --1
S : OUT WHEN 2 => S<="1101101";
STD_LOGIC_VECTOR(0 DOWNTO --2
6) );
WHEN 3 => S<="1111001"; --3
END seven_v ; WHEN 4 => S<="0110011"; --4
ARCHITECTURE a OF seven_v WHEN
IS 5 => S<="1011011"; --5
BEGIN WHEN 6 => S<="1011111"; --6
PROCESS(D) WHEN 7 => S<="1110000"; --7
BEGIN WHEN 8 => S<="1111111"; --8
WHEN 9 => S<="1111011"; --9
？？？ WHEN OTHERS => S<="0000000";
END PROCESS; END CASE;
END a;
半加器－（不考虑低位的进位）
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY hadd_v IS
PORT ( A, B : IN STD_LOGIC;
S, C : OUT STD_LOGIC);
END hadd_v;
ARCHITECTURE a OF hadd_v IS
SIGNAL temp : STD_LOGIC_VECTOR(1 downto 0);
BEGIN
temp <= ('0'& A)+B;
S <= temp(0);
C <= temp(1);
END a;
全加器
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY fadd_v IS
PORT ( A, B, Ci : IN STD_LOGIC;
S, Co : OUT STD_LOGIC);
END fadd_v;
ARCHITECTURE a OF fadd_v IS
SIGNAL temp : STD_LOGIC_VECTOR(1 downto 0);
BEGIN
temp <= ('0'& A)+B+Ci;
S <= temp(0);
Co <= temp(1);
END a;
 半加器
全加器
全加器
全加器
四位加法器
进位
四位加法器－使用PACKAGE
library IEEE;
use IEEE.std_logic_1164.all;

package add_v is

COMPONENT hadd_v
PORT( a, b : IN STD_LOGIC;
s, c : OUT STD_LOGIC);
END COMPONENT;
COMPONENT fadd_v
PORT( a, b, ci : IN STD_LOGIC;
s, co : OUT STD_LOGIC);
END COMPONENT;
end add_v;
 四位加法器－使用PACKAGE
LIBRARY IEEE;
h0:IEEE.STD_LOGIC_1164.ALL;
USE hadd_v
USEPORT
Work.add_v.all;
MAP (a =>A(0),b =>B(0),s =>S(0),c=>N1);
f1: fadd_v
ENTITY add4_v IS
PORT MAP (a =>A(1),b
( A,B : IN =>B(1),ci=>N1,s =>S(1),co=>N2);
STD_LOGIC_VECTOR(3 DOWNTO 0);
f2: fadd_v S : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
PORT MAP Cout
(a =>A(2),b =>B(2),ci=>N2,s
: OUTSTD_LOGIC ); =>S(2),co=>N3);
f3:add4_v;
END fadd_v
PORT MAP (a
ARCHITECTURE =>A(3),b
a OF add4_v=>B(3),ci=>N3,s
IS =>S(3),
Signal N1, N2, N3 : STD_LOGIC; co=>Cout);
BEGIN
？？？
END a;
四位加法器－元件例化
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
h0: ENTITY
hadd_vadd4_v IS
PORT PORT
MAP ((aA,B
S
: IN
=>A(0),b
: OUT
STD_LOGIC_VECTOR(3 DOWNTO 0);
=>B(0),s =>S(0),c=>N1);
STD_LOGIC_VECTOR(3 DOWNTO 0);
f1: fadd_v Cout : OUT STD_LOGIC );
PORT MAP (a =>A(1),b =>B(1),ci=>N1,s =>S(1),co=>N2);
END add4_v;
f2: ARCHITECTURE
fadd_v a OF add4_v IS
COMPONENT hadd_v
PORT MAPPORT(
(a =>A(2),b a, b : IN=>B(2),ci=>N2,s
STD_LOGIC; =>S(2),co=>N3);
f3: fadd_v s, c : OUT STD_LOGIC);
END COMPONENT;
PORT MAP (a =>A(3),b =>B(3),ci=>N3,s =>S(3),
COMPONENT fadd_v
PORT( a, b, ci : IN STD_LOGIC; co=>Cout);
s, co : OUT STD_LOGIC);
END COMPONENT;
Signal N1, N2, N3 : STD_LOGIC;
BEGIN
…
END a;
 D触发器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY dff_v is
PORT( CP,D : IN STD_LOGIC;
每次时钟脉冲信号CP由0变1的上升沿，将输入信号D传
Q : OUT STD_LOGIC );
递至输出信号Q，而平时Q则保持过去的状态不变。这
END dff_v;
ARCHITECTURE a OF dff_v IS
就是一个寄存器。
BEGIN
PROCESS (CP)
BEGIN
IF CP'event AND CP='1' THEN
Q <= D;
END IF;
END PROCESS;
END a;
RS触发器－真值表

S R Q

0 0 Qn-1

0 1 0

1 0 1

1 1 未定
RS触发器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY rsff_v is
PORT( S,R : IN STD_LOGIC;
Q,NOT_Q : OUT STD_LOGIC);
END rsff_v;
ARCHITECTURE a OF rsff_v IS
SIGNAL QN,NOT_QN : STD_LOGIC;
BEGIN
QN <= R NOR NOT_QN;
NOT_QN <= S NOR QN;
Q <= QN;
NOT_Q <= NOT_QN;
END a;
 只读存储器ROM(4x8)
DATAOUT <= "00001001" WHEN ADDR = "0000" AND CE='0' ELSE
LIBRARY IEEE; "00011010" WHEN ADDR = "0001" AND CE='0' ELSE
USE IEEE.STD_LOGIC_1164.ALL;
"00011011" WHEN ADDR = "0010" AND CE='0' ELSE
USE IEEE.STD_LOGIC_ARITH.ALL;
"00101100" WHEN ADDR = "0011" AND CE='0' ELSE
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
"11100000" WHEN ADDR = "0100" AND CE='0' ELSE
ENTITY test is "11110000" WHEN ADDR = "0101" AND CE='0' ELSE
PORT( DATAOUT : OUT STD_LOGIC_VECTOR(7
"00010000" WHEN ADDR = DOWNTO
"1001" 0);
AND --Data
CE='0' Output
ELSE
ADDR : IN STD_LOGIC_VECTOR(3
"00010100" WHEN ADDR = DOWNTO
"1010" 0);
AND --ROM
CE='0'ADDRESS
ELSE
CE : IN STD_LOGIC
"00011000" -- Chip
WHEN ADDR Enable
= "1011" AND CE='0' ELSE );
END test; "00100000" WHEN ADDR = "1100" AND CE='0' ELSE
ARCHITECTURE a OF test IS
"xxxxxxxx";
BEGIN
…
END a;