Emachines D725

5
http://konweer.kiev.ua
HM40-MV Block Diagram

CLK GEN.
ICS 9LPRS365BKLFT (71.09365.A03) SILEGO SLG8SP513VTR(71.08513.003) 3
Project code: 91.4BW01.001 PCB P/N : 48.4BW01.0SB REVISION : 08242-SB

PCB STACKUP
TOP VCC S S
D
Mobile CPU
Penryn 479
4, 5
THERMAL EMC2102
32
DDR2 DIMM1
667/800 MHz
16
HOST BUS 667/800MHz
667/800/1067MHz@1.05V
SYSTEM DC/DC
TPS51125
INPUTS 42 OUTPUTS
5V_S5
Cantiga
AGTL+ CPU I/F DDR Memory I/F LVDS, CRT I/F INTEGRATED GRAHPICS
GND
DDR2 DIMM2
667/800 MHz
17
C
www.kythuatvitinh.com
19
BOTTOM
CRT LCD
DCBATOUT
667/800MHz
3D3V_S5
18
6,7,8,9,10,11
X4 DMI 400MHz
C-Link0
SYSTEM DC/DC
TPS51124
INPUTS
DCBATOUT
44
Codec
CX20561
26
AZALIA
ICH9M
6 PCIe ports ACPI 2.0 4 SATA
OUTPUTS
1D05V_S0 1D8V_S3
PCIex1
PCI/PCI BRIDGE
Atheros
AR8114 AR8132 24
LAN
TXFM
25
RJ45
25 RT9026
1D8V_S3
43
DDR_VREF_S0 DDR_VREF_S3
MIC In
28
12 USB 2.0/1.1 ports ETHERNET (10/100/1000MbE) High Definition Audio LPC I/F Serial Peripheral I/F Matrix Storage Technology(DO) Active Managemnet Technology(DO)
PCIex1
Mini Card
Kedron a/b/g/n
RT9018A
1D8V_S3 1D5V_S0
43
28
B
OP AMP
G1454 27
31
LPC BUS BIOS

Winbond W25X16 16M Bits
CPU DC/DC
ISL6266A 41
B
INT.SPKR
28
KBC
KBC773L
12,13,14,15 33
LPC
34
INPUTS
DCBATOUT
OUTPUTS VCC_CORE_S0
0.35~1.5V
Line Out (NO SPDIF)
DEBUG CONN. 34
CHARGER
BQ24745 Camera (USB) 18 46 OUTPUTS BT+
DCBATOUT
USB
Blue Tooth 22 (USB) HDD SATA
Touch Pad 35
INT. KB 33 MS/MS Pro/xD 30 /MMC/SD

5 in 1
INPUTS
SATA
20
ODD SATA
SATA
21
USB 2 Port
USB
23
CardReader Realtek RTS5159 30
DCBATOUT
A
UMA Two Phase 2
Power Board 36
5 4 3 2
Title Size A3 Date:
DN: cn=dd, o=dd, ou=d email=dddd@yahoo. BLOCK DIAGRAM com, c=US Document Number Rev SB HM40-MV Date: 2009.12.04 19:33:5 Monday, November 24, 2008 Sheet 1 of 51 +07'00'
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
1
Digitally signed by Wistron Corporation dd
http://konweer.kiev.ua ICH9M Functional Strap

Signal HDA_SDOUT Usage/When Sampled XOR Chain Entrance/ PCIE Port Config1 bit1, Rising Edge of PWROK PCIE config1 bit0, Rising Edge of PWROK. PCIE config2 bit2, Rising Edge of PWROK. Reserved ESI Strap (Server Only) Rising Edge of PWROK
C
page 92
Definitions Rev.1.5 ICH9 EDS 642879

Comment
ICH9M Integrated Pull-up and Pull-down Resistors

CL_CLK[1:0] CL_RST0# DPRSLPVR/GPIO16 ENERGY_DETECT HDA_BIT_CLK HDA_DOCK_EN#/GPIO33 HDA_RST# HDA_SDIN[3:0] HDA_SDOUT HDA_SYNC GLAN_DOCK# GPIO[20] GPIO[49]
GNT[3:0]#/GPIO[55,53,51]
Cantiga chipset and ICH9M I/O controller Hub strapping configuration

Rev.1.5
Pin Name CFG[2:0]
ICH9 EDS 642879
Montevina Platform Design guide 22339

page 218 Configuration 000 = FSB1067 011 = FSB667 010 = FSB800 others = Reserved
0.5
Allows entrance to XOR Chain testing when TP3 pulled low.When TP3 not pulled low at rising edge of PWROK,sets bit1 of RPC.PC(Config Registers: offset 224h). This signal has weak internal pull-down This signal has a weak internal pull-down. Sets bit0 of RPC.PC(Config Registers:Offset 224h) This signal has a weak internal pull-up. Sets bit2 of RPC.PC2(Config Registers:Offset 0224h) This signal should not be pulled high. ESI compatible mode is for server platforms only. This signal should not be pulled low for desttop and mobile. Sampled low:Top-Block Swap mode(inverts A16 for all cycles targeting FWH BIOS space). Note: Software will not be able to clear the Top-Swap bit until the system is rebooted without GNT3# being pulled down.
SIGNAL
Resistor Type/Value
PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-DOWN 20K PULL-UP 20K PULL-DOWN 20K PULL-UP 20K PULL-DOWN 20K PULL-DOWN 20K PULL-DOWN 20K PULL-DOWN 20K
The pull-up or pull-down active when configured for native GLAN_DOCK# functionality and determined by LAN controller
Strap Description FSB Frequency Select
CL_DATA[1:0]
HDA_SYNC GNT2#/ GPIO53 GPIO20 GNT1#/ GPIO51
CFG[4:3] CFG8 CFG[15:14] CFG[18:17] CFG5 CFG6
Reserved
DMI x2 Select iTPM Host Interface Intel Management engine Crypto strap
0 = DMI x2 1 = DMI x4 (Default) 0= The iTPM Host Interface is enabled(Note2) 1=The iTPM Host Interface is disalbed(default) 0 = Transport Layer Security (TLS) cipher suite with no confidentiality 1 = TLS cipher suite with confidentiality (default) 0 = Reverse Lanes,15->0,14->1 ect.. 1= Normal operation(Default):Lane Numbered in order
GNT3#/ GPIO55
Top-Block Swap Override. Rising Edge of PWROK.
CFG7
GNT0#: SPI_CS1#/ GPIO58 SPI_MOSI
Boot BIOS Destination Selection 0:1. Rising Edge of PWROK.
Integrated TPM Enable, Rising Edge of CLPWROK
3
GPIO49
DMI Termination Voltage, The signal is required to be low for desktop Rising Edge of PWROK. applications and required to be high for mobile applications. PCI Express Lane Reversal. Rising Edge of PWROK. No Reboot. Rising Edge of PWROK.
SATALED# SPKR
CFG9 PCIE Graphics Lane Controllable via Boot BIOS Destination bit (Config Registers:Offset 3410h:bit 11:10). GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC.
PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 15K PULL-UP 20K
PULL-DOWN 20K
CFG10
PCIE Loopback enable XOR/ALL
0 = Enable (Note 3) 1= Disabled (default) = = = =
Sample low: the Integrated TPM will be disabled. Sample high: the MCH TPM enable strap is sampled low and the TPM Disable bit is clear, the Integrated TPM will be enable.
CFG[13:12]
LDA[3:0]#/FHW[3:0]# LAN_RXD[2:0] LDRQ[0] PME#
00 10 01 11
Reserve XOR mode Enabled ALLZ mode Enabled (Note 3) Disabled (default)
CFG16
FSB Dynamic ODT
0 = Dynamic ODT Disabled 1 = Dynamic ODT Enabled (Default) 0 = Normal operation(Default): Lane Numbered in Order
LDRQ[1]/GPIO23 PWRBTN#
CFG19
DMI Lane Reversal
Signal has weak internal pull-up. Sets bit 27 of MPC.LR(Device 28:Function 0:Offset D8)
SATALED#
SPI_CS1#/GPIO58/CLGPIO6
1 = Reverse Lanes DMI x4 mode[MCH -> ICH]:(3->0,2->1,1->2and0->3) DMI x2 mode[MCH -> ICH]:(3->0,2->1) 0 = Only Digital Display Port or PCIE is operational (Default) 1 =Digital display Port and PCIe are operting simulataneously via the PEG port 0 =No SDVO Card Present (Default) 1 = SDVO Card Present
If sampled high, the system is strapped to the "No Reboot" mode(ICH9 will disable the TCO Timer system reboot feature). The status is readable via the NO REBOOT bit. This signal should not be pull low unless using XOR Chain testing. Sampled low:the Flash Descriptor Security will be overridden. If high,the security measures will be in effect.This should only be enabled in manufacturing environments using an external pull-up resister.
SPI_MOSI SPI_MISO SPKR TACH_[3:0] TP[3] USB[11:0][P,N]
PULL-DOWN 20K PULL-UP 20K PULL-DOWN 20K PULL-UP 20K PULL-UP 20K PULL-DOWN 15K
CFG20
Digital Display Port (SDVO/DP/iHDMI) Concurrent with PCIe SDVO Present
TP3
XOR Chain Entrance. Rising Edge of PWROK. Flash Descriptor Security Override Strap Rising Edge of PWROK
SDVO_CTRLDATA
GPIO33/ HDA_DOCK _EN#
L_DDC_DATA
Local Flat Panel (LFP) Present
0 = LFP Disabled (Default) 1= LFP Card Present; PCIE disabled
NOTE: 1. All strap signals are sampled with respect to the leading edge of the (G)MCH Power OK (PWROK) signal. 2. iTPM can be disabled by a 'Soft-Strap' option in the Flash-decriptor section of the Firmware. This 'Soft-Strap' is activated only after enabling iTPM via CFG6. Only one of the CFG10/CFG/12/CFG13 straps can be enabled at any time.
SMBus
EMC2102
Thermal
USB Table
USB KBC
BAT_SCL
PCIE Routing
LANE1 LANE2 LANE3 LANE4 LANE5 LAN Atheros AR8114A MiniCard WLAN NC NC NC NC
Pair 0 1 2 3 4 5 6 7 8 9 10 11
Device USB1 NC NC MINIC1 WEBCAM NC NC Bluetooth NC USB2(High speed) NC CardReader

SMBC_ICH
BATTERY
LANE6
ICH9M
UMA Two Phase 2
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
9LPRS365BKLFT DDR
Size A3 Date:
Document Number
Reference
HM40-MV
Sheet 2 of
Rev
SB
51
Monday, November 24, 2008
3D3V_S0
1D05V_S0
3D3V_S0
3D3V_S0
1015 modify component size of R95

2
3D3V_48MPW R_S0
1 R95
0R2J-2-GP
SB 1124 add R302

3D3V_S0 3D3V_CLKPLL_S0
1 R302 2 Do Not Stuff 1 R80 2 1 1 1

C156 SCD1U16V2ZY-2GP C196 Do Not Stuff C173 Do Not Stuff 0R2J-2-GP
DY

1 1
C204 Do Not Stuff C179 SCD1U16V2ZY-2GP C152 Do Not Stuff

3D3V_CLKGEN_S0
1 R87 1
C1550R2J-2-GP SCD1U16V2ZY-2GP
2 1
C205 Do Not Stuff Do Not Stuff
DY
2
C165 Do Not Stuff
C149 SC4D7U10V5ZY-3GP
C176 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP
C221 Do Not Stuff
C227 SC1U16V3ZY-GP SC1U16V3ZY-GP
C226 SCD1U16V2ZY-2GP
4 3 2 1
DY
DY
2
DY
2
DY
2
DY
DY
2
SRN10KJ-6-GP RN61
5 6 7 8
3D3V_CLKGEN_S0 CLK_ICH14 PCLK_KBC
RN62 24 PCIE_REQ_LAN# 13 SATACLKREQ# 31 PCIE_REQ_MINI# 7 CLK_MCH_OE#
0915 add EC34 for EMI demand

PCLK_ICH CLK48_ICH CLK48_5159
1 2 3 4
8 PCIE_REQ_LAN#_R 7 PCLKCLK0 6 PCIE_REQ_MINI#_R 5 PCLKCLK1

SRN470J-3-GP
3D3V_48MPW R_S0
3D3V_CLKPLL_S0
EC31
EC62
EC66
EC33
1
EC34
Do Not Stuff Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
SB 1120 add RN61 and RN62 CL=20pF0.2pF SB 1120 modify RN61 and RN62 1126 modify RN61 and RN62
C229 SB SC33P50V2JN-3GP GEN_XTAL_IN 1 2
SB 1127 swap the nets of
RN61 and RN62

4 16 9 46 62 23
U14
DY
DY
DY
DY
DY
19 27 43 52 33 56
VDDREF VDD48 VDDPCI VDDSRC VDDCPU VDDPLL3
VDD96_IO VDDPLL3_IO VDDSRC_IO VDDSRC_IO VDDSRC_IO VDDCPU_IO
PCLK_FW H
1
EC25
Do Not Stuff
C230 SC33P50V2JN-3GP
3
4,7
CPU_SEL2
X4 X-14D31818M-35GP
82.30005.891 2nd = 82.30005.951
R91 0R2J-2-GP 2 1
CPUT0 CPUC0
GEN_XTAL_OUT
3 2
X1 X2
CPUT1_F CPUC1_F
58 57 54 53 51 50 48 47 41 42 40 39 37 38 34 35 31 32 28 29 24 25 20 21
CLK_MCH_BCLK 6 CLK_MCH_BCLK# 6 CLK_PCIE_LAN 24 CLK_PCIE_LAN# 24
NB
DY
GEN_XTAL_OUT_R
RN20
30 13
CLK48_5159 CLK48_ICH CPU_SEL0
1 2 2
4 3
CLK48 17
CPUT2_ITP/SRCT8 CPUC2_ITP/SRCC8
LAN
USB_48MHZ/FSLA
4,7
R88
SRN22-3-GP 1 2K2R2J-2-GP
13 PM_STPPCI# 13 PM_STPCPU#
45 44
SRCT7/CR#_F SRCC7/CR#_E SRCT6 SRCC6
PCIE_REQ_LAN#_R
SB 1126 add the net(PCIE_REQ_LAN#)
61 60
CLK_CPU_BCLK 4 CLK_CPU_BCLK# 4
CPU
PCI_STOP# CPU_STOP#
CLK_PCIE_ICH 13 CLK_PCIE_ICH# 13
SB DMI
3D3V_S0
3D3V_S0
15,16,17 SMBC_ICH 15,16,17 SMBD_ICH
7 6
SCLK SDATA
SRCT10 SRCC10
SB 1120 swap these nets(CLK_MCH_3GPLL,CLK_MCH_3GPLL#, CLK_PCIE_MINI1,CLK_PCIE_MINI1#) SB
RN28 SRN10KJ-6-GP
2 R89
DY
13 CLK_PW RGD 1 Do Not Stuff PCLKCLK0 PCLKCLK1 PCLKCLK2
8 7 6 5
63
CK_PWRGD/PD#
SRCT11/CR#_H SRCC11/CR#_G SRCT9 SRCC9
PCIE_REQ_MINI#_R
1126 add the net(PCIE_REQ_MINI#)
1 2 3 4
RN23 PCLKCLK2 CPU_SEL2_R PCLKCLK4 PCLKCLK5 13 33 13 CLK_ICH14 PCLK_KBC PCLK_ICH
1 2 3 4
SRN33J-7-GP
8 7 6 5
CPU_SEL2_R PCLKCLK3 PCLKCLK4 PCLKCLK5
8 10 11 12 13 14
CLK_PCIE_MINI1 31 CLK_PCIE_MINI1# 31 CLK_MCH_3GPLL 7 CLK_MCH_3GPLL# 7
MINI1 NB CLK
SB 1120 move these nets (CLK_PCIE_MINI1,CLK_PCIE_MINI1#)
PCI0/CR#_A PCI1/CR#_B PCI2/TME PCI3 PCI4/27_SELECT PCI_F5/ITP_EN
SRCT4 SRCC4 SRCT3/CR#_C SRCC3/CR#_D SRCT2/SATAT SRCC2/SATAC
4,7 34
CPU_SEL1 PCLK_FW H
CPU_SEL2_R ER5
64 5 55
CLK_PCIE_SATA 12 CLK_PCIE_SATA# 12 DREFSSCLK 7 DREFSSCLK# 7 DREFCLK 7 DREFCLK# 7
SB SATA NB CLK NB CLK (96 MHz)
FSLB/TEST_MODE REF0/FSLC/TEST_SEL NC#55 GND GNDSRC GNDSRC GNDSRC GNDCPU GND GND48 GNDPCI GNDREF 27MHZ_NONSS/SRCT1/SE1 27MHZ_SS/SRCC1/SE2 SRCT0/DOTT_96 SRCC0/DOTC_96
1 PCLKCLK3 Do Not Stuff
ICS9LPRS365BKLFT setting table PIN NAME DESCRIPTION PCI0/CR#_A

Byte 5, bit 7 0 = PCI0 enabled (default) 1= CR#_A enabled. Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair Byte 5, bit 6 0 = CR#_A controls SRC0 pair (default), 1= CR#_A controls SRC2 pair Byte 5, bit 5 0 = PCI1 enabled (default) 1= CR#_B enabled. Byte 5, bit 6 controls whether CR#_B controls SRC1 or SRC4 pair Byte 5, bit 4 0 = CR#_B controls SRC1 pair (default) 1= CR#_B controls SRC4 pair 0 = Overclocking of CPU and SRC Allowed 1 = Overclocking of CPU and SRC NOT allowed 3.3V PCI clock output
18 15 1
22 30 36 49 59 26
71.09365.A03 2nd = 71.08513.003
65
ICS9LPRS365BKLFT-GP-U
GND
1014 add ER5 for EMI deamnd
DY
SEL2 SEL1 SEL0 FSC FSB FSA PIN NAME SRCC3/CR#_D SRCC7/CR#_E DESCRIPTION
Byte 5, bit 1 0 = SRC3 enabled (default) 1= CR#_D enabled. Byte 5, bit 0 controls whether CR#_D controls SRC1 or SRC4 pair Byte 5, bit 0 0 = CR#_D controls SRC1 pair (default) 1= CR#_D controls SRC4 pair Byte 6, bit 7 0 = SRC7# enabled (default) 1= CR#_F controls SRC6 Byte 6, bit 6 0 = SRC7 enabled (default) 1= CR#_F controls SRC8 Byte 6, bit 5 0 = SRC11# enabled (default) 1= CR#_G controls SRC9 Title Byte 6, bit 4 0 = SRC11 enabled (default) 1= CR#_H controls SRC10
CPU
100M 133M 166M 200M 266M
FSB
X 533M 667M 800M 1066M
1
PCI1/CR#_B PCI2/TME PCI3

1
1 0 0 0 0
UMA Two Phase 2
0 0 1 1 0
1 1 1 0 0
PCI4/27M_SEL PCI_F5/ITP_EN SRCT3/CR#_C
0 = Pin24 as SRC-1, Pin25 as SRC-1#, Pin20 as DOT96, Pin21 as DOT96# 1 = Pin24 as 27MHz, Pin25 as 27MHz_SS, Pin20 as SRC-0, Pin21 as SRC-0# 0 =SRC8/SRC8# 1 = ITP/ITP# Byte 5, bit 3 0 = SRC3 enabled (default) 1= CR#_C enabled. Byte 5, bit 2 controls whether CR#_C controls SRC0 or SRC2 pair Byte 5, bit 2 0 = CR#_C controls SRC0 pair (default), 1= CR#_C controls SRC2 pair
SRCT7/CR#_F SRCC11/CR#_G SRCT11/CR#_H
Wistron Corporation
Clock Generator
Document Number Rev
Size Date:
HM40-MV
Monday, December 01, 2008 Sheet
E
SB
3 of 51
6 H_A#[35..3] H_A#[35..3] H_DINV#[3..0] U33A 1 OF 4 H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 6 6 H_ADSTB#0 H_REQ#[4..0] H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 H_DINV#[3..0] H_DSTBN#[3..0] H_DSTBP#[3..0] H_D#[63..0] 6 6 6 6
4
1 ADS# BNR# BPRI# H1 E2 G5 H5 F21 E1 F1 D20 B3 H4 C1 F3 F4 G3 G2 G6 E4

H_RS#0 H_RS#1 H_RS#2
H_DSTBN#[3..0] TP11 Do Not Stuff H_ADS# H_BNR# H_BPRI# 6 6 6 1D05V_S0 H_DSTBP#[3..0] H_D#[63..0]
J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1 K3 H2 K2 J3 L1
A3# A4# A5# A6# A7# A8# A9# A10# A11# A12# A13# A14# A15# A16# ADSTB0# REQ0# REQ1# REQ2# REQ3# REQ4#
Side Band Non GTL

6 12 12 12 12 12 12 12
DATA GRP0
Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1 A6 A5 C4 D5 C6 B4 A3 M4 N5 T2 V3 B2 C3 D2 D22 D3 F6 A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31# A32# A33# A34# A35# ADSTB1# A20M# FERR# IGNNE# STPCLK# LINT0 LINT1 SMI# RSVD#M4 RSVD#N5 RSVD#T2 RSVD#V3 RSVD#B2 RSVD#C3 RSVD#D2 RSVD#D22 RSVD#D3 RSVD#F6 KEY_NC
BGA479-SKT6-GPU7
HIT# HITM#
H_HIT# H_HITM#
6 6
XDP/ITP SIGNALS
BPM0# BPM1# BPM2# BPM3# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR#
AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20
DY
H_THERMDC
XDP_BPM#5 XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST# XDP_DBRESET#
1D05V_S0
C438 Do Not Stuff
DATA GRP2
ADDR GROUP 0 ADDR GROUP 1
CONTROL
DEFER# DRDY# DBSY# BR0# IERR# INIT# LOCK# RESET# RS0# RS1# RS2# TRDY#
H_DEFER# 6 H_DRDY# 6 H_DBSY# 6 H_BREQ#0 6 H_IERR# H_INIT# 12
R64 56R2J-4-GP
Place testpoint on H_IERR# with a GND 0.1" away
H_LOCK# 6 H_CPURST# 6,48 H_RS#[2..0]
U33B 2 OF 4 6 H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15
H_TRDY#
H_THERMDA
R63 68R2-GP
6 6 6
H_DSTBN#0 H_DSTBP#0 H_DINV#0
E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25
D0# D1# D2# D3# D4# D5# D6# D7# D8# D9# D10# D11# D12# D13# D14# D15# DSTBN0# DSTBP0# DINV0# D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# DSTBN1# DSTBP1# DINV1# GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 BSEL0 BSEL1 BSEL2
D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# DSTBN2# DSTBP2# DINV2# D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63# DSTBN3# DSTBP3# DINV3# COMP0 COMP1 COMP2 COMP3
Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22
H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47
H_DSTBN#2 6 H_DSTBP#2 6 H_DINV#2 6
THERMAL
H_ADSTB#1 H_A20M# H_FERR# H_IGNNE# H_STPCLK# H_INTR H_NMI H_SMI#
THERMTRIP#
C7
PM_THRMTRIP-A# 7,12,39
HCLK
BCLK0 BCLK1
A22 A21
CLK_CPU_BCLK 3 CLK_CPU_BCLK# 3 PM_THRMTRIP# should connect to ICH9 and MCH without T-ing ( No stub) Layout Note: "CPU_GTLREF0" 0.5" max length.
1D05V_S0
DATA GRP3
PROCHOT# THRMDA THRMDC
D21 CPU_PROCHOT# A24 B25
H_THERMDA 32 H_THERMDC 32
1 R62
DY
CPU_PROCHOT#_R
41
Do Not Stuff
RESERVED
R179 1KR2F-3-GP
6 6 6
H_DSTBN#1 H_DSTBP#1 H_DINV#1
N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24
AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20 R26 U26 AA1 Y1 E5 B5 D24 D6 D7 AE6
DATA GRP1
ICH ICH
H_DSTBN#3 6 H_DSTBP#3 6 H_DINV#3 6 COMP0 COMP1 COMP2 COMP3 R53 R51 R45 R44
CPU_GTLREF0
R181 2KR2F-3-GP
DY C352 Not Stuff Do

Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff 3,7 3,7 3,7
TP18 TP44 TP60
Do Not Stuff
TP20
RSVD_CPU_11
B1
AD26 TEST1 C23 TEST2 D25 RSVD_CPU_12 C24 1 TEST4 AF26 1RSVD_CPU_13 AF1 1RSVD_CPU_14 A26 B22 B23 C21
MISC
1 1 1 1
2 2 2 2
27D4R2F-L1-GP 54D9R2F-L1-GP 27D4R2F-L1-GP 54D9R2F-L1-GP
62.10079.001
2nd: 62.10053.401
1D05V_S0
CPU_SEL0 CPU_SEL1 CPU_SEL2
DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI#
H_DPRSTP# 7,12,41 H_DPSLP# 12 H_DPW R# 6 H_PW RGD 12,39,48 H_CPUSLP# 6 PSI# 41
BGA479-SKT6-GPU7
62.10079.001
Follow Demo Circuit

XDP_TMS XDP_TDI XDP_BPM#5 R50 R48 R43
1 1 1
2 54D9R2F-L1-GP 2 54D9R2F-L1-GP 2 54D9R2F-L1-GP 1 R65 1 R215 2 C343
DY DY
2 TEST1 Do Not Stuff 2

TEST2 Do Not Stuff
Net "TEST4" as short as possible, make sure "TEST4" routing is reference to GND and away other noisy signals
Layout Note: Comp0, 2 connect with Zo=27.4 ohm, make trace length shorter than 0.5" . Comp1, 3 connect with Zo=55 ohm, make trace length shorter than 0.5" .
H_CPURST# XDP_TCK
1
R213 1 R41 R42
DY
2 Do Not Stuff 2 54D9R2F-L1-GP 2 54D9R2F-L1-GP
1 1
TEST4 1 Do Not Stuff
XDP_TRST#
DY
3D3V_S0 UMA Two Phase 2
1
All place within 2" to CPU

XDP_DBRESET# R60
DY
2 Do Not Stuff
1D05V_S0 Title
Wistron Corporation
XDP_TDO
R47
DY
2 Do Not Stuff
Size Date: Document Number
CPU (1 of 2)
Sheet
E
Rev
HM40-MV
Monday, December 01, 2008 4 of
A B C D
SB
51
U33D 4 OF 4 VCC_CORE
4
VCC_CORE
VCC_CORE
VCC_CORE U33C 3 OF 4
VCC_CORE
C54
C97
C91
C53
C59 Do Not Stuff
C93 Do Not Stuff
C96 Do Not Stuff
C52 Do Not Stuff
A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18
Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff SC10U6D3V5MX-3GP SC10U6D3V5MX-3GP SC10U6D3V5MX-3GP SC10U6D3V5MX-3GP SC10U6D3V5MX-3GP SC10U6D3V5MX-3GP SC10U6D3V5MX-3GP SC10U6D3V5MX-3GP SC10U6D3V5MX-3GP SC10U6D3V5MX-3GP SC10U6D3V5MX-3GP SC10U6D3V5MX-3GP
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20 G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21 B26 C26 AD6 AF5 AE5 AF4 AE3 AF3 AE2 AF7 AE7
TC6 ST900U2D5VM-1-GP Do Not Stuff TP46
DY
DY
DY
DY
DY
DY
2
DY
2
DY
2
NEC
77.E9071.011
VCC_CORE
SB
1 1 1 1 1 1 1 1
C92 C70 C90 C61 C383 C382 C384
1126 add C48,C49,C71,C79...

1 1 1 1 1
C381 C48 C62 C80 C49 C71
C79
CAP
CAP
CAP
CAP
CAP
CAP
1D05V_S0
VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCA VCCA VID0 VID1 VID2 VID3 VID4 VID5 VID6 VCCSENSE VSSSENSE
1D05V_S0
C84
C68
DY
C78 SCD1U10V2KX-4GP SCD1U10V2KX-4GP
C63 Do Not Stuff
C65 SCD1U10V2KX-4GP
C66 SC4D7U6D3V3KX-GP
C446 Do Not Stuff
layout note: "1D5V_VCCA_S0" as short as possible

1D5V_S0 1D5V_VCCA_S0 L10
DY
DY
1 1
H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID6 H_VID[6..0] VCC_CORE 41 C420 Do Not Stuff
C429 SC10U6D3V5MX-3GP
PBY160808T-121Y-GP
DY
68.00206.021
2nd = 68.00230.041
R38 100R2F-L1-GP-U
VCC_SENSE 41 VSS_SENSE 41
Layout Note: R39 100R2F-L1-GP-U VCCSENSE and VSSSENSE lines should be of equal length.
BGA479-SKT6-GPU7
62.10079.001
2
Layout Note: Provide a test point (with no stub) to connect a differential probe between VCCSENSE and VSSSENSE at the location where the two 54.9ohm resistors terminate the 55 ohm transmission line.
1
A4 A8 A11 A14 A16 A19 A23 AF2 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25
2 3
1 4
Do Not Stuff
Do Not Stuff
SCD1U10V2KX-4GP
Do Not Stuff
Do Not Stuff
TP45
1 1
TP48 TP21
1 1
TP61 TP43
BGA479-SKT6-GPU7
62.10079.001
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Date:
A B C D
Document Number
CPU (2 of 2)
Sheet
E
Rev
HM40-MV
Monday, December 01, 2008 5 of 51
SB
U35A 4 H_D#[63..0] H_D#[63..0] H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 1 OF 10 H_A#[35..3]
H_SWING routing Trace width and Spacing use 10 / 20 mil H_SWING Resistors and Capacitors close MCH 500 mil ( MAX )
C478 SCD1U10V2KX-4GP
1D05V_S0
R239 221R2F-2-GP
H_SW ING
R238 100R2F-L1-GP-U
H_RCOMP routing Trace width and Spacing use 10 / 20 mil

1 R226 2 24D9R2F-L-GP
H_RCOMP
HOST
H_ADS# H_ADSTB#_0 H_ADSTB#_1 H_BNR# H_BPRI# H_BREQ# H_DEFER# H_DBSY# HPLL_CLK HPLL_CLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY# H12 B16 G17 A9 F11 G12 E9 B10 AH7 AH6 J11 F9 H9 E12 H11 C9
H_ADS# 4 H_ADSTB#0 4 H_ADSTB#1 4 H_BNR# 4 H_BPRI# 4 H_BREQ#0 4 H_DEFER# 4 H_DBSY# 4 CLK_MCH_BCLK 3 CLK_MCH_BCLK# 3 H_DPW R# 4 H_DRDY# 4 H_HIT# 4 H_HITM# 4 H_LOCK# 4 H_TRDY# 4 H_DINV#[3..0]
Place them near to the chip ( < 0.5")
F2 G8 F8 E6 G2 H6 H2 F6 D4 H3 M9 M11 J1 J2 N12 J6 P2 L2 R2 N9 L6 M5 J3 N2 R1 N5 N6 P13 N8 L7 N10 M3 Y3 AD14 Y6 Y10 Y12 Y14 Y7 W2 AA8 Y9 AA13 AA9 AA11 AD11 AD10 AD13 AE12 AE9 AA2 AD8 AA3 AD3 AD7 AE14 AF3 AC1 AE3 AC3 AE11 AE8 AG2 AD6
H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63
H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35
A14 C15 F16 H13 C18 M16 J13 P16 R16 N17 M13 E17 P17 F17 G20 B19 J16 E20 H16 J20 L17 A17 B17 L16 C21 J17 H20 B18 K17 B20 F21 K21 L20
H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35
H_A#[35..3]
H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3 H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3 H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3 H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4 H_RS#_0 H_RS#_1 H_RS#_2
J8 L3 Y13 Y1 L10 M7 AA5 AE6 L9 M8 AA6 AE5 B15 K13 F13 B13 B14 B6 F12 C8
H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 H_DSTBN#[3..0] H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#[3..0] H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 H_REQ#[4..0] H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_RS#[2..0] H_RS#0 H_RS#1 H_RS#2
H_DINV#[3..0]
H_DSTBN#[3..0]
H_DSTBP#[3..0]
1D05V_S0
H_REQ#[4..0]
H_SW ING H_RCOMP R241 1KR2F-3-GP 4,48 H_CPURST# 4 H_CPUSLP#
C5 E3 C12 E11 A11 B11
H_SWING H_RCOMP H_CPURST# H_CPUSLP# H_AVREF H_DVREF
H_RS#[2..0]
1 1
H_AVREF
R240 2KR2F-3-GP
CANTIGA-GM-GP-U-NF
71.CNTIG.00U
2
UMA Two Phase 2
Wistron Corporation
5 4 3 2
Document Number
Cantiga (1 of 6)_HOST
HM40-MV
Sheet
1
Rev
SB
6 of 51
W ednesday, November 26, 2008
1D8V_S3 R251 1KR2F-3-GP 2 M36 N36 R33 T33 AH9 AH10 AH12 AH13 K12 AL34 AK34 AN35 AM35 T24 B31 B2 M1 AY21 1
U35B RESERVED#M36 RESERVED#N36 RESERVED#R33 RESERVED#T33 RESERVED#AH9 RESERVED#AH10 RESERVED#AH12 RESERVED#AH13 RESERVED#K12 RESERVED#AL34 RESERVED#AK34 RESERVED#AN35 RESERVED#AM35 RESERVED#T24
2 OF 10 U35C 3 OF 10 R99 PEG_COMPI PEG_COMPO PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15 PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8 PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15 PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9 PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15 PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8 PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15 T37 T36 H44 J46 L44 L40 N41 P48 N44 T43 U43 Y43 Y48 Y36 AA43 AD37 AC47 AD39 H43 J44 L43 L41 N40 P47 N43 T42 U42 Y42 W47 Y37 AA42 AD36 AC48 AD40 J41 M46 M47 M40 M42 R48 N38 T40 U37 U40 Y40 AA46 AA37 AA40 AD43 AC46 J42 L46 M48 M39 M43 R47 N37 T39 U36 U39 Y39 Y46 AA36 AA39 AD42 AD46 PEG_CMP 2 1 49D9R2F-GP 1D05V_S0
DDR CLK/ CONTROL/COMPENSATION
SA_CK_0 SA_CK_1 SB_CK_0 SB_CK_1 SA_CK#_0 SA_CK#_1 SB_CK#_0 SB_CK#_1 SA_CKE_0 SA_CKE_1 SB_CKE_0 SB_CKE_1 SA_CS#_0 SA_CS#_1 SB_CS#_0 SB_CS#_1 SA_ODT_0 SA_ODT_1 SB_ODT_0 SB_ODT_1 SM_RCOMP SM_RCOMP# SM_RCOMP_VOH SM_RCOMP_VOL SM_VREF SM_PWROK SM_REXT SM_DRAMRST#
AP24 AT21 AV24 AU20 AR24 AR21 AU24 AV20 BC28 AY28 AY36 BB36 BA17 AY16 AV16 AR13 BD17 AY17 BF15 AY13 BG22 BH21 BF28 BH28 AV42 AR36 BF17 BC36 B38 A38 E41 F41 F43 E43 M_RCOMPP M_RCOMPN SM_RCOMP_VOH SM_RCOMP_VOL
M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR2 M_CLK_DDR3 M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3 M_CKE0 M_CKE1 M_CKE2 M_CKE3 M_CS0# M_CS1# M_CS2# M_CS3# M_ODT0 M_ODT1 M_ODT2 M_ODT3 17 17 16 16 17 17 16 16 17 17 16 16
17 17 16 16 17 17 16 16
18 L_BKLTCTL 33 GMCH_BL_ON
L_BKLTCTL GMCH_BL_ON LCTLA_CLK LCTLB_DATA CLK_DDC_EDID DAT_DDC_EDID GMCH_LCDVDD_ON LIBG 1 L_LVBG
L32 G32 M32 M33 K33 J33 M29 C44 B43 E37 E38 C41 C40 B37 A37 H47 E46 G40 A40 H48 D45 F40 B40 A41 H38 G37 J37 B42 G38 F37 K37
L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK L_CTRL_DATA L_DDC_CLK L_DDC_DATA L_VDD_EN LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2 LVDSA_DATA#_3 LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2 LVDSA_DATA_3 LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2 LVDSB_DATA#_3 LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2 LVDSB_DATA_3
18 CLK_DDC_EDID 18 DAT_DDC_EDID 18 GMCH_LCDVDD_ON TP73 Do Not Stuff
Close to GMCH as 500 mils.
SM_RCOMP_VOH 1 1 1
D
C489
R250 3K01R2F-3-GP 2
C487 SCD01U16V2KX-3GP SC2D2U6D3V3MX-1-GP SM_RCOMP_VOL
RSVD
RESERVED#B31 RESERVED#B2 RESERVED#M1 RESERVED#AY21
18 GMCH_TXACLK18 GMCH_TXACLK+
LVDS
BG23 BF23 BH18 BF18
RESERVED#BG23 RESERVED#BF23 RESERVED#BH18 RESERVED#BF18
18 GMCH_TXAOUT0+ 18 GMCH_TXAOUT1+ 18 GMCH_TXAOUT2+ DDR_VREF_S3
layout take note
SM_REXT R243 1 TP_SM_DRAMRST# DREFCLK DREFCLK# DREFSSCLK DREFSSCLK#
2 2 499R2F-2-GP TP36Do Not Stuff
0912 delete GMCH_TXB*
1D8V_S3
CLK
R247 80D6R2F-L-GP 2
R246 80D6R2F-L-GP 2
C
PEG_CLK PEG_CLK# CLK_MCH_3GPLL 3 CLK_MCH_3GPLL# 3 TVA_DAC TVB_DAC TVC_DAC F25 H25 K25 H24 TVA_DAC TVB_DAC TVC_DAC TV_RTN M_RCOMPP
M_RCOMPN
DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3 DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3
AE41 AE37 AE47 AH39 AE40 AE38 AE48 AH40 AE35 AE43 AE46 AH42 AD35 AE44 AF46 AH43
DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3
DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3
13 13 13 13
C31 E32
TV_DCONSEL_0 TV_DCONSEL_1
3,4 3,4 3,4
CPU_SEL0 CPU_SEL1 CPU_SEL2
GRAPHICS VID
3D3V_S0
R98
DY
2 Do Not Stuff
T25 R25 P25 P20 P24 C25 N24 M24 E21 C23 C24 N21 P21 T21 R20 M20 L21 H21 P29 R28 CFG20 T28
CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20
DMI_TXP0 13 DMI_TXP1 13 DMI_TXP2 13 DMI_TXP3 13
PCI-EXPRESS
DPLL_REF_CLK DPLL_REF_CLK# DPLL_REF_SSCLK DPLL_REF_SSCLK#
DREFCLK 3 DREFCLK# 3 DREFSSCLK 3 DREFSSCLK# 3
GRAPHICS
R248 1KR2F-3-GP 2
C483 C484 SCD01U16V2KX-3GP SC2D2U6D3V3MX-1-GP
18 GMCH_TXAOUT018 GMCH_TXAOUT118 GMCH_TXAOUT2-
TV
DMI
DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3 DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3
DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3
DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3
13 13 13 13
19
GMCH_BLUE
GMCH_BLUE
E28
CRT_BLUE
19 GMCH_GREEN 19 GMCH_RED
GMCH_GREEN GMCH_RED
G28 J28
CRT_GREEN CRT_RED
CFG
DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3
DMI_RXP0 13 DMI_RXP1 13 DMI_RXP2 13 DMI_RXP3 13
VGA
G29 H32 J32 J29 E29 L29
CRT_IRTN
19 GMCH_DDCCLK 19 GMCH_DDCDATA 19 GMCH_HSYNC 19 GMCH_VSYNC
GMCH_DDCCLK 2 1
3 4
GMCH_DDCDATA GMCH_HS GMCH_VS
13 PM_SYNC# 4,12,41 H_DPRSTP# 13,39 PWROK 13,24,30,31,33,34 PLT_RST1# 2 R110 1 R211 1 Do Not Stuff 2 100R2J-2-GP C147 Do Not Stuff 1
PM_SYNC# H_DPRSTP# PM_EXTTS#0 PM_EXTTS#1 PWROK_GD RSTIN# PM_THRMTRIP-A# PM_DPRSLPVR
R29 B7 N33 P32 AT40 AT11 T20 R32
PM_SYNC# PM_DPRSTP# PM_EXT_TS#_0 PM_EXT_TS#_1 PWROK RSTIN# THERMTRIP# DPRSLPVR
GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4
B33 B32 G33 F33 E33
RN21 SRN33J-5-GP-U 1 2 CRT_IREF R253 1K02R2F-1-GP
CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF CRT_VSYNC
CANTIGA-GM-GP-U-NF
71.CNTIG.00U FOR Cantiga: 1.02k_1% ohm Teenah: 1.3k ohm

1D05V_S0 2 R93 1KR2F-3-GP 1
0912 add these parts for EMI demand 1017 delete these parts(EC208~EC210)
PM
GFX_VR_EN
C34
CRT_IREF routing Trace width use 20 mil
DY
4,12,39 PM_THRMTRIP-A# 13,41 PM_DPRSLPVR

B
3D3V_S0
RN29 PM_EXTTS#0 PM_EXTTS#1 4 3 1 2 SRN10KJ-5-GP
CANTIGA-GM-GP-U-NF
HDA
BG48 BF48 BD48 BC48 BH47 BG47 BE47 BH46 BF46 BG45 BH44 BH43 BH6 BH5 BG4 BH3 BF3 BH2 BG2 BE2 BG1 BF1 BD1 BC1 F1 A47
NC#BG48 NC#BF48 NC#BD48 NC#BC48 NC#BH47 NC#BG47 NC#BE47 NC#BH46 NC#BF46 NC#BG45 NC#BH44 NC#BH43 NC#BH6 NC#BH5 NC#BG4 NC#BH3 NC#BF3 NC#BH2 NC#BG2 NC#BE2 NC#BG1 NC#BF1 NC#BD1 NC#BC1 NC#F1 NC#A47
CL_CLK CL_DATA CL_PWROK CL_RST# CL_VREF
ME
AH37 AH36 AN36 AJ35 AH34
CLPWROK_MCH 2 R111 1 Do Not Stuff MCH_CLVREF
CL_CLK0 13 CL_DATA0 13 PWROK 13,39 CL_RST#0 13
1014 swap these nets

RN14 GMCH_BLUE R92 511R2F-2-GP GMCH_GREEN GMCH_RED 1 2 3 4 SRN150F-1-GP 8 7 6 5
C231 SCD1U10V2KX-4GP DDPC_CTRLCLK DDPC_CTRLDATA SDVO_CTRLCLK SDVO_CTRLDATA CLKREQ# ICH_SYNC# TSATN# N28 M28 G36 E36 K36 H36 B12 1 Do Not Stuff TP34 CLK_MCH_OE# 3 MCH_ICH_SYNC# 13 R242 MCH_TSATN# 2 1 56R2J-4-GP HDA_BCLK HDA_RST# HDA_SDI HDA_SDO HDA_SYNC B28 B30 B29 C29 A28 1D05V_S0
MISC
NC
FOR Cantiga:500 ohm Teenah: 392 ohm
RN15 TVA_DAC TVB_DAC TVC_DAC 1 2 3 4 SRN75J-1-GP 8 7 6 5
3D3V_S0 RN32 LCTLB_DATA LCTLA_CLK CLK_MCH_OE# 5 6 7 8 4 3 2 1 SRN10KJ-6-GP
71.CNTIG.00U
RN22
Pin Name
Strap Description
Configuration
GMCH_LCDVDD_ON GMCH_BL_ON
1 2 3 4
8 7 6 5
A
CFG20
Digital DisplayPort (SDVO/DP/HDMI) Concurrent with PCIE
Low = Only digital DisplayPort (SDVO/DP/HDMI) or PCIE is operational (default) High = Digital DisplayPort (SDVO/DP/HDMI) and PCIE are operating simultaneously via the PEG port
LIBG
SRN100KJ-8-GP-U R103 1 2 2K37R2F-GP
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
Cantiga (2 of 6)_DMI/PM/CFG
Size Date:
5 4 3 2
Document Number
Rev
HM40-MV
Monday, December 01, 2008
1
SB
Sheet 7 of 51
U35D 17 M_A_DQ[63..0] M_A_DQ[63..0] M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63 4 OF 10 U35E 5 OF 10
DDR
DDR
SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14
BA21 BC24 BG24 BH24 BG25 BA24 BD24 BG27 BF25 AW24 BC21 BG26 BH26 BH17 AY25
M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14
M_A_A[14..0] 17
SYSTEM
M_A_DQS#[7..0] M_A_DQS#[7..0] 17 M_B_DQS#[7..0] M_B_DQS#[7..0] 16
AJ38 AJ41 AN38 AM38 AJ36 AJ40 AM44 AM42 AN43 AN44 AU40 AT38 AN41 AN39 AU44 AU42 AV39 AY44 BA40 BD43 AV41 AY43 BB41 BC40 AY37 BD38 AV37 AT36 AY38 BB38 AV36 AW36 BD13 AU11 BC11 BA12 AU13 AV13 BD12 BC12 BB9 BA9 AU10 AV9 BA11 BD9 AY8 BA6 AV5 AV7 AT9 AN8 AU5 AU6 AT5 AN10 AM11 AM5 AJ9 AJ8 AN12 AM13 AJ11 AJ12
SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63
SA_BS_0 SA_BS_1 SA_BS_2 SA_RAS# SA_CAS# SA_WE#
BD21 BG18 AT25 BB20 BD20 AY20
16 M_B_DQ[63..0] M_A_BS#0 17 M_A_BS#1 17 M_A_BS#2 17 M_A_RAS# 17 M_A_CAS# 17 M_A_W E# 17
M_A_DM[7..0]
M_A_DQS[7..0] M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7
SYSTEM
SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7
AJ44 AT44 BA43 BC37 AW12 BC8 AU8 AM7 AJ43 AT43 BA44 BD37 AY12 BD8 AU9 AM8
M_A_DQS[7..0] 17
SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7
AM37 AT41 AY41 AU39 BB12 AY6 AT7 AJ5
M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7
M_A_DM[7..0] 17
M_A_A[14..0]
M_B_DQ[63..0] M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63
AK47 AH46 AP47 AP46 AJ46 AJ48 AM48 AP48 AU47 AU46 BA48 AY48 AT47 AR47 BA47 BC47 BC46 BC44 BG43 BF43 BE45 BC41 BF40 BF41 BG38 BF38 BH35 BG35 BH40 BG39 BG34 BH34 BH14 BG12 BH11 BG8 BH12 BF11 BF8 BG7 BC5 BC6 AY3 AY1 BF6 BF5 BA1 BD3 AV2 AU3 AR3 AN2 AY2 AV1 AP3 AR1 AL1 AL2 AJ1 AH1 AM2 AM3 AH3 AJ3
SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63
SB_BS_0 SB_BS_1 SB_BS_2 SB_RAS# SB_CAS# SB_WE#
BC16 BB17 BB33 AU17 BG16 BF14
M_B_BS#0 16 M_B_BS#1 16 M_B_BS#2 16 M_B_RAS# 16 M_B_CAS# 16 M_B_W E# 16

D
M_B_DM[7..0]
SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7 SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7
AM47 AY47 BD40 BF35 BG11 BA3 AP1 AK2 AL47 AV48 BG41 BG37 BH9 BB2 AU1 AN6 AL46 AV47 BH41 BH37 BG9 BC2 AT2 AN5
M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7 M_B_DQS[7..0] M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7 M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14
M_B_DM[7..0] 16
M_B_DQS[7..0] 16
MEMORY
MEMORY
M_B_A[14..0]
SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14
AV17 BA25 BC25 AU25 AW25 BB28 AU28 AW28 AT33 BD33 BB16 AW33 AY33 BH15 AU33
M_B_A[14..0] 16
CANTIGA-GM-GP-U-NF
CANTIGA-GM-GP-U-NF
71.CNTIG.00U
71.CNTIG.00U
Wistron Corporation
5 4 3 2
Document Number
Cantiga (3 of 6)_DDR
HM40-MV
Sheet
1
Rev
SB
8 of 51
1D8V_S3 U35G
7 OF 10
1D05V_S0
667MTS 2400mA 800MTS 3000mA

D
AP33 AN33 BH32 BG32 BF32 BD32 BC32 BB32 BA32 AY32 AW32 AV32 AU32 AT32 AR32 AP32 AN32 BH31 BG31 BF31 BG30 BH29 BG29 BF29 BD29 BC29 BB29 BA29 AY29 AW29 AV29 AU29 AT29 AR29 AP29 BA36 BB24 BD16 BB21 AW16 AW13 AT13
VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC
1D05V_S0
FOR VCC SM
1D8V_S3
C207 Do Not Stuff Do Not Stuff 2 2
C203 SCD1U10V2KX-4GP 2
C225 SCD1U10V2KX-4GP SCD1U10V2KX-4GP 2
C202 Do Not Stuff
C208 SC10U6D3V5MX-3GP SC10U6D3V5MX-3GP 2 2
C210 Do Not Stuff
C211 SC10U6D3V5MX-3GP 2
DY
DY
DY
VCC GFX
Place on the Edge
VCC SM LF
VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF
AV44 SM_LF1_GMCH BA37 SM_LF2_GMCH AM40 SM_LF3_GMCH AV21 SM_LF4_GMCH AY5 SM_LF5_GMCH AM10 SM_LF6_GMCH BB13 SM_LF7_GMCH 1 1 1 1 1 1 C153 C140 C136 C172 C246 C235 1 C253 SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD22U10V2KX-1GP SCD22U10V2KX-1GP SCD47U16V3ZY-3GP SC1U10V3KX-3GP SC1U10V3KX-3GP
CANTIGA-GM-GP-U-NF
SB
1118 delete TC27

71.CNTIG.00U
TP33 TP32
VCC_AXG_SENSE VSS_AXG_SENSE CANTIGA-GM-GP-U-NF
SCD22U10V2KX-1GP 2
VCC NCTF
Coupling CAP
G9 1 2 VCC_GMCH_35 T32 VCC Do Not Stuff Y26 AE25 AB25 AA25 AE24 AC24 AA24 Y24 AE23 AC23 AB23 AA23 AJ21 AG21 AE21 AC21 AA21 Y21 AH20 AF20 AE20 AC20 AB20 AA20 T17 T16 AM15 AL15 AE15 AJ15 AH15 AG15 AF15 AB15 AA15 Y15 V15 U15 AN14 AM14 U14 T14 VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG
VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF
W28 V28 W26 V26 W25 V25 W24 V24 W23 V23 AM21 AL21 AK21 W21 V21 U21 AM20 AK20 W20 U20 AM19 AL19 AK19 AJ19 AH19 AG19 AF19 AE19 AB19 AA19 Y19 W19 V19 U19 AM17 AK17 AH17 AG17 AF17 AE17 AC17 AB17 Y17 W17 V17 AM16 AL16 AK16 AJ16 AH16 AG16 AF16 AE16 AC16 AB16 AA16 Y16 W16 V16 U16
1D05V_S0
U35F
6 OF 10
C455 Do Not Stuff
C111 Do Not Stuff
C144 Do Not Stuff
1D05V_S0
DY
DY
DY
DY
POWER
AG34 AC34 AB34 AA34 Y34 V34 U34 AM33 AK33 AJ33 AG33 AF33 AE33 AC33 AA33 Y33 W33 V33 U33 AH28 AF28 AC28 AA28 AJ26 AG26 AE26 AC26 AH25 AG25 AF25 AG24 AJ23 AH23 AF23
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
TC21 Do Not Stuff
DY
C163 Do Not Stuff
C164 Do Not Stuff
C175 SC1U10V3ZY-6GP
Coupling CAP 370 mils from the Edge
DY
DY
VCC SM
C456 Do Not Stuff
C450 Do Not Stuff
Place on the Edge
Coupling CAP DY
2
DY
VCC CORE
POWER
VCC GFX NCTF
1D05V_S0 VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF AM32 AL32 AK32 AJ32 AH32 AG32 AE32 AC32 AA32 Y32 W32 U32 AM30 AL30 AK30 AH30 AG30 AF30 AE30 AC30 AB30 AA30 Y30 W30 V30 U30 AL29 AK29 AJ29 AH29 AG29 AE29 AC29 AA29 Y29 W29 V29 AL28 AK28 AL26 AK26 AK25 AK24 AK23
Place CAP where LVDS and DDR2 taps
71.CNTIG.00U
place near Cantiga
1 1
AJ14 AH14
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Date:
5 4 3 2
Document Number
Cantiga (4 of 6)_POWER
HM40-MV
Sheet
1
Rev
SB
9 of 51
SB 1120 modify EC78
U44 5V_S0
Imax = 300 mA

3D3V_S0_DAC 1D05V_S0
3D3V_S0_DAC
1 R252 1 2 3 1 VIN GND EN VOUT NC#4 5 1 4

EC77 Do Not Stuff C485 SC22U16V0KX-1GP 0R2J-2-GP
73mA
1 1
3D3V_CRTDAC_S0
U35H
8 OF 10
852mA
1 1 1 1 U13 T13 U12 T12 U11 T11 U10 T10 U9 T9 U8 T8 U7 T7 U6 T6 U5 T5 V3 U3 V2 U2 T2 V1 U1
C209 SC4D7U6D3V3KX-GP C220 SC4D7U6D3V3KX-GP C213 SC2D2U6D3V3MX-1-GP C214 SC4D7U6D3V3KX-GP SC4D7U6D3V3KX-GP 1 2 C135
1 2
G9091-330T11U-GP EC78
SC4D7U10V3KX-GP
SB 1113 modify 2nd of U19

1D05V_S0
3D3V_S0_DAC R249 1
5mA
1
VCCA_DAC_BG VSSA_DAC_BG
CRT
74.09091.J3F 2nd = 74.09198.Q7FDY
B27 A26
VCCA_CRT_DAC VCCA_CRT_DAC
M_VCCA_DAC_BG A25 B25
HFB1608VF-102-GP
M_VCCA_DPLLA C490 SCD1U10V2KX-4GP 1D8V_TXLVDS_S3 M_VCCA_DPLLB M_VCCA_HPLL M_VCCA_MPLL
F47 L48 AD1 AE1 J48
R108
VCCA_HPLL VCCA_MPLL VCCA_LVDS
PLL
65mA
M_VCCA_DPLLA
2nd = 68.00084.A01
VCCA_DPLLB
VTT
68.00331.011
VCCA_DPLLA
1D8V_TXLVDS_S3
2
BAT54-5-GP 83.BAT54.D81 2nd = 83.BAT54.X81 3rd = 83.00054.Z81
A LVDS
DY
1D5V_S0
VSSA_LVDS
C265 Do Not Stuff
1D05V_S0
A PEG
R116 1 2 Do Not Stuff
1D05V_S0
L12
24mA
1D05V_S0
2 1
C464
M_VCCA_HPLL
26mA
SBK160808T-121Y-N-GP
68.00119.101
2
C469 Do Not Stuff
A SM
120ohm 100MHz
C178
C184
1D8V_SUS_SM_CK
M_VCCA_DPLLB
65mA
DY
AD48
VCCA_PEG_BG
1D05V_S0
720mA
1
C169
1D05V_RUN_PEGPLL AA48 C160
VCCA_PEG_PLL VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM
322mA
DY
C161
C157
DY
AR20 AP20 AN20 AR17 AP17 AN17 AT16 AR16 AP16
C481 SC1U10V3KX-3GP
C480 Do Not Stuff
13.2mA J47
R255 10R2F-L-GP
1 2 Do Not Stuff
C258 Do Not Stuff
VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT
DY
C138 Do Not Stuff
Do Not Stuff
DY
1D05V_S0 D18
1 3
1D05V_HV_S0 1
3D3V_S0
3D3V_HV_S0 R254 2 1 Do Not Stuff C497 SCD1U10V2KX-4GP
SC10U6D3V5MX-3GP
Do Not Stuff
SC1U10V3KX-3GP
SC1U10V3KX-3GP SC1U10V3KX-3GP
POWER
SC4D7U6D3V3KX-GP
1D8V_S3 R81 1 2 Do Not Stuff
Do Not Stuff
Do Not Stuff
2nd = 68.00217.161
L13
DY
AXF
2 1
M_VCCA_MPLL
139.2mA
1
C468 SCD1U10V2KX-4GP 3D3V_S0_DAC
DY
DY
A CK
68.00119.101 C463 DY 2nd = 68.00217.161 120ohm 100MHz

1D05V_S0
SM CK
79mA
1
AP28 AN28 AP25 AN25 AN24 AM28 AM26 AM25 AL25 AM24 AL24 AM23 AL23
VCCA_SM_CK VCCA_SM_CK VCCA_SM_CK VCCA_SM_CK VCCA_SM_CK VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF
VCC_AXF VCC_AXF VCC_AXF
B22 B21 A21
124mA
R82 1 C166 SCD1U10V2KX-4GP
1D8V_SUS_SM_CK_RC
1R2F-GP
VCC_SM_CK VCC_SM_CK VCC_SM_CK VCC_SM_CK
BF21 BH20 BG20 BF20
C159 SC10U6D3V5MX-3GP 1D8V_S3
L5
50mA
2 1
1D05V_RUN_PEGPLL C260 SCD1U10V2KX-4GP
TV
68.00119.111 2nd = 68.00217.521 220ohm 100MHz
50mA
A32
1D5V_S0 C181
VCC_HV VCC_HV VCC_HV VCC_PEG VCC_PEG VCC_PEG VCC_PEG VCC_PEG VCC_DMI VCC_DMI VCC_DMI VCC_DMI
HV
HDA
VCC_HDA
1D05V_S0
PEG
D TV/CRT
1D05V_S0
2 1 SCD1U10V2KX-4GP 1D5VRUN_QDAC
35mA
M25 L28 AF1
VCCD_TVDAC VCCD_QDAC VCCD_HPLL VCCD_PEG_PLL VCCD_LVDS VCCD_LVDS
V48 U48 V47 U47 U46 AH48 AF48 AH47 AG47
1782mA
1 1 1
C466 C222 C457
B24 A24
VCC_TX_LVDS VCCA_TV_DAC VCCA_TV_DAC
K47 C35 B35 A35
3D3V_HV_S0
DMI
157.2mA
1 1
C134 SCD1U10V2KX-4GP C261 SCD1U10V2KX-4GP
DY
C218
LVDS
L4
2 PBY160808T-181Y-GP 1
1D5VRUN_QDAC
VTTLF VTTLF VTTLF
180ohm 100MHz
A
68.00206.041
1D8V_S3
CANTIGA-GM-GP-U-NF
C133 1 C467 SCD47U6D3V2KX-GP 2 1 SCD47U6D3V2KX-GP 2 1 2
C139 SCD47U6D3V2KX-GP
2nd = 68.00214.051
60.3mA
1
71.CNTIG.00U
1D5V_S0
VTTLF
1D8V_TXLVDS_S3
119mA 106mA
C262 SC1KP50V2KX-1GP
R104 1 2 Do Not Stuff C254 SC1U10V3KX-3GP

B
C460 Do Not Stuff
SC22U6D3V5MX-2GP
DY
DY
1D05V_S0
1D05V_RUN_PEGPLL AA47
456mA
VTTLF1 VTTLF2 VTTLF3
M38 L37
DY
Do Not Stuff
A8 L1 AB2
Wistron Corporation
Cantiga (5 of 6)_POWER
Document Number Rev
HM40-MV
1
SB
10 of 51
U35J U35I 9 OF 10 10 OF 10
VSS VSS
BA16 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS AU16 AN16 N16 K16 G16 E16 BG15 AC15 W15 A15 BG14 AA14 C14 BG13 BC13 BA13 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF BC3 AV3 AL3 R3 P3 F3 BA2 AW2 AU2 AR2 AP2 AJ2 AH2 AF2 AE2 AD2 AC2 Y2 M2 K2 AM1 AA1 P1 H1 U24 U28 U25 U29 AF32 AB32 V32 AJ30 AM29 AF29 AB29 U26 U23 AL20 V20 AC19 AL17 AJ17 AA17 U17 BH48 BH1 A48 C1 A3 E1 D2 C3 B4 A5 A6 A43 A44 B45 C46 D47 B47 A46 F48 E48 C48 B48
Title CANTIGA-GM-GP-U-NF CANTIGA-GM-GP-U-NF
AU48 AR48 AL48 BB47 AW47 AN47 AJ47 AF47 AD47 AB47 Y47 T47 N47 L47 G47 BD46 BA46 AY46 AV46 AR46 AM46 V46 R46 P46 H46 F46 BF44 AH44 AD44 AA44 Y44 U44 T44 M44 F44 BC43 AV43 AU43 AM43 J43 C43 BG42 AY42 AT42 AN42 AJ42 AE42 N42 L42 BD41 AU41 AM41 AH41 AD41 AA41 Y41 U41 T41 M41 G41 B41 BG40 BB40 AV40 AN40 H40 E40 AT39 AM39 AJ39 AE39 N39 L39 B39 BH38 BC38 BA38 AU38 AH38 AD38 AA38 Y38 U38 T38 J38 F38 C38 BF37 BB37 AW37 AT37 AN37 AJ37 H37 C37 BG36 BD36 AK15 AU36
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
AM36 AE36 P36 L36 J36 F36 B36 AH35 AA35 Y35 U35 T35 BF34 AM34 AJ34 AF34 AE34 W34 B34 A34 BG33 BC33 BA33 AV33 AR33 AL33 AH33 AB33 P33 L33 H33 N32 K32 F32 C32 A31 AN29 T29 N29 K29 H29 F29 A29 BG28 BD28 BA28 AV28 AT28 AR28 AJ28 AG28 AE28 AB28 Y28 P28 K28 H28 F28 C28 BF26 AH26 AF26 AB26 AA26 C26 B26 BH25 BD25 BB25 AV25 AR25 AJ25 AC25 Y25 N25 L25 J25 G25 E25 BF24 AD12 AY24 AT24 AJ24 AH24 AF24 AB24 R24 L24 K24 J24 G24 F24 E24 BH23 AG23 Y23 B23 A23 AJ6
BG21 L12 AW21 AU21 AP21 AN21 AH21 AF21 AB21 R21 M21 J21 G21 BC20 BA20 AW20 AT20 AJ20 AG20 Y20 N20 K20 F20 C20 A20 BG19 A18 BG17 BC17 AW17 AT17 R17 M17 H17 C17
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
AH8 Y8 L8 E8 B8 AY7 AU7 AN7 AJ7 AE7 AA7 N7 J7 BG6 BD6 AV6 AT6 AM6 M6 C6 BA5 AH5 AD5 Y5 L5 J5 H5 F5 BE4
Y11 N11 G11 C11 BG10 AV10 AT10 AJ10 AE10 AA10 M10 BF9 BC9 AN9 AM9 AD9 G9 B9 BH8 BB8 AV8 AT8
NCTF TEST PIN: A3,C1,A48,BH1,BH48
VSS NCTF
AN13 AJ13 AE13 N13 L13 G13 E13 BF12 AV12 AT12 AM12 AA12 J12 A12 BD11 BB11 AY11 AN11 AH11
VSS SCB
NCTF_VSS_SCB#BH48 NCTF_VSS_SCB#BH1 NCTF_VSS_SCB#A48 NCTF_VSS_SCB#C1 NCTF_VSS_SCB#A3 NC#E1 NC#D2 NC#C3 NC#B4 NC#A5 NC#A6 NC#A43 NC#A44 NC#B45 NC#C46 NC#D47 NC#B47 NC#A46 NC#F48 NC#E48 NC#C48 NC#B48
1 1 1 1 1
Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff
TP71 TP67 TP74 TP65 TP66
NC
Wistron Corporation
71.CNTIG.00U
71.CNTIG.00U
Size Date:
Document Number
Cantiga (6 of 6)
HM40-MV
Sheet
1
Rev
SB
11 of 51
C76 1
RTC_X1
SC12P50V2JN-3GP
D16
D
3D3V_AUX_S5
X2 X-32D768KHZ-46GP
1016 modify X2
R57 10MR2J-L-GP
D
2 3
RTC_BAT_R
RTC_AUX_S5
82.30001.861 2nd = 82.30001.691

2 1 2
1 2
CH715FPT-GP 2nd = 83.R2004.C81
C391 SC1U16V3ZY-GP C77 1
1D05V_S0 U16A 1 OF 6 LPC_LAD[0..3]
RTC1
RN51 SRN20KJ-GP-U
SC12P50V2JN-3GP
RTC_X2 RTC_RST# SRTC_RST# INTRUDER#
PWR GND NP1 NP2
RTC_BAT 1 2 NP1 NP2
RTC LPC
DY
C281 Do Not Stuff
R193
2 1MR2J-1-GP
C396 SC1U16V3ZY-GP
FWH4/LFRAME# LDRQ0# LDRQ1#/GPIO23 A20GATE A20M#
K3 J3 J1 N7 AJ27
LDRQ0# 3D3V_LDRQ1_S0
LPC_LFRAME# 33,34
H_DPSLP#
BAT-CON2-1-GP-U
62.70001.011
Do Not Stuff TP50 G84
C392 SC1U16V3ZY-GP
INTVRMEN LAN100_SLP
B22 A22 E25
INTVRMEN LAN100_SLP GLAN_CLK
1 1
TP58 TP12
LAN_RSTYNC C13
KA20GATE 33 H_A20M# 4
LAN_RSTSYNC LAN_RXD0 LAN_RXD1 LAN_RXD2 LAN_TXD0 LAN_TXD1 LAN_TXD2
1124 delete C540
Do Not Stuff
F14 G13 D14 D13 D12 E13 B10 B28 B27
LAN / GLAN CPU
1119 add G84 and C540
near DIMM door
DPRSTP# DPSLP#
AJ25 AE23 AJ26
H_DPRSTP# H_FERR#_R
H_DPRSTP# 4,7,41 H_DPSLP# 4
R121 1 2 1KR2J-1-GP
C23 C24 A25 F20 C22
RTCX1 RTCX2 RTCRST# SRTCRST# INTRUDER#
2 1
3 4
FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3
K5 K4 L6 K2
LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3
83.R0304.B81
LPC_LAD[0..3]
33,34
DY
R223 Do Not Stuff
1D05V_S0
FERR#
RN54
H_THERMTRIP_R
CPUPWRGD IGNNE#
AD22 AF25
GLAN_COMP place within 500 mil of ICH9M
1D5V_S0
H_PW RGD 4,39,48 4 H_IGNNE# 4 H_INIT# 4 H_INTR 4 KBRCIN# 33 H_NMI 4 H_SMI# 4
H_FERR#
1 2 3 4
8 7 6 5
H_FERR#_R
13 GLAN_DOCK#
GLAN_DOCK#
GLAN_DOCK#/GPIO56 GLAN_COMPI GLAN_COMPO HDA_BIT_CLK HDA_SYNC HDA_RST#
R207 1
2 GLAN_COMP 24D9R2F-L-GP
INIT# INTR RCIN# NMI SMI#
AE22 AG25 L3 AF23 AF24
SRN56J-5-GP
ACZ_BIT_CLK_R ACZ_SYNC_R ACZ_RST#_R
AF6 AH4 AE7
H_PW RGD
STPCLK# THRMTRIP# HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_SDIN3 HDA_SDOUT
AH27 AG26 AG27 AH11 AJ11 AG12 AF12 AH9 AJ9 AE10 AF10 AH18 AJ18 AJ7 AH7
SATARBIAS H_THERMTRIP_R ICH_TP8
R222 Do Not Stuff 1 DY 2
1D05V_S0
H_STPCLK# 4
1
TP25 Do Not Stuff
26 ACZ_SDATAIN0
3D3V_S0 ACZ_SDATAOUT_R TP62 Do Not Stuff HDA_DOCK_RST#
IHDA
AF4 AG4 AH3 AE5 AG5 AG7 AE8 AG8
PECI SATA4RXN SATA4RXP SATA4TXN SATA4TXP SATA5RXN SATA5RXP SATA5TXN SATA5TXP SATA_CLKN SATA_CLKP SATARBIAS# SATARBIAS
DY R229
Do Not Stuff
PM_THRMTRIP-A# 4,7,39 Layout note: R373 needs to placed within 2" of ICH9, R379 must be placed within 2" of R373 w/o stub
1 R228
DY
HDA_DOCK_EN# 2 Do Not Stuff
HDA_DOCK_EN#/GPIO33 HDA_DOCK_RST#/GPIO34 SATALED#
33,36 MEDIA_LED#
SATA
HDD
B
20 20 20 20 21 21 21 21
SATA_RXN0 SATA_RXP0 SATA_TXN0 SATA_TXP0 SATA_RXN1 SATA_RXP1 SATA_TXN1 SATA_TXP1
C55 C56 C58 C57 C285 C286 C289 C288
1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2
SCD01U50V2KX-1GP SCD01U50V2KX-1GP SCD01U50V2KX-1GP SCD01U50V2KX-1GP SCD01U50V2KX-1GP SCD01U50V2KX-1GP SCD01U50V2KX-1GP SCD01U50V2KX-1GP
SATA_RXN0_C SATA_RXP0_C SATA_TXN0_C SATA_TXP0_C SATA_RXN1_C SATA_RXP1_C SATA_TXN1_C SATA_TXP1_C
AJ16 AH16 AF17 AG17 AH13 AJ13 AG14 AF14
SATA0RXN SATA0RXP SATA0TXN SATA0TXP SATA1RXN SATA1RXP SATA1TXN SATA1TXP
CLK_PCIE_SATA# 3 CLK_PCIE_SATA 3
ODD
RTC_AUX_S5 RTC_AUX_S5
2 1 R227 24D9R2F-L-GP
71.ICH9M.00U
1
R200 330KR2F-L-GP
R199 330KR2F-L-GP
DY RN55 Do Not Stuff
integrated VccSus1_05,VccSus1_5,VccCL1_5
2 2
INTVRMEN R197 Do Not Stuff LAN100_SLP R198 Do Not Stuff
SB
1117 delete MDC function(R231,R237,R232,R234)
INTVRMEN LAN100_SLP
High=Enable High=Enable
Low=Disable Low=Disable
0915 add EC73 for EMI demand

H_INIT#_G
integrated VccLan1_05VccCL1_05
DY
2
DY
2
SB
B
1126 delete R230,R233,R235,R236 and RN63

RN63 26 ACZ_RST#_AUDIO 26 ACZ_SDATAOUT_AUDIO 26 ACZ_SYNC_AUDIO 26 ACZ_BITCLK_AUDIO H_INIT#
SRN47J-4-GP
A
DY
EC73 Do Not Stuff
8 7 6 5
1 2 3 4
ACZ_RST#_R ACZ_SDATAOUT_R ACZ_SYNC_R ACZ_BIT_CLK_R
DY Q24 C
3 4
2 1
ICH9M-GP-NF
Place within 500 mils of ICH9 ball
1D05V_S0
3D3V_S0
FW H_INIT# 1
TP70 Do Not Stuff
Do Not Stuff
EC65 Do Not Stuff
UMA Two Phase 2

A
DY
Wistron Corporation
5 4 3 2
Document Number
ICH9-M (1 of 4)_SATA/HDA/RTC
HM40-MV
Sheet
1
Rev
SB
12 of 51
U16B
U16C PCI_REQ#0 PCI_GNT#0 PCI_REQ#1 PCI_REQ#2 PCI_REQ#3 PCI_GNT#3 Do Not Stuff TP59 15 15 SMB_CLK SMB_DATA
3 OF 6
2 OF 6
G61
MISC GPIO Controller Link
INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD#
RP5 PCI_PERR# INT_PIRQE# PCI_LOCK# INT_PIRQA# 3D3V_S0
1 2 3 4 5
SRN8K2J-2-GP-U RP3 PCI_REQ#2 PCI_REQ#1 SDATAOUT1 PM_CLKRUN# 3D3V_S0
1 2 3 4 5
Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff TP52 TP19 TP63 TP69 TP4 Do Not Stuff
J5 E1 J6 C4
Interrupt I/F
PIRQA# PIRQB# PIRQC# PIRQD#
PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5
H4 K6 F2 G2
INT_PIRQE# INT_PIRQF# INT_PIRQG# INT_PIRQH#
SB
CL_CLK0 CL_CLK1
F24 B19
CL_CLK0 7
R204 3K24R2F-GP
1120 add the net(SATACLKREQ#)
CL_DATA0 CL_DATA1 CL_VREF0 CL_VREF1 CL_RST0# CL_RST1#
F22 C19 C25 A19 F21 D18 A16 C18 C11 C20
CL_DATA0 7
ICH9M-GP-NF
3 SATACLKREQ#
CL_VREF0_ICH CL_VREF1_ICH
10 9 8 7 6
3D3V_S0
RP4
INT_PIRQH# PCI_REQ#0 INT_PIRQC# INT_PIRQB#
3D3V_S0
1 ICH_TP3
10 9 8 7 6
3D3V_S0
INT_SERIRQ PCI_DEVSEL# PCI_STOP# PCI_FRAME#
GPIO49 should be pulled down to GND only when using Teenah. When using Cantiga, this ball should be left as No Connect.
C75
SRN8K2J-2-GP-U
TP51
Do Not Stuff
SPKR MCH_SYNC# TP3 PW M0 PW M1 PW M2
Do Not Stuff TP54
DY
ICH9M-GP-NF U16D 4 OF 6
SRN8K2J-2-GP-U
LAN
24 24 24 24 31 31 31 31 PCIE_RXN1 PCIE_RXP1 PCIE_TXN1 PCIE_TXP1 PCIE_RXN2 PCIE_RXP2 PCIE_TXN2 PCIE_TXP2 C425 SCD1U10V2KX-5GP 2 C430 SCD1U10V2KX-5GP 2
No Reboot Strap SPKR LOW = Defaule High=No Reboot

V27 V26 U29 U28 Y27 Y26 W 29 W 28 AB27 AB26 AA29 AA28 AD27 AD26 AC29 AC28 T26 T25 AF29 AF28 AC5 AC4 AD3 AD2 AC1 AC2 AA5 AA4 AB2 AB3 AA1 AA2 W5 W4 Y3 Y2 W1 W2 V2 V3 U5 U4 U1 U2
DMI_RXN0 DMI_RXP0 DMI_TXN0 DMI_TXP0 DMI_RXN1 DMI_RXP1 DMI_TXN1 DMI_TXP1 DMI_RXN2 DMI_RXP2 DMI_TXN2 DMI_TXP2 DMI_RXN3 DMI_RXP3 DMI_TXN3 DMI_TXP3 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 1D5V_S0 RN5 3D3V_S5
71.ICH9M.00U
RP1 USB_OC#1 PM_BATLOW#_R ECSWI# USB_OC#0 3D3V_S5
DY
1 2 3 4 5
SRN10KJ-L3-GP RP2
R56 Do Not Stuff
DY
2
1 1
TXN1 TXP1
Direct Media Interface
N29 N28 P27 P26 L29 L28 M27 M26 J29 J28 K27 K26 G29 G28 H27 H26 E29 E28 F27 F26 C29 C28 D27 D26 D23 D24 F23 D25 E23
PERN1 PERP1 PETN1 PETP1 PERN2 PERP2 PETN2 PETP2
DMI0RXN DMI0RXP DMI0TXN DMI0TXP DMI1RXN DMI1RXP DMI1TXN DMI1TXP DMI2RXN DMI2RXP DMI2TXN DMI2TXP DMI3RXN DMI3RXP DMI3TXN DMI3TXP
C418 SCD1U10V2KX-5GP 2 C416 SCD1U10V2KX-5GP 2
1 1
TXN2 TXP2
8 7 6 5
SRN10KJ-6-GP
1 2 3 4
SMLINK0 SMLINK1 RSMRST#_SB
10 9 8 7 6
3D3V_S5 USB_OC#5 SMB_LINK_ALERT# GPIO10 SMB_ALERT#
PCI-Express
MINICARD1
PERN3 PERP3 PETN3 PETP3 PERN4 PERP4 PETN4 PETP4 PERN5 PERP5 PETN5 PETP5 PERN6/GLAN_RXN PERP6/GLAN_RXP PETN6/GLAN_TXN PETP6/GLAN_TXP
USB_OC#2 USB_OC#7 PM_RI# PCIE_WAKE#
RP7 SATA0GP SATA1GP GPIO36 GPIO37
1 2 3 4 5
SRN10KJ-L3-GP
10 9 8 7 6
3D3V_S5 PWROK GPIO57
1 2 3 4 5
SRN10KJ-L3-GP
10 9 8 7 6
3D3V_S5 USB_OC#4 DBRESET# USB_OC#3 USB_OC#6
RP6 USB_OC#8 USB_OC#9 USB_OC#10 USB_OC#11 3D3V_S5
1 2 3 4 5
SRN10KJ-L3-GP
10 9 8 7 6
3D3V_S5 SB_GPIO13 GPIO14 GLAN_DOCK# 12

B
DMI_CLKN DMI_CLKP
CLK_PCIE_ICH# 3 CLK_PCIE_ICH 3 DMI_IRCOMP_R USBPN0 23 USBPP0 23
R224 24D9R2F-L-GP
DMI_ZCOMP DMI_IRCOMP
SPI_CS#1
23
USB_OC#0
USB_OC#0 USB_OC#1 USB_OC#2 USB_OC#3 USB_OC#4 USB_OC#5 USB_OC#6 USB_OC#7 USB_OC#8 USB_OC#9 USB_OC#10 USB_OC#11 R73
N4 N5 N6 P6 M1 N2 M4 M3 N3 N1 P5 P3
1
22D6R2F-L1-GP
USB_RBIAS_PN AG2 AG1
USBP0N USBP0P USBP1N USBP1P SPI_CLK USBP2N SPI_CS0# USBP2P SPI_CS1#/GPIO58/CLGPIO6 USBP3N USBP3P SPI_MOSI USBP4N SPI_MISO USBP4P USBP5N OC0#/GPIO59 USBP5P OC1#/GPIO40 USBP6N OC2#/GPIO41 USBP6P OC3#/GPIO42 USBP7N OC4#/GPIO43 USBP7P OC5#/GPIO29 USBP8N OC6#/GPIO30 USBP8P OC7#/GPIO31 USBP9N OC8#/GPIO44 USBP9P OC9#/GPIO45 USBP10N OC10#/GPIO46 USBP10P OC11#/GPIO47 USBP11N USBP11P USBRBIAS USBRBIAS#
USB Pair 0 1 2 3 4 5 6 7 8 9 10 11 Device USB1 NC NC MINIC1 WEBCAM NC NC Bluetooth NC USB2(High speed) NC CardReader
PCI_GNT#3 BOOT BIOS Strap PCI_GNT#0 SPI_CS#1 BOOT BIOS Location
33 RSMRST#_KBC
DY
R195 1 2 Do Not Stuff
D15
SPI
USBPN3 USBPP3 USBPN4 USBPP4
31 31 18 18
1 3 2
BAT54-5-GP 83.BAT54.D81 2nd = 83.BAT54.X81 3rd = 83.00054.Z81 UMA Two Phase 2
RSMRST#_SB
R196 100KR2J-1-GP
USB
USBPN7 22 USBPP7 22 USBPN9 23 USBPP9 23 USBPN11 30 USBPP11 30
A16 swap override strap
0 1 1
1 0 1
SPI PCI LPC(Default)
PCI_REQ#3 INT_PIRQF# INT_PIRQG# PCI_SERR#
1 2 3 4 5
10 9 8 7 6
3D3V_S0
INT_PIRQD# PCI_IRDY# PCI_TRDY# ECSCI#_1
26 ACZ_SPKR 7 MCH_ICH_SYNC#
M7 AJ24 B21 AH20 AJ20 AJ21
GPIO24/MEM_LED GPIO10/SUS_PW R_ACK GPIO14/AC_PRESENT GPIO9/W OL_EN
GPIO24 1 GPIO10 GPIO14 GPIO9 1
Do Not Stuff TP3
R55 Do Not Stuff
TP68
Do Not Stuff
SDATAOUT1 1 GPIO49 GPIO57
CL_RST#0
3D3V_S5
71.ICH9M.00U
Do Not Stuff
D11 C8 D9 E12 E9 C9 E10 B7 C7 C5 G11 F8 F11 E7 A3 D2 F10 D5 D10 B3 F7 C3 F3 F4 C1 G7 H7 D1 G5 H6 G1 H3
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
SMB
SATA GPIO
PCI
RI# SUS_STAT#/LPCPD# SYS_RESET# PMSYNC#/GPIO0 SMBALERT#/GPIO11
1 PM_SUS_STAT# DBRESET#
R4 G19 M6
Clocks
REQ0# GNT0# REQ1#/GPIO50 GNT1#/GPIO51 REQ2#/GPIO52 GNT2#/GPIO53 REQ3#/GPIO54 GNT3#/GPIO55 C/BE0# C/BE1# C/BE2# C/BE3# IRDY# PAR PCIRST# DEVSEL# PERR# PLOCK# SERR# STOP# TRDY# FRAME# PLTRST# PCICLK PME#
F1 G4 B6 A7 F13 F12 E6 F6 D8 B4 D6 A5 D3 E3 R1 C6 E4 C2 J4 A4 F5 D7
G16 A13 SMB_LINK_ALERT# E17 SMLINK0 C17 SMLINK1 B18

PM_RI#
SMBCLK SMBDATA LINKALERT#/GPIO60/CLGPIO4 SMLINK0 SMLINK1
SATA0GP/GPIO21 SATA1GP/GPIO19 SATA4GP/GPIO36 SATA5GP/GPIO37 CLK14 CLK48 SUSCLK SLP_S3# SLP_S4# SLP_S5# S4_STATE#/GPIO26
AH23 AF19 AE21 AD20 H1 AF3 P1 C16 E16 G17 C10 G20 M2 B13 R3 D20 D22 R5 R6 B16
SATA0GP SATA1GP GPIO36 GPIO37 CLK_ICH14 3 CLK48_ICH 3 PM_SUS_CLK 32 PM_SLP_S3# 33,39,43,44 PM_SLP_S4# 33,43,44 TP57 Do Not Stuff S4_STATE# 1 TP53 Do Not Stuff PWROK PM_DPRSLPVR PM_BATLOW#_R PWRBTN#_ICH R216 1 DY 2 Do Not Stuff D17 1 7,39 PM_DPRSLPVR 7,41
D
F19
PM_SYNC# SMB_ALERT#
SLPS5#
A17 A14 E19 L4 E20 M5 AJ23 D21
TP55 Do Not Stuff
SYS GPIO Power MGT
PCI_IRDY# PCI_PAR PCI_DEVSEL# PCI_PERR# PCI_LOCK# PCI_SERR# PCI_STOP# PCI_TRDY# PCI_FRAME#
3 3
PM_STPPCI# PM_STPCPU#
STP_PCI# STP_CPU# CLKRUN# W AKE# SERIRQ THRM# VRMPW RGD SST TACH1/GPIO1 TACH2/GPIO6 TACH3/GPIO7 GPIO8 LAN_PHY_PW R_CTRL/GPIO12 ENERGY_DETECT/GPIO13 TACH0/GPIO17 GPIO18 GPIO20 SCLOCK/GPIO22 GPIO27 GPIO28 SATACLKREQ#/GPIO35 SLOAD/GPIO38 SDATAOUT0/GPIO39 SDATAOUT1/GPIO48 GPIO49 GPIO57/CLGPIO5
PW ROK DPRSLPVR/GPIO16 BATLOW # PW RBTN# LAN_RST# RSMRST# CK_PW RGD CLPW ROK SLP_M#
33 PM_CLKRUN# 24 PCIE_WAKE# 33 INT_SERIRQ 32 THRM# 32,41 VGATE_PWRGD PLT_RST1# 7,24,30,31,33,34 PCLK_ICH 3
DY
1
R209
C405 Do Not Stuff
3D3V_S0
PM_PWRBTN# 33
C14 PLT_RST#_R D4 R2
ICH_PME#
1 0R2J-2-GP 1
1 R194
Do Not Stuff TP64
DY Do Not Stuff
SB_GPIO1
ICH_TP7
A20 AG19 AH21 AG21 A21 C12 C21 AE18 K1 AF8 AJ22 A9 D19 L1 AE19 AG22 AF21 AH24 A8
RSMRST#_SB
3 83.00016.B11 2 BAS16-1-GP 2nd = 83.00016.F11

CLK_PWRGD 3 PWROK 7,39 3D3V_S0
TP22 Do Not Stuff
R225 10KR2J-3-GP
33 33 33
EC_TMR ECSCI#_1 ECSWI#
1 GPIO12 SB_GPIO13 PSW_CLR# 1 GPIO18 1 GPIO20 1 GPIO22
PM_SLP_M#
R205 453R2F-1-GP
Do Not Stuff
low = A16 swap override enable high = default

1 R210 1 R212 1 R208
Do Not Stuff 2 Do Not Stuff 2 Do Not Stuff 2
Wistron Corporation
PCI_GNT#0 SPI_CS#1 PCI_GNT#3 GNT0 and SPI_CS#1 have a weak internal pull up
DY DY DY
ICH9-M (2 of 4)_PCIE/USB/DMI
Size Date: Document Number Rev
ICH9M-GP-NF
71.ICH9M.00U
5 4
1017 modify USB signal connection

3 2
HM40-MV
1
SB
Sheet 13 of 51
1D5V_S0
RTC_AUX_S5
U16F
6 OF 6 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCCDMIPLL VCCDMI VCCDMI A15 B15 C15 D15 E15 F15 L11 L12 L14 L16 L17 L18 M11 M18 P11 P18 T11 T18 U11 U18 V11 V12 V14 V16 V17 V18 R29 W23 1D05V_DMI_ICH_S0 Y23 AB23 AC23
6uA in G3
C388 Do Not Stuff 1 V5REF_S0 V5REF_S5 2
A23 A6 AE1 AA24 AA25 AB24 AB25 AC24 AC25 AD24 AD25 AE25 AE26 AE27 AE28 AE29 F25 G25 H24 H25 J24 J25 K24 K25 L23 L24 L25 M24 M25 N23 N24 N25 P24 P25 R24 R25 R26 R27 T24 T27 T28 T29 U24 U25 V24 V25 U23 W24 W25 K23 Y24 Y25 AJ19 AC16 AD15 AD16 AE15 AF15 AG15 AH15 AJ15 AC11 AD11 AE11 AF11 AG10 AG11 AH10 AJ10 AC9 AC18 AC19 AC21 G10 G9 AC12 AC13 AC14 AJ5
VCCRTC V5REF V5REF_SUS VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B
1.63A
Layout Note:Place near ICH9M 1 1 1 1 1 1 C434 SCD1U10V2KX-4GP
1D05V_S0
DY
DY
C439 Do Not Stuff
DY
DY
1 2
646mA
1 1 1 1 C414 Do Not Stuff C459 Do Not Stuff C415 C443 SCD1U10V2KX-4GP
DY
2
DY
2
C444
C447
*Within a given well, 5VREF needs to be up before the corresponding 3.3V rail
1015 modify component size of C390,C419
2mA
V5REF_S0
C
D6 R54 100R2J-2-GP RB751V-40-2-GP 83.R2004.B8F 2nd = 83.R0304.A8F 3rd = 83.R3004.A8F 2
68.1R220.10D
VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3
C477 SC1U16V3ZY-GP
AC10
VCCP_CORE
V5REF_S5
C440 SC1U16V3ZY-GP
C413 Do Not Stuff
DY
VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCCUSBPLL VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCCLAN1_05 VCCLAN1_05 VCCLAN3_3 VCCLAN3_3
VCCSUS1_05 VCCSUS1_05 ARX VCCSUS1_5 VCCSUS1_5 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCCL1_05 VCCCL1_5 VCCCL3_3 VCCCL3_3 USB CORE
AD8 1 F18 A18 D16 D17 E22 AF1 T1 T2 T3 T4 T5 T6 U6 U7 V6 V7 W6 W7 Y6 Y7 T7 1D5V_S5
SCD1U10V2KX-4GP C410 SCD1U10V2KX-4GP 1D5V_S5 3D3V_S5
VCCPSUS
C394 Do Not Stuff
DY
C458 Do Not Stuff
VCCSUS3_3=212mA
3D3V_S5
AC8 VccSus1_05 F17
C403 1 2
2mA
D7 R72 100R2J-2-GP RB751V-40-2-GP 83.R2004.B8F 2nd = 83.R0304.A8F 3rd = 83.R3004.A8F
PCI
1D5V_S0
1.34A
VCCHDA VCCSUSHDA
AJ4 AJ3
Layout Note: Place near ICH9
3D3V_S5
5V_S5
B9 F9 G3 G6 J2 J7 K7
C406 Do Not Stuff
C412 Do Not Stuff
C72 SCD1U16V2ZY-2GP
AD19 AF20 AG24 AC20
VCC3_3=308mA 3D3V_S0
3D3V_S0
2 IND-1D2UH-10-GP
VCC3_3
AG29 AJ6
3D3V_S0
47mA
L14 5V_S0 1D5V_S0 1D5V_APLL_S0 V_CPU_IO V_CPU_IO 3D3V_S0 C419 SC4D7U6D3V3KX-GP VCCA3GP C474 SCD1U10V2KX-4GP C465 SCD1U10V2KX-4GP
SC4D7U6D3V3KX-GP
1D5V_DMIPLL_ICH_S0 1 1 1 C431 SCD01U16V2KX-3GP
L11
23mA
1D5V_S0
CORE
2 IND-1D2UH-10-GP
DY
C435 Do Not Stuff
68.1R220.10D
1 R221 2 Do Not Stuff C448 Do Not Stuff
48mA
1D05V_S0
SCD1U10V2KX-4GP
Do Not Stuff
DY
DY
2mA
1D05V_S0
DY
DY
11mA
3D3V_S0
DY
VCCSATAPLL
11mA
3D3V_S5
ATX
DY
1 2
C437 Do Not Stuff
1D5V_S0
USBPLL=11mA
1 1 1 C473 Do Not Stuff C451 SCD1U10V2KX-4GP
VCCPUSB
DY
DY
2
3D3V_S0
A24 B24
19mA in S0;78mA in S3/S4/S5

1 C74 SCD1U10V2KX-4GP
A
C409 Do Not Stuff
C73
VccLan1D05 SCD1U10V2KX-4GP
A10 A11 A12 B12 A27
19mA in S0;73mA in S3/S4/S5
DY
2
23mA
1 C385 1 SCD1U10V2KX-4GP 2
1D5V_S0
AA7 AB6 AB7 AC6 AC7
G23 VccSus1_5[3] 1
TP56 Do Not Stuff
DY
3D3V_S0
G22 VccSus1_05[3]
C411 Do Not Stuff
VCCGLANPLL GLAN POWER VCCGLAN1_5 VCCGLAN1_5 VCCGLAN1_5 VCCGLAN1_5 VCCGLAN3_3 ICH9M-GP-NF
DY
2
C421 Do Not Stuff
1D5V_S0
80mA
1 1 3D3V_S0 C408 Do Not Stuff
D28 D29 E26 E27 A26
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Document Number
DY
2 2
1mA
4
ICH9-M (3 of 4)_POWER
HM40-MV
Sheet
1
71.ICH9M.00U
Rev
SB
14 of 51
Date: Monday, December 01, 2008

5 3 2
U16E
5 OF 6
8 7 6 5
3D3V_S5 3D3V_S0 RN50 SRN2K2J-2-GP 13 SMB_CLK
AA26 AA27 AA3 AA6 AB1 AA23 AB28 AB29 AB4 AB5 AC17 AC26 AC27 AC3 AD1 AD10 AD12 AD13 AD14 AD17 AD18 AD21 AD28 AD29 AD4 AD5 AD6 AD7 AD9 AE12 AE13 AE14 AE16 AE17 AE2 AE20 AE24 AE3 AE4 AE6 AE9 AF13 AF16 AF18 AF22 AH26 AF26 AF27 AF5 AF7 AF9 AG13 AG16 AG18 AG20 AG23 AG3 AG6 AG9 AH12 AH14 AH17 AH19 AH2 AH22 AH25 AH28 AH5 AH8 AJ12 AJ14 AJ17 AJ8 B11 B14 B17 B2 B20 B23 B5 B8 C26 C27 E11 E14 E18 E2 E21 E24 E5 E8 F16 F28 F29 G12 G14 G18 G21 G24 G26 G27 G8 H2 H23 H28 H29
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
H5 J23 J26 J27 AC22 K28 K29 L13 L15 L2 L26 L27 L5 L7 M12 M13 M14 M15 M16 M17 M23 M28 M29 N11 N12 N13 N14 N15 N16 N17 N18 N26 N27 P12 P13 P14 P15 P16 P17 P2 P23 P28 P29 P4 P7 R11 R12 R13 R14 R15 R16 R17 R18 R28 T12 T13 T14 T15 T16 T17 T23 B26 U12 U13 U14 U15 U16 U17 AD23 U26 U27 U3 V1 V13 V15 V23 V28 V29 V4 V5 W26 W27 W3 Y1 Y28 Y29 Y4 Y5 AG28 AH6 AF2 B25 A1 A2 B1 A29 A28 B29 AJ1 AJ2 AH1 AJ28 AJ29 AH29
3 2 1
1 2 3 4
5V_S0 Q7
4 5 6 2N7002DW -1-GP
SMBC_ICH 3,16,17
2
13
SMB_DATA SMBD_ICH 3,16,17
SMBUS
NCTF TEST PIN: A1,A2,B1,A28,A29,B29 AH1,AJ1,AJ2,AH29,AJ28,AJ29
NCTF_VSS#A1 NCTF_VSS#A2 NCTF_VSS#B1 NCTF_VSS#A29 NCTF_VSS#A28 NCTF_VSS#B29 NCTF_VSS#AJ1 NCTF_VSS#AJ2 NCTF_VSS#AH1 NCTF_VSS#AJ28 NCTF_VSS#AJ29 NCTF_VSS#AH29
1 1 1 1 1 1 1 1 1 1 1 1
Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff
TP1 TP2 TP10 TP8 TP7 TP9 TP30 TP31 TP28 TP29 TP27 TP26 Title Size Date: Document Number
Wistron Corporation
ICH9-M (4 of 4)
Sheet
E
ICH9M-GP-NF
Rev
71.ICH9M.00U
A B C D
HM40-MV
Monday, December 01, 2008 15 of
SB
51
DM1 8 M_B_A[14..0] M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15 102 101 100 99 98 97 94 92 93 91 105 90 89 116 86 84 85 107 106 M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63 5 7 17 19 4 6 14 16 23 25 35 37 20 22 36 38 43 45 55 57 44 46 56 58 61 63 73 75 62 64 74 76 123 125 135 137 124 126 134 136 141 143 151 153 140 142 152 154 157 159 173 175 158 160 174 176 179 181 189 191 180 182 192 194 11 29 49 68 129 146 167 186 13 31 51 70 131 148 169 188 114 119 1 2 C290 SCD1U16V2ZY-2GP 202 MH1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2 BA0 BA1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 RAS# WE# CAS# CS0# CS1# CKE0 CKE1 CK0 CK0# CK1 CK1# DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 SDA SCL VDDSPD 108 109 113 110 115 79 80 30 32 164 166 10 26 52 67 130 147 170 185 195 197 199 198 200 50 69 83 120 163 81 82 87 88 95 96 103 104 111 112 117 118 3 8 9 12 15 18 21 24 27 28 33 34 39 40 41 42 47 48 53 54 59 60 65 66 71 72 77 78 121 122 127 128 132 133 138 139 144 145 149 150 155 156 161 162 165 168 171 172 177 178 183 184 187 190 193 196 201 MH2 M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7 M_B_RAS# 8 M_B_WE# 8 M_B_CAS# 8 M_CS2# 7 M_CS3# 7 M_CKE2 7 M_CKE3 7 M_CLK_DDR2 7 M_CLK_DDR#2 7 M_CLK_DDR3 7 M_CLK_DDR#3 7 M_B_DM[7..0]
4
PARALLEL TERMINATION
4
DDR_VREF_S3
Put decap near power(0.9V) and pull-up resistor

RN19 8 7 6 5 1 2 3 4 M_B_BS#1 M_B_A0 M_B_A2 M_B_A4
SRN56J-5-GP RN31 8 1 7 2 6 3 5 4
M_CKE3 M_CKE2 M_B_A12 M_B_BS#2
Do Not Stuff TP37 8 8 8 M_B_BS#2 M_B_BS#0 M_B_BS#1
8 7 6 5
SRN56J-5-GP RN26 1 M_B_A6 2 M_B_A9 3 M_B_A8 4 M_B_A5 SRN56J-5-GP RN18 1 M_B_A1 2 M_B_A3 3 M_B_A10 4 M_B_WE# SRN56J-5-GP RN10
8 M_B_DQ[63..0]
SMBD_ICH SMBC_ICH
3,15,17 3,15,17
3D3V_S0
8 7 6 5
1 2 3 4
M_B_RAS# M_CS2# M_ODT2 M_B_A13
REVERSE TYPE
SA0 SA1 DDRB_SA0 NC#50 NC#69 NC#83 NC#120 NC#163/TEST VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD 2 2 R220 10KR2J-3-GP 1 1 C428 Do Not Stuff
8 7 6 5
DY
SRN56J-5-GP RN27
8 7 6 5
1 2 3 4
M_B_A14 M_B_A11 M_B_A7
SRN56J-5-GP RN13
1D8V_S3
8 7 6 5
1 2 3 4
M_B_BS#0 M_B_CAS# M_CS3# M_ODT3
SRN56J-5-GP
Decoupling Capacitor
DDR_VREF_S3
2

8 M_B_DQS#[7..0] 1 1 1 1 1 1 1 1 1 C234 C190 C154 C237 C191 C243 C206 C171 C223 1 C217
C219
DY
DY
DY
DY
M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7 M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 7 7 M_ODT2 M_ODT3
DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7# DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 OTD0 OTD1 VREF VSS GND MH1 DDR2-200P-23-GP-U1
8 M_B_DQS[7..0]
DDR_VREF_S3_1
C292 Do Not Stuff
DY
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
1D8V_S3
Place these Caps near DM1

1 1 1 1 C200 SC2D2U6D3V3MX-1-GP C488 Do Not Stuff C502 SC2D2U6D3V3MX-1-GP C503 Do Not Stuff Do Not Stuff 1 2 C496 SC2D2U6D3V3MX-1-GP
DY
DY
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
Do Not Stuff
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
Do Not Stuff
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
Do Not Stuff
SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP
C174 Do Not Stuff
C195 Do Not Stuff
1 2
C493 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP
DY
DY
GND MH2
High 9.2mm
62.10017.A71 2nd = 62.10017.B51 3rd = 62.10017.K51
Wistron Corporation
DDR2 Socket 0 (DM1)

Size Date:
A B C D
Document Number
HM40-MV
Sheet 16 of
E
Rev 51
SB
PARALLEL TERMINATION
4
M_A_A[14..0]
DM2 M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15 102 101 100 99 98 97 94 92 93 91 105 90 89 116 86 84 85 107 106 M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63 5 7 17 19 4 6 14 16 23 25 35 37 20 22 36 38 43 45 55 57 44 46 56 58 61 63 73 75 62 64 74 76 123 125 135 137 124 126 134 136 141 143 151 153 140 142 152 154 157 159 173 175 158 160 174 176 179 181 189 191 180 182 192 194 11 29 49 68 129 146 167 186 13 31 51 70 131 148 169 188 114 119 1 2 C291 202 SCD1U16V2ZY-2GP A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2 BA0 BA1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 /RAS /WE /CAS /CS0 /CS1 CKE0 CKE1 CK0 /CK0 CK1 /CK1 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 SDA SCL 108 109 113 110 115 79 80 30 32 164 166 10 26 52 67 130 147 170 185 195 197 199 198 200 50 69 83 120 163 81 82 87 88 95 96 103 104 111 112 117 118 3 8 9 12 15 18 21 24 27 28 33 34 39 40 41 42 47 48 53 54 59 60 65 66 71 72 77 78 121 122 127 128 132 133 138 139 144 145 149 150 155 156 161 162 165 168 171 172 177 178 183 184 187 190 193 196 201 M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7 M_A_RAS# 8 M_A_WE# 8 M_A_CAS# 8 M_CS0# 7 M_CS1# 7 M_CKE0 7 M_CKE1 7 M_CLK_DDR0 7 M_CLK_DDR#0 7 M_CLK_DDR1 7 M_CLK_DDR#1 7 M_A_DM[7..0]
4
DDR_VREF_S3

RN12 8 7 6 5 1 2 3 4 SRN56J-5-GP RN24 8 7 6 5 1 2 3 4 SRN56J-5-GP RN11 8 7 6 5 1 2 3 4 SRN56J-5-GP RN30 M_A_WE# M_A_CAS# M_CS1# M_ODT1 M_A_A5 M_A_A8 M_A_A9 M_A_A3 Do Not Stuff TP38 8 8 8 M_A_BS#2 M_A_BS#0 M_A_BS#1 1
M_A_A13 M_CS0# M_ODT0 M_A_RAS#
8 M_A_DQ[63..0]
RN17
8 7 6 5
1 2 3 4
M_A_A2 M_A_A0 M_A_A6 M_A_A4
REVERSE TYPE
8 7 6 5 1 2 3 4 VDDSPD M_CKE0 M_A_BS#2 M_A_A12 SA0 SA1 1 SRN56J-5-GP RN25 8 7 6 5 1 2 3 4 M_A_A7 M_A_A11 M_A_A14 M_CKE1 NC#50 NC#69 NC#83 NC#120 NC#163/TEST VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD 2 C433 Do Not Stuff
SMBD_ICH SMBC_ICH
3,15,16 3D3V_S0 3,15,16
DY
SRN56J-5-GP
1D8V_S3
SRN56J-5-GP RN16
8 7 6 5
1 2 3 4
M_A_A1 M_A_BS#1 M_A_A10 M_A_BS#0
SRN56J-5-GP
Decoupling Capacitor
DDR_VREF_S3

1 1 1 1 1 1 1 1 1 C167 C216 C232 C233 C236 C187 C170 C189 C215 1 C249 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff SCD1U16V2ZY-2GP Do Not Stuff SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP
C188
DY
DY
DY
DY
DY
8 M_A_DQS#[7..0]
M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7 M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 7 7 M_ODT0 M_ODT1
/DQS0 /DQS1 /DQS2 /DQS3 /DQS4 /DQS5 /DQS6 /DQS7 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 ODT0 ODT1 VREF VSS GND SKT-SODIMM20022U2GP
8 M_A_DQS[7..0]
1D8V_S3
Place these Caps near DM2

1 1 1 C241 C500 C486 C498 1 DDR_VREF_S3_1 SC2D2U6D3V3MX-1-GP C168
DY
DY
C293 Do Not Stuff
DY
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
1 2
C495
C212
C491
SCD1U16V2ZY-2GP
SC2D2U6D3V3MX-1-GP SCD1U16V2ZY-2GP
SC2D2U6D3V3MX-1-GP SC2D2U6D3V3MX-1-GP Do Not Stuff Do Not Stuff
Do Not Stuff SCD1U16V2ZY-2GP
GND
62.10017.691 2nd = 62.10017.891 3rd = 62.10017.K41
High 5.2mm
C238
DY
DY
Wistron Corporation
DDR2 Socket 1 (DM2)

Size Date:
A B C D
Document Number
HM40-MV
Sheet 17 of
E
Rev
SB
51
http://konweer.kiev.ua CONN LCD/CCD

LCDVDD
1015 modify F1 1015 modify LCD1 pin define 1016 modify LCD1 pin define 1017 modify USB signal connection
CCD Pin Pin 1 2 3 4 5 Symbol CCD_PWR USBUSB+ GND GND

R2 1 R1 1 USBPN4_R
SC10U10V5ZY-1GP
SCD1U25V3ZY-1GP
DY
2
Do Not Stuff
C302
C304
C305
SB
LCD1
1121 add EC87 for EMI demand 1128 modify LCD1
41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 42
SB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
USBPN4_R USBPP4_R CCD_PW R
2 0R0402-PAD 2 0R0402-PAD 1
USBPN4 USBPP4 F1
13 13 3D3V_S0
USBPP4_R
SC4D7U10V5ZY-3GP 2 1
EC1
1
EC2 Do Not Stuff Do Not Stuff
Do Not Stuff
3D3V_S0 C2 CLK_DDC_EDID DAT_DDC_EDID BLON_OUT_1 R124 2 CLK_DDC_EDID DAT_DDC_EDID 7 7
7 GMCH_TXACLK+ 7 GMCH_TXACLK7 GMCH_TXAOUT2+ 7 GMCH_TXAOUT27 GMCH_TXAOUT1+ 7 GMCH_TXAOUT17 GMCH_TXAOUT0+ 7 GMCH_TXAOUT0-
DY
69.50007.691 2ND = 69.50007.771
DY
BLON_OUT 1 33R2J-2-GP BRIGHTNESS_CN DCBATOUT F2
PW R_INVERTER
2
POLYSW -1D1A24V-GP
1 1 1
C3
EC87
20.F1296.040
DY
R126 R125
2 2
1 Do Not Stuff 1 Do Not Stuff
L_BKLTCTL 7
BRIGHTNESS_CN
BRIGHTNESS 33
DY
BLON_OUT
BLON_OUT 33
C309 Do Not Stuff
C308
DY
DY
SB SB
1106 modify R125,R126 1125 modify R125,R126
3D3V_S0
1014 swap the part

RN34 SRN2K2J-1-GP
CLK_DDC_EDID DAT_DDC_EDID
3 4
2 1
Layout 40 mil
LCDVDD U30 7 GMCH_LCDVDD_ON GMCH_LCDVDD_ON 3D3V_S0
DY
C307 G5285T11U-GP SC4D7U6D3V3KX-GP
C306 Do Not Stuff
SB
C303 Do Not Stuff
1 2 3
EN GND OUT
IN#5 IN#4
5 4
ACES-CONN40C-4-GP
69.50007.A31EC3 2nd = 69.50007.A41

SCD1U50V3ZY-GP
1015 modify component size of C303,C307
UMA Two Phase 2
C1
FUSE-1D1A6V-4GP-U
DY
Do Not Stuff
SC10U25V6KX-1GP
DY
74.05285.07F 2nd = 74.09724.09F
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Date: Document Number
LCD CONN
Sheet 18 of
Rev
HM40-MV
Friday, November 28, 2008 51
SB
Layout Note: Place these resistors close to the CRT-out connector 7 GMCH_RED
Ferrite bead impedance: 10 ohm@100MHz

L3
Hsync & Vsync level shift

5V_S0 CRT_R
1016 modify U8
68.00119.081 2nd = 68.00230.021

L2
4
1
CRT_G
7 GMCH_GREEN
C44 SCD1U16V2ZY-2GP
4
14
68.00119.081 2nd = 68.00230.021

L1 7 GMCH_BLUE
1 1 1 1 8 7 6 5
EC20 EC19 Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff
2 1 1
C46 C42
CRT_B
7 GMCH_HSYNC
2 14
3
U8A TSAHCT125PW -GP
CRT_HSYNC1
RN39 SRN150F-1-GP
DY
1 2 3 4
DY
DY
68.00119.081 2nd = 68.00230.021
7 GMCH_VSYNC
5 1 1
DY
C21 Do Not Stuff
DY
7
C27 Do Not Stuff
U8B TSAHCT125PW -GP
Layout Note: * Must be a ground return path between this ground and the ground on the VGA connector. Pi-filter & 150 Ohm pull-down resistors should be as close as to CRT CONN. RGB will hit 75 Ohm first, pi-filter, then CRT CONN.
1016 modify L1,L2 and L3
73.74125.L13 2nd = 73.74125.L12
EC18 SBK160808T-100Y-N-GP
C38
SC6D8P50V2DN-GP
SC6D8P50V2DN-GP
SC6D8P50V2DN-GP
73.74125.L13 2nd = 73.74125.L12 CRT_VSYNC1
CRT I/F & CONNECTOR

2
DDC_CLK & DATA level shift

5V_S0
83.R5003.C8F
3D3V_S0
2
17
CRT_R 5V_CRT_S0 CRT_G CRT_B
SB
1127 modify CRT1
6 1 7 2 8 3 9 4 10 5
11 12 13 14 15 16
VIDEO-15-75-GP-U DAT_DDC1_5 CRT_HSYNC1 CRT_VSYNC1 CLK_DDC1_5
1 2 3 4
2 1
CRT_IN#_R
6 1 7 2 8 3 9 4 10 5
3D3V_S0
5V_CRT_S0
1
F3 5V_CRT_DDC
CRT1
2nd = 83.R5003.H8H 3rd = 83.5R003.08F

CH551H-30PT-GP D4
3 4
1016 modify D4
8 7 6 5
RN37 SRN10KJ-6-GP
RN38 SRN2K2J-1-GP
FUSE-1D1A6V-4GP-U
69.50007.691 2nd = 69.50007.771

Q5
3 2 1
CRT_IN#_R CLK_DDC1_5

5 6
20.20715.015
CRT_VSYNC1 CRT_HSYNC1 CLK_DDC1_5 DAT_DDC1_5
2nd = 20.20728.015
7 GMCH_DDCCLK 7 GMCH_DDCDATA 2N7002DW -1-GP
DAT_DDC1_5
1
C30 SC18P50V2JN-1-GP SC18P50V2JN-1-GP
C23 SC18P50V2JN-1-GP
C20 Do Not Stuff
5V_S0 C26 Do Not Stuff D3
UMA Two Phase 2
2
36 CRT_IN#_R CRT_IN#_R
DY
DY
1
DY
Wistron Corporation
Do Not Stuff 1
Size Date:
A B C D
Document Number
CRT Connector
HM40-MV
Sheet
E
Rev
SB
19 of 51
0912 add these parts for EMI demand 1021 modify SATA1 1001 delete these parts for EMI demand
SATA1
SATA Connector
23 NP1 1 2 3 4 5 6 7
SATA_TXP0 12 SATA_TXN0 12
SATA_RXN0 12 SATA_RXP0 12
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 NP2 24
SKT-SATA22P-47-GP
B
1021 modify TC5
5V_S0
TC5
C50
K
SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP
1016 modify D23

D5 SR24-GP
DY
Do Not Stuff
83.2R004.J8M 2nd = 83.2R004.H8M

B
62.10065.741
UMA Two Phase 2
Wistron Corporation
5 4 3 2
Document Number
HDD
HM40-MV
Sheet
1
Rev
SB
20 of 51
SATA ODD Connector

5V_S0
D D
C273 SCD1U16V2ZY-2GP 2 2
TC7 SC10U10V5ZY-1GP
0912 add these parts for EMI demand 1001 delete these parts for EMI demand
ODD1 P2 P3 S2 S3 S6 S5 +5V +5V A+ AB+ BDP MD GND GND GND GND GND GND GND P1 P4 S1 S4 S7 P5 P6 8 9 ODD_DP ODD_MD 1 1 TP40 Do Not Stuff TP39 Do Not Stuff
NP1 NP2 NP1 NP2 SKT-SATA7P+6P-22-GP
12 12 12 12
SATA_TXP1 SATA_TXN1 SATA_RXP1 SATA_RXN1
62.10065.351
2nd = 62.10065.521 3rd = 62.10065.421
UMA Two Phase 2

A
Wistron Corporation
ODD
Size Document Number Rev
HM40-MV
5 4 3 2
SB
21 of 51
1
Sheet
BLUETOOTH MODULE
1.5A / High Active Voltage 2V
D D
3D3V_BT_S0 U48 3D3V_BT_S0 1 EC85 SCD1U16V2ZY-2GP 1 2 3 VOUT GND FLG# VIN EN 5 4 3D3V_S0 1 C530 SC4D7U10V5ZY-3GP 2
BLUETOOTH_EN 33
RT9715CGBG-GP
74.09715.A7F 2nd = 74.05240.A7F
SB 1113 modify U48
BLUE1 6 4 3 2 1 5 USB_7USB_7+ R123 Do Not Stuff 2 1 2 1 R122 Do Not Stuff USBPN7 USBPP7 13 13 1 3D3V_BT_S0 EC92 EC93 2 ETY-CON4-21-GP-U
EC21 put near BLUE1 / all USB put one choke near connector by EMI request
DY
Do Not Stuff
DY
20.F0984.004 2nd = 20.D0197.104
48 48 48
USB_7USB_7+ 3D3V_BT_S0
1017 modify USB signal connection SB 0930 modify BLUE1

B
1125 add EC92 and EC93

B
1017 modify BLUE1
UMA Two Phase 2

A
Wistron Corporation
Bluetooth
HM40-MV
Sheet
1
Rev
SB
22 of 51
Date: Wednesday, November 26, 2008

5 4 3 2
1017 modify USB signal connection 1021 modify and swap these parts(USB1 and USB2)
D D
5V_USB1_S0
USB2
R218 Do Not Stuff 2 1 2 1 R219 Do Not Stuff
USB2
6 8 1
USB_9USB_9+
13 13
USBPN9 USBPP9
2 3 4 7 5
SKT-USB-177-GP
22.10218.U11
5V_S5 5V_USB1_S0
U12
5V_USB1_S0
USB1 13 13 USBPN0 USBPP0 R244 Do Not Stuff 2 1 2 1 R245 Do Not Stuff
USB1
6 8 1 2 3 4 7 5
USB_0USB_0+
RT9715DGF-GP 74.09715.079
C142 SC4D7U10V3KX-GP
33 USB_PWR_EN#
1 2 3 4
GND VIN VIN EN#
VOUT VOUT VOUT FLG#
8 7 6 5
USB_OC#0 13
EC32
DY
Do Not Stuff
2nd = 74.00547.A79
SKT-USB-177-GP
22.10218.U11
1021 delete TC23
5V_USB1_S0
0912 add these parts for EMI demand

USB_0USB_0+ USB_9USB_9+
100 mil
EC69 Do Not Stuff
EC74 Do Not Stuff
EC72 Do Not Stuff
EC70 Do Not Stuff
EC76 Do Not Stuff
EC75 Do Not Stuff
80.15715.12L 2nd = 77.C1571.09L

B
DY
DY
DY
DY
TC22 ST150U6D3VBM-2-GP
DY
DY
UMA Two Phase 2

A A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Date:
5 4 3 2
Document Number Monday, December 01, 2008
USB
HM40-MV
Sheet
1
Rev
SB
23 of 51
3D3V_S5 R69

2
3D3V_LAN_S5 0R2J-2-GP Close 1 1 2 C119
to AR8114 Pin2
1D2V_LAN_S5 PCIE_TXP1 PCIE_TXN1 CLK_PCIE_LAN_1 1 CLK_PCIE_LAN#_1 C127 1 C126 AVDDL_REG 1D2V_LAN_S5_D 1D2V_LAN_S5_D 1D2V_LAN_S5
DY
DY
13 13
2 SCD1U10V2KX-4GP 2 SCD1U10V2KX-4GP
CLK_PCIE_LAN 3 CLK_PCIE_LAN# 3
1
R71 0R2J-2-GP
SB
AR8132 use 0 ohm resiter AR8114A Atheros suggestion change to Bead 60 ohms/100Mhz 500mA (68.60090.0D1)
2
AVDDL_REG
LAN_RXP1 C130 LAN_RXN1 C129
1 1
25 10M/100M_LED# LAN_ACT_LED
PCIE_RXP1 13 PCIE_RXN1 13
FOR AR8114A LAN_ACT_LED is high enable pin

U11 3D3V_LAN_S5
R70 10KR2J-3-GP
1016 modify RN53 and U10

49 48 47 46 45 44 43 42 41 40 39 38 37
C449 3D3V_LAN_S5
GND LED_10_100# LED_ACT# DVDDL DVDDL RX_N RX_P AVDDL/AVDDL_REG REFCLKP REFCLKN AVDD TX_P TX_N
25 LAN_ACT_LED
2 1 2
RN53 SRN4K7J-8-GP
SCD1U10V2KX-4GP
VDD18O LAN_RST CTRL12 AVDDHO
C109 SC1KP50V2KX-1GP
C102
SCD1U10V2KX-4GP
SC1KP50V2KX-1GP
TRXP0 TRXN0 AVDDH AVDD TRXP1 TRXN1 AVDDH NC#20 NC#21 AVDDL NC#23 NC#24
1001 modify RN9
AVDDH
1D2V_LAN_S5 MDI1+ MDI1-
MDI1MDI1+ MDI0MDI0+
1 2 3 4
8MDIS1_LAN 1 C95 7 6MDIS0_LAN 1 5

SRN49D9F-1-GP
MDI0+ MDI0-
RN9
C94
1D2V_LAN_S5
R68 7,13,30,31,33,34 PLT_RST1#
25 25
MDI0+ MDI0-
1 0R2J-2-GP
LAN_RST
XTAL-25MHZ-96GP C103 SC15P50V2JN-2-GP
13 PCIE_W AKE#
1D2V_LAN_S5 LANX1 LANX2
C104
1 2 3 4 5 6 7 8 9 10 11 12
VDD18O VDD33 PERST# WAKE# CTR12 VDDHO VBG1P18V AVDD XTLO XTLI AVDDL_REG RBIAS
AVDD NO_CONN TESTMODE SMDATA VDDL SMCLK TWSI_DATA TWSI_CLK DVDDL LED_DUPLEX# NC#26 AVDDH
36 35 34 33 32 31 30 29 28 27 26 25
1D2V_LAN_S5 3D3V_LAN_S5 TP24 Do Not Stuff 1 Do Not Stuff 1 TP23
Close to U13 Pin8

U10
VPD_DATA VPD_CLK 1D2V_LAN_S5_D
R61 Do Not Stuff
4 3
1D2V_LAN_S5_D
SB
1126 add R303,R304
1 2 3 4
NC#1 NC#2 E2 VSS
VCC WC# SCL SDA
8 7 6 5
VPD_CLK VPD_DATA
DY
R303 1
PCIE_REQ_LAN#
M24C08-W MN6TP-GP
Do Not Stuff
72.24C08.I01
R59 2K37R2F-GP
AR8132
R304 0R2J-2-GP
2nd = 72.24C08.J01
AR8114
13 14 15 16 17 18 19 20 21 22 23 24
AR8114-AL1E-GP
82.30020.791 2nd = 82.30020.851 1113 X3 LANX2 1 2 LANX1
SB
modify
C103 and C106
C106 SC18P25V2JN-GP
1D2V_LAN_S5_D
Close to AR8114 Pin28

C114 Do Not Stuff
DY
1 C113 1 C107 1 C124DY 1 C123
1D2V_LAN_S5
DY
25 25 MDI1+ MDI1-
Close to AR8114 Pin32 Close to AR8114 Pin45 Close to AR8114 Pin46
AR8114 use 0ohm resister AR8132 Atheros suggest to change 4.7uH choke
SB
2 Do Not Stuff 2 SCD1U10V2KX-4GP 2 Do Not Stuff 2 SCD1U10V2KX-4GP

B
3D3V_LAN_S5
R79
1 1
3D3V_LAN_S5_2
1D8V_LAN_S5 C146 SC4D7U6D3V3KX-GP
L19 1
Do Not Stuff
2
R295 1 VDD18O
SB 1128 Add L19
Close to AR8114 Pin8 Close to AR8114 Pin16 Close to AR8114 Pin22
0R2J-2-GP R66 4K7R2J-2-GP CTRL12
C143
AR8132
2
SB
DY
1 C101 1 C125 1 C108 1 C99 1 C131 2 Do Not Stuff 2 SCD1U10V2KX-4GP 2 SCD1U10V2KX-4GP 2 SCD1U10V2KX-4GP 2 Do Not Stuff
DY
3 1 2
BCP69-GP Q8
Do Not Stuff
0R2J-2-GP
AR8114
2
C538
SB
C121 Do Not Stuff
Close to AR8114 Pin36 Close to AR8114 Pin39
C537 1D2V_LAN_S5
Do Not Stuff
84.00069.B1B 2nd = 84.DCP69.01B 3rd = 84.00069.A1B
AR8132
AR8132
1
Do Not Stuff
SB
Close to AR8114 Pin6 Close to AR8114 Pin15 Close to AR8114 Pin19 Close to AR8114 Pin25
AVDDH
DY
1 C110 1 C105 1 C98 1 C100 2 SC1U6D3V2KX-GP 2 SCD1U10V2KX-4GP 2 SCD1U10V2KX-4GP 2 Do Not Stuff
C115 Do Not Stuff
DY Close to AR8114 Pin1
1016 modify Q8
SB
DY
C132 SC10U6D3V5KX-1GP
SB
1D2V_LAN_S5_D 1D2V_LAN_S5 1D8V_LAN_S5 R296 1 Do Not Stuff R67 AVDDHO R297 1 0R2J-2-GP AVDDH
DY
2
A
UMA Two Phase 2

A
AR8132
2 1
0R2J-2-GP
AR8114
C539 SC1U6D3V2KX-GP
1D8V_LAN_S5
Wistron Corporation
Atheros suggestion change to Bead 60 ohms/100Mhz 500mA (68.60090.0D1)
AR8114 SB
Close to AR8114 Pin6
C89
DY
2 Do Not Stuff 2 SC1KP50V2KX-1GP
Title
Atheros AR8114/8132
Size A3 Date: Document Number Rev
1 C120
HM40-MV
Friday, November 28, 2008 Sheet
1
SB
24 of 51
3D3V_LAN_S5 10M/100M_LED# R214 1 2 510R2F-L-GP CONN_PW R_2 ACT_LED_B2 ACT_LED_B1
4
EC67 1 EC68 1 EC61 1 EC64 1
DY Do Not Stuff
2 2 2 2
LAN Connector
RJ1 24 10M/100M_LED# CONN_PW R_2 RJ45_1
DY Do Not Stuff DY Do Not Stuff DY Do Not Stuff

9 A1 A2 A3 1 2 3 4 5 6 7 8 B1 B2 10
RJ45-125-GP-U1 ACT_LED_B1 ACT_LED_B2
A2(+) A1(-)::GREEN A2(+) A3(-):ORANGE

4
SB
SB AR8114
24 LAN_ACT_LED R298 1 R299 1
RJ45_2 RJ45_3 RJ45_45 RJ45_6
2 0R2J-2-GP ACT_LED_B1 2 Do Not Stuff ACT_LED_B2
SB
3D3V_LAN_S5
RJ45_78 ACT_LED_B1 ACT_LED_B2
AR8132 AR8132
R300 1 2 Do Not Stuff R301 1 2 510R2F-L-GP
B1(+) B2(-):YELLOW
AR8114
10/100 Lan Transformer

XF1
22.10277.021
2nd = 22.10277.081
MCT1 MCT2 RJ45_45 RJ45_78
1D8V_LAN_S5
R58
24
MDI1-
1 3 2 5 4 6
12 10 11 8 9 7
RJ45_6 MCT2
XRF_TDC
0R2J-2-GP
24 24
MDI1+ MDI0-
RJ45_3 RJ45_2 MCT1
SB
C85
SB
C88
4 3 2 1
DY
DY
DY
24
MDI0+
RJ45_1
RN6 SRN75J-1-GP
Do Not Stuff
Do Not Stuff
XFORM-271-GP
LAN_TERMINAL
C64 1
5 6 7 8
2
SC1KP2KV8KX-GP
68.HD081.301 2nd = 68.68160.30B 3rd = 68.NS014.301
1016 modify XF1
1.route on bottom as differential pairs. 2.Tx+/Tx- are pairs. Rx+/Rx- are pairs. 3.No vias, No 90 degree bends. 4.pairs must be equal lengths. 5.6mil trace width,12mil separation. 6.36mil between pairs and any other trace. 7.Must not cross ground moat,except RJ-45 moat. RJ11 signal must leave the other signal or power plane 100mil.
DOC_TIP,DOC_RING,TIP,RING: W/S : 10/100 @ Surface layers 10/20 @ Inner layers

1
10/100 LAN Transformer TD+ --> TX+ TD- --> TXRD+ --> RX+ RD- --> RX-
RJ45 PIN RJ45-1 RJ45-2 RJ45-3 RJ45-6
UMA Two Phase 2
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date:
B C D
Document Number
LAN Connector
HM40-MV
Sheet
E
Rev
SB
25 of 51
3D3V_S0
VDD_20561
1 R102 2 Do Not Stuff
3VA_S0
DY
1
C259
C242 C248 SCD1U10V2KX-4GP DVDD_1_8 Do Not Stuff 2
3VA_S0 C264 SCD1U10V2KX-4GP
L18
3D3V_S0 5V_S0 3VA_S0
2
U19
SB
1118 delete C245 and C270
SCD1U10V2KX-4GP 3D3V_S0
DY
D
AUD_AVEE
68.00119.081 2nd = 68.00230.021

C277 C276 SCD1U10V2KX-4GP Do Not Stuff 2
1 2 3
VIN GND EN
Do Not Stuff
VOUT NC#4
5 4 1 2
C280 Do Not Stuff
DY
C247
1001 Add R107 SB SB 1113 modify 2nd of U19

C274 Do Not Stuff
0911 add net name(DVDD_1_8)
1118 delete R107 and add L18
DY
SB
Do Not Stuff 2nd = 74.09198.G7F
DY
SCD1U10V2KX-4GP
1113 modify 2nd of U19
9 4 3 44
U18
VDD_IO DVDD_1_8 DVDD_3_3 DVDD
ACZ_SDATAOUT_AUDIO SC27P50V2JN-2-GP
C
C541
12 ACZ_RST#_AUDIO
0911 add net name(ACZ_SDATAIN0_R)
AVDD AVDD AVEE
26 40 36
11
RESET#
PORTA_L 5.11K PORTA_R
34 35 19 20 21 18 16 17 27 28 14 15 29 30 31
FRONTL 28 FRONTR 28
1014 modify these nets
12 ACZ_BITCLK_AUDIO 12 ACZ_SYNC_AUDIO 12 ACZ_SDATAIN0 12 ACZ_SDATAOUT_AUDIO
R101 1 2 ACZ_SDATAIN0_R ACZ_SDATAOUT_AUDIO 47R2J-2-GP
6 10 8 5 43 42 12 48
BIT_CLK SYNC SDATA_IN SDATA_OUT DIB_P DIB_N
MICBIASB MIC_L MIC_R
RN33
SB
1126 add C541 and modify R101

RN56 C501 1 2
MICBIASC PORTC_L 20K PORTC_R PORTD_L PORTD_R
MICBIASC
1 2
4 3
AUD_MICIN_L AUD_MICIN_R
SRN2K2J-1-GP
MIC1-L_PORT-C MIC1-R_PORT-C
33 13
KBC_BEEP ACZ_SPKR
1 2
4 3
AUDIO_BEEP
AUDIP_PC_BEEP
PC_BEEP S/PDIF
39.2K
C251 2 C255 2
1 SC2D2U10V3KX-1GP 1 SC2D2U10V3KX-1GP
AUD_MICIN_L AUD_MICIN_R
28 28
SC1U10V3KX-3GP
SRN1KJ-7-GP
PORTB_L 10K PORTB_R MONO STEREO_L STEREO_R
AUD_GPIO2 AUD_GPIO1 27 EAPD#
45 46 47
GPIO2 GPIO1 EAPD#/GPIO0
SOUNDL 27 SOUNDR 27
CX20561
1 2
SENSEA VREF FLY_P FLY_N
13 24 39 37 22 23 32 33
CX_SENSE AUD_AVREF C271 FLY_P 1 SC1U10V3KX-3GP 2 FLY_N VREF_LO VREF_HI
Default gain is -6dB without populating the 10K-ohms pull-down resistors going to GPIO1 and GPIO2. 0912 add the part for EMI demand
AUD_GPIO1
B
VREF_LO VREF_HI RESERVED#32 RESERVED#33
C505
C504
7 41
49
AUD_GPIO2
25 38
CX20561-15Z-GP
SCD1U10V2KX-4GP
SC10U10V5ZY-1GP 2
DVSS DVSS
AVSS AVSS
GND
2
SC1U10V3KX-3GP SC1U10V3KX-3GP
PC BEEP GAIN CONTROL
DMIC_CLOCK DMIC_1/2
C507 C506
ACZ_BITCLK_AUDIO
0911 add net name(FLY_P,FLY_N,VREF_LO,VREF_HI)
1
R106 Do Not Stuff
EC35 Do Not Stuff 3VA_S0
R105 10KR2J-3-GP
DY
1 1
DY
2
R257 5K1R2F-2-GP R256 1 5K1R2F-2-GP 2
GAIN
10K GPIO RESISTORS R615 R614 CX_SENSE Populate
LINEOUT_JD# MIC_JD# 28
28
0dB
Populate
1 R258
20KR2F-L-GP -6dB Omit Omit
1014 modify R258 from 10k to 20k ohm

-12dB Populate Omit
-18dB
Omit
Populate
UMA Two Phase 2
Wistron Corporation
5 4 3 2
Azalia codec CX20561

Document Number Rev
HM40-MV
W ednesday, November 26, 2008 Sheet
1
SB
26 of 51
AUDIO OP AMPLIFIER
5V_S0 G2 5VA_OP_S0
1
Do Not Stuff
4
2 1
C6 SC4D7U10V5ZY-3GP
AGND
2
26 SOUNDL C15 1 RN2
1009 modify net name for GND to AGND

2
L_LINE_IN_1 LIN+RC
SCD47U16V3ZY-3GP
1 2
4 3
L_LINE_IN LIN+
SRN20KJ-GP-U C13 1
RN3
5VA_OP_S0
3
SC4D7U10V5ZY-3GP 2 1
C14 C16
1 1
2 RIN+RC SCD47U16V3ZY-3GP 2 LIN+RC SCD47U16V3ZY-3GP
RINRIN+ LINLIN+
LVO1 LVO2 RVO1 RVO2
C7
SCD47U16V3ZY-3GP 5VA_OP_S0 3D3V_S0 SRN20KJ-GP-U
26
SOUNDR
R_LINE_IN_1 RIN+RC
1 2
4 3
R_LINE_IN RIN+
1 2

C9 1 SC4D7U6D3V3KX-GP
RN35 SRN10KJ-5-GP
U1
2 11 7 8 15 16
VCC VCC
BYPASS SHUTDOWN
5 14 1 4 12 9 3 10 17
BYPASS
AGND
4 3
R134
DY
AGND
AGND AGND
6 13
VSS VSS NC#6 NC#13

G1454R41U-GP 74.01454.013
SC1U16V3ZY-GP
C8
R_LINE_IN RIN+ L_LINE_IN LIN+
SPKR_LSPKR_L+ SPKR_RSPKR_R+
28,48 28,48 28,48 28,48
1 Do Not Stuff
R135
AMP_SHUTDOW N# 33
Q1
G
2N7002-11-GP
EAPD#_R
1 0R2J-2-GP
EAPD#
26
84.27002.N31
GND
AGND
AC decopling
RN36 R5 R4
2 2
1 0R2J-2-GP 1 Do Not Stuff
L_LINE_IN LIN+ R_LINE_IN RIN+
1 2 3 4
8 7 6 5
SRN51KJ-GP
DY
AGND
UMA Two Phase 2
Wistron Corporation
A B C D
Document Number
AUDIO AMP HM40-MV

Sheet
E
Rev
SB
27 of 51
MIC IN
MIC1
0930 add 2nd for MIC1

D
1015 modify RN57

RN57 26 AUD_MICIN_R 26 AUD_MICIN_L 26 MIC_JD# AUD_MIC_R AUD_MIC_L
1 2 1 1
R260 R259
4 3
SRN100J-3-GP
EU3
EU4
NP2 NP1 5 4 3 6 2 1
SHIELDING
DY DY
EC79 PHONE-JK233-GP-U3
2 2
DY
Do Not Stuff 2
DY
MLVS0603M04-1-GP 2 MLVS0603M04-1-GP
22.10133.B01 2nd = 22.10251.491
LINE OUT
0930 modify
LOUT1
LOUT1
SB
1126 modify EU1,EU2 and add EU3,EU4
26 LINEOUT_JD# FRONTR FRONTL
RN58
26 26
1 2
4 3
LOUT_R+1 LOUT_L+1
SRN68J-5-GP
NP2 NP1 5 4 3 6 2 1
EU1
EU2
1 2
EC81
ERN1
EC82 Do Not Stuff
PHONE-JK235-GP-U2 Do Not Stuff
1014 swap the part
DY
4 3
DY
1
DY
1
22.10133.B21
MLVS0603M04-1-GP MLVS0603M04-1-GP
2nd = 22.10251.511
0930 add 2nd for SPK1
Internal Speaker
SB
1119 modify SPK1
SPK1 27,48 27,48 27,48 27,48 SPKR_LSPKR_L+ SPKR_RSPKR_R+ SPKR_LSPKR_L+ SPKR_RSPKR_R+ ER1 ER2 ER3 ER4
1 1 1 1
2 0R3-0-U-GP SPKR_L-_R 2 0R3-0-U-GP SPKR_L+_R 2 0R3-0-U-GP SPKR_R-_R 2 0R3-0-U-GP SPKR_R+_R
4 3 2 1 5
ACES-CON4-7-GP-U
DY DY
2 2 2 2
1 1 1 1
DY DY
20.F0772.004
UMA Two Phase 2
A
SHIELDING
B
Do Not Stuff
EC6 EC7 EC8 EC9 Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff
Wistron Corporation
2
Document Number
AUDIO JACK HM40-MV

Sheet
1
Rev
SB
28 of 51
MDC 1.5 CONN
0912 add the part for EMI demand 1002 modify MDC1 SB 1112 delete MDC function
UMA Two Phase 2
Wistron Corporation
MDC
Size Document Number Rev
HM40-MV
Date: Monday, November 24, 2008
5 4 3 2
SB
29 of 51
Sheet
1
3D3V_S0 3D3V_D_S0 XD_CD# SD_WP SD_CD# XD_D4/SD_DAT1 XD_D5/MS_BS XD_D3/MS_D1 SD_DAT0/XD_D6/MS_D0 SD_DAT7/XD_D2/MS_D2 MS_INS# SD_DAT6/XD_D7/MS_D3 SD_CLK/XD_D1/MS_CLK SD_DAT5/XD_D0 SD_DAT4/XD_WP# XD_R/B# SD_DAT3/XD_WE# SD_DAT2/XD_RE# XD_ALE XD_CE# XD_CLE R84 Do Not Stuff 1 2
CARD_3D3V_S0
DY
1
C186 Do Not Stuff
0910 update footprint of

SP1 SP2 SP3 SP4 SP5 SP6 SP7 SP8 SP9 SP10 SP11 SP12 SP13 SP14 SP15 SP16 SP17 SP18 SP19 19 20 21 23 25 26 27 28 29 31 34 35 37 38 39 40 41 42 43
U15
C185 SC1U10V3KX-3GP
2
R85 Do Not Stuff 1 2
C199 SCD1U16V2ZY-2GP AV_PLL VREG 3V_VBUS_S0
9 1 10 8
CARD_3V3 AV_PLL VREG 3V3_IN D3V3 D3V3

U15
1015 modify component size of C182

MS_D5 MS_D4
24 22
3D3V_S0
2 1
C182 SC4D7U6D3V3KX-GP C197 Do Not Stuff 3D3V_D_S0
DY
DY
C192 Do Not Stuff
33 11
RTS5159-GR-GP
NC#30 NC#7 NC#3
30 7 3
MODE_SEL SD_CMD
XTAL_CTR
R86 1
2RREF
R96
7,13,24,31,33,34
PLT_RST1#
5 4
13
47 48
17 16
0R2J-2-GP
DY

13 13 USBPP11 USBPN11 3D3V_D_S0
3D3V_D_S0
RST#
R100 100KR2J-1-GP
MODE_SEL 3 R94 0R2J-2-GP CLK48_5159
C228
5 IN1 CARD-READER (SD/MMC/MS/MS PRO/XD)

CARD1 SD_DAT0/XD_D6/MS_D0 XD_D4/SD_DAT1 SD_DAT2/XD_RE# SD_DAT3/XD_W E# SD_CMD SD_CLK/XD_D1/MS_CLK SD_CD# SD_W P SD_DAT0/XD_D6/MS_D0 XD_D3/MS_D1 SD_DAT7/XD_D2/MS_D2 SD_DAT6/XD_D7/MS_D3 XD_D5/MS_BS MS_INS# SD_CLK/XD_D1/MS_CLK
C240 SC1U10V3KX-3GP
DY
Do Not Stuff
15 18
1 Do Not Stuff
RST#
1 R97
RST#_CHIP
EEDO EEDI
EESK EECS
XTLO XTLI
1009 add R96
6K19R2F-GP
45 36 14 2 44
MODE_SEL SD_CMD GPIO0 RREF RST#
GND GND GND GND
6 12 32 46
DP DM
71.05159.00G
1009 modify this net 1013 modify card1
CARD_3D3V_S0
23 14 33 8 9 26 27 28 30 31 32 1 2 3 4 5 6 7 34 NP2 NP1
SD_VCC MS_VCC XD_VCC XD_D0 XD_D1 XD_D2 XD_D3 XD_D4 XD_D5 XD_D6 XD_D7 XD_R/B XD_RE XD_CE XD_CLE XD_ALE XD_WE XD_WP XD_CD_SW NP2 NP1
SD_DAT0 SD_DAT1 SD_DAT2 SD_DAT3 SD_CMD SD_CLK SD_CD_SW SD_WP_SW MS_DATA0 MS_DATA1 MS_DATA2 MS_DATA3 MS_BS MS_INS MS_SCLK 4IN1_GND 4IN1_GND GROUND GROUND
25 29 10 11 12 24 36 35 19 20 18 16 21 17 15 13 22 38 37
SD_DAT0/XD_D6/MS_D0 XD_D4/SD_DAT1 SD_DAT2/XD_RE# SD_DAT3/XD_W E#
SD_CLK/XD_D1/MS_CLK SD_CMD SD_CD# SD_W P
SD_DAT5/XD_D0 SD_CLK/XD_D1/MS_CLK SD_DAT7/XD_D2/MS_D2 XD_D3/MS_D1 XD_D4/SD_DAT1 XD_D5/MS_BS SD_DAT0/XD_D6/MS_D0 SD_DAT6/XD_D7/MS_D3 XD_R/B# SD_DAT2/XD_RE# XD_CE# XD_CLE XD_ALE SD_DAT3/XD_W E# SD_DAT4/XD_W P# XD_CD#
EC40 Do Not Stuff
EC38 Do Not Stuff
EC39 Do Not Stuff
EC43 Do Not Stuff
EC36 Do Not Stuff
DY
DY
DY
DY DY
DY
DY
DY
CARD_3D3V_S0
UMA Two Phase 2

A
Wistron Corporation
C275 SC4D7U10V5ZY-3GP C279 Do Not Stuff 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Date: Document Number
1 2
CARD-PUSH-36P-GP-U1
DY
CARD READER- RTS5159

HM40-MV
Sheet
1
20.I0043.001
Rev
SB
30 of 51
Mini Card Connector(WLAN)

4 4
1D5V_S0
3D3V_MINI
3D3V_MINI
MINIC1
Do Not Stuff TP49
1MINI_W AKE#
53 NP1 1 3 5 7 9 11 13 15
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52
3 PCIE_REQ_MINI# 3 CLK_PCIE_MINI1# 3 CLK_PCIE_MINI1 33 33 E51_RxD E51_TxD
13 PCIE_RXN2 13 PCIE_RXP2 13 PCIE_TXN2 13 PCIE_TXP2 3D3V_MINI 5V_S5
17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 NP2 54
PLT_RST1#_W LAN C47
Do Not Stuff
DY
2 R37 300R2F-GP R168 2 1 DY Do Not Stuff
W IRELESS_EN 33 PLT_RST1# 7,13,24,30,33,34

USBPN3 13 USBPP3 13
LED_W W AN# LED_W PAN#
1 1
TP42 Do Not Stuff TP41 Do Not Stuff
W LAN_LED#_MC 36
SKT-MINI52P-20-GP
20.F1117.052 2nd = 62.10043.391
1015 modify component size of R158,R159

3D3V_S0 3D3V_S5
1 R159
3D3V_MINI
0R2J-2-GP 1 R158 2 Do Not Stuff
DY
1021 modify TC16

2
Place near MINIC1

3D3V_MINI 1D5V_S0
2
SB
1 1 1 1 1 1
DY
SB
TC16 Do Not Stuff
C332 SC1U6D3V2KX-GP
C334 Do Not Stuff
C333 Do Not Stuff
C330 SC1U6D3V2KX-GP
C356 Do Not Stuff
SB
DY
DY
Do Not Stuff 2nd = 77.C3371.051
DY
UMA Two Phase 2

1 1
Wistron Corporation
A B C D
Document Number
MINI CARD
HM40-MV
Sheet
E
Rev
SB
31 of 51
3D3V_S0 R165
G7922_FAN_TACH 48 G7922_FAN_DRIVE 48 G7922_FAN_TACH G7922_FAN_DRIVE FAN1
5 3 2 1 4
10KR2J-3-GP
0930 modify 1017 modify
FAN1 FAN1
*Layout* 15 mil
D11 SSM14PT-GP-U 83.1R004.080 3rd = 83.1R004.M8M 2nd = 83.1R004.K8M
MLX-CON3-10-GP-U
Layout notice : Both H_THERMDA and THERMDC routing 10 mil trace width and 10 mil spacing
20.F1000.003 2nd = 20.F0714.003
H_THERMDC
H_THERMDC
C376 SC470P50V2JN-GP 4 H_THERMDA H_THERMDA
1 2
2
49D9R2F-GP
G7922_VDD_3D3 5V_S0
3D3V_S0
R188
33 33
SMBC_Therm SMBD_Therm
THRM# 13 R177 Do Not Stuff
DY
ALERT# 2
1.For CPU Sensor

C374 must be near Q7
84.T3904.C11 2nd = 84.03904.L06
G7922_DXP2
2.System Sensor, Put between CPU and NB.
1124 modify U42
FAN1#25 FAN1#26
2 1
G7922_FAN_DRIVE
MMBT3904-4-GP Q14
POWER_OK CLK RESET# SGND1 SGND2 SGND3 DGND GND
14
VGATE_PW RGD
1
SCD1U16V2KX-3GP
C370
C373 must be near EMC2102

G7922_SGND2
Layout notice : Both SGND2 and DXP2 routing 10 mil trace width and 10 mil spacing
3D3V_S0
27 24
22 23
SDA SCL
ALERT#
DVCC DVCC
VCCS
C361 SC4D7U10V5ZY-3GP
C357 Do Not Stuff
U42
19
DY
SCD1U16V2ZY-2GP
SB
SB 1127 modify C377

C377 SC470P50V2JN-GP
DY
C272 Do Not Stuff
SB
H_THERMDA G7922_DXP2 G7922_DXP3
3 5 7
DXP1 DXP2 DXP3
FG1
28 25 26 11 12 13
G7922_FAN_TACH
C349
R178 10KR2F-2-GP
8 9 10 15 17 21
NC#8 NC#9 NC#10 NC#15 NC#17 NC#21
THERM_SET THERM# THERMTRIP#
V_DEGREE PURE_HW _SHUTDOW N#
TRIP_SET Pin Voltage V_DEGREE =(((Degree-75)/21)

R180 3KR2F-GP
SCD1U16V2ZY-2GP
C355
18 16
2 4 6
20
G7922_SGND3
Pin 9
CLK_32K MMBT3904-4-GP Q6
29
C372 must be near EMC2102 C375 must be near Q8

E 2
G7922RV1U-GP
84.T3904.C11 2nd = 84.03904.L06 3RD = 84.03904.H11
DY
C
C51 Do Not Stuff G7922_DXP3
-->Channel 3 Pin 10 --> Fan is OFF
3.HW T8 sensor
H_THERMDC G7922_SGND2 G7922_SGND3
THERM_SET =(Test-75)*(1/32)*(15/33)VCCS
G7922_PW ROK 39 EC60 Do Not Stuff
DY
RUN_POW ER_ON
SB 1125 modify RN40 and delete RN42

3D3V_S0 3D3V_AUX_S5 RN40
Q22
13
PM_SUS_CLK
CLK_32K_R
5 6 7 8 1
R170 240KR3-GP
4 3 2 1
SRN10KJ-6-GP
PURE_HW _SHUTDOW N# RSMRST# THRM# CLK_32K
2N7002-11-GP
84.27002.N31
32K suspend clock output
3D3V_AUX_S5
13,41 VGATE_PW RGD
Q21
D10 Do Not Stuff Do Not Stuff 2nd = 83.BAT54.X81 3rd = 83.00054.Z81 RSMRST# 33,39 (dummy, KBC already delay)
DY
UMA Two Phase 2
PURE_HW _SHUTDOW N#
RSMRST#
Layout notice : Both SGND3 and DXP3 routing 10 mil trace width and 10 mil spacing
T8 90 degree
Wistron Corporation
2N7002-11-GP
84.27002.N31
2
C335 DY Do Not Stuff
Thermal/Fan Controllor
HM40-MV
Sheet 32 of
Rev
SB
51
SC10U10V5ZY-1GP 2 1
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP 2 1
SCD1U16V2ZY-2GP 2 1
SCD1U16V2ZY-2GP
SC10U10V5ZY-1GP 2 1
C366
C363
C374
C353
C354
C386
C380
C359
C362
DY
DY
SCD1U16V2ZY-2GP
Do Not Stuff 2 1
SB
Do Not Stuff 2 2 7,13,24,30,31,34 PLT_RST1# R189 1 2 0R2J-2-GP C368 45 BAT_IN# 1 BAT_IN# Do Not Stuff
3D3V_AUX_S5 AVCC 2 R184 1 Do Not Stuff
3D3V_AUX_S5
3D3V_S0
SB
1016 modify X1
SC15P50V2JN-2-GP SC15P50V2JN-2-GP
3D3V_S0
82.30001.861 2nd = 82.30001.691

X-32D768KHZ-46GP C67 2 3 2 1
C359,C362 colse to Pin VDD

C60 U9A 102 19 46 76 88 115 80 4
DY
2
4
1 OF 2
1KBC_XO_R 2
GPIO41
AVCC
VDD
VCC VCC VCC VCC VCC
2 R201 4 1
1 Do Not Stuff
4
DY
R46 X1 1 R49 2 20MR3-GP KBC_XI 77 U9B 2 OF 2
33KR2J-3-GP 33KR2J-3-GP
PLT_RST1#_1 3 PCLK_KBC 12,34 LPC_LFRAME# 12,34 LPC_LAD0 12,34 LPC_LAD1 12,34 LPC_LAD2 12,34 LPC_LAD3 13 INT_SERIRQ 13 PM_CLKRUN# 12 12 KBRCIN# KA20GATE 7 GMCH_BL_ON ECSCI#_KBC ECSWI#_KBC 2
DY
1 Do Not Stuff C371 1
R187 Do Not Stuff
2PCLK_KBC_RC
DY
124 7 2 3 126 127 128 1 125 8 122 121 29 9 123
GPIO10/LPCPD# LRESET# LCLK LFRAME# LAD0 LAD1 LAD2 LAD3 SERIRQ GPIO11/CLKRUN# KBRST# GA20 ECSCI#/GPIO54 GPIO65/SMI# GPIO67/PWUREQ#
VREF
104 97 98 99 100 108 96 AD_IA 46 TP_LOCK_BN# 36 WIRELESS_BTN# 36
A/D LPC
GPI90/AD0 GPI91/AD1 GPI92/AD2 GPI93/AD3 GPIO05 GPIO04
32KX1/32KCLKIN
27 AMP_SHUTDOWN# 101 105 106 107 KBC_THERMALTRIP# PCB_VER0 PCB_VER1 KBC_THERMALTRIP# 39
KBC_XO 79 30 63 117 31 32 118 62
32KX2 GPIO55/CLKOUT GPIO14/TB1 GPIO20/TA2 GPIO56/TA1 GPIO15/A_PWM GPIO21/B_PWM GPIO13/C_PWM
D/A
GPI94 GPI95 GPI96 GPI97
CRT_DEC# 36
13 46 26 13 18
PM_PWRBTN# CHG_ON# KBC_BEEP EC_TMR BRIGHTNESS
THERMAL-----> BATTERY----->
32 SMBD_Therm 32 SMBC_Therm 45,46 BAT_SDA 45,46 BAT_SCL
68 67 69 70
GPIO74/SDA2 GPIO73/SCL2 GPIO22/SDA1 GPIO17/SCL1
SMB
39,42,48 S5_ENABLE
S5_ENABLE 2 2K2R2J-2-GP
36 NUM_LED 81 GPIO66/G_PWM
SP
22 BLUETOOTH_EN
SHBM
31 WIRELESS_EN 36 WLAN_TEST_LED
84 83 82 91
GPIO77 GPIO76/SHBM GPIO75 GPIO81
SPI
GPIO
31 31
E51_TxD E51_RxD
E51_TxD E51_RxD
111 113 112 114 14 15
GPO83/SOUT_CR/BADDR1 GPIO87/SIN_CR GPO84/BADDR0 GPIO16 GPIO34 GPIO36
38
DC_BATFULL 1 R192
S5_ENABLE_KBC
SER/IR
GPIO01/TB2 GPIO03 GPIO06 GPIO07 GPIO23 GPIO24 GPIO30 GPIO31 GPIO32/D_PWM GPIO33/H_PWM GPIO40/F_PWM GPIO42/TCK GPIO43/TMS GPIO44/TDI GPIO45/E_PWM GPIO46/TRST# GPIO47 GPIO50/TDO GPIO51 GPIO52/RDY# GPIO53 GPIO70 GPIO71 GPIO72 GPO82/TRIS#
64 95 93 94 119 6 109 120 65 66 16 17 20 21 22 23 24 25 26 27 28 73 74 75 110
KBC_PWRBTN# PLATFORM_ID Pin 120: MODEL_ID_0
PM_SLP_S3# 13,39,43,44 KBC_PWRBTN# 36 AC_IN# 46 LID_CLOSE# 37 35 35 TPDATA TPCLK TPDATA TPCLK
13 12 11 10 71 72
GPIO12/PSDAT3 GPIO25/PSCLK3 GPIO27/PSDAT2 GPIO26/PSCLK2 GPIO35/PSDAT1 GPIO37/PSCLK1
KBSOUT0/JENK# KBSOUT1/TCK KBSOUT2/TMS KBSOUT3/TDI KBSOUT4/JEN0# KBSOUT5/TDO KBSOUT6/RDY# KBSOUT7 KBSOUT8 KBSOUT9 KBSOUT10 KBSOUT11 KBSOUT12/GPIO64 KBSOUT13/GPIO63 KBSOUT14/GPIO62 KBSOUT15/GPIO61/XOR_OUT GPIO60/KBSOUT16 GPIO57/KBSOUT17
KBC
53 52 51 50 49 48 47 43 42 41 40 39 38 37 36 35 34 33 54 55 56 57 58 59 60 61 85
KCOL0 KCOL1 KCOL2 KCOL3 KCOL4 KCOL5 KCOL6 KCOL7 KCOL8 KCOL9 KCOL10 KCOL11 KCOL12 KCOL13 KCOL14 KCOL15 KCOL16 KCOL17 KROW0 KROW1 KROW2 KROW3 KROW4 KROW5 KROW6 KROW7
PS/2
AD_OFF RSMRST#_KBC
PWRLED 38 STDBY_LED 38 CAP_LED 36 AD_OFF 45 RSMRST#_KBC 13 PM_SLP_S4# 13,43,44 CHARGE_LED 38 SPI_WP# 34 TP_LOCK_LED 36 BLON_OUT 18
34 34 34
34
SPIDI SPIDO SPICS# SPICLK
86 87 90 92
F_SDI F_SDO F_CS0# F_SCK
FIU
KBSIN0 KBSIN1 KBSIN2 KBSIN3 KBSIN4 KBSIN5 KBSIN6 KBSIN7
Pin 24: MODEL_ID_1
VCC_POR#
ECRST#
BLON_OUT Pin 28:UMA=NC; DIS=PL
0916 move net(SPI_WP#) from U9 pin120 to pin25
WPCE773LA0DG-GP
RN46
3D3V_AUX_S5
USB_PWR_EN#
23
VCORF
AGND
GND GND GND GND GND GND
103
5 18 45 78 89 116
WPCE773LA0DG-GP
SRN10KJ-6-GP
84.03906.R11 2ND = 84.03906.F11 3RD = 84.03906.P11
SB
FOR KBC DEBUG

DY
1 R202 2 Do Not Stuff KCOL2
3D3V_AUX_S5
3D3V_S0
1106 modify net connection of RN46 and RN44
0912 add the part for EMI demand

3D3V_S5 8 7 6 5 SPIDI RN49 SRN4K7J-12-GP 2 KCOL3 1 2 3 4 AD_OFF SMBC_Therm SMBD_Therm PCLK_KBC Do Not Stuff D14 13 ECSCI#_1 6 5 4 1 2 3 ECSWI#_KBC ECSCI#_KBC 3D3V_AUX_S5 RN47 13 ECSWI# 1 2 4 3 KBC_PWRBTN# BAT_IN# SRN10KJ-6-GP
2
RN48 8 7 6 5 SRN10KJ-6-GP RN44 1 2 3 4 RSMRST#_KBC S5_ENABLE_KBC BLON_OUT
EC63 1
2 Do Not Stuff
DY
1
R203
DY
R191 1 2 1KR2J-1-GP C369 DY 1 2 3D3V_S0
Do Not Stuff BAT_SCL BAT_SDA
KA20GATE KBRCIN# E51_TxD SHBM
8 7 6 5
1 2 3 4
SRN10KJ-6-GP 32,39
RSMRST#
Q23 B
1 2
VCORF
44
RN45
3D3V_S0
5 6 7 8
4 3 2 1
ECRST#
KBC_THERMALTRIP# LID_CLOSE#
C378 SC1U10V3KX-3GP
MMBT3906-3-GP
DY:
ISP Mode disable
1 2 3 4
8 7 6 5
PLATFORM_ID WIRELESS_BTN# MEDIA_LED# TP_LOCK_BN#
MEDIA_LED#
12,36
0930 modify net name for BIOS demand

3D3V_AUX_S5 1 1 R174 DY Do Not Stuff Do Not Stuff R175 10KR2J-3-GP
SRN100KJ-6-GP
CH731UPT-GP 83.R0304.A8H 2nd = 83.R2002.B8E 3rd = 83.R3004.A8E 48 48 48 48 48 48 28 KCOL17 KCOL0 KCOL16 KCOL15 KCOL14 KCOL13 KCOL17 2 KCOL0 KCOL16 KCOL15 KCOL14 KCOL13 PCB_VER0 PCB_VER1
Internal KeyBoard Connector

KB1 PTWO-CON26-1-GP
20.K0326.026
2nd = 20.K0320.026
R176 Do Not Stuff
R173 10KR2J-3-GP 10KR2J-3-GP
SB
DY
2
PlanarID (0,1) SA: 0,0 SB: 0,1 SC: 1,0 SD: 1,1
27
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
KROW0 KROW1 KROW2 KROW3 KROW4 KROW5 KROW6 KROW7
48 48 48 48
KCOL8 KCOL7 KCOL6 KCOL5
1118 modify PCB Ver. from SA to SB
KCOL1 KCOL2 KCOL3 KCOL4 KCOL5 KCOL6 KCOL7 KCOL8 KCOL9 KCOL10 KCOL11 KCOL12 KCOL13 KCOL14 KCOL15 KCOL16 KCOL17
KCOL0
48 48 48 48
0930 modify
1
KB1
48 48 48 48
KROW0 KROW7 KROW6 KROW5
Internal KeyBoard CONN

1 ........ 26
48 48 48 48
UMA Two Phase 2
Wistron Corporation
CHECK KB SPEC. AND PIN DEFINE
48 48 48 48
KBC WPCE773L
Rev
Size Document Number Custom Date:

A
HM40-MV
Sheet 33 of 51
SB
Wednesday, November 26, 2008
3D3V_AUX_S5
4
ERN2 SPICLK_ROM SPIDO_ROM SPIDI_ROM RN41 SRN10KJ-6-GP
SPI_HOLD#
16M Bits SPI FLASH ROM

U40
3D3V_AUX_S5
1 2 3 4
8 7 6 5
SRN0J-7-GP
SPICLK SPIDO SPIDI
33 33 33
5 6 7 8
4 3 2 1
ER6 Do Not Stuff
33
SPICS# 33 SPI_W P#
1 2
Do Not Stuff
SPIDI_ROM SPI_W P#
1 2 3 4
CS# DO WP# GND
VCC HOLD# CLK DIO
8 7 6 5
3D3V_AUX_S5_SPI_ROM SPI_HOLD# SPICLK_ROM SPIDO_ROM DY EC57
EC59 SC4D7P50V2CN-1GP
DY EC55
GOLDEN FINGER FOR DEBUG BOARD
W 25X16AVSSIG-GP
72.25X16.A01 2nd = 72.25165.A01
DY EC58 Do Not Stuff
Do Not Stuff
3D3V_S0
1013 modify U40 from 72.25X16.001 to 0912 add the part for EMI demand
72.25X16.A01
SB
GF1
SPI_HOLD#EC56 1
2 Do Not Stuff
DY
1 2 3 4 5 6 7 8 9 10 11 12
LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3 LPC_LFRAME# PLT_RST1# PCLK_FW H
LPC_LAD[0..3]
LPC_LAD[0..3]
12,33
LPC_LFRAME# 12,33 PLT_RST1# 7,13,24,30,31,33 PCLK_FW H 3 PCLK_FW H EC26 Do Not Stuff
Do Not Stuff
DY
Do Not Stuff
DY
UMA Two Phase 2
Wistron Corporation
A B C D
BIOS/GOLDEN FINGER
Document Number Rev
HM40-MV
E
SB
34 of 51
TOUCH PAD
1 1
EC28 Do Not Stuff Do Not Stuff Do Not Stuff
5V_S0
1
EC27
0930 modify 1013 modify 1015 modify

TPAD1
TPAD1 TPAD1 TPAD1
1124 modify
TPAD1
T/P
1
TP_CLK TP_DATA
DY
DY
7 2 3 4 5 6
8
5V_S0 PTW O-CON6-12-GP
37,48 37,48
TP_LEFT TP_RIGHT
20.K0382.006 2nd = 20.K0320.006
1 2
RN7
SRN10KJ-5-GP
4 3
RN8
33 33
TPDATA TPCLK
1 2
SRN33J-5-GP-U
4 3
TP_DATA TP_CLK
TP_DATA 48 TP_CLK 48
DY
DY
0910 delete RIGHT1 and LEFT1
UMA Two Phase 2

A A
Wistron Corporation
5 4 3 2
Document Number
Touch pad
HM40-MV
Sheet
1
Rev
SB
35 of 51
Q18 R1 R1 31 W LAN_LED#_MC R133 R2
SB
1119 modify R130 and R133

5V_S0 R130
2 3
W LAN_LED#_1
1
15R2J-GP
W LAN_LED#
2 10R2F-L-GP
W LAN_LED#_R
C4 1
Do Not Stuff 2 Do Not Stuff 2 Do Not Stuff 2
1013 modify these power
DY
EC4 1
DTA143ZUB-GP
D
Q19 2N7002-11-GP
84.00143.F1K
D
33 W LAN_TEST_LED
G S
PowerCN1
17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18
DY
EC5 1
D
1016 modify Q18
DY
SB 1120 modify PowerCN1 pin3 and remove EC44

W LAN_LED#_R 48 W IRELESS_BTN#_1 48 TP_LOCK_LED#_R 48 TP_LOCK_BN#_1 48 PW RLED#_R 48 KBC_PW RBTN#_1 48 3D3V_S0 CAP_LED#_R 48 NUM_LED#_R 48 MEDIA_LED#_R 48
TP_LOCK_LED#_R PW RLED#_R KBC_PW RBTN#_1 CAP_LED#_R MEDIA_LED#_R
Q17 33 TP_LOCK_LED
R132
R1
3 2
TP_LOCK_LED#
2 100R2J-2-GP
TP_LOCK_LED#_R
33
C
NUM_LED
33
CAP_LED
R2 DTC143ZUB-GP
84.00143.G1K 2nd = 84.00143.D1K 3rd = 84.00143.E1K

Q16 R1
1016 modify Q15,Q16 and Q17
SB
NUM_LED#
R129 1 2 604R2F-2-GP
KYO-CON16-GP
NUM_LED#_R
2 R2 DTC143ZUB-GP
20.K0384.016 2nd = 20.K0395.016
1112 remove the signal( STDBY_LED#_R)
84.00143.G1K 2nd = 84.00143.D1K 3rd = 84.00143.E1K

Q15 R1
R128
CAP_LED#
1 2 604R2F-2-GP
CAP_LED#_R
2 R2 DTC143ZUB-GP
16
84.00143.G1K 2nd = 84.00143.D1K 3rd = 84.00143.E1K

12,33 MEDIA_LED# R3 1 2 604R2F-2-GP MEDIA_LED#_R
38 PW RLED#_FR
R127 1 2 604R2F-2-GP
PW RLED#_R
SB 1112 remove these signals( STDBY_LED#_FR and STDBY_LED#_R) and R131

RN1 KBC_PW RBTN#_1 W IRELESS_BTN#_1 TP_LOCK_BN#_1 33 CRT_DEC#
1 2 3 4
8 7 6 5 CRT_IN#_R
SRN470J-3-GP
KBC_PW RBTN# 33 W IRELESS_BTN# 33 TP_LOCK_BN# 33 CRT_IN#_R 19
KBC_PW RBTN#_1 G1 Do Not Stuff W LAN_LED#_R TP_LOCK_LED#_R NUM_LED#_R CAP_LED#_R
EC46 Do Not Stuff
EC45 Do Not Stuff
1
EC47 Do Not Stuff
UMA Two Phase 2
DY
DY
DY
DY
Wistron Corporation
Power Board
HM40-MV
Sheet
1
Rev
SB
36 of 51
TP_LEFT
1017 modify RN60
TP_L1 RN60 TP_LEFT#_1
1
D
3 1 5
1 2
4 3
TP_LEFT 35,48 TP_RIGHT 35,48
Cover Up Switch
3D3V_AUX_S5
4 2
SW -TACT-119-GP
EC84 Do Not Stuff
SRN470J-4-GP-U
1
U4
DY
62.40009.671 2nd = 62.40012.101

3 OUT 2
DY
2
R40 Do Not Stuff LID_CLOSE# LID_CLOSE# 33
TP_RIGHT
TP_R1
GND VDD 1
EC22 Do Not Stuff
DY
1
ME268-002-GP
5 4
EC21 SCD1U16V2ZY-2GP
EC83 Do Not Stuff
DY
SW -TACT-119-GP
62.40009.671
C
1016 modify U4 1017 modify U4
2nd = 62.40012.101
3
TP_RIGHT#_1
74.00268.07B
1017 add U61,R52,EC24 and EC23 1020 delete U61,R52,EC24 and EC23
UMA Two Phase 2
Wistron Corporation
5 4 3 2
Document Number Monday, December 01, 2008
SWITCHS
HM40-MV
Sheet
1
Rev
SB
37 of 51
1015 modify the power from 3D3V_S5 to 5V_S5 SB
D
1106 modify LED11

D
PW RLED#_FR 36
Blue
PW RLED#_FR_R STDBY_LED#_FR_R
5V_S5
Q27 33 PW RLED
R1
3 2
PW RLED#_FR STDBY_LED#_FR
R291 1 2 604R2F-2-GP
3 4
LED11 LED-BO-4-GP
1 2
R2 DTC143ZUB-GP
1 R292 2 100R2J-2-GP
84.00143.G1K 2nd = 84.00143.D1K 3rd = 84.00143.E1K

Q28 33 STDBY_LED
SB
Orange
33
DC_BATFULL
2 R2 DTC143ZUB-GP
R1
83.00195.G70 2nd = 83.19223.A70
1112 remove the signal( STDBY_LED#_FR) 1017 modify R291 and R293
1014 modify these LEDs(LED11,LED12)
84.00143.G1K 2nd = 84.00143.D1K 3rd = 84.00143.E1K
1015 modify the power from 3D3V_S5 to 5V_S5 Blue
5V_AUX_S5
Q29 R1
R293
SB 1106 modify LED12
3 2
1 2 604R2F-2-GP
DC_BATFULL#_FR
3 4
1 2
1106 modify LED power from 5V_S5 to 5V_AUX_S5
R2 DTC143ZUB-GP
84.00143.G1K 2nd = 84.00143.D1K 3rd = 84.00143.E1K

Q30
LED12
LED-BO-4-GP
Orange
33
CHARGE_LED
R1
R294 1 2 100R2J-2-GP
CHARGE_LED_FR
83.00195.G70 2nd = 83.19223.A70
2 R2 DTC143ZUB-GP
84.00143.G1K 2nd = 84.00143.D1K 3rd = 84.00143.E1K
1016 modify Q27~Q30
UMA Two Phase 2
Wistron Corporation
5 4 3 2
Document Number W ednesday, November 26, 2008
LED
HM40-MV
Sheet
1
Rev
SB
38 of 51
Aux Power
U43
3D3V_AUX_S5
Run Power
I min = 300 mA
5V_AUX_S5 3D3V_AUX_S5 5V_S0 U20 S S S G AO4468-GP D D D D 5V_S5
1 2 3
VIN GND EN
Do Not Stuff
VOUT NC#4
5 4
DCBATOUT C379 R119 1 3D3V_S0 Z_12V Q13 NDS0610-NL-GP Do Not Stuff Do Not Stuff RUN_POW ER_ON C269 1
DY
2
1 2 3 4
8 7 6 5
DY
C375 3D3V_AUX_S5_EN
10KR2J-3-GP
1 R115 10KR2J-3-GP 2 C278 SCD22U25V3KX-GP
5V_AUX_S5 R190 Do Not Stuff 2 1
R120 330KR2J-L1-GP
Do Not Stuff 2nd = 74.09198.Q7F DY
DY
84.04468.037
S D
D9 PDZ9D1B-GP
SB
R109 Do Not Stuff
3D3V_S0
3D3V_S5
DY
DY
3D3V_runpwr 2
330KR2J-L1-GP R117 100KR2J-1-GP
C372
Do Not Stuff
AO4468-GP
83.9R103.C3F 2nd = 83.9R103.F3F
Z_12V_D4
1016 modify D9
1113 modify 2nd of U43
R118 1
Z_12V_G3
1 2 3 4
U21 S S S G
D D D D
8 7 6 5
84.04468.037
Q12
DY
Q11 Do Not Stuff
Z_12V_D3
4 5 6
3 2 1
Z_12V_D3
2N7002DW -1-GP
84.27002.D3F
PM_SLP_S3# 13,33,43,44
3D3V_S5 Do Not Stuff U17 32 G7922_PW ROK 13,33,43,44 PM_SLP_S3# G7922_PW ROK C257 1
1 2 3
B VCC A Y GND
5 4
DY
PW ROK 7,13
74LVC1G08GW -1-GP
73.01G08.L04 2nd = 73.7SZ08.AAH 3rd = 73.01G08.L03

1D05V_S0
1D05V_S0
1
R112 Do Not Stuff
DY
2
R113 56R2J-4-GP
PM_THRMTRIP-A# 4,7,12 R114 1KR2J-1-GP 4,12,48 H_PW RGD
C266 1
DY
C
Q9
DY
E E
H_PW RGD#
2 Do Not Stuff
KBC_THERMALTRIP# 33
B C 1
Q10 MMBT2222A-3-GP
Do Not Stuff
D8 33,42,48 S5_ENABLE
1 3 83.00016.B11 2 BAS16-1-GP 2nd = 83.00016.F11

RSMRST# 32,33 UMA Two Phase 2
C268 SC2D2U16V3KX-GP
84.02222.V11 2nd = 84.02222.R11
Wistron Corporation
RUN POWER and 3D3V_AUX_S5

Document Number Rev
HM40-MV
Monday, December 01, 2008 Sheet 39 of 51
SB
http://konweer.kiev.ua CPU_CORE
ISL6266A
VID0
D
TPS51125 5V/3D3V
Input Power VGATE_PWRGD DCBATOUT_51125 VIN Input Signal EN0 Output Signal PGOOD Output Power 5V(O) 5V_S5 (6A) 1D8V_S3 VIN
RT9018A
1D5V_S0
1D5V(O) 1D5V_S0 (2.5A)
D
VID Setting VID0(I / 3.3V) VID1(I / 3.3V) VID2(I / 3.3V) VID3(I / 3.3V) VID4(I / 3.3V) VID5(I / 3.3V) VID6(I / 3.3V) Input Signal
Output Signal PGOOD
VID1 VID2 VID3 VID4 VID5 VID6
S5_ENABLE Output Power VCC_CORE_PWR(O) VCC_CORE(Imax=38A) ALW_PWRGD_3V_5V
3D3V(O) 5V(O) 3D3V(O)
3D3V_S5 (6A) 5V_AUX_S5
PM_SLP_S3#
EN
PGOOD
CPUCORE_ON
RT9026
3D3V_AUX_S5 5V_S5 1D8V_S3 PM_SLP_S4# VIN VLDOIN S3 S5
0D9V_S0
VTT 0D9V_S3 (1A)
CPUCORE_ON
C
VCC_SENSE VSS_SENSE
VTTREF 0D9V_S3_1 EN (I / 3.3V) Voltage Sense VSEN(I / Vcore) RGND(I / Vcore) Input Power VCC(I) VCC(I) VCC(I) CHG_ON# 24750_CELLS
DCBATOUT_6266A 5V_S0 3D3V_S0

B
Charger BQ24745
Input Signal CHGEN# CELLS Output Signal ACGOOD# SRSET AC_IN#
B
AD_IA
TPS51124 1D8V/1D05V
5V_S5 DCBATOUT_51124 Input Power VDD VCC Input Signal EN1 EN2 Output Signal PGOOD1 PGOOD2 AD_JK 5V_AUX_S5
4
Output Power 1D8V (O) 1D8V_S3 (10A) AD+
Input Power ACN
Output Power VOUT (O) VOUT (O) BT+ DCBATOUT
PM_SLP_S4# PM_SLP_S3#
A
1D05V(O)
1D05V_S0 (15A)
Adapter
Input Signal AD_OFF (I) Output Signal (O) AD_IN#
UMA Two Phase 2
Wistron Corporation
CPUCORE_ON Input Power VCC(I) VCC(I)
3 2
Output Power VCC(O) AD+

Title
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Power Sequence Logic

Size B Document Number Rev
HM40-MV
Sheet
1
SB
40 of 51
Date: Monday, November 24, 2008

5
DCBATOUT DCBATOUT_6266A DCBATOUT G53
DCBATOUT_6266A
4,7,12 H_DPRSTP#
PM_DPRSLPVR 7,13
DCBATOUT_6266A
G48
3D3V_S0
C12 Do Not Stuff
C311 Do Not Stuff
C313 SC10U25V6KX-1GP
2 1
2
TC17 Do Not Stuff
2 1
499R2F-2-GP
CPUCORE_ON
43,44 H_VID[6..0] 5
2008/05/06
DY
2 2
U38 BSC120N03MS-G-GP
0R2J-2-GP
H_VID6
H_VID5
H_VID4
H_VID3
H_VID2
H_VID1
Do Not Stuff 1
1 R144 0R2J-2-GP 1 R143 0R2J-2-GP 1 R139 0R2J-2-GP 1 R138 0R2J-2-GP 1 R146 0R2J-2-GP 1 R142 0R2J-2-GP 1 R137 0R2J-2-GP 1 R136 0R2J-2-GP
Do Not Stuff G54 1 2
H_VID0
DY
R141 10R3F-GP
DY
DY
C317 Do Not Stuff
5 6 7 8
D D D D
6266A_DPRSTP# 2 R140
6266A_DPRSLPVR 2 R145
Do Not Stuff G51 1 2 Do Not Stuff
4 3 2 1
TC18 SE100U25VM-L1-GP
Vcc_core Iomax=38A
VCC_CORE
S S S G
6266A_UGATE1
C314
6266A_VR_ON 2
SCD1U10V2KX-4GP 3D3V_S0
R147 R147 2
79.10712.L02 Do Not Stuff 2nd = 79.10112.3JL
DY
2
20080930
6266A_PHASE1
Cyntec 10*10*4 DCR=1.05+-5%mohm, Irating=30A Isat=60A

L8
1 5 6 7 8 5 6 7 8
2
L-D36UH-1-GP
6266A_3V3
6266A_D6
6266A_D5
6266A_D4
6266A_D3
6266A_D2
6266A_D1
20081117
1
U5 R148 1K91R2F-1-GP
6266A_D0
TC4 Do Not Stuff Do Not Stuff
TC20 SE330U2VDM-L-GP
1 2
D D D D
D D D D D
BSC057N03MSG-GP
R154 68R2-GP
4 CPU_PROCHOT#_R
POWER SA C25 1 R17 1
1 R13 2 SC100P50V2JN-3GP 2 6266A_COMP_R 97K6R2F-GP

C24 1
2 10K5R2F-GP
6266A_FB
11
FB FB2 DROOP VDIFF ISEN2 ISEN1 VSUM VSEN GND VDD RTN DFB
BOOT2 NC#25
26 25
6266A_FB2 12
R156 6266A_BOOT2 1 26266A_BOOT2_R 2D2R2J-GP
one phase
5 6 7 8
VIN
VO
6266A_VDIFF 13
6266A_VSEN14
6266A_RTN 15
16266A_DROOP 16
6266A_DFB 17
1 18 6266A_VO 6266A_VSUM 19
6266A_VIN 20
6266A_ISEN2 23
6266A_VDD
R19 1
C32 2 6266A_FB2_R 1 2 100R2F-L1-GP-U SC2200P50V2KX-2GP 6266A_VDIFF R15 1 6266A_SOFT
C34 S S S S G 6266A_ISEN1 C33
26266A_VO
one phase
2 SC270P50V2KX-1GP
21
22
24
R14 1KR2F-3-GP one phase
U34 BSC120N03MS-G-GP
DY
DY
SCD22U10V2KX-1GP
R23 1KR2F-3-GP 1KR2F-3-GP
DCBATOUT_6266A R24
2
SCD22U10V2KX-1GP
6266A_UGATE2 6266A_PHASE2
2 1KR2F-3-GP
2 R16 Do Not Stuff
R18 2K87R2F-1-GP 2K87R2F-1-GP POWER SB
Cyntec 10*10*4 DCR=1.05+-5%mohm, Irating=30A Isat=60A

L9
4 3 2 1
SB 20081121
1
one phase
R20
DY
C35 SC330P50V2KX-3GP
5 6 7 8
5 6 7 8
10R3F-GP
one phase
one phase
C37
1 2 Do Not Stuff 2 phase

5V_S0 R25 1
5V_S0 U6 BSC057N03MSG-GP
BSC057N03MSG-GP
C29
20080930
R21 5 VCC_SENSE 0R2J-2-GP 1 2 C28 SC330P50V2KX-3GP 0R2J-2-GP 1 2
4 3 2 1
4 3 2 1
C41
2 10R2F-L-GP C31 SC1U25V3KX-1-GP
G60 Do Not Stuff
SA
G59 Do Not Stuff
VSS_SENSE
R22
Do Not Stuff Do Not Stuff 2nd = 77.C3371.0512nd = 77.C3371.051
6266A_LGATE2 R31 1
2 Do Not Stuff
6266A_VSUM 6266A_ISEN2 6266A_VO
SB
6266A_VSUM
A
20081121
1
R30 2K61R2F-1-GP 6266A_ISEN1
R27 1 R26 1 R29 1 R28 1
one phase
2 3K65R2F-1-GP 2 10KR2F-2-GP 2
6266A_ISEN2_P2_VCORE
one phase one phase 1R2F-GP one phase
6266A_ISEN1_P2_VCORE UMA Two Phase 2

A
C43 SCD033U25V3KX-GP
R32 11KR2F-L-GP
2 10KR2F-2-GP
6266A_VSUM_R_VO R162 NTC-10K-26-GP
Single Phase R47=1.2K, R63=5.6K,R460=0R C33=47p, C49=0.033u, C52=0.1u DY=U7,U28,U29,L9,R62,R56,R42, R45,R37,R39,R48,C20

3
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date: Document Number
ISL6266A_CPU_CORE HM40-MV
Sheet
1
6266A_VO
5
1013 modify R162

4 2
6266A_COMP 10
COMP
UGATE2
27
6266A_UGATE2
6266A_NTC 1 R161 26266A_NTC_R R155 1 2 6 NTC-470K-8-GP 4K02R2F-GP C328 C325 6266A_SOFT 1 2 7 SCD015U50V3KX-GP 1 2 SCD01U25V2KX-3GP 6266A_VO 1 26266A_OCSET 8 R157 12KR3F-GP 1013 modify R161 C22 1 6266A_VW 9 2 SC1000P50V3JN-GP
VID6 VID5 VID4 VID3 VID2 VID1 DPRSTP# CLK_EN# DPRSLPVR VR_ON VID0 GND 3V3
1D05V_S0 S S S G S S S S G
Id=19.5A Qg=21.5~33nC, Rdson=5.5~6.7mohm

POWER SB
U7 BSC057N03MSG-GP
U37
68.R3610.20A 2nd = 68.R3610.20C

2
G57 Do Not Stuff
CAP
2
CAP
49
48
47
46
45
44
43
42
41
40
39
38
37
20080930
G58 Do Not Stuff
4 3 2 1
13,32 VGATE_PW RGD 4 C320 1 PSI#
1 0R2J-2-GP R149 1 26266A_PSI# 2
PGOOD PSI#
BOOT1
36 35 34 33 32 31 30 29 28
UGATE1
R151 6266A_BOOT1 1 2 6266A_BOOT1_R 2D2R2J-GP 1 6266A_UGATE1 6266A_PHASE1 2
4 3 2 1
6266A_PMON_R 1 2 6266A_PMON PMON 3 R150 4K99R2F-L-GP SCD1U25V3KX-GP 1 26266A_RBIAS4 RBIAS R152 147KR2F-GP 5 VR_TT#
PHASE1 PGND1
6266A_ LGATE1 C321 SCD22U25V3KX-GP 6266A_VSUM
Do Not Stuff Do Not Stuff 2nd = 77.C3371.051 2nd = 77.C3371.051
ISL6266AHRZ-GP
LGATE1
6266A_ LGATE1 5V_S0
C327
1 R33 1 R36 1 R35 1 R34
2 3K65R2F-1-GP 2 10KR2F-2-GP 2 1R2F-GP
NTC
74.06266.073
PVCC
6266A_ISEN1 6266A_VO
SOFT
LGATE2 PGND2
6266A_LGATE2
SC2D2U16V3KX-GP
one phase
OCSET VW
PHASE2
6266A_PHASE2
6266A_ISEN2 C329 SCD22U25V3KX-GP
2 10KR2F-2-GP
DCBATOUT_6266A
one phase
one phase -1 -1
C310 Do Not Stuff C312 SC10U25V6KX-1GP C11 Do Not Stuff Do Not Stuff C316 Do Not Stuff
2008/05/06
D D D D D D D D
DY
VCC_CORE
2
L-D36UH-1-GP TC1 Do Not Stuff
D D D D D
U36
SC180P50V2JN-1GP
68.R3610.20ACAP 2nd = 68.R3610.20C
CAP
SCD01U25V2KX-3GP
S S S S G
S S S S G
SCD33U10V3KX-3GP
Rev
SB
41 of 51
DCBATOUT DCBATOUT_51125 G73 1 2 3D3V_PW R G30 3D3V_S5
POWER SA 5V_PW R G37 5V_S5
5V_AUX_S5
Do Not Stuff G45 1 2 Do Not Stuff G46 1 2 Do Not Stuff G74 1 2
Do Not Stuff G40 1 2 Do Not Stuff G11 1 2 Do Not Stuff G41 1 2 Do Not Stuff G10 1 2 Do Not Stuff G12 1 2 Do Not Stuff G38 1 2 Do Not Stuff 51125_ENTIP2 33,39,48 S5_ENABLE
1
Q25
3 4
RN59 SRN100KJ-6-GP
Q26
3 2 1
4 2 1 5 6
2N7002DW -1-GP
4 5 6
3 2 1
51125_ENTIP1 S5_ENABLE 33,39,48
Do Not Stuff G35 1 2 Do Not Stuff G83 1 2 Do Not Stuff G36 1 2 Do Not Stuff G34 1 2 Do Not Stuff G31 1 2 Do Not Stuff G32 1 2 Do Not Stuff
D
51125_ENTIP2 2N7002DW -1-GP
51125_ENTIP1
79.68612.30L 2nd = 79.68612.L01
SB
1121 modify R275
TC13 Do Not Stuff
DY
VIN
Cyntec 7*7*3 DCR=30mohm, Irating=6A Isat=13.5A Iomax=5A

3D3V_PW R
Do Not Stuff
20081117
1020 delete C537 for Power demand
DCBATOUT_51125
DCBATOUT_51125
DCBATOUT_51125 C298 Do Not Stuff C508 SC10U25V6KX-1GP
C295 Do Not Stuff
C299 Do Not Stuff
DY
2
R268 110KR3F-GP
R275 120KR3F-GP
C294 Do Not Stuff
C521 Do Not Stuff
TC30 SE68U25VM-3-GP
C519 Do Not Stuff
DY
DY
U47
16
84.04800.D37 2nd = 84.08884.037

C528 2 1
84.04800.D37 2nd = 84.08884.037

C529 SCD1U25V3KX-GP
D D D D
DY
U22 SI4800BDY-T1
Id=7A Qg=8.7~13nC Rdson=23~30mohm
8 7 6 5
U28
5 6 7 8
DY
DY
G S S S
1 2 3 4
68.3R310.20AS 2nd = 68.3R31A.10E

L15
51125_VBST2 51125_DRVH2 51125_LL2
9 10 11 12 7 5
VBST2 DRVH2 LL2 DRVL2 VO2 VFB2 EN0 ENTRIP2 VREF TONSEL SKIPSEL VREG3 VREG5
VBST1 DRVH1 LL1 DRVL1 VO1 VFB1 PGOOD ENTRIP1 GND GND VCLK
22 21 20 19 24 2 23 1 15 25 18
51125_VBST1 51125_DRVH1
4 3 2 1
D D D D D G S S S S
SI4800BDY-T1
SCD1U25V3KX-GP
Cyntec 7*7*3 DCR=30mohm, Irating=6A Isat=13.5A

L6
Iomax=5A
5V_PW R
1 2 IND-3D3UH-57GP
C287 Do Not Stuff
51125_LL1 51125_DRVL1 U29
DY
ST220U6D3VDM-15GP
D
TC8 Do Not Stuff SI4812BDY-T1-E3-GP
8 7 6 5
51125_DRVL2 U23 51125_VO2
IND-3D3UH-57GP
1 2
51125_VO1 SI4812BDY-T1-E3-GP SI4812BDY-T1-E3-GP 51125_FB1 51125_PGOOD 51125_ENTIP1
68.3R310.20A 2nd = 68.3R31A.10E
5 6 7 8
D D D D
4 3 2 1
G42
1 R280
51125_VREF
2 51125_EN 13 820KR2F-GP 51125_ENTIP2 6 3
1 2 3 4
G S S S
D D D D D
TC11 G39 Do Not Stuff Do Not Stuff C283 Do Not Stuff SE220U6D3VM-7GP
84.04812.A37 2nd = 84.08878.037

G S S S S
51125_FB2
84.04812.A37 2nd = 84.08878.037
DY
77.C2271.00L 2nd = 77.22271.27L
C517
51125_TONSEL
4 14
1 2
TPS51125RGER-GP
1 2
R265 6K65R2F-GP
Id=7.7A Qg=8.5~13nC R262 Do Not Stuff Rdson=16.5~21mohm DY

51125_FB2_R C516 DYDo Not Stuff
51125_SKIPSEL
51125_VCLK Do Not Stuff
Id=7.7A Qg=8.5~13nC Rdson=16.5~21mohm
79.22710.6AL 2nd = 77.92271.021

R273 DY Do Not Stuff
SCD22U6D3V2KX-1GP
1013 modify TC11 and add TC12

R270 30KR2F-GP
51125_FB1_R
74.51125.073
3D3V_AUX_S5 G79
17
3D3V_AUX_S5_5_51125
G80
5V_AUX_S5
3D3V_S5
C518 Do Not Stuff
DY
1
SB 1118 delete TC12
R269 10KR2F-2-GP
51125_VREF 3D3V_AUX_S5
R264 Do Not Stuff 2 1 R261
15V_AUX_S5_51125
1
Do Not Stuff
Do Not Stuff
R276 Do Not Stuff
2 2
DY Not1Stuff Do
R283 C524 SC10U10V5KX-2GP
C534 SC10U10V5KX-2GP UMA Two Phase 2

A
51125_VREF
A
Close to VFB Pin (pin5)

3D3V_AUX_S5
R281
DY Not1Stuff Do
1 0R2J-2-GP
R282
DY
R266 20KR2F-L-GP
Close to VFB Pin (pin2)
Wistron Corporation
DY
1 Do Not Stuff
DCDC 5V/3D3V (TPS51125)

HM40-MV
Sheet
1
Rev
SB
42 of 51
1D8V_S3
1D5V_S0 Iomax=2.5A
D
DY
1
C151 Do Not Stuff C150 SC10U10V5KX-2GP
G6
2
Do Not Stuff G8 2 Do Not Stuff G7 2 Do Not Stuff G5 2 Do Not Stuff 1D5V_S0
13,33,39,44 PM_SLP_S3#
PM_SLP_S3#
R76 2
1 15912_EN_U111 Do Not Stuff

3D3V_S0 1D5V_LDO 1D5V_LDO U13
20081001
Vo(cal.)=1.5024V
1
C158
G966-25ADJF1UF-GP-U SC1U16V3KX-2GP
1 1
R78 2K2R2J-2-GP 5V_S5
6 3 4 2 1
VO VIN VPP
GND GND
9 8
DY
C148 Do Not Stuff
41,44 CPUCORE_ON
R77 2
1 Do Not Stuff
5912_POK_U111
VEN POK
NC#5 ADJ
5 7
5912_FB_U111
R74 18KR2J-GP
R75 20K5R2F-GP
74.0G966.03D 2nd = 74.09018.A3D
Vo=0.8*(1+(R1/R2))
20081001
5V_S5 1D8V_S3
Iomax=1A OCP>2A
2
DDR_VREF_PW R G78 DDR_VREF_S3 C523 SCD1U10V2KX-4GP
C520 SC1U10V3KX-3GP
1016 modify U45

U45
13,33,44 PM_SLP_S4# DDR_VREF_S3_1
R267 2 1 R263 Do Not Stuff 2 1 Do Not Stuff C513 SC1U10V2KX-1GP
9026_S5 9026_S3
10 9 8 7 6
VIN S5# GND S3# VTTREF
VDDQSNS VLDOIN VTT PGND VTTSNS
1 2 3 4 5 1
Do Not Stuff G76 1 2 Do Not Stuff
1 2
G2997BP71U-GP
74.02997.A79 2nd = 74.09026.079
UMA Two Phase 2

A A
Wistron Corporation
5 4 3 2
Document Number
1D5V & 0D9V

HM40-MV
Sheet
1
Rev
SB
43 of 51
DCBATOUT G71 DCBATOUT_51124
1D8V_S3 1D8V_PW R G28 1D8V_S3
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L

1
TC29 SE68U25VM-3-GP DCBATOUT_51124
79.3971V.6AL 2nd = 79.3971V.E0L
Vtrip(mV)=Rtrip(Kohm)*10(uA) Iocp=(Vtrip/Rdson)+((1/(2*L*f))*((Vin-Vout)*Vout)/Vin))
SB 1128 add TC26
TC26 SE390U2D5VM-2GP
Do Not Stuff G25 1 2 Do Not Stuff G21 1 2 Do Not Stuff G22 1 2 Do Not Stuff G19 1 2 Do Not Stuff G20 1 2 Do Not Stuff G18 1 2 Do Not Stuff G26 1 2 Do Not Stuff G29 1 2 Do Not Stuff G27 1 2 Do Not Stuff G24 1 2 Do Not Stuff G23 1 2 Do Not Stuff
D
DY
TC28 Do Not Stuff
Do Not Stuff G68 1 2 Do Not Stuff G67 1 2 Do Not Stuff G70 1 2 Do Not Stuff G72 1 2 Do Not Stuff
C297 Do Not Stuff
79.68612.30L 2nd = 79.68612.L01
U24 SI4800BDY-T1
DY
20081117
2008/06/16
84.04800.D37 2nd = 84.08884.037
D D D D

41,43
4 3 2 1
Cyntec 10*10*4 DCR=4.2mohm, Irating=16A Isat=33A

L17
G S S S
CPUCORE_ON
68.1R510.10J 2nd = 68.1R51A.10A

1 1 1
C535 Do Not Stuff
1D8V_PW R
13,33,43 PM_SLP_S4#
0R2J-2-GP
1 DY 2
BC2 Do Not Stuff
PGOOD1 PGOOD2
5V_S5
5 6 7 8
C531 Do Not Stuff
C282 Do Not Stuff
DY
1 2 IND-1D5UH-34-GP
TC10 SE330U2D5VDM-LGP SE330U2D5VDM-LGP
D D D D
51124RGER_PG1 51124RGER_PG2
51124_VFB1
R274 3D3R3J-L-GP
C300
4 3 2 1
C525 SC4D7U10V5KX-1GP
1D05V_PW R 1D8V_PW R 51124_VFB2 51124_VFB1
R284 Do Not Stuff
84.04812.A37 2nd = 84.08878.037
R290 21K5R3F-GP
G S S S
U25 SI4812BDY-T1-E3-GP
R285 30KR2F-GP
DY
DY
C515 Do Not Stuff
5 6 7 8
DY
R278
VFB1 VFB2
VO1 VO2
SC1U10V3KX-3GPU46
51124_V5FILT 51124_EN1 51124_EN2
15 16 23 8 3 25 13 18
V5FILT V5IN EN1 EN2 GND GND PGND2 PGND1
DRVH1 LL1 DRVL1
21 20 19
51124_DRVH1 51124_LL1 51124_DRVL1
Id=7.7A Qg=8.5~13nC Rdson=16.5~21mohm
1D8V Iomax=10A OCP>15A
77.23371.L01 2nd = 77.C3371.10L
24 7
2 5
1 6
1013 modify TC10 and add TC26
20081117
20080930
R277 13,33,39,43 PM_SLP_S3#
DCBATOUT_51124 1D05V_PW R 1D05V_S0 G65 C510 C514 SC10U25V6KX-1GP
TONSEL
VBST1 VBST2
TRIP1 TRIP2
5 6 7 8
1
0R2J-2-GP
DRVH2 LL2 DRVL2
10 11 12
51124_DRVH2 51124_LL2 51124_DRVL2 U26 AOL1426-GP
22 9
1 DY 2
17 14
TPS51124RGER-GPU1
DY
BC1 Do Not Stuff
51124_TRIP1 51124_TRIP2
74.51124.073
51124_TONSEL
R271 19K6R3F-GP
R272 10KR2F-2-GP
84.01426.037 2nd = 84.07686.037
4 3 2 1
Cyntec 10*10*4 DCR=4.2mohm, Irating=16A Isat=33A

L16
Do Not Stuff
DY
Do Not Stuff G62 1 2 Do Not Stuff G63 1 2 Do Not Stuff G64 1 2 Do Not Stuff G17 1 2 Do Not Stuff G16 1 2 Do Not Stuff G13 1 2 Do Not Stuff G14 1 2 Do Not Stuff G15 1 2 Do Not Stuff G66 1 2 Do Not Stuff
SB
1121 modify L16,R286 1D05V_PW R

1
C536 Do Not Stuff C284 Do Not Stuff
D D D D D S S S S G
SB
1121 modify R271,R272
20081121
2 2
51124_LL1
1 2
1 2 IND-D88UH-GP
TC9 ST330U2D5VDM-9GP ST330U2D5VDM-9GP
SCD1U16V2KX-3GP 51124_LL2 C526 1 51124_VBST2
DY R288
1
Do Not Stuff
DY
1
R287 Do Not Stuff
U27 AOL1712-GP
51124_VFB2 R289 30KR2F-GP
4 3 2 1
SCD1U16V2KX-3GP 51124_V5FILT
Id=7.7A Qg=8.5~13nC Rdson=16.5~21mohm SB
84.01712.037
C527 1
51124_VBST1
R286 11K8R2F-GP
DY
5 6 7 8
DY
D D D D D S S S S G
77.23371.13L 2nd = 77.C3371.10L
1127 modify U27
1D05V Iomax=14A OCP>24A

1D05V_S0
GND TONSEL
A
OPEN 300k/CH1 360k/CH2
V5FILT 360k/CH1 420k/CH2 SB 1128 add TC25

DY
240k/CH1 300k/CH2
20081117
UMA Two Phase 2 Do Not Stuff
TC25
Vout=0.758V*(R1+R2)/R2 --> PWM mode Vout=0.764V*(R1+R2)/R2 --> Skip Mode
Wistron Corporation
1017 add TC25

Do Not Stuff 2nd = 79.3971V.E0L
TPS51124_1D8V_1D05V
HM40-MV
Sheet
1
Rev
SB
44 of 51
Friday, November 28, 2008
DC1
GND
6 5 4 1 2 3 NP1 DC-JACK131-GP
SB 1121 add the part(EC88) for EMI demand

AD_JK
Adaptor in to generate DCBATOUT

1 2 3 4 U2 S S S G D D D D 8 7 6 5
AD+
EC11 SCD1U50V3KX-GP
DY
DY
22.10037.F11
C5 D1 SCD1U50V3ZY-GP P6SMBJ20A-GP 83.P6SMB.AAG 2nd = 83.P6SBM.AAG
AD+_2 2
AO4407A-GP C10 SC1U50V5ZY-1-GP
R7 200KR2F-L-GP 1 R2
84.04407.F37 2nd = 84.04433.A37
1022 modify DC1
AD_OFF#_JK
2 3 1
Q3 R1 R1 1
1013 modify U2
R6 100KR2J-1-GP
DTA124EUB-GP Q4 R1 3 33 AD_OFF 1
SB 1125 add the part(EC91) for EMI demand
84.00124.T1K 2nd = 84.00124.N1K 3rd = 84.00124.K1K
2 R2 DTC124EUB-GP
1016 modify Q3
1016 modify Q4
84.00124.S1K 2nd = 84.00124.M1K 3rd = 84.00124.H1K
BATA_SDA_1 48 BATA_SCL_1 48 BAT_IN#_1 48
BATTERY CONNECTOR
SB 1127 modify BAT1
BAT1
2 2
RN4 33,46 BAT_SDA 33,46 BAT_SCL 33 BAT_IN# BT+ 1 2 3 4 8 7 6 5 BATA_SDA_1 BATA_SCL_1 BAT_IN#_1
SRN33J-7-GP 1 1
9 8 7 6 5 4 3 2 1
GND GND GND GND DAT CLK BAT_IN BT+2 BT+1
DY
Do Not Stuff
SB
1
DY
SB
Do Not Stuff
EL3
EL1
Do Not Stuff
EL2
EC50 Do Not Stuff
EC51 Do Not Stuff SYN-CON7-40-GP
MLVS0402M04-GP
EC13 SCD1U50V3ZY-GP D2 Do Not Stuff
EC14 SCD1U50V3ZY-GP
EC53
EC52
DY
DY
DY DY
20.81171.007
UMA Two Phase 2
DY
A
1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 46 BATT_SENSE R8 1 2 Do Not Stuff Title Size Document Number
1119 modify EC52 and EL3
AD/BATT CONN
HM40-MV
Sheet 45
E
Rev
SB
of 51

A B C D
1013 modify U3
DCBATOUT AD+ U3 S S S G AO4433-GP
NEAR
8 7 6 5
D D D D
2
EC54 SCD1U50V3KX-GP DCBATOUT
1 2 3 4
1013 modify U31

U31 S S S G AO4433-GP
BT+
1
R11 100KR2J-1-GP
AD+_TO_SYS
R9 1
2
AD+
84.04433.A37 2nd = 84.04407.F37

2
D01R2512F-4-GP AD+_G_2
1 2 3 4
D D D D
8 7 6 5
20080605
1
AD+ C324 SCD1U25V2ZY-1GP
AD+_G_1
D13 1SS400GPT-GP
G3
G4
R10 10KR2F-2-GP
R12 49K9R2F-L-GP
1016 modify D13
84.04433.A37 2nd = 84.04407.F37

R153 470KR2J-2-GP
DC_IN_D
ICREF
BQ24745_ACIN
ACIN
3D3V_AUX_S5
11
VDDSMB
CSSN ICOUT BOOT VDDP
27 26 25 21 24 23 20 19 18
BQ24745_CSSN TP47
D12
C367 1
R169 49K9R2F-L-GP
AC_OK
R183 1 2BQ24745_ACOK 13 Do Not Stuff
BQ24745_BST BQ24745_VDDP
ACOK UGATE SCL PHASE

BQ24745_LX1
C350 SC1U10V3KX-3GP 33,45 BAT_SCL
83.R0203.08F 2nd = 83.R2003.A8M 24745_HIGH_G
4 3 2 1
CH520S-30PT-GP SC1U10V3KX-3GP
G S S S
D D D D
DCIN
CSSP
84.04800.D37 2nd = 84.08884.037
DY
DY
SI4800BDY-T1
BQ24745_DCIN
5 6 7 8
2
Q2 2N7002DW -1-GP C358 SC1U25V5KX-1GP
83.00400.C1F 2nd = 83.1S400.A2F
AD+
POWER SB
Do Not Stuff
Do Not Stuff
C347
DCBATOUT
R164 309KR3F-GP
C340 2 1 BQ24745_CSSP SCD1U50V3KX-GP
CHG_AGND
C344 SCD1U50V3KX-GP
SCD1U25V3KX-GP
AC_OK
U41
CHG_AGND
C17
C319 Do Not Stuff
Do Not Stuff
22
28
U32
DY
BT+ L7 R160 1
10
1 2 C351 SCD1U50V3KX-GP 5 6 7 8
24745_LOW _G U39
2
IND-5D6UH-32-GP
BT+_R
33,45 BAT_SDA CHG_AGND CHG_AGND R172 1 2 Do Not Stuff C336 1 CHG_AGND BQ24745_IINP SC150P50V2JN-3GP
SDA LGATE
D01R2512F-4-GP C323 SC10U25V6KX-1GP C322 SC10U25V6KX-1GP C19 SC10U25V6KX-1GP C18 SC10U25V6KX-1GP C318 SCD1U50V3KX-GP
14
NC#14
PGND CSOP
G56 Do Not Stuff
G55 Do Not Stuff
33
B
AD_IA
VICM
C348 SC220P50V2KX-3GP
2 BQ24745_FBO_RC R171 1 2 200KR2F-L-GP
R166 1 2BQ24745_FBO 4K7R2J-2-GP
SCD1U50V3KX-GP
4 3 2 1
CSON
G S S S
17
C365
84.04800.D37 2nd = 84.08884.037

SI4800BDY-T1
68.5R610.10I 2nd = 68.5R610.201
D D D D
GND
C337 R167 SC2200P50V2KX-2GP 7K5R2F-1-GP 2 1BQ24745_EAO_RC 2 1
C338 SC1U10V3KX-3GP
6 BQ24745_EAI 5 BQ24745_EAO 4 BQ24745_VREF 3 BQ24745_CHG_ON 7 12
FBO EAI EAO VREF CE GND
NC#16
16
VFB
15
BATT_SENSE
BATT_SENSE 45
MAX8731A_CSIP MAX8731A_CSIN
1 2 C341 SC56P50V2JN-2GP
29
BQ24745RHDR-GP
1 2
74.24745.073
C364 SCD1U25V2ZY-1GP R163 1 2 Do Not Stuff
CHG_AGND CHG_AGND BQ24745_VREF RN43 CHG_AGND AC_OK CHG_ON# AC_IN# BQ24745_CHG_ON BQ24745_CHG_ON C345 Do Not Stuff
3D3V_AUX_S5
A
1 2 3 4
8 7 6 5
Q20
3 2 1
4 5 6
2N7002DW -1-GP CHG_ON# AC_IN# CHG_ON# AC_IN# 33 33
UMA Two Phase 2
SRN100KJ-8-GP-U
DY
AC_OK
Wistron Corporation
AC_IN# to KBC
Title Size A3 Date: Document Number 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
1 2
C339 SC1U10V3KX-3GP
BQ24745 Charger
HM40-MV
Sheet
1
Rev
SB
46 of 51
5V_S0 5V_S0 DCBATOUT
1020 delete TC14,TC15 SB

1
14
10
14
13
9
U8C
12
U8D
11
TC24 SE100U25VM-L1-GP
1117 delete TC19
TSAHCT125PW -GP
TSAHCT125PW -GP
73.74125.L13 2nd = 73.74125.L12
73.74125.L13 2nd = 73.74125.L12 79.10712.L02 2nd = 79.10112.3JL
1016 modify U32 1017 add these parts(EC10,EC12,EC15~EC17,EC86) for EMI demand 1020 add the part(EC86) for EMI demand SB 1121 add the part(EC89) for EMI demand
DCBATOUT
1125 add the part(EC90) for EMI demand 1128 add EC94,EC95 for EMI demand
1D8V_S3
EC15
DY
1 1 1 1 1 1 1
EC12 EC10 EC17 EC16 EC89 EC90 EC94
EC95
1 2
EC86
Do Not Stuff
Do Not Stuff
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
DY
DY
DY
DY
DY
DY
DY
1016 add GND1 and GND2 for EMI demand 1017 add GND3 and modify GND2 for EMI demand
CPU
HOLE355X355R111-S1-GP H36 H37
HOLE355X355R111-S1-GP
HOLE355X355R111-S1-GP
HOLE355X355R111-S1-GP HOLE355X355R111-S1-GP
H35
H38
TOP
1 1 1 1 1
34.4B312.002
34.4F822.002
34.49U23.001
DY Do Not Stuff
DY Do Not Stuff
GND1 SPRING-58-GP
GND2 SPRING-51-GP
GND3 SPRING-9-GP
GND4 Do Not Stuff
GND7 Do Not Stuff
GND8 Do Not Stuff
DY Do Not Stuff
34.42Y01.011
34.42Y01.011
34.42Y01.011
34.42Y01.011
SB 1128 Add GND4,GND7,GND8 1016 modify H31 and H32 SB 1120 remove H31and H32
1016 modify H35~H38 1016 delete H9~H12
H18 Do Not Stuff
H19 Do Not Stuff
H20 Do Not Stuff
H21 Do Not Stuff
H22 Do Not Stuff
H23 Do Not Stuff
H24 Do Not Stuff
H26 Do Not Stuff
H27 Do Not Stuff
H28 Do Not Stuff
H29 Do Not Stuff
H30 Do Not Stuff
Do Not Stuff
Do Not Stuff H1
Do Not Stuff
Do Not Stuff Do Not Stuff Do Not Stuff H2
Do Not Stuff
Do Not Stuff H3
Do Not Stuff
Do Not Stuff H4 H5
Do Not Stuff
Do Not Stuff H6
Do Not Stuff
Do Not Stuff Do Not Stuff H7
Do Not Stuff
Do Not Stuff H8
Do Not Stuff
Do Not Stuff Do Not Stuff H17
Do Not Stuff
Do Not Stuff H43
Do Not Stuff
Do Not Stuff
Do Not Stuff
UMA Two Phase 2
Wistron Corporation
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
SB 1128 Add H43

Size Date:
Document Number
EMI/Spring/Boss
HM40-MV
Sheet
1
Rev
SB
47 of 51
Friday, November 28, 2008
Speaker
27,28 27,28 27,28 27,28 SPKR_R+ SPKR_RSPKR_L+ SPKR_L1 1 1 1 Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff TP244 TP243 TP245 TP246
LED
5V_S0 36 WLAN_LED#_R 36 TP_LOCK_LED#_R 36 TP_LOCK_BN#_1 36 WIRELESS_BTN#_1 36 CAP_LED#_R 36 NUM_LED#_R 36 MEDIA_LED#_R 36 3D3V_S0 PWRLED#_R 1 1 1 1 1 1 1 1 1 1 1 Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff TP88 TP229 TP228 TP230 TP231 TP91 TP90 TP234 TP253 TP252 TP254
Touch pad
5V_S0 35 35 35,37 35,37 TP_DATA TP_CLK TP_RIGHT TP_LEFT
1 1 1 1 1
TP109 TP105 TP110 TP114 TP113
36 KBC_PWRBTN#_1
SB 1112 remove the signal( STDBY_LED#_R) Battery
33 33 33 33 KCOL16 KCOL15 KCOL14 KCOL13 1 1 1 1 Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff TP127 TP139 TP148 TP146 AD_JK 1 1 Do Not Stuff Do Not Stuff TP6 TP5 33 33 33 33 KCOL8 KCOL7 KCOL6 KCOL5 1 1 1 1 Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff TP98 TP99 TP101 TP100
Keyboard
45 45 45
BATA_SDA_1 BATA_SCL_1 BAT_IN#_1 BT+ BT+
1 1 1 1 1
TP16 TP17 TP15 TP14 TP13
Check test point

1 1 1 1
3D3V_S0
Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff
TP237 TP240 TP236 TP238
33 33 33 33
1 1 1 1
TP118 TP138 TP122 TP123
3D3V_AUX_S5
3D3V_S5 5V_S5
33 33 33 33
1 1 1 1
TP152 TP154 TP153 TP151
4,12,39 H_PWRGD 33,39,42 S5_ENABLE 4,6 H_CPURST#
1 1 1
Do Not Stuff Do Not Stuff Do Not Stuff
TP241 TP242 TP239
33 33 33 33
1 1 1 1
TP94 TP95 TP92 TP97
33 33 33 33 33 33
KCOL12 KCOL11 KCOL10 KCOL9 KCOL17 KCOL0
1 1 1 1 1 1
Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff
TP260 TP116 TP117 TP102 TP72 TP87
FAN
32 G7922_FAN_TACH 1 1 Do Not Stuff Do Not Stuff TP187 TP188 UMA Two Phase 2
Bluetooth
A
32 G7922_FAN_DRIVE 1 1 1 Do Not Stuff Do Not Stuff Do Not Stuff TP134 TP136 TP133
22 22 22

Wistron Corporation
A
Test Point
Dimm Door
AFTE test point

HM40-MV
Sheet
1
Rev
SB
48 of 51

2
0910 delete F4(Page 18) 0910 update footprint of U15(Page 30) 0910 delete RIGHT1 and LEFT1(Page 33) 0910 modify net names of TP_LEFT and TP_RIGHT(Page 36) 0910 modify
D
test points of AFTE and TPAD

D
0911 modify net name from LPC_RST to PLT_RST1#(Page 24) 0911 add net name(RBIAS,LED_DUPLEX#,SMDATA,SMCLK)(Page 24) 0911 add net name(DVDD_1_8,ACZ_SDATAIN0_R,FLY_P,FLY_N,VREF_LO,VREF_HI)(Page 26) 0911 add net name(EAPD#_R)(Page 27) 0912 modify the schematic of Page 33 0912 delete GMCH_TXB*(Page 7& 18) 0912 add these parts for EMI demand(page 7,18,20,21,23,26,28,29,30,32,33,34,35) 0915 modify net name from 10M/100M/1G_LED# to 10M/100M_LED#(page24,25) 0915 delete these parts for EMI demand(page 30) 0915 add EC34 for EMI demand(page3) 0915 modify LEDs port 0915 add EC73 for EMI demand(page 12)
0916 move net(SPI_WP#) from U9 pin120 to pin25(page33) 0930 modify BLUE1(page22)

C
0930 add 2nd for SPK1, MIC1 and modify LOUT1 (page28) 0930 modify 0930 modify 0930 modify FAN1(page32) KB1(page33) TPAD1(page35)
0930 modify net name for BIOS demand(page33) 1009 modify net name for GND to AGND(page27) 1009 add R4,R5 for AC decopling(page27) 1009 add R96(page30) 1013 modify TPAD1(page35)
1001 delete these parts for EMI demand(ED1~8)
1013 modify U40 from 72.25X16.001 to 72.25X16.A01(page 34) 1013 modify TC11 and add TC12(page42) 1013 modify TC10 and add TC26(page44) 1013 modify U2(page45)
B
1013 modify U3 and U31(page 46) 1013 modify R161 and R162(page41) 1013 modify card1(page 30) 1014 modify these LEDs(LED11,LED12)(page38) 1014 modify these nets(page 26) 1014 modify R258 from 10k to 20k ohm(page26) 1014 add ER5 for EMI deamnd(page3) 1015 modify LCD1 pin define(page 18) 1015 modify the power from 3D3V_S5 to 5V_S5(page38) 1015 modify TPAD1(page35) 1015 modify RN57(page28) 1015 modify F1(page18)
UMA Two Phase 2

A A
Wistron Corporation
5 4 3 2
Document Number
Change List
HM40-MV
Sheet
1
Rev
SB
49 of 51
1016 modify XF1(page 25) 1016 modify U8(page19,47) 1016 modify U4(page 37) 1016 modify U23(page 43)
D
1016 modify L1,L2 and L3(page 19) 1016 modify RN53 and U10(page 24)
1016 modify X2(page12) 1016 modify X1(page 33) 1016 modify X3(page 3) 1016 modify D13(page 46) 1016 modify D23(page 20) 1016 modify D9(page 39) 1016 modify D4(page 19) 1016 modify Q3 and Q4(page45) 1016 modify Q18(page 36) 1016 modify Q15~Q17(page 36) 1016 modify Q27~Q30(page38) 1016 modify Q8(PAGE 24)
1016 modify Q6 and Q14(page 32)
1016 add GND1 nad GND2 for EMI demand(page 47)

C
1016 modify LCD1 pin define(page 18)
1016 delete H9~H12 and modify H35~H38,H31,H32(page 47) 1017 add these parts for EMI demand(page 47) 1017 delete these parts(EC208~EC210)(page 7) 1017 modify BLUE1(page 22) 1017 modify FAN1(page 32) 1017 modify R291 and R293(page 38) 1017 add U61,R52,EC23 and EC24(page 37) 1017 modify RN60(page37) 1017 add TC25(page 44) 1017 add GND3 and modify GND2 for EMI demand(page 47)
1017 modify USB signal connection(page13,18,22,23,30,31,48) 1020 delete C537 for Power demand(page42) 1020 add the part(EC86) for EMI demand(page 47) 1020 delete U61,R52,EC24 and EC23(page 37)
B
1020 delete TC14,TC15(page 47) 1021 modify TC16(page 31) 1021 delete TC23(page 23) 1021 modify TC5(page 20) 1021 modify and swap these parts(USB1 and USB2)(page 23) 1021 modify SATA1(page 20) 1022 modify DC1(page 45)
UMA Two Phase 2

A A
Wistron Corporation
5 4 3 2
Document Number
Change List
HM40-MV
Sheet
1
Rev
SB
50 of 51
SA to SB 1127 modify C377(page32) for thermal function
1106 modify net connection of RN46 and RN44(page33) for layout demand 1106 modify LED11 and LED12(page38) for fixing issue 1106 modify LED power from 5V_S5 to 5V_AUX_S5(page38) for customer demand 1112 remove the signal(STDBY_LED#_FR)page38 for customer demand
D
1128 Add H43,GND4,GND7,GND8(page47) for EMI demand 1128 modify LCD1(page18) for cost down 1128 Add L19(page24) for vender demand 1128 add EC94,EC95 for EMI demand(page47)
D
1112 remove these signals( STDBY_LED#_FR and STDBY_LED#_R) and R131(page36) for customer demand 1112 remove the signal( STDBY_LED#_R)page36 for customer demand 1112 remove the signal( STDBY_LED#_R)and TP253(page48) for customer demand 1113 modify C103 and C106(page24) for crystal issue 1113 modify 2nd of U19(page26) 1113 modify 2nd of U43(page39) 1113 modify 2nd of U44(page10) 1113 modify U48(page22)
1117 delete MDC function(R231,R237,R232,R234)(page12) 1117 delete TC19(page 47) for ME deamnd
1118 modify PCB Ver. from SA to SB(page33) 1118 delete TC12(page42) for layout demand 1118 delete TC27(page9) for layout demand
1118 delete R107 and add L18 for cost down
1119 modify R130 and R133(page 36) for LED brightness

C
1119 modify EC52 and EL3(page45) for EMI demand 1119 modify SPK1(page 28) for ME deamnd 1119 add G84 for RTC reset demand
1120 modify EC78for EMI demand((page10)
1120 modify PowerCN1 pin3 and remove EC44(page36) fro LED function 1120 remove H31 and H32(page47)for ME demand 1120 add RN61 and RN62(page3) for layout demand
1120 swap these nets(CLK_MCH_3GPLL,CLK_MCH_3GPLL#, CLK_PCIE_MINI1,CLK_PCIE_MINI1#)(page3)for CLK REQ demand 1120 add the net( SATACLKREQ#)(page3,13)for CLK REQ demand 1120 move these nets (CLK_PCIE_MINI1,CLK_PCIE_MINI1#)(page3)for CLK REQ demand 1120 modify RN61 and RN62(page3)for CLK REQ demand 1121 add EC87 for EMI demand(page18) 1121 add the part(EC89) for EMI demand(page47) 1121 add the part(EC88) for EMI demand(page45)
B
1121 modify R18,C43(page41) for Power demand 1121 modify R275(page42)for Power demand 1121 modify R271,R272,R286 and L16(page44) for Power demand 1124 modify U42 and delete R182,R185 (page32) for thermal function 1124 modify these names of these nets(G7922_SGND2,G7922_SGND3...) (page32) for thermal function 1124 add R302(page3) for clock gen function 1125 add the part(EC90) for EMI demand(page47) 1125 add the part(EC91) for EMI demand(page45) 1125 modify R125,R126(page18) for LCD brightness control 1125 modify RN40 and delete RN42(page32) for layout demand 1125 add EC92 and EC93 for EMI demand(page 22) 1126 add these nets (PCIE_REQ_LAN#,PCIE_REQ_MINI#)(page3)for CLK REQ demand 1126 delete R230,R233,R235,R236 and RN63(page12) for removing MDC function 1126 add C541 and modify R101(page26) for codec function 1126 modify RN61 and RN62(page3) for layout demand
UMA Two Phase 2
1126 modify EU1,EU2 and add EU3,EU4 for EMI demand(page28) 1127 modify CRT1(page19) for customer demand 1127 swap the nets of RN61 and RN62 for layout demand(page3)
Title Size Date:
5 4 3 2
Wistron Corporation
1127 modify BAT1(page45) for ME demand 1127 modify U27(page44) for power demand
Document Number
Change List
HM40-MV
Sheet
1
Rev
SB
51 of 51

Emachines D725

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5

HM40-MV Block Diagram

Project code: 91.4BW01.001 PCB P/N : 48.4BW01.0SB REVISION : 08242-SB

HOST BUS 667/800MHz

LPC BUS BIOS

Line Out (NO SPDIF)

INT. KB 33 MS/MS Pro/xD 30 /MMC/SD

CardReader Realtek RTS5159 30

UMA Two Phase 2

Title Size A3 Date:

Digitally signed by Wistron Corporation dd

http://konweer.kiev.ua ICH9M Functional Strap

Definitions Rev.1.5 ICH9 EDS 642879

ICH9M Integrated Pull-up and Pull-down Resistors

Cantiga chipset and ICH9M I/O controller Hub strapping configuration

ICH9 EDS 642879

Montevina Platform Design guide 22339

Strap Description FSB Frequency Select

HDA_SYNC GNT2#/ GPIO53 GPIO20 GNT1#/ GPIO51

CFG[4:3] CFG8 CFG[15:14] CFG[18:17] CFG5 CFG6

Top-Block Swap Override. Rising Edge of PWROK.

GNT0#: SPI_CS1#/ GPIO58 SPI_MOSI

Boot BIOS Destination Selection 0:1. Rising Edge of PWROK.

Integrated TPM Enable, Rising Edge of CLPWROK

PCIE Loopback enable XOR/ALL

0 = Enable (Note 3) 1= Disabled (default) = = = =

LDA[3:0]#/FHW[3:0]# LAN_RXD[2:0] LDRQ[0] PME#

FSB Dynamic ODT

DMI Lane Reversal

SPI_MOSI SPI_MISO SPKR TACH_[3:0] TP[3] USB[11:0][P,N]

Digital Display Port (SDVO/DP/iHDMI) Concurrent with PCIe SDVO Present

GPIO33/ HDA_DOCK _EN#

Local Flat Panel (LFP) Present

0 = LFP Disabled (Default) 1= LFP Card Present; PCIE disabled

Device USB1 NC NC MINIC1 WEBCAM NC NC Bluetooth NC USB2(High speed) NC CardReader

UMA Two Phase 2

Monday, November 24, 2008

1015 modify component size of R95

SB 1124 add R302

1 R302 2 Do Not Stuff 1 R80 2 1 1 1

1015 modify component size of R80

1015 modify component size of R87

C165 Do Not Stuff

C176 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP

C221 Do Not Stuff

C227 SC1U16V3ZY-GP SC1U16V3ZY-GP

3D3V_CLKGEN_S0 CLK_ICH14 PCLK_KBC

RN62 24 PCIE_REQ_LAN# 13 SATACLKREQ# 31 PCIE_REQ_MINI# 7 CLK_MCH_OE#

0915 add EC34 for EMI demand

8 PCIE_REQ_LAN#_R 7 PCLKCLK0 6 PCIE_REQ_MINI#_R 5 PCLKCLK1

Do Not Stuff Do Not Stuff

SB 1127 swap the nets of

RN61 and RN62

VDDREF VDD48 VDDPCI VDDSRC VDDCPU VDDPLL3

VDD96_IO VDDPLL3_IO VDDSRC_IO VDDSRC_IO VDDSRC_IO VDDCPU_IO

82.30005.891 2nd = 82.30005.951

CLK_MCH_BCLK 6 CLK_MCH_BCLK# 6 CLK_PCIE_LAN 24 CLK_PCIE_LAN# 24

CLK48_5159 CLK48_ICH CPU_SEL0

SRCT7/CR#_F SRCC7/CR#_E SRCT6 SRCC6

SB 1126 add the net(PCIE_REQ_LAN#)

15,16,17 SMBC_ICH 15,16,17 SMBD_ICH

SB 1120 swap these nets(CLK_MCH_3GPLL,CLK_MCH_3GPLL#, CLK_PCIE_MINI1,CLK_PCIE_MINI1#) SB