DELL Inspiron N4020

5
DJ1 Montevina UMA Schematics Document uFCPGA Mobile Penryn

C
Intel GM45+ICH9M 2010-02-10 REV : A00
DY : Nopop Component
DJ1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date:
5 4 3 2
Document Number
Cover Page
Sheet
1
Rev
DJ1 Montevina UMA

W ednesday, February 24, 2010 1 of 88
A00
DJ1 Montevina UMA Block Diagram

D
CPU DC/DC
TPS51620
INPUTS
+PWR_SRC
47
Clock Generator SLG8SP513VTR

7
Intel Mobile CPU Penryn Socket P

8,9
Project code : 91.4EK01.001 PCB P/N : 48.4EK06.0SA Revision : 09275-SA
OUTPUTS
+VCC_CORE
SYSTEM DC/DC
TPS51218
INPUTS
+PWR_SRC
49
D
OUTPUTS
+1.05V_VCCP
SYSTEM DC/DC
TPS51125
46
FSB 800/1066MHz
INPUTS
+PWR_SRC
OUTPUTS
+5V_ALW2 +3.3V_RTC_LDO +5V_ALW +3.3V_ALW +15V_ALW
CRT
55
RGB CRT
Intel GM45
AGTL + CPU I/F DDR Memory I/F External Graphics
10,11,12,13,14,15
DDRIII 800/1066 Channel A
DDRIII 800/1066 DDRIII 800/1066
Slot 0
18
SYSTEM DC/DC
TPS51116
INPUTS OUTPUTS
+1.5V_SUS +0.75V_DDR_VTT +V_DDR_REF +PWR_SRC
50
DDRIII 800/1066 Channel B
Slot 1
19
LCD
C
54
LVDS(Dual Channel)
MAXIM CHARGER
BQ24745
INPUTS OUTPUTS
+PWR_SRC
C
DMIx4
C-LINK
10/100 NIC
Atheros AR8132
+DC_IN +PBATT
RJ45 CONN
26
SYSTEM DC/DC
Switches
42
I/O Board Connector
Intel ICH9-M
CardReader
SD/MMC/MS/ MS Pro/xD
70
SATA
PCIE x 2
26
Mini-Card
802.11a/b/g
INPUTS
+1.5V_SUS +5V_ALW +3.3V_ALW
OUTPUTS
+1.5V_RUN +5V_RUN +3.3V_RUN
PCIE USB2.0 USB 2.0/1.1 ports (12) PCI Express ports (8) High Definition Audio SATA ports (4) LPC I/F USB 2.0
USB 2.0 x 1
Realtek RTS5138
32
Left Side: USB x 1

75
PCB LAYER
L1: Top L2: VCC
USB 2.0 x 1
CAMERA
L3: Signal
54
ACPI 1.1
L4: Signal
USB 2.0 x 1
MIC IN
60
Internal Analog MIC

60
Azalia CODEC
IDT 92HD79B1
30
AZALIA
PCI/PCI BRIDGE
Bluetooth
L5: GND
72
L6: Bottom
20,21,22,23
LPC Bus
USB 2.0 x 2
HP1
60
Right Side: USB x 2
63
KBC
SPI
SATA
SATA
NUVOTON
NPCE781BA0DX
37
2CH SPEAKER HDD

59 60
DJ1
ODD
59
Flash ROM 2MB 62
Touch PAD
67
Int. KB
67
Thermal
EMC2102
39 25 Title Size A3 Date: Document Number
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Block Diagram
Rev
Fan 58
5 4 3 2
DJ1 Montevina UMA

W ednesday, February 24, 2010 Sheet
1
A00
of 88
DJ1 Montevina UMA Power Block Diagram

D D
Adapter
+PWR_SRC TPS51125 Charger BQ24745

+VCC_CORE 47 +1.05V_VCCP 49
+V_DDR_REF +0.75V_DDR_VTT
TPS51620
TPS51218
TPS51116
Battery
C
+VCHGR
50
50
+1.5V_SUS 50
FSD8880
+15V_ALW
46
+3.3V_RTC_LDO 46
+5V_ALW2
46
+5V_ALW
46
+3.3V_ALW
46
+1.5V_RUN 42
G547F2P81U
SI4800
G547F2P81U
FDS8880
PA102
+5V_USB1 63
B
+5V_RUN 42
+5V_USB2 63
+3.3V_RUN 42
+3.3V_LAN
B
G9091 G5285T11U
+3.3V_CRT_LDO 15 +LCDVDD 54
+3.3V_RUN_CARD +1.8V_NB_S0
RTS5159
RT9198
RTL8103T
+1.2V_LOM
32
15
Power Shape
Regulator LDO Switch
DJ1
Wistron Corporation
5 4 3 2
Document Number
Power Block Diagram

Sheet
1
Rev
DJ1 Montevina UMA

A00
ICH SMBus Block Diagram

+3.3V_ALW +3.3V_RUN +3.3V_RUN SRN4K7J-8-GP
KBC SMBus Block Diagram

+5V_RUN
SRN4K7J-8-GP
ICH
1
DIMM 1
ICH_SMBCLK ICH_SMBDATA SCL SDA PSDAT1 PSCLK1 TPDATA TPCLK +KBC_PWR
SMBCLK SMBDATA
SMB_CLK SMB_DATA
SMBus Address:A0
2N7002SPT
DIMM 2
ICH_SMBCLK ICH_SMBDATA
SCL SDA
SRN4K7J-8-GP
SMBus Address:A4
SCL1 BAT_SCL BAT_SDA
Clock Generator
SCLK SDATA
SDA1
SMBus address:D2
KBC NPCE781BA0DX
+KBC_PWR
SMB_CLK
SMB_DATA SRN4K7J-8-GP
+3.3V_RUN
GPIO61/SCL2 GPIO62/SDA2
KBC_SCL1 2N7002DW-1-GP KBC_SDA1
+3.3V_RUN
SRN2K2J-1-GP
3
DDC1CLK DDC1DATA
LDDC_CLK LDDC_DATA
LCD CONN
+5V_CRT_RUN
+3.3V_RUN
+3.3V_RUN SRN2K2J-1-GP
VGA
DDC2CLK DDC2DATA GMCH_DDCCLK GMCH_DDCDATA
2N7002DW-1-GP
Minicard WLAN
SRN10KJ-5-GP
TouchPad Conn.
TPDATA TPCLK TPDATA TPCLK
1
SRN100J-3-GP PBAT_SMBCLK1 PBAT_SMBDAT1
Battery Conn.
CLK_SMB DAT_SMB
SMBus address:16
BQ24745
SCL SDA
SMBus address:12
+3.3V_RUN
2
SRN4K7J-8-GP
Thermal
THERM_SCL THERM_SDA SCL SDA
SMBus address:7A
SRN2K2J-1-GP
DDC_CLK_CON DDC_DATA_CON
CRT CONN
DJ1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A2 Date:
D
Document Number
SMBUS Block Diagram

Sheet 4 of
E
DJ1 Montevina UMA
Rev
A00
88
Wednesday, February 24, 2010
Thermal Block Diagram

1
Audio Block Diagram

1
SPKR_PORT_D_L-/L+ SPKR_PORT_D_R-/R+
2CH SPEAKERS
DP1
H_THERMDA SC470P50V3JN-2GP
CPU
THRMDA HP1_PORT_B_L HP1_PORT_B_R THRMDC
HP OUT
2
DN1
H_THERMDC
Codec 92HD79B1
Thermal EMC2102
DP2 EMC2102_DP2 PMBS3904-1-GP SC470P50V3JN-2GP DN2 EMC2102_DN2
HP0_PORT_A_L HP0_PORT_A_R VREFOUT_A_OR_F
MIC IN
Put between CPU and NB
DP3
EMC2102_DP3 PMBS3904-1-GP SC470P50V3JN-2GP
DN3
EMC2102_DN3
HW T8 sensor
PORTC_L PORTC_R VREFOUT_C
Analog MIC
DJ1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Document Number Custom Date:
A B C D
Thermal/Audio Block Diagram

DJ1 Montevina UMA
Sheet
E
Rev
A00
5 of 88
ICH9M Functional Strap Definitions

Signal
HDA_SDOUT
1
Usage/When Sampled
XOR Chain Entrance / PCI Express* Port Config 1 bit 1 (Port 1-4), Rising Edge of PWROK PCI Express Port Config 1 bit 0 (Port 1-4), Rising Edge of PWROK. PCI Express Port Config 2 bit 2 (Port 5-6), Rising Edge of PWROK Reserved, Rising Edge of PWROK ESI Strap (Server Only), Rising Edge of PWROK.
ICH9 EDS 642879 Comment
Rev.2.3
ICH9 Integrated pull-up and pull-down Resistors

ICH9 EDS 642879 Rev.2.3
Cantiga chipset and ICH9M I/O controller Hub strapping configuration

Montevina Platform Design guide 355648 Rev.2.3
Pin Name
CFG2:0
Allows entrance to XOR Chain testing when TP3 pulled low at rising edge of PWROK. When TP3 not pulled low at rising edge of PWROK, sets bit 1 of RPC.PC (Chipset Config Registers: Offset 224h).This signal has a weak internal pull-down. This signal has a weak internal pull-down. Sets bit 0 of RPC.PC (Chipset Config Registers: Offset 224h) This signal has a weak internal pull-up. Sets bit 2 of RPC.PC2 (Chipset Config Registers:Offset 0224h) when sampled low. This signal has a weak internal pull-down. NOTE: This signal should not be pulled high Tying this strap low configures DMI for ESIcompatible operation. This signal has a weak internal pull-up. NOTE: ESI compatible mode is for server platforms only. This signal should not be pulled low for desktop and mobile. Sampled low: this indicates that the system is strapped to the top-block swap mode (IntelR ICH9 inverts A16 for all cycles targeting BIOS space). The status of this strap is readable via the Top Swap bit (Chipset Config Registers:Offset 3414h: bit 0). Note that software will not be able to clear the Top-Swap bit until the system is rebooted without GNT3# being pulled down. Controllable via Boot BIOS Destination bit (Chipset Config Registers:Offset 3410h:bit 11). This strap is used in conjunction with Boot BIOS Destination Selection 0 strap. Bit11 (GNT0#) 0 1 1 0 Bit 10 Boot BIOS (SPI_CS1#) Destination 1 SPI 0 PCI 1 LPC 0 Reserved
SIGNAL
CL_CLK[1:0] CL_DATA[1:0] CL_RST0# DPRSLPVR/GPIO16 HDA_BIT_CLK HDA_DOCK_EN#/GPIO33 HDA_RST# HDA_SDIN[3:0] HDA_SDOUT HDA_SYNC
GNT0#, GNT[3:1]#/ GPIO[55,53,51]
Resistor Type/Value
PULL-UP 20K PULL-UP 20K PULL-UP 10K PULL-DOWN 20K PULL-DOWN 20K PULL-UP 20K PULL-DOWN 20K PULL-DOWN 20K PULL-DOWN 20K PULL-DOWN 20K PULL-UP 20K
Strap Description
FSB Frequency
Configuration
000 = FSB1066 010 = FSB800 011 = FSB667 Others = Reserved 0 = DMI x2 1 = DMI x4 (Default) 0 = The iTPM Host Interface is enabled (Note 2) 1 = The iTPM Host Interface is disabled (default) 0 = Intel Management Engine Crypto Transport Layer Security (TLS) cipher suite with no confidentiality 1 = Intel Management Engine Crypto TLS cipher suite with confidentiality (default) 0 = Reverse Lanes, 15->0, 14->1 etc. 1 = Normal operation (default): Lane Numbered in Order
1
HDA_SYNC
CFG5
DMI x2 Select
GNT2#/ GPIO53 GPIO20 GNT1#/ GPIO51
CFG6
ITPM Host Interface
CFG7
Intel Management engine crypto strap
CFG9
PCIE Graphics Lane
GPIO20 GPIO49 LAD[3:0]# / FHW[3:0]# LAN_RXD[2:0] LDRQ0 LDRQ1 / GPIO23 PME# PWRBTN# SATALED#
SPI_CS1# / GPIO58 (Desktop Only) / CLGPIO6 (Digital Office Only)
PULL-DOWN 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 15K PULL-UP 20K
CFG19 DMI Lane Reversal CFG13 CFG16 XOR FSB Dynamic ODT CFG12 CFG10
GNT3#/ GPIO55
Top-Block Swap override. Rising Edge of PWROK.
PCIE Loopback enable 0 = Enable (Note 3) 1 = Disable (Default) ALLZ 0 =ALLZ mode enabled (Note 3) 1 = Disable (Default) 0 = XOR mode enabled (Note 3) 1 = Disable (Default) 0 = Dynamic ODT Disabled 1 = Dynamic ODT Enabled (Default) 0 = Normal operation (Default): Lane Numbered in Order 1 = Reverse Lanes DMI x4 mode [MCH->ICH]: (3->0, 2->1, 1->2 and 0->3) DMI x2 mode [MCH->ICH]: (3->0, 2->1)
2
GNT0#
Boot BIOS Destination Selection 1, Rising Edge of PWROK.
SPI_MOSI SPI_MISO SPKR TACH[3:0] TP3 USB[11:0][P,N]
PULL-DOWN 20K PULL-UP 20K

CFG20
SPI_CS1#/ GPIO58
Boot BIOS Destination Controllable via Boot BIOS Destination Selection 0, bit (Chipset Config Registers:Offset 3410h:bit 10). Rising Edge of CLPWROK. This strap is used in conjunction with Boot BIOS Destination Selection 1 strap. Bit11 (GNT0#) 0 1 1 0 Bit 10 Boot BIOS (SPI_CS1#) Destination 1 SPI 0 PCI 1 LPC 0 Reserved
PULL-DOWN 20K PULL-UP 20K PULL-UP 20K PULL-DOWN 15K

SDVO _CTRLDATA (Note4) L_DDC_DATA
Digital Display Port 0 = Only digital DisplayPort (SDVO/DP/HDMI) or (SDVO/DP/HDMI) PCIe is operational (default) Concurrent with PCIe 1 = Digital DisplayPort (SDVO/DP/HDMI) and PCIe are operating simultaneously via the PEG port SDVO Present 0 = No SDVO/HDMI/DP interface disabled (default) 1 = SDVO/HDMI/DP interface enabled 0 = LFP Disabled (Default) 1 = LFP Card Present; PCIE disabled 0 = Digital display (HDMI/DP) device absent (default) 1 = Digital display (HDMI/DP) Device Present
3
PCIE Routing
LANE1 LANE2 LANE3
USB Pair 0 1 2 3 4 5 6 7 8 9 10 11
Local Flat Panel (LFP) Present Digital Display Present
SATALED#
PCI Express Lane Reversal (Lanes 1-4). Rising Edge of PWROK.
Signal has weak internal pull-up. Sets bit 27 of MPC.LR (Device 28: Function 0: Offset D8) Sampled high: this indicates that the system is strapped to the No Reboot mode (ICH9 will disable the TCO Timer system reboot feature). The status of this strap is readable via the NO REBOOT bit (Chipset Config Registers:Offset 3410h:bit 5).
MiniCard WLAN LAN

Device USB0 (I/O Board) USB1 (I/O Board 17") USB2 USB3 BLUETOOTH RESERVED WLAN RESERVED RESERVED RESERVED Card Reader CAMERA
C
SPKR
No Reboot, Rising Edge of PWROK.
USB Table
DDPC _CTRLDATA (Note4) CFG4:3 CFG8 CFG11 CFG14 CFG15 CFG17 CFG18 NOTE:
Reserved
TP3
XOR Chain Entrance. Rising Edge of PWROK.
This signal should not be pull low unless using XOR Chain testing. Sampled low: the Flash Descriptor Security will be overridden. Sampled high: the security measures will be in effect. This strap should only be enabled in manufacturing environments. The signal is required to be high for mobile applications. Sampled low: the Integrated TPM will be disabled. Sampled high: the MCH TPM enable strap is sampled low and the TPM Disable bit is clear, the Integrated TPM will be enabled. NOTE: This signal is required to be floating or pulled low for desktop applications.
GPIO33 / HDA_DOCK_ Flash Descriptor Security Override Strap. EN# Rising Edge of PWROK. (Mobile Only)
4
1. All strap signals are sampled with respect to the leading edge of the GMCH Power OK (PWROK) signal. 2. iTPM can be disabled by a Soft-Strap option in the Flash-descriptor section of the Firmware. This Soft-Strap is activated only after enabling iTPM via CFG6. 3. Only one of the CFG10/CFG12/CFG13 straps can be enabled at any time. 4. DDPC_CTRL_DATA & SDVO_CTRL_DATA straps should both be high to enable Display Port.
DJ1
4
GPIO49
DMI Termination Voltage. Rising Edge of CLPWROK. Integrated TPM Enable. Rising Edge of CLPWROK.
Wistron Corporation
SPI_MOSI (Moble Only)
Table of Content
Sheet
E
Rev
DJ1 Montevina UMA

6 of 88
A00
SSID = CLOCK
3D3V_S0_CK505 +1.05V_VCCP R704 C702 SC1U10V3KX-3GP 1D05V_CK505_IO 1D05V_CK505_IO MINI1_CLKREQ# R702 1
2 10KR2J-3-GP
+3.3V_RUN
2
C704 SCD1U16V2KX-3GP C705 SCD1U16V2KX-3GP C706 SCD1U16V2KX-3GP C707 SCD1U16V2KX-3GP C708 SCD1U16V2KX-3GP Do Not Stuff C709 SCD1U16V2KX-3GP
CLK_XTAL_IN X701 CLK_XTAL_OUT

D
1 1
C710 SC15P50V2JN-2-GP
X-14D31818M-37GP
C711
4 16 9 46 62 23
U701
VDD_IO VDD_PLL3_IO VDD_SRC_IO VDD_SRC_IO VDD_SRC_IO VDD_CPU_IO
VDD_REF VDD_48 VDD_PCI VDD_SRC VDD_CPU VDD_PLL3
SC15P50V2JN-2-GP
19 27 43 52 33 56
CPUT0 CPUC0 CPUT1 CPUC1 SRCT8/CPU2_ITPT SRCC8/CPU2_ITPC SRCT7/CR#_F SRCC7/CR#_E SRCT6 SRCC6
61 60 58 57 54 53 51 50 48 47 41 42 40 39 37 38 34 35 31 32 28 29 24 25 20 21
CLK_CPU_BCLK CLK_CPU_BCLK# CLK_MCH_BCLK CLK_MCH_BCLK#
CLK_CPU_BCLK 8 CLK_CPU_BCLK# 8 CLK_MCH_BCLK 10 CLK_MCH_BCLK# 10
+3.3V_RUN R706 C713 SC1U10V3KX-3GP
3D3V_S0_CK505 32 CLK_48M_CARD R705 1
2 22R2J-2-GP 1
R701 2 22R2J-2-GP FSA
3 2 17
XN XOUT USB_48/FSA
2
C715 SCD1U16V2KX-3GP C716 SCD1U16V2KX-3GP C701 SCD1U16V2KX-3GP C717 SCD1U16V2KX-3GP C714 SC10U6D3V5KX-1GP C718 SCD1U16V2KX-3GP Do Not Stuff C719 Do Not Stuff 22 CLK_48M_ICH
DY
1 C712
22 22 H_STP_PCI# H_STP_CPU#
2 DYDo Not Stuff 45 44 PC_STOP# CPU_STOP#
CLK_PCIE_LAN CLK_PCIE_LAN# CLK_PCIE_ICH CLK_PCIE_ICH#
CLK_PCIE_LAN 76 CLK_PCIE_LAN# 76 CLK_PCIE_ICH 21 CLK_PCIE_ICH# 21
18,19,22,76 ICH_SMBCLK 18,19,22,76 ICH_SMBDATA 22 CK_PWRGD
7 6 63
SCLK SDATA CKPW RGD/PW RDW N#
SRCT10 SRCC10 SRCT1/CR#_H SRCC1/CR#_G SRCT9 SRCC9 SRCT4 SRCC4 SRCT3/CR#_C SRCC3/CR#_D SRCT2/SATAT SRCC2/SATAC
MINI1_CLKREQ# CLK_PCIE_MINI1 CLK_PCIE_MINI1# CLK_MCH_3GPLL CLK_MCH_3GPLL#
76
C
22 CLKSATAREQ# 11 CLKREQ#_B 58 PCLK_FWH 37 21 PCLK_KBC CLK_PCI_ICH
R707 1 R708 2 R709 1 R710 1
2 475R2F-L1-GP 1 Do Not Stuff
CLKSATAREQ# CLKREQ#_1 PCI2_TME 27_SEL ITP_EN
DY
2 33R2J-2-GP 2 33R2J-2-GP
8 10 11 12 13 14
PCI0/CR#_A PCI1/CR#_B PCI2/TME PCI3 PCI4/GCLK_SEL PCIF0/ITP_EN
CLK_PCIE_MINI1 76 CLK_PCIE_MINI1# 76 CLK_MCH_3GPLL 11 CLK_MCH_3GPLL# 11
CLK_PCIE_SATA CLK_PCIE_SATA# MCH_SSCDREFCLK MCH_SSCDREFCLK# CLK_MCH_DREFCLK CLK_MCH_DREFCLK#
22
CLK_14M_ICH C720 Do Not Stuff C721 Do Not Stuff
R711 1 C722 Do Not Stuff
2 33R2J-2-GP
FSB FSC
64 5 55
CLK_PCIE_SATA 20 CLK_PCIE_SATA# 20 MCH_SSCDREFCLK 11 MCH_SSCDREFCLK# 11 CLK_MCH_DREFCLK 11 CLK_MCH_DREFCLK# 11
FSB/TEST_MODE REF0/FSC/TEST_SEL NC#55 VSS_IO VSS_SRC VSS_SRC VSS_SRC VSS_CPU VSS_PLL3 VSS_48 VSS_PCI VSS_REF SRCT1/LCDT_100/27M_NSS SRCC1/LCDT_100/27M_SS SRCT0/DOT96T SRCC0/DOT96C
DY
DY
DY
GND 65
18 15 1
22 30 36 49 59 26
SLG8SP513VTR-GP
Main = 71.08513.003(SLG) Second = 71.09356.00W(ICS)

B B
3D3V_S0_CK505
3D3V_S0_CK505
27_SEL R713 10KR2J-3-GP
R712 10KR2J-3-GP
ITP_EN 0 1
Output SRC8 CPU_ITP

2
PCI2_TME
PCI2_TME
Output Overclocking of CPU and SRC allowed Overclocking of CPU and SRC not allowed
1
ITP_EN R715 Do Not Stuff
R714 10KR2J-3-GP
0
R716 Do Not Stuff
DY
2
DY
2
27_SEL 0 1
PIN20/21 96M 100M
PIN24/25 100M 27M
SEL2 SEL1 SEL0 FSC FSB FSA 1 0 0 0 0 0 0 1 1 0

5
CPU
100M 133M 166M 200M 266M
FSB
X 533M 667M 800M 1067M
8 8 8
CPU_BSEL2 CPU_BSEL1 CPU_BSEL0
R717 1 R718 1 R719 1 R720 1 R721 1 R722 1
2 10KR2J-3-GP 2 Do Not Stuff 2 2K2R2J-2-GP 2 1KR2J-1-GP 2 1KR2J-1-GP 2 1KR2J-1-GP
FSC FSB FSA DJ1

A
1 1 1 0 0
Wistron Corporation
MCH_CLKSEL0 11 MCH_CLKSEL1 11 MCH_CLKSEL2 11 Title Size Document Number Custom Date: 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Clock Generator SLG8SP513VTR

DJ1 Montevina UMA
Sheet
1
Rev
A00
of 88
Friday, February 26, 2010
SSID = CPU
CPU1A 1 OF 4
D
1 ADS# BNR# BPRI# H1 E2 G5 H5 F21 E1 F1 D20 CPU_IERR# B3 H4 C1 F3 F4 G3 G2 G6 E4 AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20
H_CPURST# H_RS#0 H_RS#1 H_RS#2
TP801 H_ADS# H_BNR# H_BPRI# 10 10 10

D
10
H_A#[35..3]
H_A#[35..3]
H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35
10 H_ADSTB#0 10 H_REQ#[4..0]
J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1 K3 H2 K2 J3 L1 Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1 A6 A5 C4 D5 C6 B4 A3
A3# A4# A5# A6# A7# A8# A9# A10# A11# A12# A13# A14# A15# A16# ADSTB0# REQ0# REQ1# REQ2# REQ3# REQ4# A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31# A32# A33# A34# A35# ADSTB1# A20M# FERR# IGNNE# STPCLK# LINT0 LINT1 SMI#
XDP/ITP SIGNALS
BPM0# BPM1# BPM2# BPM3# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR#
H_THERMDC ITP_BPM#5 ITP_TCK ITP_TDI ITP_TDO ITP_TMS ITP_TRST# ITP_DBRESET# R803 1 R804 1
H_THERMDA, H_THERMDC routing together, Trace width / Spacing = 10 / 10 mil
DATA GRP2
ADDR GROUP 0 ADDR GROUP 1
CONTROL
DEFER# DRDY# DBSY# BR0# IERR# INIT# LOCK# RESET# RS0# RS1# RS2# TRDY# HIT# HITM#
H_DEFER# 10 H_DRDY# 10 H_DBSY# 10 H_BREQ#0 10 R802 1 H_DINV#[3..0] +1.05V_VCCP H_DSTBN#[3..0] H_DSTBP#[3..0] H_D#[63..0] H_DINV#[3..0] H_DSTBN#[3..0] H_DSTBP#[3..0] H_D#[63..0] 10 10 10 10
2 56R2J-4-GP H_INIT# 20
H_LOCK# 10 H_CPURST# 10 H_RS#[2..0] 10
H_TRDY# H_HIT# H_HITM#
10 10 10 CPU1B 2 OF 4 H_THERMDA C849 Do Not Stuff H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15
DY
THERMAL
PROCHOT# THRMDA THRMDC THERMTRIP# D21 A24 B25 C7
DY
2 Do Not Stuff 2 56R2J-4-GP
CPU_PROCHOT# +1.05V_VCCP H_THERMDA 39 H_THERMDC 39 H_THRMTRIP# 11,20,37,42
47 10 10 10 H_DSTBN#0 H_DSTBP#0 H_DINV#0
10 20 20 20 20 20 20 20
H_ADSTB#1 H_A20M# H_FERR# H_IGNNE# H_STPCLK# H_INTR H_NMI H_SMI# TP802 TP803 TP804 TP805 TP806 TP807 TP808 TP809 TP810 TP811 TP812 RSVD_CPU_1 RSVD_CPU_2 RSVD_CPU_3 RSVD_CPU_4 RSVD_CPU_5 RSVD_CPU_6 RSVD_CPU_7 RSVD_CPU_8 RSVD_CPU_9 RSVD_CPU_10 RSVD_CPU_11
H_THERMDA H_THERMDC
E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25 N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24 AD26 C23 D25 C24 AF26 AF1 A26 B22 B23 C21
D0# D1# D2# D3# D4# D5# D6# D7# D8# D9# D10# D11# D12# D13# D14# D15# DSTBN0# DSTBP0# DINV0# D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# DSTBN1# DSTBP1# DINV1# GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 BSEL0 BSEL1 BSEL2
D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# DSTBN2# DSTBP2# DINV2# D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63# DSTBN3# DSTBP3# DINV3# COMP0 COMP1 COMP2 COMP3 DPRSTP# DPSLP# DPW R# PW RGOOD SLP# PSI#
Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W 22 Y23 W 24 W 25 AA23 AA24 AB25 Y26 AA26 U22 AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20 R26 U26 AA1 Y1 E5 B5 D24 D6 D7 AE6
H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_DSTBN#2 10 H_DSTBP#2 10 H_DINV#2 10 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DSTBN#3 10 H_DSTBP#3 10 H_DINV#3 10 COMP0 COMP1 COMP2 COMP3 R807 R809 R811 R814
DATA GRP0
R805 1
DY
2 Do Not Stuff
+1.05V_VCCP CLK_CPU_BCLK 7 CLK_CPU_BCLK# 7
HCLK
M4 N5 T2 V3 B2 C3 D2 D22 D3 F6 B1
RSVD#M4 RSVD#N5 RSVD#T2 RSVD#V3 RSVD#B2 RSVD#C3 TEST7 RSVD#D2 RSVD#D22 RSVD#D3 RSVD#F6
RESERVED
+1.05V_VCCP
R806 1KR2F-3-GP
DATA GRP3
BCLK0 BCLK1
A22 A21
H_THRMTRIP# should connect to ICH9 and MCH without T-ing.
H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_DSTBN#1 H_DSTBP#1 H_DINV#1 R808 1 R810 1 R813 1 R815 1
KEY_NC
BGA479-SKT6-GPU7
62.10079.001
R812 2KR2F-3-GP
ICH ICH
DATA GRP1
10 10 10 CPU_GTLREF0 C801 SC1KP50V2KX-1GP
DY DY DY DY
2 Do Not Stuff 2 Do Not Stuff 2 Do Not Stuff 2 Do Not Stuff
TEST1 TEST2 CPU_TEST3 CPU_TEST5
MISC
1 1 1 1
2 2 2 2
27D4R2F-L1-GP 54D9R2F-L1-GP 27D4R2F-L1-GP 54D9R2F-L1-GP
+1.05V_VCCP
7 7 7
CPU_BSEL0 CPU_BSEL1 CPU_BSEL2
H_DPRSTP# 11,20,47 H_DPSLP# 20 H_DPWR# 10 H_PWRGOOD 20,42 H_CPUSLP# 10 PSI# 47
ITP_TMS ITP_TDI ITP_BPM#5 ITP_TDO
R816 1 R817 1 R818 1 R801 1
2 51R2F-2-GP 2 51R2F-2-GP 2 51R2F-2-GP
Layout notes Z= 55 Ohm 0.5" MAX for CPU_GTLREF0
BGA479-SKT6-GPU7
62.10079.001
DY
2 Do Not Stuff
Layout Note: Comp0, 2 connect with Zo=27.4 ohm, make trace length shorter than 0.5". Comp1, 3 connect with Zo=55 ohm, make trace length shorter than 0.5".
DJ1
A
+3.3V_RUN
A
ITP_DBRESET#
R825 1
DY
2 Do Not Stuff
TP813 ITP_TCK ITP_TRST# R819 1 R820 1
2 51R2F-2-GP 2 51R2F-2-GP
H_CPURST#
Wistron Corporation
All place within 2" to CPU
CPU-FSB(1/2)
Sheet
1
Rev
DJ1 Montevina UMA

8 of 88
A00
SSID = CPU
+VCC_CORE C907 SC22U6D3V5MX-2GP C909 SC22U6D3V5MX-2GP C902 Do Not Stuff C901 Do Not Stuff C920 Do Not Stuff C903 Do Not Stuff C904 Do Not Stuff C905 Do Not Stuff C906 Do Not Stuff C908 Do Not Stuff CPU1D 4 OF 4
DY
+VCC_CORE +VCC_CORE
DY
DY
DY
DY
DY
DY
DY
C910 SC10U6D3V5KX-1GP
CPU1C3 OF 4
+VCC_CORE
A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
SCD1U10V2KX-5GP
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCA VCCA VID0 VID1 VID2 VID3 VID4 VID5 VID6 VCCSENSE VSSSENSE
AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20 G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W 21 B26 C26 AD6 AF5 AE5 AF4 AE3 AF3 AE2 AF7 AE7
CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6 CPU_VID[6..0]
+VCC_CORE C923 SC22U6D3V5MX-2GP C926 SC22U6D3V5MX-2GP C927 SC22U6D3V5MX-2GP C930 SC22U6D3V5MX-2GP C931 SC22U6D3V5MX-2GP C924 SC10U6D3V5KX-1GP C928 SC10U6D3V5KX-1GP C925 Do Not Stuff C929 Do Not Stuff
DY
DY
C932 SC22U6D3V5MX-2GP
DY
DY
DY
DY
DY
DY
+1.05V_VCCP C934 SCD1U16V2KX-3GP C935 SCD1U10V2KX-5GP C936 SCD1U16V2KX-3GP C938 SCD1U10V2KX-5GP C937 SC1U6D3V2KX-GP TC901 Do Not Stuff
DY
2
layout note: "+1.5V_VCCA" as short as possible
+1.5V_VCCA
+1.5V_RUN
1 R901 2 Do Not Stuff

47
C939 SCD01U16V2KX-3GP PG902
Layout Note: Place as close as possible to the CPU VCCA pin.
1 R902 2 100R2F-L1-GP-U
2 Do Not Stuff
+VCC_CORE VCC_SENSE 47 VSS_SENSE 47
VCC_SENSE and VSS_SENSE lines should be of equal length.
BGA479-SKT6-GPU7
PG901
A4 A8 A11 A14 A16 A19 A23 AF2 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
62.10079.001
1 R903 2 100R2F-L1-GP-U
2 Do Not Stuff
BGA479-SKT6-GPU7
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W 23 W 26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25
C911 Do Not Stuff
C912 Do Not Stuff
C913 Do Not Stuff
C914 Do Not Stuff
C916 Do Not Stuff
C922 Do Not Stuff
C933
NCTF PIN
CPU_GND1 TP902
B
CPU_GND2 CPU_GND3
TP901 TP903
CPU_GND4
TP904
62.10079.001
DJ1
Wistron Corporation
5 4 3 2
CPU-Power(2/2)
Sheet
1
Rev
DJ1 Montevina UMA

9 of 88
A00
SSID = MCH
NB1A 8 H_D#[63..0] H_D#[63..0] H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63
1 OF 10
H_A#[35..3]
+1.05V_VCCP
H_SWING routing Trace width and Spacing use 10 / 20 mil H_SWING Resistors and Capacitors close MCH 500 mil ( MAX )
1
R1002 221R2F-2-GP
H_SWING
C1002 SCD1U10V2KX-5GP
R1001 100R2F-L1-GP-U
H_RCOMP routing Trace width and Spacing use 10 / 20 mil

B
1 R1003
2 H_RCOMP 24D9R2F-L-GP
Place R1001 near to the chip ( < 0.5")
F2 G8 F8 E6 G2 H6 H2 F6 D4 H3 M9 M11 J1 J2 N12 J6 P2 L2 R2 N9 L6 M5 J3 N2 R1 N5 N6 P13 N8 L7 N10 M3 Y3 AD14 Y6 Y10 Y12 Y14 Y7 W2 AA8 Y9 AA13 AA9 AA11 AD11 AD10 AD13 AE12 AE9 AA2 AD8 AA3 AD3 AD7 AE14 AF3 AC1 AE3 AC3 AE11 AE8 AG2 AD6
H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63
H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35 H_ADS# H_ADSTB#_0 H_ADSTB#_1 H_BNR# H_BPRI# H_BREQ# H_DEFER# H_DBSY# HPLL_CLK HPLL_CLK# H_DPW R# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY#
A14 C15 F16 H13 C18 M16 J13 P16 R16 N17 M13 E17 P17 F17 G20 B19 J16 E20 H16 J20 L17 A17 B17 L16 C21 J17 H20 B18 K17 B20 F21 K21 L20 H12 B16 G17 A9 F11 G12 E9 B10 AH7 AH6 J11 F9 H9 E12 H11 C9
H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35
H_A#[35..3]
H_ADS# 8 H_ADSTB#0 8 H_ADSTB#1 8 H_BNR# 8 H_BPRI# 8 H_BREQ#0 8 H_DEFER# 8 H_DBSY# 8 CLK_MCH_BCLK 7 CLK_MCH_BCLK# 7 H_DPWR# 8 H_DRDY# 8 H_HIT# 8 H_HITM# 8 H_LOCK# 8 H_TRDY# 8
HOST
H_DINV#[3..0]
H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3 H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3 H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3 H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4 H_RS#_0 H_RS#_1 H_RS#_2
J8 L3 Y13 Y1 L10 M7 AA5 AE6 L9 M8 AA6 AE5 B15 K13 F13 B13 B14 B6 F12 C8
H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 H_DSTBN#[3..0] H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#[3..0] H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 H_REQ#[4..0] H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_RS#[2..0] H_RS#0 H_RS#1 H_RS#2
H_DINV#[3..0]
H_DSTBN#[3..0]
H_DSTBP#[3..0]
H_REQ#[4..0]
+1.05V_VCCP
H_SWING H_RCOMP H_CPURST# H_CPUSLP#
C5 E3 C12 E11 A11 B11
H_SW ING H_RCOMP H_CPURST# H_CPUSLP# H_AVREF H_DVREF

CANTIGA-GM-GP-U-NF
2
8 R1004 8 1KR2F-3-GP
H_RS#[2..0]
H_AVREF
R1005 2KR2F-3-GP
1 2
DY
C1001 Do Not Stuff
DJ1
Wistron Corporation
5 4 3 2
Cantiga-Host(1/6)
Sheet
1
Rev
DJ1 Montevina UMA

10 of 88
A00
+1.5V_SUS
SSID = MCH *
D
NB1B
2 OF 10
DDR CLK/ CONTROL/COMPENSATION
is current setting CFG Strap CFG 5 CFG 6 CFG 7 CFG 9 CFG 10 CFG 12 CFG 13 CFG 16 Low DMI X 2 ITPM enable TLS cipher suite with no confidentiality PCIE GFX lane reversed PCIE loopback enable ALLZ mode enable XOR mode enable
FSB dynamic ODT disable
High
C1105 Do Not Stuff
C1106 Do Not Stuff
CFG 19 DMI Lane Reserved CFG 20 SDVO concurrent with PCIE SDVO_CTRLDATA L_DDC_DATA DDPC_CTRLDATA
C
* ITPM disable * TLS cipher suite with * confidentiality PCIE GFX lane numbered in oder * PCIE loopback disable * ALLZ mode disable * XOR mode disable * FSB Dynamic ODT enable *
DMI X 4
C1104 SC2D2U6D3V3KX-GP
B31 B2 M1 AY21
SA_CKE_0 SA_CKE_1 SB_CKE_0 SB_CKE_1 SA_CS#_0 SA_CS#_1 SB_CS#_0 SB_CS#_1 SA_ODT_0 SA_ODT_1 SB_ODT_0 SB_ODT_1 SM_RCOMP SM_RCOMP# SM_RCOMP_VOH SM_RCOMP_VOL SM_VREF SM_PWROK SM_REXT SM_DRAMRST#
BC28 AY28 AY36 BB36 BA17 AY16 AV16 AR13 BD17 AY17 BF15 AY13 BG22 BH21 BF28 BH28 AV42 AR36 BF17 BC36 B38 A38 E41 F41 F43 E43
M_RCOMPP M_RCOMPN SM_RCOMP_VOH SM_RCOMP_VOL CANTIGA_SM_VREF SM_PW ROK SM_REXT DDR3_DRAMRST# CLK_MCH_DREFCLK CLK_MCH_DREFCLK# MCH_SSCDREFCLK MCH_SSCDREFCLK# CLK_MCH_3GPLL CLK_MCH_3GPLL#
M_CKE0 M_CKE1 M_CKE2 M_CKE3 M_CS#0 M_CS#1 M_CS#2 M_CS#3 M_ODT0 M_ODT1 M_ODT2 M_ODT3
18 18 19 19 18 18 19 19 18 18 19 19
R1104 3K01R2F-3-GP
RESERVED#B31 RESERVED#B2 RESERVED#M1 RESERVED#AY21
R1105 80D6R2F-L-GP
SM_RCOMP_VOL
M36 N36 R33 T33 AH9 AH10 AH12 AH13 K12 AL34 AK34 AN35 AM35 T24
RESERVED#M36 RESERVED#N36 RESERVED#R33 RESERVED#T33 RESERVED#AH9 RESERVED#AH10 RESERVED#AH12 RESERVED#AH13 RESERVED#K12 RESERVED#AL34 RESERVED#AK34 RESERVED#AN35 RESERVED#AM35 RESERVED#T24
SA_CK_0 SA_CK_1 SB_CK_0 SB_CK_1 SA_CK#_0 SA_CK#_1 SB_CK#_0 SB_CK#_1
AP24 AT21 AV24 AU20 AR24 AR21 AU24 AV20
M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR2 M_CLK_DDR3 M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3
18 18 19 19 18 18 19 19
2
+1.5V_SUS R1102 1KR2F-3-GP
R1103 80D6R2F-L-GP
SM_RCOMP_VOH
Normal operation Only PCIE or SDVO is operational
* Reverse DMI lanes PCIE and SDVO are * operatiing simultaneously via the PEG port * * *
SDVO interface enable LFP card present SDVO/iHDMI/DP interface enabled
BG23 BF23 BH18 BF18
RESERVED#BG23 RESERVED#BF23 RESERVED#BH18 RESERVED#BF18
+V_DDR_REF
DDR3_DRAMRST# SM_PW ROK 41
18,19 R1108
1 1 2 R1109 499R2F-2-GP
Do Not Stuff
SDVO interface disable LFP disable SDVO/iHDMI/DP interface disabled
DPLL_REF_CLK DPLL_REF_CLK# DPLL_REF_SSCLK DPLL_REF_SSCLK# PEG_CLK PEG_CLK#
CLK_MCH_DREFCLK 7 CLK_MCH_DREFCLK# 7 MCH_SSCDREFCLK 7 MCH_SSCDREFCLK# 7 CLK_MCH_3GPLL 7 CLK_MCH_3GPLL# 7
DY
2
DY
2
+3.3V_RUN
CLK
RSVD RSVD
R1106 1KR2F-3-GP
R1112 1 R1113 1
DY DY
RN1102
2 Do Not Stuff 2 Do Not Stuff 1 2
CFG19 CFG20
FSB setting
7 7 7 MCH_CLKSEL0 MCH_CLKSEL1 MCH_CLKSEL2 TP1102 TP1103
DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3 T25 R25 P25 P20 P24 C25 N24 M24 E21 C23 C24 N21 P21 T21 R20 M20 L21 H21 P29 R28 T28 CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20 DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3
AE41 AE37 AE47 AH39 AE40 AE38 AE48 AH40 AE35 AE43 AE46 AH42 AD35 AE44 AF46 AH43
DMI_ITXN0_MRXN0 DMI_ITXN1_MRXN1 DMI_ITXN2_MRXN2 DMI_ITXN3_MRXN3 DMI_ITXP0_MRXP0 DMI_ITXP1_MRXP1 DMI_ITXP2_MRXP2 DMI_ITXP3_MRXP3 DMI_IRXN0_MTXN0 DMI_IRXN1_MTXN1 DMI_IRXN2_MTXN2 DMI_IRXN3_MTXN3 DMI_IRXP0_MTXP0 DMI_IRXP1_MTXP1 DMI_IRXP2_MTXP2 DMI_IRXP3_MTXP3
DMI_ITXN0_MRXN0 DMI_ITXN1_MRXN1 DMI_ITXN2_MRXN2 DMI_ITXN3_MRXN3 DMI_ITXP0_MRXP0 DMI_ITXP1_MRXP1 DMI_ITXP2_MRXP2 DMI_ITXP3_MRXP3 DMI_IRXN0_MTXN0 DMI_IRXN1_MTXN1 DMI_IRXN2_MTXN2 DMI_IRXN3_MTXN3 DMI_IRXP0_MTXP0 DMI_IRXP1_MTXP1 DMI_IRXP2_MTXP2 DMI_IRXP3_MTXP3
21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21
4 3
PM_EXTTS#0 PM_EXTTS#1
DMI CFG
CFG3 CFG4
SRN10KJ-5-GP CFG9 CFG10
DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3 DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3
+1.05V_VCCP
+3.3V_RUN
TP1104 TP1105 TP1101 R1118 1

B
R1119 1
DY DY
2 Do Not Stuff 2 Do Not Stuff
CFG9 CFG10 CFG19 CFG20
GRAPHICS VID
CFG14 CFG15 CFG16 CFG17
R1122 56R2J-4-GP
DY
2
R1123 Do Not Stuff

B
22,37 PM_PW ROK 21,37,58,76 PLT_RST#
PW ROK_R RSTIN#
GFX_VR_EN
C34
+1.05V_VCCP
DY
ME
8,20,37,42
H_THRMTRIP#
22,47 DPRSLPVR
BG48 BF48 BD48 BC48 BH47 BG47 BE47 BH46 BF46 BG45 BH44 BH43 BH6 BH5 BG4 BH3 BF3 BH2 BG2 BE2 BG1 BF1 BD1 BC1 F1 A47
NC#BG48 NC#BF48 NC#BD48 NC#BC48 NC#BH47 NC#BG47 NC#BE47 NC#BH46 NC#BF46 NC#BG45 NC#BH44 NC#BH43 NC#BH6 NC#BH5 NC#BG4 NC#BH3 NC#BF3 NC#BH2 NC#BG2 NC#BE2 NC#BG1 NC#BF1 NC#BD1 NC#BC1 NC#F1 NC#A47 CANTIGA-GM-GP-U-NF
CL_CLK CL_DATA CL_PWROK CL_RST# CL_VREF
AH37 AH36 AN36 AJ35 AH34
MCH_CLVREF
CL_CLK0 22 CL_DATA0 22 M_PW ROK 22 CL_RST#0 22
R1126 1KR2F-3-GP
+3.3V_RUN R1129 CLKREQ#_B
MCH_CLVREF ~= 0.35V
DDPC_CTRLCLK DDPC_CTRLDATA SDVO_CTRLCLK SDVO_CTRLDATA CLKREQ# ICH_SYNC# TSATN# N28 M28 G36 E36 K36 H36 B12
10KR2J-3-GP R1128 499R2F-2-GP
MISC
GMCH_HDMI_DATA
TP1106 CLKREQ#_B 7 MCH_ICH_SYNC# 22
TSATN#
A
DJ1
HDA
HDA_BCLK HDA_RST# HDA_SDI HDA_SDO HDA_SYNC
B28 B30 B29 C29 A28

Title Size Document Number Custom Date:
R1124 1
DY
2 Do Not Stuff
CFG16
22 PM_SYNC# 8,20,47 H_DPRSTP# 18 PM_EXTTS#0 19 PM_EXTTS#1 1 R1125 2 Do Not Stuff 1 2 100R2J-2-GP R1127 C1107 Do Not Stuff
R29 B7 N33 P32 AT40 AT11 T20 R32
PM_SYNC# PM_DPRSTP# PM_EXT_TS#_0 PM_EXT_TS#_1 PWROK RSTIN# THERMTRIP# DPRSLPVR
GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4
B33 B32 G33 F33 E33
TSATN#_KBC TSATN#
TSATN#_KBC 37
C B
DY
Q1101 Do Not Stuff
PM NC NC
Wistron Corporation
Cantiga-DMI/CFG(2/6)
DJ1 Montevina UMA
Sheet
1
Rev
A00
of 88
11
SSID = MCH
18 M_A_DQ[63..0]
M_A_DQ[63..0] M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63
NB1D
4 OF 10
AJ38 AJ41 AN38 AM38 AJ36 AJ40 AM44 AM42 AN43 AN44 AU40 AT38 AN41 AN39 AU44 AU42 AV39 AY44 BA40 BD43 AV41 AY43 BB41 BC40 AY37 BD38 AV37 AT36 AY38 BB38 AV36 AW 36 BD13 AU11 BC11 BA12 AU13 AV13 BD12 BC12 BB9 BA9 AU10 AV9 BA11 BD9 AY8 BA6 AV5 AV7 AT9 AN8 AU5 AU6 AT5 AN10 AM11 AM5 AJ9 AJ8 AN12 AM13 AJ11 AJ12
SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63
SA_BS_0 SA_BS_1 SA_BS_2 SA_RAS# SA_CAS# SA_W E#
BD21 BG18 AT25 BB20 BD20 AY20
19 M_B_DQ[63..0] M_A_BS0 18 M_A_BS1 18 M_A_BS2 18 M_A_RAS# 18 M_A_CAS# 18 M_A_WE# 18
M_B_DQ[63..0] M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63
NB1E
5 OF 10
M_A_DM[7..0]
M_A_DQS[7..0] M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7 M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14
SYSTEM
DDR
DDR
SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14
BA21 BC24 BG24 BH24 BG25 BA24 BD24 BG27 BF25 AW 24 BC21 BG26 BH26 BH17 AY25
M_A_A[14..0]
18
SYSTEM
SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7
AJ44 AT44 BA43 BC37 AW 12 BC8 AU8 AM7 AJ43 AT43 BA44 BD37 AY12 BD8 AU9 AM8
M_A_DQS[7..0]
18
SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7
AM37 AT41 AY41 AU39 BB12 AY6 AT7 AJ5
M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7
M_A_DM[7..0]
18
M_A_DQS#[7..0]
M_A_DQS#[7..0]
18
M_A_A[14..0]
AK47 AH46 AP47 AP46 AJ46 AJ48 AM48 AP48 AU47 AU46 BA48 AY48 AT47 AR47 BA47 BC47 BC46 BC44 BG43 BF43 BE45 BC41 BF40 BF41 BG38 BF38 BH35 BG35 BH40 BG39 BG34 BH34 BH14 BG12 BH11 BG8 BH12 BF11 BF8 BG7 BC5 BC6 AY3 AY1 BF6 BF5 BA1 BD3 AV2 AU3 AR3 AN2 AY2 AV1 AP3 AR1 AL1 AL2 AJ1 AH1 AM2 AM3 AH3 AJ3
SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63
SB_BS_0 SB_BS_1 SB_BS_2 SB_RAS# SB_CAS# SB_W E#
BC16 BB17 BB33 AU17 BG16 BF14
M_B_BS0 19 M_B_BS1 19 M_B_BS2 19 M_B_RAS# 19 M_B_CAS# 19 M_B_WE# 19
M_B_DM[7..0]
SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7 SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7 SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14
AM47 AY47 BD40 BF35 BG11 BA3 AP1 AK2 AL47 AV48 BG41 BG37 BH9 BB2 AU1 AN6 AL46 AV47 BH41 BH37 BG9 BC2 AT2 AN5 AV17 BA25 BC25 AU25 AW 25 BB28 AU28 AW 28 AT33 BD33 BB16 AW 33 AY33 BH15 AU33
M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7 M_B_DQS[7..0] M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7 M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14
M_B_DM[7..0]
19
M_B_DQS[7..0]
19
MEMORY
MEMORY
M_B_DQS#[7..0]
M_B_DQS#[7..0]
19
C
M_B_A[14..0]
M_B_A[14..0]
19
CANTIGA-GM-GP-U-NF
CANTIGA-GM-GP-U-NF
DJ1
Wistron Corporation
5 4 3 2
Cantiga-DDR(3/6)
Sheet
1
Rev
DJ1 Montevina UMA

12 of 88
A00
SSID = MCH
NB1I AU48 AR48 AL48 BB47 AW47 AN47 AJ47 AF47 AD47 AB47 Y47 T47 N47 L47 G47 BD46 BA46 AY46 AV46 AR46 AM46 V46 R46 P46 H46 F46 BF44 AH44 AD44 AA44 Y44 U44 T44 M44 F44 BC43 AV43 AU43 AM43 J43 C43 BG42 AY42 AT42 AN42 AJ42 AE42 N42 L42 BD41 AU41 AM41 AH41 AD41 AA41 Y41 U41 T41 M41 G41 B41 BG40 BB40 AV40 AN40 H40 E40 AT39 AM39 AJ39 AE39 N39 L39 B39 BH38 BC38 BA38 AU38 AH38 AD38 AA38 Y38 U38 T38 J38 F38 C38 BF37 BB37 AW37 AT37 AN37 AJ37 H37 C37 BG36 BD36 AK15 AU36 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 9 OF 10 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS AM36 AE36 P36 L36 J36 F36 B36 AH35 AA35 Y35 U35 T35 BF34 AM34 AJ34 AF34 AE34 W34 B34 A34 BG33 BC33 BA33 AV33 AR33 AL33 AH33 AB33 P33 L33 H33 N32 K32 F32 C32 A31 AN29 T29 N29 K29 H29 F29 A29 BG28 BD28 BA28 AV28 AT28 AR28 AJ28 AG28 AE28 AB28 Y28 P28 K28 H28 F28 C28 BF26 AH26 AF26 AB26 AA26 C26 B26 BH25 BD25 BB25 AV25 AR25 AJ25 AC25 Y25 N25 L25 J25 G25 E25 BF24 AD12 AY24 AT24 AJ24 AH24 AF24 AB24 R24 L24 K24 J24 G24 F24 E24 BH23 AG23 Y23 B23 A23 AJ6 BG21 L12 AW21 AU21 AP21 AN21 AH21 AF21 AB21 R21 M21 J21 G21 BC20 BA20 AW20 AT20 AJ20 AG20 Y20 N20 K20 F20 C20 A20 BG19 A18 BG17 BC17 AW17 AT17 R17 M17 H17 C17 BA16 AU16 AN16 N16 K16 G16 E16 BG15 AC15 W15 A15 BG14 AA14 C14 BG13 BC13 BA13 AN13 AJ13 AE13 N13 L13 G13 E13 BF12 AV12 AT12 AM12 AA12 J12 A12 BD11 BB11 AY11 AN11 AH11 Y11 N11 G11 C11 BG10 AV10 AT10 AJ10 AE10 AA10 M10 BF9 BC9 AN9 AM9 AD9 G9 B9 BH8 BB8 AV8 AT8 NB1J VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 10 OF 10 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS AH8 Y8 L8 E8 B8 AY7 AU7 AN7 AJ7 AE7 AA7 N7 J7 BG6 BD6 AV6 AT6 AM6 M6 C6 BA5 AH5 AD5 Y5 L5 J5 H5 F5 BE4 BC3 AV3 AL3 R3 P3 F3 BA2 AW2 AU2 AR2 AP2 AJ2 AH2 AF2 AE2 AD2 AC2 Y2 M2 K2 AM1 AA1 P1 H1 U24 U28 U25 U29 AF32 AB32 V32 AJ30 AM29 AF29 AB29 U26 U23 AL20 V20 AC19 AL17 AJ17 AA17 U17 BH48 BH1 A48 C1 A3 E1 D2 C3 B4 A5 A6 A43 A44 B45 C46 D47 B47 A46 F48 E48 C48 B48 GMCH_GND1 GMCH_GND2 GMCH_GND3 GMCH_GND4 +1.05V_VCCP 2 54 LBKLT_CTL 37 GMCH_BL_ON RN1302 +3.3V_RUN +3.3V_RUN RN1301 1 2 4 3 SRN2K2J-1-GP LDDC_CLK LDDC_DATA 54 54 4 3 1 2 SRN10KJ-5-GP LDDC_CLK LDDC_DATA L_CTRL_CLK L_CTRL_DATA L32 G32 M32 M33 K33 J33 M29 C44 B43 E37 E38 C41 C40 B37 A37 H47 E46 G40 A40 H48 D45 F40 B40 A41 H38 G37 J37 B42 G38 F37 K37 NB1C 3 OF 10 R1303 49D9R2F-GP 1
L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK L_CTRL_DATA L_DDC_CLK L_DDC_DATA L_VDD_EN LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2 LVDSA_DATA#_3 LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2 LVDSA_DATA_3 LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2 LVDSB_DATA#_3 LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2 LVDSB_DATA_3
Place R1303 close to MCH within 500 mils.
PEG_COMPI PEG_COMPO PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15 PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8 PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15 PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9 PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15 PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8 PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15
T37 T36 H44 J46 L44 L40 N41 P48 N44 T43 U43 Y43 Y48 Y36 AA43 AD37 AC47 AD39 H43 J44 L43 L41 N40 P47 N43 T42 U42 Y42 W47 Y37 AA42 AD36 AC48 AD40 J41 M46 M47 M40 M42 R48 N38 T40 U37 U40 Y40 AA46 AA37 AA40 AD43 AC46 J42 L46 M48 M39 M43 R47 N37 T39 U36 U39 Y39 Y46 AA36 AA39 AD42 AD46
PEG_CMP
54 LCDVDD_EN 2 R1302 1 2K37R2F-GPTP1302
LIBG LVDS_VBG 1 Do Not Stuff
54 VGA_TXACLK54 VGA_TXACLK+
LVDS
54 VGA_TXAOUT054 VGA_TXAOUT154 VGA_TXAOUT254 VGA_TXAOUT0+ 54 VGA_TXAOUT1+ 54 VGA_TXAOUT2+
VSS
VSS
R1301 1 R1305 1 R1306 1
2 75R2F-2-GP 2 75R2F-2-GP 2 75R2F-2-GP
TV_DACA TV_DACB TV_DACC
F25 H25 K25 H24
TVA_DAC TVB_DAC TVC_DAC TV_RTN
PCI-EXPRESS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_SCB VSS_SCB VSS_SCB VSS_SCB VSS_SCB NC#E1 NC#D2 NC#C3 NC#B4 NC#A5 NC#A6 NC#A43 NC#A44 NC#B45 NC#C46 NC#D47 NC#B47 NC#A46 NC#F48 NC#E48 NC#C48 NC#B48
GRAPHICS
TV
C31 E32
TV_DCONSEL_0 TV_DCONSEL_1
55 55 55
M_BLUE M_GREEN M_RED
M_BLUE M_GREEN M_RED 1 R1307 1 R1308 1 R1309 2 150R2F-1-GP 2 150R2F-1-GP
E28 G28 J28 2 150R2F-1-GP G29 H32 J32 J29 E29 L29
CRT_BLUE CRT_GREEN CRT_RED
VSS NCTF
VGA
CRT_IRTN CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF CRT_VSYNC
CRT_IREF routing Trace width use 20 mil.
55 GMCH_HSYNC 55 GMCH_VSYNC
33R2J-2-GP 1 R1310 1K02R2F-1-GP1 R1311 33R2J-2-GP 1 R1312
2 2 2
GMCH_DDCCLK GMCH_DDCDATA GMCH_HS CRT_IREF GMCH_VS
VSS SCB
TP1303 TP1304 TP1301 TP1305
NCTF PIN
CANTIGA-GM-GP-U-NF
+3.3V_RUN RN1303 3 4 +3.3V_RUN SRN2K2J-1-GP 2 1
NC
U1301 GMCH_DDCDATA 4 5 55 DDC_CLK_CON DDC_CLK_CON 6 3 2 1 2N7002EDW-GP GMCH_DDCCLK DDC_DATA_CON DDC_DATA_CON 55
CANTIGA-GM-GP-U-NF CANTIGA-GM-GP-U-NF
DJ1
Wistron Corporation
5 4 3 2
Cantiga-GND/LVDS/VGA(4/6)
DJ1 Montevina UMA
Sheet
1
Rev
A00
of 88
13
SSID = MCH
NB1F +1.05V_VCCP C1427 SC10U6D3V5KX-1GP +1.05V_VCCP +1.5V_SUS NB1G 7 OF 10 6 OF 10
Close to (G)MCH
POWER
On the edge
AP33 AN33 BH32 BG32 BF32 BD32 BC32 BB32 BA32 AY32 AW 32 AV32 AU32 AT32 AR32 AP32 AN32 BH31 BG31 BF31 BG30 BH29 BG29 BF29 BD29 BC29 BB29 BA29 AY29 AW 29 AV29 AU29 AT29 AR29 AP29 BA36 BB24 BD16 BB21 AW 16 AW 13 AT13
VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM
VCC GFX NCTF
+1.05V_VCCP
VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC
VCC SM LF
Y26 AE25 AB25 AA25 AE24 AC24 AA24 Y24 AE23 AC23 AB23 AA23 AJ21 AG21 AE21 AC21 AA21 Y21 AH20 AF20 AE20 AC20 AB20 AA20 T17 T16 AM15 AL15 AE15 AJ15 AH15 AG15 AF15 AB15 AA15 Y15 V15 U15 AN14 AM14 U14 T14
VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG
+1.05V_VCCP +1.05V_VCCP +1.05V_VCCP +1.05V_VCCP +1.05V_VCCP
VCCA_MPLL VCCD_HPLL VCCA_PEG_PLL VCCD_PEG_PLL VCC_AXF VCCD_TVDAC VCC_SM VCC_SM_CK VCCA_PEG_BG VCC_HV
139.2mA 157.2mA 50mA 50mA 321.35mA 35mA 3000mA 124mA 414uA 105.3mA
VCC NCTF
VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF
W 28 V28 W 26 V26 W 25 V25 W 24 V24 W 23 V23 AM21 AL21 AK21 W 21 V21 U21 AM20 AK20 W 20 U20 AM19 AL19 AK19 AJ19 AH19 AG19 AF19 AE19 AB19 AA19 Y19 W 19 V19 U19 AM17 AK17 AH17 AG17 AF17 AE17 AC17 AB17 Y17 W 17 V17 AM16 AL16 AK16 AJ16 AH16 AG16 AF16 AE16 AC16 AB16 AA16 Y16 W 16 V16 U16
SC1U6D3V2KX-GP C1408 2 1
AG34 AC34 AB34 AA34 Y34 V34 U34 AM33 AK33 AJ33 AG33 AF33 AE33 AC33 AA33 Y33 W 33 V33 U33 AH28 AF28 AC28 AA28 AJ26 AG26 AE26 AC26 AH25 AG25 AF25 AG24 AJ23 AH23 AF23 T32
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
C1405 SC1U6D3V2KX-GP
3060mA
POWER
Coupling CAP
1
C1414 SCD1U10V2KX-5GP C1412 SC10U6D3V5KX-1GP C1411 SCD1U10V2KX-5GP
DY
2
Coupling CAP
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
C1413 SC1U10V3KX-3GP
TC1401 Do Not Stuff
VCC SM
VCC CORE
3000mA
SC22U6D3V5MX-2GP C1415
SC22U6D3V5MX-2GP C1416
+1.05V_VCCP
Supply +1.05V_VCCP +1.05V_VCCP +1.05V_VCCP +1.05V_VCCP +1.05V_VCCP +1.05V_VCCP +1.05V_VCCP
Signal Group VCC VTT VCC_PEG VCC_DMI VCCA_SM VCCA_SM_CK VCCA_HPLL
Imax 3060mA 852mA 1782mA 456mA 720mA 26mA 24mA
+1.5V_RUN +1.8V_SUS +1.8V_SUS +1.5V_RUN +3.3V_RUN
VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF
AM32 AL32 AK32 AJ32 AH32 AG32 AE32 AC32 AA32 Y32 W 32 U32 AM30 AL30 AK30 AH30 AG30 AF30 AE30 AC30 AB30 AA30 Y30 W 30 V30 U30 AL29 AK29 AJ29 AH29 AG29 AE29 AC29 AA29 Y29 W 29 V29 AL28 AK28 AL26 AK26 AK25 AK24 AK23
C1429 SCD1U16V2KX-3GP 2 1
C1428 SC4D7U6D3V5KX-3GP 2 1
VCC GFX
C1420 SCD47U6D3V2KX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C1417 2 1
C1418 2 1
8700mA
VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF AV44 SM_LF1_GMCH BA37 SM_LF2_GMCH AM40 SM_LF3_GMCH AV21 SM_LF4_GMCH AY5 SM_LF5_GMCH AM10 SM_LF6_GMCH BB13 SM_LF7_GMCH
1 2
CANTIGA-GM-GP-U-NF
DJ1
TP1401 TP1402
VCC_AXG_SENSE VSS_AXG_SENSE
AJ14 AH14
VCC_AXG_SENSE VSS_AXG_SENSE
Wistron Corporation
CANTIGA-GM-GP-U-NF
Cantiga-Power(5/6)
DJ1 Montevina UMA
Sheet
1
Rev
A00
of 88
14
+1.05V_VCCP R1502 C1502 SCD1U16V2KX-3GP C1503 SCD1U16V2KX-3GP
SSID = MCH
2 1
M_VCCA_DPLLA
Do Not Stuff
DY
2
C1504 Do Not Stuff
+3.3V_CRT_LDO
R1503
2 1
Do Not Stuff
3D3V_CRTDAC_S0
+1.05V_VCCP NB1H 8 OF 10 C1508 SC1U10V3KX-3GP C1509 SC1U10V3KX-3GP C1510 SC1U10V3KX-3GP C1507 SCD1U16V2KX-3GP EC1501 SC1U10V3KX-3GP TC1501 Do Not Stuff
1
R1504 C1511 SCD1U16V2KX-3GP C1512 SCD1U16V2KX-3GP
2 1
Do Not Stuff
M_VCCA_DPLLB
+3.3V_CRT_LDO C1513 Do Not Stuff
DY
2
R1505
VCCA_DAC_BG VSSA_DAC_BG
CRT
2 1
Do Not Stuff
M_VCCA_DAC_BG
B27 A26 A25 B25
VCCA_CRT_DAC VCCA_CRT_DAC
SC1U6D3V2KX-GP 1 2
852mA
M_VCCA_DPLLB M_VCCA_HPLL M_VCCA_MPLL
L48 AD1 AE1 J48 J47
VCCA_DPLLB
C1517 SCD1U10V2KX-5GP +1.5V_RUN R1508
VSSA_LVDS
A LVDS
120ohm 100MHz
L1502 1 2 BLM18PG121SN1D-GP
VCCA_MPLL 139.2mA VCCA_LVDS 13.2mA
PLL
VCCA_HPLL 24mA
M_VCCA_HPLL
G9091-180T11U-GP
C1518 SC1KP50V2KX-1GP
74.09091.G3F
2 1
Do Not Stuff C1519 SCD1U10V2KX-5GP
VCCA_PEG_BG
AD48
VCCA_PEG_BG
R1509 1D05V_VCC_AXF C1522 SC1U10V3KX-3GP
+1.05V_VCCP
414uA
A PEG
Do Not Stuff 2 1
L1501 1 2 BLM18PG121SN1D-GP
1 1
2
C
C1521
DY
SCD1U10V2KX-5GP
C1520
120ohm 100MHz
+1.05V_VCCP R1510 C1524 SC22U6D3V5MX-2GP
1D05V_RUN_PEGPLL 1D05V_SM C1525 SC4D7U6D3V3KX-GP C1526 SC1U10V3KX-3GP
AA48 AR20 AP20 AN20 AR17 AP17 AN17 AT16 AR16 AP16
VCCA_PEG_PLL 50mA VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM
M_VCCA_MPLL
Do Not Stuff
2
TC1502 Do Not Stuff C1501 Do Not Stuff Do Not Stuff
DY
DY
POWER
A SM
1D8V_VCC_SM_CK
DY C1523 Stuff Do Not
R1511
+1.5V_SUS
1 2
SCD1U10V2KX-5GP
2
Do Not Stuff
+1.05V_VCCP L1503 SC10U6D3V5KX-1GP 2 1
+1.05V_VCCP R1513 1D05V_RUN_PEGPLL
C1534 Do Not Stuff
2 1
Do Not Stuff
1D05V_SM_CK C1531 SCD1U10V2KX-5GP
1 1
1 2 BLM18BB221SN1D-GP
C1532 2 1
R1512 1R3F-GP C1535 SC10U6D3V3MX-GP
C1533
321.35mA
220ohm 100MHz
DY
C1537
L1504 C1540 SCD01U16V2KX-3GP
+1.5V_RUN
SM CK
Do Not Stuff
C1538 Do Not Stuff
124mA
R1515
1 1 2 1
PBY160808T-181Y-GP 1D5VRUN_QDAC
2
Do Not Stuff
VCC_SM_CK VCC_SM_CK VCC_SM_CK VCC_SM_CK
BF21 BH20 BG20 BF20
1D8V_TXLVDS_S3
+3.3V_CRT_LDO
+3.3V_TV_DAC
AP28 AN28 AP25 AN25 AN24 AM28 AM26 AM25 AL25 AM24 AL24 AM23 AL23
DY
2
DY
VCCA_SM_CK VCCA_SM_CK VCCA_SM_CK VCCA_SM_CK VCCA_SM_CK VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF
AXF
VCC_AXF VCC_AXF VCC_AXF
B22 B21 A21
A CK
R1514
+1.8V_NB_S0
2
Do Not Stuff +3.3V_RUN R1523 +3.3V_VCC_HV
B
2
Do Not Stuff +3.3V_VCC_HV
C1559 2 1
SCD1U10V2KX-5GP
+1.05V_VCCP
HDA
Do Not Stuff
VCC_HDA
A32
VCC_HDA 50mA
M25
1D5VRUN_QDAC 1D05V_RUN_HPLL 1D05V_RUN_PEGPLL
VCCD_TVDAC 35mA VCCD_QDAC 2mA VCCD_HPLL 157.2mA VCCD_PEG_PLL 50mA VCCD_LVDS VCCD_LVDS
D TV/CRT
+1.05V_VCCP +5V_RUN
R1520
L28 AF1 AA47 M38 L37
456mA
DMI
2
Do Not Stuff
VCC_DMI VCC_DMI VCC_DMI VCC_DMI
AH48 AF48 AH47 AG47

1D05V_VCC_DMI
VCC_PEG VCC_PEG VCC_PEG VCC_PEG VCC_PEG
PEG
1782mA
V48 U48 V47 U47 U46
R1501
+1.05V_VCCP
SCD1U10V2KX-5GP 2 1
C1548
U1502
VTTLF
LVDS
2
Do Not Stuff
R1521
+3.3V_CRT_LDO
1 2 3 4 5 1
EN GND VIN VOUT NC#5
60.31mA
VTTLF VTTLF VTTLF
A8 L1 AB2
VTTLF1 VTTLF2 VTTLF3
A
DJ1
+1.8V_NB_S0
CANTIGA-GM-GP-U-NF R1522 1
74.09091.H3F Second = 74.09198.07F Reserved for CRT ripple

5
C1554 G9091-330T12U-GP SC10U6D3V5KX-1GP
2
Do Not Stuff
1D8V_SUS_DLVDS
1 2
1 2
Wistron Corporation
1
2
Do Not Stuff
VCC_HDA
Cantiga-Power/Filter(6/6)
DJ1 Montevina UMA
Sheet
1
VCCD_TVDAC
R1516
105.3mA
TV
+1.5V_RUN
B24 A24
118.8mA VCC_TX_LVDS
VCC_HV VCC_HV VCC_HV
K47 C35 B35 A35
HV
VCCA_TV_DAC VCCA_TV_DAC
Rev
A00
of 88
15
C1558
1D8V_TXLVDS_S3
1 2 3 4 5
VIN GND EN NC#4 VOUT
SC1U6D3V2KX-GP 1 2
VTT
+1.05V_VCCP
C1515 SCD1U10V2KX-5GP M_VCCA_DPLLA
F47
VCCA_DPLLA
VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT
U13 T13 U12 T12 U11 T11 U10 T10 U9 T9 U8 T8 U7 T7 U6 T6 U5 T5 V3 U3 V2 U2 T2 V1 U1
DY
NB:180mA
+3.3V_RUN
I=300mA
U1501
+1.8V_NB_S0
C1557
64.8mA 37.5mA 79mA
720mA
(Blanking)
DJ1
Wistron Corporation
5 4 3 2
Document Number
Reserved
Sheet
1
Rev
DJ1 Montevina UMA

A00
(Blanking)
DJ1
Wistron Corporation
5 4 3 2
Document Number
Reserved
Sheet
1
Rev
DJ1 Montevina UMA

A00
M_A_DM[7..0] 12 M_A_DQS#[7..0] 12 M_A_DQS[7..0] 12 NP1 NP2 110 113 115 114 121 73 74 101 103 102 104 11 28 46 63 136 153 170 187 200 202 198 199 197 201 77 122 125 75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124 2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 205 206 SA0_DIM0 SA1_DIM0 C1801 SCD1U10V2KX-5GP +1.5V_SUS
C
DM1 M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15 98 97 96 95 92 91 90 86 89 85 107 84 83 119 80 78 79 109 108 M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7 M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 11 11 +0.75V_DDR_VTT
A
M_A_A[14..0] 12
TP1801 12 M_A_BS2
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2 BA0 BA1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7# DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 ODT0 ODT1 VREF_CA VREF_DQ RESET# VTT1 VTT2 DDR3-204P-41-GP-U 62.10017.N41
NP1 NP2 RAS# WE# CAS# CS0# CS1# CKE0 CKE1 CK0 CK0# CK1 CK1# DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 SDA SCL EVENT# VDDSPD SA0 SA1 NC#1 NC#2 NC#/TEST VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
M_A_RAS# 12 M_A_WE# 12 M_A_CAS# 12 M_CS#0 11 M_CS#1 11 M_CKE0 11 M_CKE1 11
SA0_DIM0 SA1_DIM0 1 1
Note: If SA0 DIM0 = 0, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA0 SO-DIMMA TS Address is 0x30
D
R1802 10KR2J-3-GP 2 2
R1803 10KR2J-3-GP
If SA0 DIM0 = 1, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA2 SO-DIMMA TS Address is 0x32
M_CLK_DDR0 11 M_CLK_DDR#0 11 M_CLK_DDR1 11 M_CLK_DDR#1 11 M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7 ICH_SMBDATA 7,19,22,76 ICH_SMBCLK 7,19,22,76 PM_EXTTS#0 11 +3.3V_RUN
12 M_A_BS0 12 M_A_BS1 12 M_A_DQ[63..0]
+V_DDR_REF 1
R1806 2 M_VREF_CA_DIMM0 1 1 C1812 SC2D2U6D3V3KX-GP
SCD1U10V2KX-5GP
Layout Note: Place these Caps near SO-DIMMA.
Do Not Stuff C1811
+V_DDR_REF
R1807 1 2 Do Not Stuff M_VREF_DQ_DIMM0 1 1 C1818 SC2D2U6D3V3KX-GP
5 7 15 17 4 6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194 10 27 45 62 135 152 169 186 12 29 47 64 137 154 171 188 116 120
DY
2 2
C1802 Do Not Stuff
SODIMM A DECOUPLING
+1.5V_SUS
DY
TC1801 C1803 Do Not Stuff C1813 SCD1U16V2KX-3GP SC10U10V5ZY-1GP
C1804 SC10U10V5ZY-1GP SC10U10V5ZY-1GP
C1805 SC10U10V5ZY-1GP
C1807 SC10U10V5ZY-1GP SC10U10V5ZY-1GP
C1815 C1815 SCD1U16V2KX-3GP SCD1U16V2KX-3GP
Place between DM1 and DM2.

+0.75V_DDR_VTT
C1824 Do Not Stuff
DY
M_ODT0 M_ODT1 M_VREF_CA_DIMM0 M_VREF_DQ_DIMM0
Place these caps close to VTT1 and VTT2.

1 1 1
126 1 30 203 204
11,19 DDR3_DRAMRST# +0.75V_DDR_VTT
DJ1
C1820 C1821 C1822 C1823 SC1U6D3V2KX-GP SC1U6D3V2KX-GP SC1U6D3V2KX-GP SC1U6D3V2KX-GP
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
H =5.2mm
DDR3-SODIMM1
Size Date:
5 4 3 2
Document Number
Rev
DJ1 Montevina UMA

1
A00
of 88
Sheet
18
DM2 M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15 98 97 96 95 92 91 90 86 89 85 107 84 83 119 80 78 79 109 108 M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7 2 Do Not Stuff M_VREF_DQ_DIMM1 C1914 SC2D2U6D3V3KX-GP M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 11 11 M_ODT2 M_ODT3 M_VREF_CA_DIMM1 M_VREF_DQ_DIMM1 +0.75V_DDR_VTT 11,18 DDR3_DRAMRST# 1 1 5 7 15 17 4 6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194 10 27 45 62 135 152 169 186 12 29 47 64 137 154 171 188 116 120 126 1 30 203 204 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2 BA0 BA1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7# DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 ODT0 ODT1 VREF_CA VREF_DQ RESET# VTT1 VTT2 DDR3-204P-40-GP-U 62.10017.N11 NP1 NP2 RAS# WE# CAS# CS0# CS1# CKE0 CKE1 CK0 CK0# CK1 CK1# DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 SDA SCL EVENT# VDDSPD SA0 SA1 NC#1 NC#2 NC#/TEST VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NP1 NP2 110 113 115 114 121 73 74 101 103 102 104 11 28 46 63 136 153 170 187 200 202 198 199 1 197 201 77 122 125 75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124 2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 205 206 SA0_DIM1 SA1_DIM1 C1901 SCD1U10V2KX-5GP +1.5V_SUS 1 M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7 ICH_SMBDATA 7,18,22,76 ICH_SMBCLK 7,18,22,76 PM_EXTTS#1 11 +3.3V_RUN M_B_RAS# 12 M_B_WE# 12 M_B_CAS# 12 M_CS#2 11 M_CS#3 11 M_CKE2 11 M_CKE3 11 M_CLK_DDR2 11 M_CLK_DDR#2 11 M_CLK_DDR3 11 M_CLK_DDR#3 11 M_B_DM[7..0] 12 M_B_DQS#[7..0] 12 M_B_DQS[7..0] 12 M_B_A[14..0] 12 2 SA1_DIM1
D
+3.3V_RUN
1 R1901 10KR2J-3-GP SA0_DIM1 1 R1902 10KR2J-3-GP 2
TP1901 12 M_B_BS2
12 M_B_BS0 12 M_B_BS1 12 M_B_DQ[63..0]
DY
2 2
C1902 Do Not Stuff
Note: SO-DIMMB SPD Address is 0xA4 SO-DIMMB TS Address is 0x34 SO-DIMMB is placed farther from the Processor than SO-DIMMA
SODIMM B DECOUPLING
+1.5V_SUS
+V_DDR_REF
B
R1906 1 2 Do Not Stuff M_VREF_CA_DIMM1 1 1 C1904 SC2D2U6D3V3KX-GP
Layout Note: Place these Caps near SO-DIMMB.
DY
B
+V_DDR_REF 1
R1907
C1918 Do Not Stuff
DY
TC1901 C1810 Do Not Stuff SC10U10V5ZY-1GP
Place these caps close to VTT1 and VTT2.
H = 9.2mm
C1919 C1920 C1921 C1922 SC1U6D3V2KX-GP SC1U6D3V2KX-GP SC1U6D3V2KX-GP SC1U6D3V2KX-GP
DJ1
Wistron Corporation
DDR3-SODIMM2
Size Date:
5 4 3 2
Document Number
Rev
DJ1 Montevina UMA

1
A00
of 88
Sheet
19
SSID = ICH
ICH_RTCX1 R2002 1 X2001
2 10MR2J-L-GP
ICH_RTCX2
4 1
C2002
1 1
C2001
SC15P50V2JN-2-GP
SC15P50V2JN-2-GP
X-32D768KHZ-46GP
+RTC_CELL R2003
2nd 82.30001.A81
SB1A
1 OF 6
LPC_LAD[0..3]
LPC_LAD[0..3]
37,58
2 1 2
ICH_RTCRST# ICH_RTCRST# SRTCRST# SM_INTRUDER# ICH_INTVRMEN LAN100_SLP
C23 C24 A25 F20 C22 B22 A22 E25
RTCX1 RTCX2
RTC LPC
20KR2F-L-GP C2003 SC1U10V3KX-3GP
G2001 Do Not Stuff
RTCRST# SRTCRST# INTRUDER# INTVRMEN LAN100_SLP GLAN_CLK LAN_RSTSYNC LAN_RXD0 LAN_RXD1 LAN_RXD2 LAN_TXD0 LAN_TXD1 LAN_TXD2 GLAN_DOCK#/GPIO56 GLAN_COMPI GLAN_COMPO HDA_BIT_CLK HDA_SYNC HDA_RST#
FW H0/LAD0 FW H1/LAD1 FW H2/LAD2 FW H3/LAD3 FW H4/LFRAME# LDRQ0# LDRQ1#/GPIO23 A20GATE A20M#
K5 K4 L6 K2 K3 J3 J1 N7 AJ27 AJ25 AE23 AJ26 AD22 AF25 AE22 AG25 L3 AF23 AF24 AH27 AG26 AG27 AH11 AJ11 AG12 AF12 AH9 AJ9 AE10 AF10 AH18 AJ18 AJ7 AH7
LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3 LPC_LFRAME# 37,58 +3.3V_RUN R2001
DY
R2005
+RTC_CELL R2004
Do Not Stuff KA20GATE 37 H_A20M# 8 H_DPRSTP# H_FERR#_R H_DPRSTP# 8,11,47 H_DPSLP# 8 +1.05V_VCCP
C13 2
20KR2F-L-GP
F14 G13 D14 D13 D12 E13 2GPIO56

GLAN_COMP ACZ_BIT_CLK_R ACZ_SYNC_R ACZ_RST#_R
LAN / GLAN CPU
DPRSTP# DPSLP# FERR# CPUPW RGD IGNNE# INIT# INTR RCIN# NMI SMI# STPCLK# THRMTRIP#
56R2J-4-GP H_FERR# 8 +3.3V_RUN R2008
1 R2006
2 56R2J-4-GP
H_PWRGOOD 8,42 H_IGNNE# H_INIT# 8 H_INTR 8 H_NMI 8 H_SMI# 8 H_STPCLK# 8 8
+1.5V_RUN
R2007
Place within 500 mil of SB.

R2009 1
DY
B10 B28 B27 AF6 AH4 AE7 AF4 AG4 AH3 AE5
DY
Do Not Stuff KBRCIN# +1.05V_VCCP R2011 37
2 24D9R2F-L-GP
Do Not Stuff
30 ICH_AZ_CODEC_BITCLK 30 ICH_AZ_CODEC_SYNC 30 ICH_AZ_CODEC_RST#
R2010 R2012 R2015
1 1 1
2 2 2
33R2J-2-GP 33R2J-2-GP 33R2J-2-GP 30 ICH_SDIN_CODEC
1 1 R2014
2 56R2J-4-GP 2 Do Not Stuff

H_THRMTRIP# 8,11,37,42
H_THERMTRIP_R
IHDA
HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_SDIN3 HDA_SDOUT
1 R2013
2 H_THERMTRIP_1 54D9R2F-L1-GP
PECI SATA4RXN SATA4RXP SATA4TXN SATA4TXP SATA5RXN SATA5RXP SATA5TXN SATA5TXP SATA_CLKN SATA_CLKP SATARBIAS# SATARBIAS
Placed Within 2" from SB.
A00
30 ICH_SDOUT_CODEC
R2016
33R2J-2-GP
ACZ_SDATAOUT_R
AG5 AG7 AE8
HDA_DOCK_EN#/GPIO33 HDA_DOCK_RST#/GPIO34 SATALED#
66
SATA_LED#
SATA_LED#
AG8 AJ16 AH16 AF17 AG17 AH13 AJ13 AG14 AF14
C2005 1 C2006 1
2 SCD01U50V2KX-1GP 2 SCD01U50V2KX-1GP
SATA_TXN0_C SATA_TXP0_C
SATA
HDD
B
59 59 59 59 59 59 59 59
SATA_RXN0_C SATA_RXP0_C SATA_TXN0 SATA_TXP0 SATA_RXN1_C SATA_RXP1_C SATA_TXN1 SATA_TXP1
SATA0RXN SATA0RXP SATA0TXN SATA0TXP SATA1RXN SATA1RXP SATA1TXN SATA1TXP

ICH9M-GP-NF
CLK_PCIE_SATA# 7 CLK_PCIE_SATA 7 SATARBIAS

B
ODD
C2007 1 C2008 1
2 SCD01U50V2KX-1GP 2 SCD01U50V2KX-1GP
SATA_TXN1_C SATA_TXP1_C
1 R2017
2 24D9R2F-L-GP
Place within 500 mils from SB.
2010/01/04
+RTC_CELL R2018
1
A
2
330KR2J-L1-GP R2019
ICH_INTVRMEN
integrated VccSus1_05,VccSus1_5,VccCL1_5
INTVRMEN
LAN100_SLP
High=Enable High=Enable
Low=Disable Low=Disable
ICH_AZ_CODEC_BITCLK
integrated VccLan1_05VccCL1_05
1 2
DJ1
LAN100_SLP
Wistron Corporation
EC2001 Do Not Stuff Title 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
330KR2J-L1-GP R2020
1
1MR2J-1-GP
SM_INTRUDER#
DY
Lay Out Close SB1

5 4 3 2
Size Document Number Custom Date:
ICH9-LAN/HDA/SATA/LPC(1/4)
DJ1 Montevina UMA
Sheet
1
Rev
A00
of 88
20
SSID = ICH
5 OF 6 SB1E
2 OF 6 SB1B
+3.3V_RUN
AA26 AA27 AA3 AA6 AB1 AA23 AB28 AB29 AB4 AB5 AC17 AC26 AC27 AC3 AD1 AD10 AD12 AD13 AD14 AD17 AD18 AD21 AD28 AD29 AD4 AD5 AD6 AD7 AD9 AE12 AE13 AE14 AE16 AE17 AE2 AE20 AE24 AE3 AE4 AE6 AE9 AF13 AF16 AF18 AF22 AH26 AF26 AF27 AF5 AF7 AF9 AG13 AG16 AG18 AG20 AG23 AG3 AG6 AG9 AH12 AH14 AH17 AH19 AH2 AH22 AH25 AH28 AH5 AH8 AJ12 AJ14 AJ17 AJ8 B11 B14 B17 B2 B20 B23 B5 B8 C26 C27 E11 E14 E18 E2 E21 E24 E5 E8 F16 F28 F29 G12 G14 G18 G21 G24 G26 G27 G8 H2 H23 H28 H29
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
ICH9M-GP-NF
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
H5 J23 J26 J27 AC22 K28 K29 L13 L15 L2 L26 L27 L5 L7 M12 M13 M14 M15 M16 M17 M23 M28 M29 N11 N12 N13 N14 N15 N16 N17 N18 N26 N27 P12 P13 P14 P15 P16 P17 P2 P23 P28 P29 P4 P7 R11 R12 R13 R14 R15 R16 R17 R18 R28 T12 T13 T14 T15 T16 T17 T23 B26 U12 U13 U14 U15 U16 U17 AD23 U26 U27 U3 V1 V13 V15 V23 V28 V29 V4 V5 W 26 W 27 W3 Y1 Y28 Y29 Y4 Y5 AG28 AH6 AF2 B25 A1 A2 A28 A29 AH1 AH29 AJ1 AJ2 AJ28 AJ29 B1 B29
ICH_GND1 ICH_GND2 ICH_GND3 ICH_GND4
11,37,58,76 PLT_RST#
PLT_RST#
R2102
2 Do Not Stuff
PCI_PLTRST#
D11 C8 D9 E12 E9 C9 E10 B7 C7 C5 G11 F8 F11 E7 A3 D2 F10 D5 D10 B3 F7 C3 F3 F4 C1 G7 H7 D1 G5 H6 G1 H3

PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 PIRQA# PIRQB# PIRQC# PIRQD#
PCI
REQ0# GNT0# REQ1#/GPIO50 GNT1#/GPIO51 REQ2#/GPIO52 GNT2#/GPIO53 REQ3#/GPIO54 GNT3#/GPIO55 C/BE0# C/BE1# C/BE2# C/BE3# IRDY# PAR PCIRST# DEVSEL# PERR# PLOCK# SERR# STOP# TRDY# FRAME# PLTRST# PCICLK PME#
F1 G4 B6 A7 F13 F12 E6 F6 D8 B4 D6 A5 D3 E3 R1 C6 E4 C2 J4 A4 F5 D7 C14 D4 R2
PCI_REQ0# PCI_GNT0# PCI_REQ1# PCI_GNT1# PCI_REQ2# PCI_GNT2# PCI_REQ3# PCI_GNT3#
RN2102 PCI_REQ1# PCI_DEVSEL# PCI_REQ3# PCI_TRDY#
TP2102 TP2103
8 7 6 5
1 2 3 4
SRN8K2J-4-GP RN2101
PCI_SERR# PCI_PIRQE# PCI_PIRQH# PCI_PIRQB# PCI_IRDY# PCIRST1# PCI_DEVSEL# PCI_PERR# PCI_PLOCK# PCI_SERR# PCI_STOP# PCI_TRDY# PCI_FRAME# PCI_PLTRST# ICH_PME# CLK_PCI_ICH TP2105 7 TP2104 PCI_REQ0# PCI_PLOCK# PCI_PIRQG# PCI_IRDY#
8 7 6 5
1 2 3 4
SRN8K2J-4-GP RN2103
8 7 6 5
1 2 3 4
SRN8K2J-4-GP RN2104
PCI_FRAME# PCI_PIRQC# PCI_PIRQF# PCI_REQ2#
8 7 6 5
1 2 3 4
SRN8K2J-4-GP RN2105
J5 E1 J6 C4
Interrupt I/F
PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5
H4 K6 F2 G2
PCI_PIRQE# PCI_PIRQF# PCI_PIRQG# PCI_PIRQH#
PCI_STOP# PCI_PIRQD# PCI_PERR# PCI_PIRQA#
8 7 6 5
1 2 3 4
SRN8K2J-4-GP
C
Layout Note: Place as close as possible to the ICH Pin

RP2101 USB_OC#7 USB_OC#11 USB_OC#5 USB_OC#4 +3.3V_ALW RN2106
ICH9M-GP-NF
1 2 3 4 5
SRN10KJ-L3-GP
10 9 8 7 6
USB_OC#0_1 USB_OC#1 USB_OC#6 USB_OC#2_3
+3.3V_ALW
+3.3V_ALW
8 7 6 5
1 2 3 4
SRN8K2J-4-GP
USB_OC#9 USB_OC#8 USB_OC#10 USB_OC#3
PCI_GNT0# 1 R2103 SPI_CS#1 1 R2104 PCI_GNT3# 1 R2105
DY DY DY
2 2 2
Do Not Stuff Do Not Stuff Do Not Stuff
BOOT BIOS Strap PCI_GNT#0 SPI_CS#1 BOOT BIOS Location
4 OF 6 SB1D
Direct Media Interface
N29 N28 P27 P26

76 76 76 76 76 76 76 76 PCIE_RXN2 PCIE_RXP2 PCIE_TXN2 PCIE_TXP2 PCIE_RXN3 PCIE_RXP3 PCIE_TXN3 PCIE_TXP3 SCD1U10V2KX-5GP 2 PCIE_C_TXN2 2 PCIE_C_TXP2 SCD1U10V2KX-5GP SCD1U10V2KX-5GP 2 PCIE_C_TXN3 2 PCIE_C_TXP3 SCD1U10V2KX-5GP
PERN1 PERP1 PETN1 PETP1 PERN2 PERP2 PETN2 PETP2
DMI0RXN DMI0RXP DMI0TXN DMI0TXP DMI1RXN DMI1RXP DMI1TXN DMI1TXP DMI2RXN DMI2RXP DMI2TXN DMI2TXP DMI3RXN DMI3RXP DMI3TXN DMI3TXP
V27 V26 U29 U28 Y27 Y26 W 29 W 28 AB27 AB26 AA29 AA28 AD27 AD26 AC29 AC28 T26 T25 AF29 AF28 AC5 AC4 AD3 AD2 AC1 AC2 AA5 AA4 AB2 AB3 AA1 AA2 W5 W4 Y3 Y2 W1 W2 V2 V3 U5 U4 U1 U2
0
DMI_IRXN0_MTXN0 DMI_IRXP0_MTXP0 DMI_ITXN0_MRXN0 DMI_ITXP0_MRXP0 DMI_IRXN1_MTXN1 DMI_IRXP1_MTXP1 DMI_ITXN1_MRXN1 DMI_ITXP1_MRXP1 DMI_IRXN2_MTXN2 DMI_IRXP2_MTXP2 DMI_ITXN2_MRXN2 DMI_ITXP2_MRXP2 DMI_IRXN3_MTXN3 DMI_IRXP3_MTXP3 DMI_ITXN3_MRXN3 DMI_ITXP3_MRXP3 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 +1.5V_RUN
1 0 1
SPI PCI LPC(Default)
1 1
WLAN LAN
C2101 1 C2104 1
L29 L28 M27 M26 J29 J28 K27 K26 G29 G28 H27 H26 E29 E28 F27 F26 C29 C28 D27 D26
A16 swap override strap PCI_GNT#3 low = A16 swap override enable high = default
C2105 1 C2106 1
PCI-Express
PERN3 PERP3 PETN3 PETP3 PERN4 PERP4 PETN4 PETP4 PERN5 PERP5 PETN5 PETP5
USB Pair 0 1 2 3
Device USB0 (I/O Board) RESERVED USB2 USB3 BLUETOOTH RESERVED WLAN RESERVED RESERVED RESERVED Card Reader CAMERA
A
2
R2106 24D9R2F-L-GP
DMI_CLKN DMI_CLKP
CLK_PCIE_ICH# 7 CLK_PCIE_ICH 7 DMI_IRCOMP_R USB_PN0 USB_PP0 USB_PN2 USB_PP2 USB_PN3 USB_PP3 USB_PN4 USB_PP4 USB_PN6 USB_PP6 USB_PN7 USB_PP7 USB_PN8 USB_PP8 USB_PN9 USB_PP9 USB_PN10 USB_PP10 USB_PN0 76 USB_PP0 76 USB_PN2 USB_PP2 USB_PN3 USB_PP3 USB_PN4 USB_PP4 63 63 63 63 73 73
DMI_ZCOMP DMI_IRCOMP
PERN6/GLAN_RXN PERP6/GLAN_RXP PETN6/GLAN_TXN PETP6/GLAN_TXP
TP2106 TP2107 TP2110 TP2111 63 TP2113 TP2117 63 USB_OC#0_1 USB_OC#2_3
SPI_CS#1
D23 D24 F23 D25 E23
NCTF PIN
TP2120 TP2101
USB_OC#0_1 USB_OC#1 USB_OC#2_3 USB_OC#3 USB_OC#4 USB_OC#5 USB_OC#6 USB_OC#7 USB_OC#8 USB_OC#9 USB_OC#10 USB_OC#11
N4 N5 N6 P6 M1 N2 M4 M3 N3 N1 P5 P3
1
R2101 22D6R2F-L1-GP
USB_RBIAS_PN AG2 AG1
USBP0N USBP0P USBP1N USBP1P SPI_CLK USBP2N SPI_CS0# USBP2P SPI_CS1#/GPIO58/CLGPIO6 USBP3N USBP3P SPI_MOSI USBP4N SPI_MISO USBP4P USBP5N OC0#/GPIO59 USBP5P OC1#/GPIO40 USBP6N OC2#/GPIO41 USBP6P OC3#/GPIO42 USBP7N OC4#/GPIO43 USBP7P OC5#/GPIO29 USBP8N OC6#/GPIO30 USBP8P OC7#/GPIO31 USBP9N OC8#/GPIO44 USBP9P OC9#/GPIO45 USBP10N OC10#/GPIO46 USBP10P OC11#/GPIO47 USBP11N USBP11P USBRBIAS USBRBIAS#
USB0 USB2 USB3
4 5 6 7 8 9 10 11
DJ1
SPI
USB
USB_PN6 76 USB_PP6 76 TP2115 TP2116 TP2118 TP2119 TP2112 TP2114 USB_PN10 32 USB_PP10 32 USB_PN11 54 USB_PP11 54
WLAN
Wistron Corporation
Card Reader CAMERA Title
Size Document Number Custom Date: 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
ICH9M-GP-NF
ICH9-PCI/PCIE/DMI/USB/GND(2/4) Rev
DJ1 Montevina UMA
Sheet
1
A00
of 88
21
+3.3V_RUN
SSID = ICH
3 OF 6 +3.3V_ALW SB1C SMB_CLK SMB_DATA LINKALERT# ME_EC_CLK1 ME_EC_DATA1 ICH_RI# TP2204 R2202 1 RN2201 SUS_STAT# SYS_RESET# RN2203
RN2202 SATA0GP SATA2GP SATA3GP SATA1GP
4 3
D
1 2
SRN4K7J-8-GP
SMB_CLK SMB_DATA
SMB
G16 A13 E17 C17 B18 F19 R4 G19 M6
SMBCLK SMBDATA LINKALERT#/GPIO60/CLGPIO4 SMLINK0 SMLINK1 RI# SUS_STAT#/LPCPD# SYS_RESET# PMSYNC#/GPIO0 SMBALERT#/GPIO11
SATA GPIO
SATA0GP/GPIO21 SATA1GP/GPIO19 SATA4GP/GPIO36 SATA5GP/GPIO37 CLK14 CLK48 SUSCLK SLP_S3# SLP_S4# SLP_S5# S4_STATE#/GPIO26
AH23 AF19 AE21 AD20 H1 AF3 P1 C16 E16 G17 C10 G20 M2 B13 R3 D20 D22 R5 R6 B16 F24 B19 F22 C19 C25 A19 F21 D18 A16 C18 C11 C20
SATA0GP SATA1GP SATA2GP SATA3GP CLK_14M_ICH CLK_48M_ICH 7 7 ICH_SUSCLK_2102 22R2J-2-GP ICH_SUSCLK_KBC 39 37
8 7 6 5
1 2 3 4
SRN10KJ-6-GP
Clocks
ICH_SUSCLK SB_SLP_S3# R2220 PM_SLP_S5# GPIO26 PM_PWROK
2 10KR2J-3-GP
LINKALERT# 11 PM_SYNC# TP2203 7 7 H_STP_PCI# H_STP_CPU# SMB_ALERT# H_STP_PCI# H_STP_CPU#
1 R2221 2 Do Not Stuff 1 2
PM_PWROK DPRSLPVR LAN_RST#1 RSMRST#_KBC
R2203 1 R2205 1 R2204 1 R2206 1
DY
2 2 2 2
10KR2J-3-GP Do Not Stuff Do Not Stuff 10KR2J-3-GP
3 4
2 1
SRN10KJ-5-GP
ME_EC_DATA1 ME_EC_CLK1
A17 A14 E19 L4
PM_SLP_S4# 37,41,50 TP2202 R2209 TP2205 M_PWROK
SYS GPIO Power MGT
STP_PCI# STP_CPU# CLKRUN# W AKE# SERIRQ THRM# VRMPW RGD SST TACH1/GPIO1 TACH2/GPIO6 TACH3/GPIO7 GPIO8 LAN_PHY_PW R_CTRL/GPIO12 ENERGY_DETECT/GPIO13 TACH0/GPIO17 GPIO18 GPIO20 SCLOCK/GPIO22 GPIO27 GPIO28 SATACLKREQ#/GPIO35 SLOAD/GPIO38 SDATAOUT0/GPIO39 SDATAOUT1/GPIO48 GPIO49 GPIO57/CLGPIO5 SPKR MCH_SYNC# TP3 PW M0 PW M1 PW M2
ICH9M-GP-NF
PW ROK DPRSLPVR/GPIO16 BATLOW # PW RBTN# LAN_RST# RSMRST# CK_PW RGD CLPW ROK SLP_M# CL_CLK0 CL_CLK1
2 Do Not Stuff
R2226
PM_PWROK 11,37
37 PM_CLKRUN# R2207 1 RN2204
DPRSLPVR 11,47 PM_BATLOW#_R PM_PWRBTN# 37 LAN_RST#1 RSMRST#_KBC 37 CK_PWRGD 7 M_PWROK PM_SLP_M# M_PWROK 11 TP2207 CL_CLK0 11 CL_DATA0 11 CL_VREF0_ICH +3.3V_RUN
SB_SLP_S3#
2 10KR2J-3-GP
PCIE_WAKE#
76 37
PCIE_WAKE# INT_SERIRQ
PCIE_WAKE# INT_SERIRQ THERM_SCI# VGATE_PWRGD ICH_TP7 ECSCI# ECSWI# ECSMI#
2
Do Not Stuff
E20 M5 AJ23 D21 A20 AG19 AH21 AG21 A21 C12 C21 AE18 K1 AF8 AJ22 A9 D19 L1 AE19 AG22 AF21 AH24 A8 M7 AJ24 B21 AH20 AJ20 AJ21
PM_SLP_S3# 37,42,49,50
8 7 6 5
1 2 3 4
SRN8K2J-4-GP
SMB_ALERT# ICH_RI# PM_BATLOW#_R
37,47 VGATE_PWRGD R2208 1 37 37 37
DY
ECSCI# ECSWI# ECSMI#
2 Do Not Stuff
R2210 R2211
1 1
2 10KR2J-3-GP 2 10KR2J-3-GP
ECSMI# SYS_RESET#
TP2210
C
GPIO18
MISC GPIO Controller Link
CL_DATA0 CL_DATA1 CL_VREF0 CL_VREF1 CL_RST0# CL_RST1# GPIO24/MEM_LED GPIO10/SUS_PW R_ACK GPIO14/AC_PRESENT GPIO9/W OL_EN
R2212 3K24R2F-GP
+3.3V_RUN RN2205
CLKSATAREQ#
iTPM_EN 30 ACZ_SPKR 11 MCH_ICH_SYNC# TP2219
Do Not Stuff R2214 2 R2215 2 R2201 2 R2216 2 R2217 1 R2218 2 R2219 1 10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP 8K2R2J-3-GP PM_CLKRUN# INT_SERIRQ GPIO18 ECSCI# ECSWI# CLKSATAREQ# THERM_SCI# ICH_TP3
C2201 2 1
DY
1 1 1 1 2 1 2
iTPM Select(Not Strap Pin)

B B
iTPM_EN
iTPM_EN
R2223 100KR2J-1-GP
0 = Disable 1 = Enable
+3.3V_RUN
RN2206
4 3
1 2
SRN4K7J-8-GP
R2213 453R2F-1-GP
4 3
1 2
CL_RST#0 11
SCD1U10V2KX-5GP
H_STP_CPU# H_STP_PCI#
DJ1 U2202 7,18,19,76 ICH_SMBDATA
1 2
SMB_CLK
6 5 4
2N7002EDW-GP
SMB_DATA
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. ICH_SMBCLK 7,18,19,76 Title Size Document Number Custom Date:
ICH9-GPIO/PM/CL(3/4)
DJ1 Montevina UMA
Sheet
1
Rev
A00
of 88
22
+RTC_CELL
6 OF 6 SB1F +1.05V_VCCP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SSID = ICH
C2302 2 1
A23
C2309 2 1 V5REF_S0 V5REF_S5
VCCRTC V5REF 2mA V5REF_SUS 2mA VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B
C2303 Do Not Stuff
C2305 Do Not Stuff
A6 AE1 AA24 AA25 AB24 AB25 AC24 AC25 AD24 AD25 AE25 AE26 AE27 AE28 AE29 F25 G25 H24 H25 J24 J25 K24 K25 L23 L24 L25 M24 M25 N23 N24 N25 P24 P25 R24 R25 R26 R27 T24 T27 T28 T29 U24 U25 V24 V25 U23 W 24 W 25 K23 Y24 Y25 AJ19 AC16 AD15 AD16 AE15 AF15 AG15 AH15 AJ15 AC11 AD11 AE11 AF11 AG10 AG11 AH10 AJ10 AC9 AC18 AC19 AC21 G10 G9
1634mA
*Within a given well, 5VREF needs to be up before the corresponding 3.3V rail
+3.3V_RUN +5V_RUN +3.3V_ALW +5V_ALW
CORE
D2301 CH751H-40PT-GP
R2304 10R2J-2-GP
CH751H-40PT-GP
R2302 10R2J-2-GP
D2302
V5REF_S0
V5REF_S5
C2313 2 1
SCD1U10V2KX-5GP
VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05
A15 B15 C15 D15 E15 F15 L11 L12 L14 L16 L17 L18 M11 M18 P11 P18 T11 T18 U11 U18 V11 V12 V14 V16 V17 V18 R29 W 23 Y23 AB23 AC23 AG29 AJ6
1 2
DY
2
DY
2
1D5V_DMIPLL_ICH_S0 L2301 C2308 SCD01U16V2KX-3GP 1D5V_DMIPLL_ICH_S0
+1.5V_RUN
2 1
1 COIL-1UH-31-GP
+1.05V_VCCP R2305
VCCDMI
2
Do Not Stuff +1.05V_VCCP R2306 SB_V_CPU_IO C2316 SCD1U10V2KX-5GP C2318 SC4D7U6D3V3KX-GP C2317 Do Not Stuff
23mA VCCDMIPLL 50mA VCCDMI

VCCDMI
+1.5V_RUN
VCC3_3
VCCA3GP
+3.3V_RUN
DY
2
C2319 Do Not Stuff
C2320 Do Not Stuff
TC2301 Do Not Stuff
VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3
DY
2
DY
2
DY
VCCP_CORE
308mA
AD19 AF20 AG24 AC20 B9 F9 G3 G6 J2 J7 K7 AJ4 AJ3 AC8 F17 AD8 F18 A18 D16 D17 E22 AF1 T1 T2 T3 T4 T5 T6 U6 U7 V6 V7 W6 W7 Y6 Y7 T7 G22 G23
VCCSUSHDA_ICH VCCSUS1_05[1] VCCSUS1_05[2] VCCSUS1_5[1] VCCSUS1_5[2]
AC10
VCC3_3
+3.3V_RUN
+1.5V_RUN +3.3V_RUN R2308 L2302
+VCCSATAPLL
PCI
1 2
SB_VCCLAN3_3 C2333 SCD1U10V2KX-5GP C2334 Do Not Stuff
2
IND-10UH-215-GP
646mA
2mA V_CPU_IO
V_CPU_IO
SB_V_CPU_IO
2
Do Not Stuff
+3.3V_RUN
11mA VCCHDA
+3.3V_ALW
Do Not Stuff
DY
2
R2316 Do Not Stuff
2 1
VCCSATAPLL47mA 11mA VCCSUSHDA VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A
VCCPUSB
1 R2317 1 1
TP2302 TP2301
VCCSUS1_05 VCCSUS1_05
ARX
Do Not Stuff
VCCSUS1_5 VCCSUS1_5 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCCL1_05 VCCCL1_5
DY
+1.5V_RUN
+1.5V_RUN
R2311
VCCPSUS
+1.5V_RUN
2 1
B
ATX
2
Do Not Stuff
VCC_GLAN_PLL C2339 SC2D2U6D3V3KX-GP
1342mA
R2312 SB_VCCSUS3_3 C2341 SCD1U10V2KX-5GP C2342 Do Not Stuff C2343 Do Not Stuff
+3.3V_ALW
1 1 1 1
2
Do Not Stuff
212mA
VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCCUSBPLL 11mA VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCCLAN1_05 VCCLAN1_05 VCCLAN3_3 78mA VCCLAN3_3 VCCGLANPLL 23mA
USB CORE
DY
2
DY
2
+1.5V_RUN
R2313
2
C2344 Do Not Stuff Do Not Stuff
1D5V_USB_S0 C2345 SCD1U10V2KX-5GP C2346 SCD1U10V2KX-5GP
AC12 AC13 AC14 AJ5 AA7 AB6 AB7 AC6 AC7 A10 A11 A12 B12 A27 D28 D29 E26 E27 A26
+3.3V_ALW R2314
ICH9_SUS3_3 C2347 SCD1U10V2KX-5GP C2348 SCD1U16V2KX-3GP C2349 SCD022U16V2KX-3GP
1 1 1 1
2
Do Not Stuff
DY
2
73mA
VCCCL3_3 VCCCL3_3
A24 B24
VCCLAN1D05 C2350 Do Not Stuff
VCCSUS1_05[3] DJ1 VCCSUS1_5[3] C2354 SCD1U10V2KX-5GP C2301 SCD1U10V2KX-5GP C2351 Do Not Stuff
A
DY
+1.5V_RUN
SB_VCCLAN3_3 VCC_GLAN_PLL
Wistron Corporation
GLAN POWER
C2353 Do Not Stuff
DY
+3.3V_RUN
VCCGLAN1_5 VCCGLAN1_5 VCCGLAN1_5 VCCGLAN1_5
80mA
R2315 SB_VCCCL3_3
2
Do Not Stuff
+3.3V_RUN
DY
VCCGLAN3_3 1mA
ICH9M-GP-NF
ICH9-Power(4/4)
Sheet
1
Rev
DJ1 Montevina UMA

23 of 88
A00
(Blanking)
DJ1
Wistron Corporation
5 4 3 2
Reserved
Sheet
1
Rev
DJ1 Montevina UMA

24 of 88
A00
(Blanking)
DJ1
Wistron Corporation
5 4 3 2
Reserved
Sheet
1
Rev
DJ1 Montevina UMA

25 of 88
A00
(Blanking)
DJ1
Wistron Corporation
5 4 3 2
Reserved
Sheet
1
Rev
DJ1 Montevina UMA

26 of 88
A00
(Blanking)
DJ1
Wistron Corporation
5 4 3 2
Reserved
Sheet
1
Rev
DJ1 Montevina UMA

27 of 88
A00
(Blanking)
DJ1
Wistron Corporation
5 4 3 2
Reserved
Sheet
1
Rev
DJ1 Montevina UMA

28 of 88
A00
(Blanking)
DJ1
Wistron Corporation
5 4 3 2
Document Number
Reserved
Sheet
1
Rev
DJ1 Montevina UMA

A00
SSID = AUDIO
+AVDD
D
+5V_RUN
D
+3.3V_RUN ICH_AZ_CODEC_BITCLK
+3.3V_RUN
Close to codec
Close to codec
C3005 SCD1U10V2KX-5GP C3006 SC1U10V3KX-3GP AUD_DVDDCORE
R3021
2
+5V_RUN
Do Not Stuff
DY
C3010 Do Not Stuff
U3001
1 9 3
ICH_AZ_CODEC_BITCLK
DVDD_CORE DVDD DVDD_IO HDA_BITCLK HDA_SDI HDA_SDO HDA_SYNC HDA_RST#
AVDD AVDD PVDD PVDD SENSE_A SENSE_B HP0_PORT_A_L HP0_PORT_A_R VREFOUT_A_OR_F HP1_PORT_B_L HP1_PORT_B_R PORT_C_L PORT_C_R VREFOUT_C
27 38 39 45 13 14 28 29 23 31 32 19 20 24 40 41 43 44 15 16 17 18 12 25
20 ICH_AZ_CODEC_BITCLK 20 ICH_SDIN_CODEC +3.3V_RUN 20 ICH_SDOUT_CODEC 20 ICH_AZ_CODEC_SYNC R3001 1
6 8 5 10 11
AUD_SENSE_A AUD_SENSE_B AUD_EXT_MIC_L AUD_EXT_MIC_R AUD_VREFOUT_B AUD_HP1_JACK_L AUD_HP1_JACK_R AUD_INT_MIC_R_L AUD_VREFOUT_C AUD_SPK_L+ AUD_SPK_LAUD_SPK_RAUD_SPK_R+ C3011 1 R3004
AUD_AGND
2 33R2J-2-GP
ICH_SDIN_CODEC_C0 ICH_SDOUT_CODEC ICH_AZ_CODEC_SYNC ICH_AZ_CODEC_RST#
AUD_EXT_MIC_L 60 AUD_EXT_MIC_R 60 AUD_VREFOUT_B 60 60 60
AUD_AGND
R3005 10KR2J-3-GP
20 ICH_AZ_CODEC_RST#
AUD_HP1_JACK_L AUD_HP1_JACK_R
SC1U10V3KX-3GP
INT_MIC_L_R
60
2 2K2R2J-2-GP
AUD_SPK_L+ 60 AUD_SPK_L- 60 AUD_SPK_RAUD_SPK_R+ 60 60 R3006 120KR2F-L-GP 1 2
AMP_MUTE#
2 4 46
DMIC_CLK/GPIO1 DMIC0/GPIO2 DMIC1/GPIO0/SPDIF_OUT_1 SPDIF_OUT_0 EAPD
SPKR_PORT_D_L+ SPKR_PORT_D_LSPKR_PORT_D_RSPKR_PORT_D_R+ PORT_E_L PORT_E_R PORT_F_L PORT_F_R PC_BEEP
From SB
ACZ_SPKR 22
C
2 2 2
G3001 Do Not Stuff
48
37 AMP_MUTE# AMP_MUTE# PUMP_CAPN
1 C3012 SCD1U10V2KX-5GP 1 C3013 SCD1U10V2KX-5GP
SB_SPKR_R
47
KBC_BEEP_R 1 2 R3007 499KR2F-1-GP
KBC_BEEP 37
From EC
35 36 7 33 30 26 42 49
CAPCAP+
AUD_PC_BEEP
C3014 SC2D2U25V5KX-1GP
PUMP_CAPP
MONO_OUT DVSS AVSS AVSS AVSS PVSS GND

92HD79B1A5NLGXTAX-GP 71.92H79.003 AUD_AGND
AUD_PC_BEEP Trace width>15 mils

AUD_CAP2 AUD_VREFFLT AUD_V_B AUD_VREG C3015 SC4D7U6D3V5KX-3GP 2 1 C3018 SC1U6D3V2KX-GP
CAP2 VREFFILT VVREG
22 21 34 37
AUD_AGND AUD_AGND AUD_AGND AUD_AGND

B
Close to codec
C3016 C3017 SC10U6D3V5KX-1GP SC10U6D3V5KX-1GP
Azalia I/F EMI

ICH_SDOUT_CODEC
DY
2
ICH_AZ_CODEC_SDOUT1
R3013 Do Not Stuff
+AVDD
1
R3016 2K49R2F-GP
R3015 20KR2F-L-GP 2
+AVDD
R3012
1
AUD_HP1_JD# 60 R3017 2K49R2F-GP
Do Not Stuff R3014
1 2
AUD_SENSE_A AUD_SENSE_B C3019 SC1000P50V3JN-GP-U
2
DJ1
Do Not Stuff R3019 20KR2F-L-GP R3018
EXT_MIC_JD# 60
DY
2
C3020 Do Not Stuff
AUD_AGND AUD_AGND
R3020 39K2R2F-L-GP 1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title AUD_AGND
Do Not Stuff
Close to Pin13
Close to Pin14
4 3
A00
2
Audio Codec 92HD79B1

Rev Friday, February 26, 2010
DJ1 Montevina UMA Sheet

1
A00
30 of 88
(Blanking)
DJ1
Wistron Corporation
5 4 3 2
Document Number
Reserved
Sheet
1
Rev
DJ1 Montevina UMA

A00
SSID = SDIO
D D
7 CLK_48M_CARD
XD_D7 XD_D6/MS_BS XD_D5/SD_D2/MS_D5 XD_D4/SD_D3/MS_D1 XD_D3/SD_D4/MS_D4
XD_D7 71 XD_D6/MS_BS 71 XD_D5/SD_D2/MS_D5 XD_D4/SD_D3/MS_D1 XD_D3/SD_D4/MS_D4
71 71 71
C301 1 2 +3.3V_RUN Do Not Stuff
CLK_IN XD_D7 SP14 SP13 SP12 SP11
R301 1 2 6K2R2F-GP USB_PN10_1 USB_PP10_1
U301
24 23 22 21 20 19
DY
RREF
SCD1U10V2KX-5GP C302
+3.3V_RUN_CARD C303 Do Not Stuff 2 1
V18
DY
C304 SC1U6D3V2KX-GP
25
GND
XD_CD# SP1 SP2 SP3 SP4 SP5
1 2 3 4 5 6
RREF DM DP 3V3_IN CARD_3V3 V18
SP10 GPIO0 SP9 SP8 SP7 SP6
18 17 16 15 14 13
XD_D2/SD_CMD CR_GPIO0 1 XD_D1/SD_D5/MS_D0 XD_D0/SD_CLK/MS_D2 XD_WP/SD_D6/MS_D6 XD_WE#/SD_CD#
XD_D2/SD_CMD 71 TP2 Do Not Stuff XD_D1/SD_D5/MS_D0 71 XD_D0/SD_CLK/MS_D2 71 XD_WP/SD_D6/MS_D6 71 XD_WE#/SD_CD# 71
7 8 9 10 11 12
RTS5138-GR-GP
XD_ALE/SD_D7/MS_D3 XD_CLE/SD_D0/MS_D7 XD_CE#/SD_D1 XD_RE#/MS_INS# XD_RDY/SD_WP/MS_CLK_R XD_CD#
XD_ALE/SD_D7/MS_D3 XD_CLE/SD_D0/MS_D7 XD_CE#/SD_D1 71 XD_RE#/MS_INS# 71 XD_CD# 71
71 71
R302 1 22R2J-2-GP
XD_RDY/SD_WP/MS_CLK
71
Close U27
Close to U301
+3.3V_RUN_CARD
2 1
Do Not Stuff USB_PN10_1 USB_PP10_1
XD_D4/SD_D3/MS_D1 XD_D5/SD_D2/MS_D5 XD_CE#/SD_D1 XD_CLE/SD_D0/MS_D7
1 R3211 1 R3210
2 2
USB_PN10 21 USB_PP10 21
Do Not Stuff
2010/01/05
EC302 Do Not Stuff
EC303 Do Not Stuff Do Not Stuff
EC304 Do Not Stuff Do Not Stuff
EC301 Do Not Stuff
DY
2
DY
2
DY
2
DY
2
A
DJ1
Wistron Corporation
5 4 3 2
Card Reader-RTS5138
Sheet
1
Rev
DJ1 Montevina UMA

32 of 88
A00
(Blanking)
DJ1
Wistron Corporation
5 4 3 2
Document Number
Reserved
Sheet
1
Rev
DJ1 Montevina UMA

A00
(Blanking)
DJ1
Wistron Corporation
5 4 3 2
Document Number
Reserved
Sheet
1
Rev
DJ1 Montevina UMA

A00
(Blanking)
DJ1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Date:
A B C D
Document Number
(Reserved)
Sheet
E
Rev
DJ1 Montevina UMA

A00
(Blanking)
DJ1
Wistron Corporation
5 4 3 2
Document Number
Reserved
Sheet
1
Rev
DJ1 Montevina UMA

A00
+KBC_PWR +KBC_PWR R3747 L3701 C3704 SC2D2U6D3V3KX-GP 1 1
CAP close to VCC-GND pin pair

DY
2 Do Not Stuff +3.3V_RTC_LDO 2 BLM18AG601SN-3GP C3710 SC2D2U6D3V3KX-GP C3707 SCD1U10V2KX-5GP 2 1 C3708 SCD1U10V2KX-5GP 2 1 C3709 SCD1U10V2KX-5GP 2 1 C3701 SCD1U10V2KX-5GP VBAT
+3.3V_RUN R3745 1 R3746 SCD1U10V2KX-5GP C3702 1 1 C3703 Do Not Stuff
+KBC_PWR
DY
2 KBC_PWRBTN_EC# Do Not Stuff 1
1 100KR2J-1-GP +3.3V_RTC_LDO
SSID = KBC
+3.3V_RTC_LDO
DY
2
76 KBC_PWRBTN#
C3706 Do Not Stuff 2 1
KBC_PWRBTN#
BAT54C-U-GP D3705 R3744 2 10KR2J-3-GP KBC_ON# 1 1 R3754 2 10KR2J-3-GP C3718 1 G Q3704 S
DY
115 88 76 46 19
102
U3701A
80
+KBC_PWR BAT_IN# 76 R3751 1 2 1 R3752 10KR2J-3-GP AC_IN#_KBC
1 OF 2
SCD1U16V2KX-3GP
VCC VCC VCC VCC VCC
AVCC
VDD
GPIO41
DY
1
SI2301CDS-T1-GE3-GP D +KBC_PWR
+KBC_PWR
Do Not Stuff D3704 BAT54C-U-GP 3
VREF GPI90/AD0 GPI91/AD1 GPI92/AD2 GPI93/AD3 GPIO05 GPIO04
76 R3749 2K2R2J-2-GP KB_DET_KBC R3753 Do Not Stuff
AD_IA
DJ1/DJ2
1 2
76 PSID_EC KBC_GPIO05
DJ3
2
11
TSATN#_KBC TP3704
KB_DET_KBC 1SUBWOOFER_MUTE# PCB_VER2
PH for DJ1 PL for DJ2/DJ3

22,42,49,50 PM_SLP_S3# +KBC_PWR 69 LID_CLOSE# R3710 66 66
C
101 105 106 107
GPI94 GPI95 GPI96 GPI97
ECSCI#_KBC ECSWI#_KBC R3709 2
INT_SERIRQ 22 PM_CLKRUN# 22 KBRCIN# 20 KA20GATE 20 GMCH_BL_ON 13 1 100KR2J-1-GP
KBC_ON# +3.3V_RUN
EC_ENABLE#
2N7002E-1-GP E51_RxD R3706 +1.05V_VCCP
D/A
KBC_THERMTRIP#
97 98 99 100 108 96
A/D LPC
GPIO10/LPCPD# LRESET# LCLK LFRAME# LAD0 LAD1 LAD2 LAD3 SERIRQ GPIO11/CLKRUN# KBRST# GA20 ECSCI#/GPIO54 GPIO65/SMI# GPIO67/PWUREQ#
PLT_RST1#_1 LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3 PCLK_KBC 7 LPC_LFRAME# 20,58 LPC_LAD[0..3] 20,58
+KBC_PWR
AC_IN# 76
Q3705
104
124 7 2 3 126 127 128 1 125 8 122 121 29 9 123
. . . .
DY
RN3702
Do Not Stuff +KBC_PWR
KBC_PWRBTN_EC# AC_IN#_KBC PCB_VER0 KBC_BIOS_ID 2K2R2J-2-GP PCB_VER1
PWR_LED# BATCHG
SP SPI
GPIO66/G_PWM
TP3706
81
KBC_GPIO66 1
H_THERMTRIP_R# 2
C3711
Do Not Stuff
22 RSMRST#_KBC 22,41,50 PM_SLP_S4# 46 3V_5V_POK 11,22 PM_PWROK 62 EC_SPI_WP#_R 54 BLON_OUT 47 CPUCORE_ON 76 PSID_DISABLE# 63 USB_PWR_EN# R3718 1 PM_PWROK_R 2 Do Not Stuff EC_ENABLE# 2 CPUCORE_ON_R Do Not Stuff
GPIO
GPIO77 GPIO76/SHBM GPIO75 GPIO81
84 83 82 91
BLUETOOTH_EN_L 73,76 WIFI_RF_EN 76 8,11,20,42 H_THRMTRIP#
ECSMI#_KBC
SRN4K7J-8-GP
C
3 Q3703 PMBS3904-1-GP
KBC_THERMTRIP#
LCD_CBL_DET# 1 R3713 KB_DET# 1 R3714 KBC_THERMTRIP# 1 R3717 S5_ENABLE
2 2
100KR2J-1-GP 100KR2J-1-GP
R3719 1
GPO83/SOUT_CR/BADDR1 GPIO87/SIN_CR GPO84/BADDR0 GPIO16 GPIO34 GPIO36
111 113 112 114 14 15
E51_TxD E51_RxD
E51_TxD 76 E51_RxD 76 PM_LAN_ENABLE 76 S5_ENABLE 42
22
ECSWI#
D3702 3 ECSWI#_KBC 2 100KR2J-1-GP
RUNPWROK_R 1 R3711 2 Do Not Stuff
RUNPWROK 49 22 ECSCI#
2 1
BAS16-6-GP D3701 KCOL0 R3721 3 ECSCI#_KBC CPUCORE_ON 1 R3730 2 10KR2J-3-GP R3720 1 1 2 10KR2J-3-GP Do Not Stuff
SER/IR
DY
76
PSID_EC D GND GND GND GND GND GND Q3706 AGND
VCORF
44
KBC_VCORF C3712 SC1U10V3KX-3GP 22 ECSMI# BAS16-6-GP 2 D3703 1 1
. . . . .
G Do Not Stuff KBC_GPIO05 +3.3V_RUN
116 89 78 45 18 5
103
DY
S
NPCE781BA0DX-GP
3 KBC_AGND 2 BAS16-6-GP
ECSMI#_KBC
BLUETOOTH_EN_L 1 R3742
10KR2J-3-GP
A00 For RCID Function
Do Not Stuff 1 2 R3725
Layout note: 1. Connect KBC_AGND and GND at one point 2. R3725 close to Pin 103 (AGND)
22 ICH_SUSCLK_KBC
U3701B 1 R3748 2 KBC_XI Do Not Stuff
2 OF 2 KCOL[0..16] 68
77
A00
1 1
B
32KX1/32KCLKIN
A00
DY
2 PCB_VER0 PCB_VER1 PCB_VER2 1
DY
2
MB VERSION ID
VER2 VER1 VER0
+3.3V_RUN
30
AMP_MUTE#
79 30 63 117 31 32 118 62
32KX2 GPIO55/CLKOUT GPIO14/TB1 GPIO20/TA2 GPIO56/TA1 GPIO15/A_PWM GPIO21/B_PWM GPIO13/C_PWM
DY
2
X00 X01 A00 A01
0 0 0 0
0 0 1 1
0 1 0 1
1 R3702
DY
Q3702
2 Do Not Stuff
22,47 VGATE_PWRGD 22 PM_PWRBTN# 54 LCD_TST_EN 30 KBC_BEEP 66 BATLOW_LED
39 THERM_SDA
4 5 KBC_SCL1 6
3 2 1 2N7002EDW-GP
KBC_SDA1 68 KB_DET# 54 LCD_CBL_DET# THERM_SCL 39 54 68 68 LCD_TST TPDATA TPCLK 13 12 11 10 71 72 GPIO12/PSDAT3 GPIO25/PSCLK3 GPIO27/PSDAT2 GPIO26/PSCLK2 GPIO35/PSDAT1 GPIO37/PSCLK1
KBSOUT0/JENK# KBSOUT1/TCK KBSOUT2/TMS KBSOUT3/TDI KBSOUT4/JEN0# KBSOUT5/TDO KBSOUT6/RDY# KBSOUT7 KBSOUT8 KBSOUT9 KBSOUT10 KBSOUT11 KBSOUT12/GPIO64 KBSOUT13/GPIO63 KBSOUT14/GPIO62 KBSOUT15/GPIO61/XOR_OUT GPIO60/KBSOUT16 GPIO57/KBSOUT17
KBC
53 52 51 50 49 48 47 43 42 41 40 39 38 37 36 35 34 33 54 55 56 57 58 59 60 61 85
KCOL0 KCOL1 KCOL2 KCOL3 KCOL4 KCOL5 KCOL6 KCOL7 KCOL8 KCOL9 KCOL10 KCOL11 KCOL12 KCOL13 KCOL14 KCOL15 KCOL16 KCOL17 KROW0 KROW1 KROW2 KROW3 KROW4 KROW5 KROW6 KROW7 ECRST#
1 DY
BAT_SDA BAT_SCL
4 3
SRN4K7J-8-GP RN3701 1 2
DY
EC3701 Do Not Stuff

B
64 95 93 94 119 6 109 120 65 66 16 17 20 21 22 23 24 25 26 27 28 73 74 75 110
GPIO01/TB2 GPIO03 GPIO06 GPIO07 GPIO23 GPIO24 GPIO30 GPIO31 GPIO32/D_PWM GPIO33/H_PWM GPIO40/F_PWM GPIO42/TCK GPIO43/TMS GPIO44/TDI GPIO45/E_PWM GPIO46/TRST# GPIO47 GPIO50/TDO GPIO51 GPIO52/RDY# GPIO53 GPIO70 GPIO71 GPIO72 GPO82/TRIS#
SMB
GPIO74/SDA2 GPIO73/SCL2 GPIO22/SDA1 GPIO17/SCL1
68 67 69 70
KBC_SDA1 KBC_SCL1 BAT_SDA 76 BAT_SCL 76
R3705 2K2R2J-2-GP
KBC_SCL1 KBC_SDA1
4 3
1 2 1 TP3703 Do Not Stuff KROW[0..7] 68
Do Not Stuff R3722 10KR2J-3-GP R3727
10KR2J-3-GP R3723 Do Not Stuff R3728
Do Not Stuff Do Not Stuff R3724 R3724 10KR2J-3-GP 10KR2J-3-GP R3729 R3729
PS/2
R3704 1 E51_TxD 2
DY
2 62 62 62 62 EC_SPI_DI EC_SPI_DO_R EC_SPI_CS# EC_SPI_CLK
KBC CLK PCLK_KBC EMI

2 R3734
Do Not Stuff
EC_SPI_DI EC_SPI_DO_R R3750 1 EC_SPI_CS# EC_SPI_CLK 1 R3731
2 33R2J-2-GP 2 33R2J-2-GP
86 87 90 EC_SPI_CLK_C 92 EC_SPI_DO
F_SDI F_SDO F_CS0# F_SCK
FIU
KBSIN0 KBSIN1 KBSIN2 KBSIN3 KBSIN4 KBSIN5 KBSIN6 KBSIN7 VCC_POR#
DY R3735 Stuff Do Not

1
DY
1 PCLK_KBC_RC
R3732 Do Not Stuff
PLT_RST1#_1 1
2 Do Not Stuff
PLT_RST# 11,21,58,76 NPCE781BA0DX-GP
DY
C3714 Do Not Stuff +KBC_PWR U3702 +KBC_PWR 1 1 ECRST#_C 2 GND
ECRST#
DJ1
76
AD_IA
DY C3716 Stuff Do Not

1 C3721 2
RESET#
DY VCC
3 39,42 PURE_HW_SHUTDOWN#
1 1
4K7R2J-2-GP R3737 2 2 ECRST#_C R3738 Do Not Stuff
Wistron Corporation
C3715 Do Not Stuff 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Document Number Custom Date:
1 3
DY
DY
Do Not Stuff
Do Not Stuff
Q3701 PMBS3906-GP
KBC Nuvoton NPCE781BA0DX

DJ1 Montevina UMA
Sheet
1
Rev
A00
5 4 3 2
A00
37 of 88
(Blanking)
DJ1
Wistron Corporation
5 4 3 2
Document Number
Reserved
Sheet
1
Rev
DJ1 Montevina UMA

A00
SSID = Thermal
+5V_RUN
+3.3V_RUN
1 2 2
C3908 C3905 SC10U6D3V5KX-1GP SCD1U16V2KX-3GP R3902 10KR2J-3-GP
EMC2102_FAN_TACH_1
D
EMC2102_FAN_TACH_1 EMC2102_FAN_DRIVE RN3901
58
D
EMC2102_FAN_DRIVE
58
3 4
2 1
SRN4K7J-8-GP
+3.3V_RUN
+3.3V_RUN
R3907 49D9R2F-GP
THERM_SCL 37 THERM_SDA 37
29
28
27
26
25
24
23 SMCLK
U3901
VDD_5Va
VDD_5Vb
SMDATA
GND
TACH
FANa
FANb
22
EMC2102_VDD_3D3
+3.3V_RUN
1.For CPU Sensor

8 H_THERMDC C3901
SC470P50V2JN-GP
H_THERMDA, H_THERMDC routing together, Trace width / Spacing = 10 / 10 mil
VDD_3V DN1 DP1 DN2 DP2 DN3 DP3 THERMTRIP# POWER_OK# SYS_SHDN# FAN_MODE SHDN_SEL TRIP_SET
NC#21 GND ALERT#
21 20 19 18 17 16 15
CLK_32K EMC2102_CLK_SEL
H_THERMDC H_THERMDA EMC2102_DN2
2 3 4 5 6 7
H_THERMDA Layout notice : Both DN2 and DP2 routing 10 mil trace width and 10 mil spacing. C3903
EMC2102
CLK_IN CLK_SEL RESET# NC#15
EMC2102_DP2 EMC2102_DN3
C388 must be near Q18

1 1 2
1 R3911
GND = Internal Oscillator Selected +3.3V = External 32.768kHz Clock Selected
Do Not Stuff
EMC2102_DP3
Q3904 PMBS3904-1-GP
84.03904.L06 1
DY
C3904 Do Not Stuff
SC470P50V2JN-GP
2.System Sensor, Put between CPU and NB.

C3907 must be near Q3902
C3909
GND = Channel 1 OPEN = Channel 3 +3.3V = Disabled

R3914
NC#8
C61 must be near EMC2102
1st SMSC 74.02102.A73 2nd GMT 74.07922.0B3

EMC2102-DZK-GP SRN10KJ-5-GP THERM_POWER_OK# THERMTRIP#
10
11
12
13
14
THERM_SYS_SHDN#
Q3903 PMBS3904-1-GP
84.03904.L06 1
DY
C3902 Do Not Stuff
SC470P50V2JN-GP
DY
R3909
EMC2102_SHDN
3 4
+3.3V_RTC_LDO RN3959
2 1
+3.3V_RUN
+3.3V_RUN
Do Not Stuff
C63 must be near EMC2102
+3.3V_RUN
2 1
+3.3V_RUN RN3960 SRN10KJ-5-GP
3.HW T8 sensor
Layout notice : Both DN3 and DP3 routing 10 mil trace width and 10 mil spacing.
B
DY
EMC2102_FAN_mode
THERMAL_P_HW_SHT Q3901
Do Not Stuff
3 4
1 R3906
G 2 S
1
R3905 10KR2F-2-GP
. . . . .
GND = Fan is OFF OPEN = Fan is at 60% full-scale +3.3V = Fan is at 75% full-scale
2N7002E-1-GP V_DEGREE
Do Not Stuff
PURE_HW_SHUTDOWN#
37,42
. .
TRIP_SET Pin Voltage V_DEGREE=(((Degree-75)/21)

R3915 2K37R2F-GP
T8 shutdown is set 88 deg-C.
32K suspend clock output
42
RUN_ENABLE 2N7002E-1-GP
22 ICH_SUSCLK_2102
A
. . . .
S
Q3902
CLK_32K_R
1 R3901
2 1
CLK_32K DJ1
A
Do Not Stuff
DY
C3912 Do Not Stuff
Wistron Corporation
Thermal/Fan Controllor EMC2102

DJ1 Montevina UMA
Sheet
1
Rev
A00
39 of 88
(Blanking)
DJ1
Wistron Corporation
5 4 3 2
Document Number
Reserved
Sheet
1
Rev
DJ1 Montevina UMA

A00
SSID = Reset.Suspend
+3.3V_ALW U4101
5
D
VCC Y
11
SM_PW ROK
1 2
SM_PW ROK_R
A B GND
1 2 3
S3_PW RGD 50 PM_SLP_S4# 22,37,50
R4101 12K1R2F-L1-GP NL17SZ08DFT2G-GP R4102 10KR2J-3-GP
DJ1
Wistron Corporation
5 4 3 2
Document Number Friday, February 26, 2010
Power On Logic
Sheet
1
Rev
DJ1 Montevina UMA

41 of 88
A00
SSID = Reset.Suspend
R4202 8,20 H_PW RGOOD
H_THRMTRIP# 8,11,20,37
C4202 2 1
DY
H_PW RGD_R
DY
C
Do Not Stuff
D
DY
Do Not Stuff
Q4202 Do Not Stuff

D
2
D4202 46 3V_5V_EN
3
BAS16-6-GP
PURE_HW _SHUTDOW N#
37,39
1 1 1 R4201
DY
2
Run Power
C
+15V_ALW
AO4468 MAX 11.6A RDS(ON) < 14m (VGS = 10V)

C
+3.3V_ALW _2 R4204
+5V_ALW
R4203 Do Not Stuff
2 1KR2J-1-GP
S5_ENABLE 37
+5V_RUN
RUN_ON_5V#
R4205 100KR2J-1-GP
R4206 Q4203 2N7002EDW -GP
AO4468-GP
100KR2J-1-GP
D G S
8 7 6 5 2 1
5V_RUN_ENABLE
D D D D
U4202 S S S G
1 2 3 4
MAX Current 2313.3 mA Design Current 1619.3 mA

+3.3V_RUN
1
R4211 100R2J-2-GP Q4205 RUN_ON_5V# G
10KR2J-3-GP
22,37,49,50 PM_SLP_S3# 39 RUN_ENABLE
RUN_ENABLE
+3.3V_ALW
+3.3V_RUN
2010/01/07
R4210
8 7 6 5
D D D D
U4203 S S S G AO4468-GP
1 2 3 4

2N7002E-1-GP
B
D4203 CH751H-40PT-GP
+1.5V_SUS
+1.5V_RUN
R4215
AO4468-GP
8 7 6 5 1
A
D D D D
U4201 S S S G
3.3V_RUN_ENABLE 2 10KR2J-3-GP 2
1 2 3 4

C4207 SC10U6D3V5KX-1GP DJ1
A
100KR2J-1-GP
C4208 SCD1U25V2KX-GP
1.5V_RUN_ENABLE
Q4205_D
C4201 SC6800P25V2KX-1GP
Title Size A3 Date:

5 4 3 2
. . . . . .
Wistron Corporation
Document Number
Power Plane Enable

Sheet
1
Rev
DJ1 Montevina UMA

42 of 88
A00
(Blanking)
DJ1
Wistron Corporation
5 4 3 2
Document Number
Reserved
Sheet
1
Rev
DJ1 Montevina UMA

A00
(Blanking)
DJ1
Wistron Corporation
5 4 3 2
Document Number
Reserved
Sheet
1
Rev
DJ1 Montevina UMA

A00
(Blanking)
DJ1
Wistron Corporation
5 4 3 2
Document Number
Reserved
Sheet
1
Rev
DJ1 Montevina UMA

A00
+3.3V_ALW
+3D3V_PWR PG4603 2 1
+3.3V_ALW_2 1 51125_VCLK 1 1 PR4602 100KR2J-1-GP 2 PC4603 SCD1U25V3KX-GP 1 3 PD3904_1 2 PC4604 SCD1U25V3KX-GP PC4602 SC1KP50V2KX-1GP
Do Not Stuff PG4604 2 1 Do Not Stuff PG4607 2 1 Do Not Stuff PG4609 2 1 1

4
51125_ENTRIP +PWR_SRC +PWR_SRC_3V D PG4634 2 PQ4602 51125_ENTIP1 1 1
Do Not Stuff PG4612 2 1 Do Not Stuff PG4613 1 2 Do Not Stuff PG4616 1 2 Do Not Stuff
Do Not Stuff PG4614 2 1 Do Not Stuff PG4617 2 1
2N7002E-1-GP 42 3V_5V_EN
Do Not Stuff PG4601 2 1
. . . . .
PC4605 Do Not Stuff
PD3903_1
Do Not Stuff PG4611 2 1
DY
PR4603 130KR2F-GP
PD4602 BAT54S-5-GP PQ4601 2N7002EDW-GP
PD4601 BAT54S-5-GP
+15V_ALW PG4615 Do Not Stuff 1 2 PD3903_2 1
+5V_PWR
51125_ENTIP2 1 PC4606 Do Not Stuff PC4607 SC1U25V3KX-1-GP 1
PD3903_04
Do Not Stuff
DY
2
+PWR_SRC_3V +PWR_SRC +PWR_SRC_5V PC4612 Do Not Stuff 1 1 1 1 PC4610 SCD01U50V2KX-1GP PC4611 SC10U25V6KX-1GP PC4613 SCD01U50V2KX-1GP +5V_PWR 1 PG4618 2 +5V_ALW 1 PG4602 2 +PWR_SRC +PWR_SRC_5V
DY
2
PC4609 SCD1U25V3KX-GP
PR4604 160KR2F-GP
1 PC4608 SCD1U25V3KX-GP
8 7 6 5
5 6 7 8
PC4614 PC4618 SC10U25V6KX-1GP SC10U25V6KX-1GP
PC4615 Do Not Stuff PG4621 1 2 SCD01U50V2KX-1GP
Design Current =7.6A 11.95A<OCP<14.12A
D D D D
Do Not Stuff PG4605 1 2 Do Not Stuff PG4606 1 2 Do Not Stuff PG4608 1 2 Do Not Stuff PG4610 1 2 Do Not Stuff
D D D D
16
PU4602 FDS8884-GP PC4616 SCD1U25V3KX-GP PR4605 0R3J-0-U-GP 1 251125_VBST2 51125_DRVH2 51125_LL2 9 10 11 12 7 5
PU4603
PU4604 FDS8884-GP PR4606 0R3J-0-U-GP
S
+3D3V_PWR PL4602 1 2 IND-2D2UH-111-GP Do Not Stuff Do Not Stuff 1 1 PTC4603 Do Not Stuff PTC4601 ST220U6D3VDM-15GP PR4607 2D2R5F-2-GP 2
51125_VBST2_1
VBST2 DRVH2 LL2 DRVL2 VO2 VFB2 EN0 ENTRIP2 VREF TONSEL SKIPSEL VREG3
VBST1 DRVH1 LL1 DRVL1 VO1 VFB1 PGOOD ENTRIP1 GND GND VCLK VREG5
22 21 20 19 24 2 23 1 15 25 18
51125_VBST1 51125_DRVH1 51125_LL1
51125_VBST1_1
SCD1U25V3KX-GP PC4617 1 2
Design Current = 7A 11A<OCP< 13A

+5V_PWR
Do Not Stuff PG4619 1 2 Do Not Stuff PG4620 1 2 Do Not Stuff PG4622 1 2 Do Not Stuff PG4625 1 2 Do Not Stuff PG4626 1 2 Do Not Stuff PG4627 1 2 Do Not Stuff
VIN
S S S G
S S S G
1 2 3 4
4 3 2 1
PL4601 1 2 IND-2D2UH-111-GP
PC4619 Do Not Stuff
D
8 7 6 5 D D D D PU4601 FDS6690AS-GP
PC4620
PG4623
PG4624
51125_FB2
51125_FB1 FDS6690AS-GP S S S G 3V_5V_POK 51125_ENTIP1
DY
20100118
1 2 3 4
G
SCD22U10V2KX-1GP
4 3 2 1
PC4622 SC680P-GP
1 PR4609
DY
51125_VREF 1 PC4623
3 51125_TONSEL 4 14 51125_SKIPSEL TPS51125RGER-GP
2 51125_EN 13 Do Not Stuff 51125_ENTIP2 6
S S S G
PC4621 SC680P-GP
1 2
PR4601 6K65R2F-GP 2
DY
1 2
PR4610 Do Not Stuff
DY
51125_VCLK
PR4611 Do Not Stuff
PR4612 33KR2F-GP 2
51125_FB1_R
3D3V_AUX_S5_5_51125 8
51125_FB2_R PC4601 DYDo Not Stuff
74.51125.073
+3.3V_ALW_2 1 PG4628 2
17
+5V_ALW2
+3.3V_ALW
PC4624 Do Not Stuff
DY
PR4615 51125_VREF +3.3V_ALW_2 51125_VREF 2
PR4613 10KR2F-2-GP 2
DYDo1Not Stuff
1 PR4617 2 Do Not Stuff 1 PR4618 2 Do Not Stuff PR4619 2 PR4620 2
Do Not Stuff
3V_5V_POK 37 PC4626 SC22U6D3V5MX-2GP PC4627

2
Close to VFB Pin (pin5)

+3.3V_ALW_2
DY DY
1 Do Not Stuff
1 Do Not Stuff
+3.3V_ALW_2 PR4621 1
+3.3V_RTC_LDO
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L Inductor: 2.2UH FDVE0630-2R2M=P3 TOKO 21mohm Isat =8.7Arms 68.2R21B.10A O/P cap: 220U 6.3V TLPSLV0J227M(15)12RE 15mOhm 2.887Arms NEC_TOKIN/77.C2271.31L H/S: FDSS8884 SO-8/ 23mohm/30mOhm@4.5Vgs/ 84.08884.037 L/S: FDS6690AS SO-8/ 12mohm/15mOhm@4.5Vgs/ 84.06690.E37
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L Inductor: 2.2UH FDVE0630-2R2M=P3 TOKO 21mohm Isat =8.7Arms 68.2R21B.10A O/P cap: 220U 6.3V PSLV0J227M(25) 25mOhm 2.236Arms NEC_TOKIN/77.C2271.00L O/P cap: 100U 6.3V TEPSLB20J107M(45)8R 45mOhm 1.374Arms NEC_TOKIN/77.C1071.081 H/S: FDSS8884 SO-8/ 23mohm/30mOhm@4.5Vgs/ 84.08884.037 L/S: FDS6690AS SO-8/ 12mohm/15mOhm@4.5Vgs/ 84.06690.E37
TONSEL GND VREF VREG3 VREG5 CH1 200kHz 245kHz 300kHz 365kHz CH2 265kHz 305kHz 375kHz 460kHz
2 Do Not Stuff
SKIPSEL Operating Mode
VREG3 or VREG5 OOA Auto Skip
VREF(2V) Auto Skip
GND PWM only
EN0 Operating Mode
Open
enable both LDOs, VCLK on and ready to turn on switcher channels
820k
to GND
GND disable all circuit
enable both LDOs, VCLK off and ready to turn on switcher channels
Do Not Stuff PG4631 1 2 PC4625 SC4D7U10V5KX-4GP
PR4616 100KR2J-1-GP
PR4614 21K5R2F-GP
51125_VO2
51125_VO1
PU4605
PR4608 2D2R5F-2-GP
PTC4602 ST220U6D3VDM-15GP
Do Not Stuff 2 1
DY
DY
5 6 7 8
51125_DRVL2
51125_DRVL1 D D D D
20100118
Do Not Stuff
SC10U6D3V5KX-1GP
DJ1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A2 Date:
A B C D
Document Number
TPS51125_5V/3D3V
Sheet
E
Rev
DJ1 Montevina UMA

Friday, February 26, 2010 46 of 88
A00
SSID = CPU.Regulator
+3.3V_RUN V5FILT
DY
1 PR4704 2 PR4706
51620_TRIPSEL
51620_PWRMON
TP4702
51620_VR_ON 1 Do Not Stuff VREF

D
2 PR4705 1
PR4708 1 2 499R2F-2-GP
CPUCORE_ON
37
+PWR_SRC
D
1 Do Not Stuff
2 PR4707
51620_TONSEL 51620_CLKEN# 51620_OSRSEL 51620_DPRSLPVR TP4701
1 PC4702
SC10U25V6KX-1GP
1 PC4706 2
PC4703 SC10U25V6KX-1GP
V5FILT VREF
DY
1 PR4710 2 PR4726
DPRSLPVR +3.3V_RUN
11,22 PU4702
PU4703 SI7686DP-T1-GP
1K91R2F-1-GP VGATE_PWRGD 22,37 84.07686.037 51620_ISLEW PR4712 V5FILT PC4701 SC1U10V3KX-3GP
1 124KR2F-GP
2 PR4711
4 3 2 1
4 3 2 1
84.07686.037 +VCC_CORE
1
51620_V5IN
2
2D2R3-1-U-GP
+5V_RUN
VREF PC4707 1 2 SC68P50V2JN-1GP
1 PR4709 2
1 PC4708
PC4709 51620_VBST1_R 1
2 5 6 7 8 5 6 7 8 1
PU4701 SIR460DP-T1-GE3-GP PU4704 SIR460DP-T1-GE3-GP PR4772 Do Not Stuff PG4632 Do Not Stuff
41
40 39 38 37 36 35 34 33 32 31
1 2
2 DY 1 1 DY 2 PR4714 PC4710 Do Not Stuff Do Not Stuff

VREF PC4711
DY
S S S G
1 PR4713 2 5K1R2F-2-GP
51620_DROOP
1 2
SC2D2U6D3V3KX-GP
SC1U25V3KX-1-GP
PL4701
1 2 L-D36UH-1-GP
PTC4703 Do Not Stuff PTC4701 ST330U2VDM-4-GP PTC4702 ST330U2VDM-4-GP D D D D D D D D
SCD1U25V3KX-GP
5 6 7 8
5 6 7 8
D D D D S S S G
D D D D
V5FILT ISLEW OSRSEL TONSEL TRIPSEL PWRMON VR_ON CLK_EN# DPRSLPVR PGOOD
GND
4 3 2 1
4 3 2 1
PR4719 9 VSS_SENSE
1 2 Do Not Stuff
PC4713 SC100P50V2JN-3GP
VR_TT# DPRSTP# PSI# VID6 VID5 VID4 VID3 VID2 VID1 VID0
2K7R2J-GP
PR4744
11 12 13 14 15 16 17 18 19 20
TPS51620RHAR-GP
PR4743
SCD033U16V2KX-GP
2009/10/30 X02
9 VCC_SENSE
1
0R3J-0-U-GP 51620_VBST2_R
51620_CSP1 PC4715 SC100P50V2JN-3GP 51620_CSN1
PC4716
8D2R2J-GP PC4718 SC100P50V2JN-3GP
1 PR4724 2 1
PR4721 1 2 470R2F-GP PC4714 SC100P50V2JN-3GP PR4723 1 2 470R2F-GP
51620_CSP1_R
CPU noise
51620_CSN1_R
PR4725 1
1 2
PG4711 2
SC1U25V3KX-1-GP PC4723 SCD1U25V3KX-GP 2 1 PC4719 SC10U25V6KX-1GP 2 1 PC4720 SC10U25V6KX-1GP 2 1 PC4721 SC10U25V6KX-1GP 2 1 PC4722 SC10U25V6KX-1GP 2 1 PC4724 SCD1U25V3KX-GP
Do Not Stuff
20KR2F-L-GP
5 6 7 8
PC4717 SC100P50V2JN-3GP
+PWR_SRC
Thermal Design Current = 34A PeakCurrent = 47A OCP >57.8A
5 6 7 8
PR4727 +1.05V_VCCP 8 CPU_PROCHOT# 8,11,20 H_DPRSTP# 8 9 CPU_VID[6..0] PSI#
51620AGND
56R2J-4-GP 51620_DPRSTP# 51620_PSI#
4 3 2 1
1 PR4729
2 Do Not Stuff
84.07686.037
84.07686.037 +VCC_CORE
4 3 2 1
1 PR4728
2 Do Not Stuff
PC4712 1
DY
PTC4704 Do Not Stuff
51620_CSP1 51620_CSN1 51620_CSN2 51620_CSP2 51620_GNDS 51620_VSNS 51620_THERM
SCD22U10V3KX-2GP
1 2 3 4 5 6 7 8 9 10
DROOP VREF GND CSP1 CSN1 CSN2 CSP2 GNDSNS VSNS THERM
DRVH1 VBST1 LL1 DRVL1 V5IN PGND DRVL2 LL2 VBST2 DRVH2
30 29 28 27 26 25 24 23 22 21
Do Not Stuff
51620_DRVH1 51620_VBST1 51620_LL1 51620_DRVL1 51620_DRVL2 51620_LL2 51620_VBST2 51620_DRVH2
DY PC4740
2
PR4715
2
56K2R2F-2-GP +PWR_SRC
PR4717
PR4718
2PR4717_R 1
2
20K5R2F-GP PTC4705 Do Not Stuff
PU4705
PR4742 0R3J-0-U-GP
SI7686DP-T1-GP
S S S G
PG4633
DY
Do Not Stuff
14KR2F-GP PR4716
S S S G
NTC-100K-10-GP
DY
D D D D D S S S G G
D D D D S S S G
CPU_VID6 CPU_VID5 CPU_VID4 CPU_VID3 CPU_VID2 CPU_VID1 CPU_VID0
PR4730 1 PR4731 1 PR4732 1 PR4733 1 PR4701 1 PR4734 1 PR4736 1
Do 2 Not Stuff Do 2 Not Stuff Do 2 Not Stuff Do 2 Not Stuff Do 2 Not Stuff Do 2 Not Stuff Do 2 Not Stuff
VID6 VID5 VID4 VID3
PL4702
1 2 L-D36UH-1-GP 5 6 7 8 5 6 7 8 1 1
PU4708 SIR460DP-T1-GE3-GP PU4709 SIR460DP-T1-GE3-GP
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L Inductor: 0.36UH ETQP4LR36WFC Irat =24Arms PANASONIC 1.1mohm/ 68.R3610.20A O/P cap: 330U 2V EEFSX0D331XE 6mOhm 3.0Arms Panasonic/79.33719.20L H/S: SI7686DP/ POWERPAK-8/ 11mOhm/14mOhm @4.5Vgs/ 84.07686.037 L/S: SiR460DP/ POWERPAK-8/ 4.9mOhm/6.1mohm@4.5Vgs/ 84.00460.037 NTC:TH11-3H103FT Mitsubishi 10Kohm /B-vaLue 3370K / 69.60026.001 Freq=300KHz@PER PHASE
DY PC4741
Do Not Stuff
PR4735 14KR2F-GP PR4737 1
56K2R2F-2-GP PR4738 PR4739
2PR4738_R 1
2
20K5R2F-GP
NTC-100K-10-GP PC4725 1 2
GND
A
VREF 20mV
3.3V 25mV
V5FILT
51620_CSP2
SCD033U16V2KX-GP PR4740 1 2 51620_CSP2_R 470R2F-GP PC4726 SC100P50V2JN-3GP PR4741 51620_CSN2_R 1 2 470R2F-GP
Do Not Stuff
4 3 2 1
4 3 2 1
VID2 VID1 VID0
PTC4708 ST330U2VDM-4-GP
PTC4707 ST330U2VDM-4-GP ST330U2VDM-4-GP
DYDo Not Stuff

S S S G
PG4629
TRIPSEL
15mV
30mV
PC4727 SC100P50V2JN-3GP 51620_CSN2
D D D D D S S S G
D D D D
Do Not Stuff
PR4773
PG4630
DJ1
OSRSEL TONSEL OVPSEL
Minimum 200KHz ENABLE
Medium 300KHz DISABLE
Maximum 400KHz N/A
OFF 500KHz N/A
PC4728 SC100P50V2JN-3GP Title
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
CPU VCORE POWER

Rev Friday, February 26, 2010
DJ1 Montevina UMA

Sheet 47
1
A00
of 88
(Blanking)
DJ1
Wistron Corporation
5 4 3 2
Document Number
CPU VCORE POWER(2/2)

DJ1 Montevina UMA
Sheet
1
Rev
A00
of 88
W ednesday, February 24, 2010
48
+1.05VTT_PWR
+1.05V_VCCP
+1.05VTT_PWR
+1.05V_VCCP
SSID = PWR.Plane.Regulator_1p05v
PG4902 1 2 Do Not Stuff PG4904 1 2 Do Not Stuff PG4906 1 2
PG4903 1 2 Do Not Stuff PG4905 1 2 Do Not Stuff PG4907 1 2 Do Not Stuff PG4910 1 2 Do Not Stuff PG4912 1 2 Do Not Stuff PG4916 1 2 Do Not Stuff PG4918 1 2 Do Not Stuff
+PWR_SRC
+1.05V_VTT_PWR_SRC PG4908 1 2
TPS51218 for +1.05V_VCCP

+1.05V_VTT_PWR_SRC Do Not Stuff PM_SLP_S3#
Do Not Stuff PG4909 1 2 Do Not Stuff PG4911 1 2 Do Not Stuff PG4914 1 2 PC4903 PC4903 Do Not Stuff PG4917 1 2 Do Not Stuff SC10U25V6KX-1GP SC10U25V6KX-1GP SC10U25V6KX-1GP SCD1U50V3KX-GP SC4D7U25V5KX-GP
+5V_RUN
2
PD4901
5 6 7 8
100KR2J-1-GP +3.3V_RUN 37 PR4902 1
1
PR4901 S S S S S G
DY
PC4902
PC4904
PC4905
D D D D D D
RUNPWROK
22,37,42,50 PM_SLP_S3#
C
SCD1U10V2KX-5GP 2 1
PTC4902 SE220U2VDM-8GP
51218_SW_GND_VTT 2
PU4901 D D D D D S S S G 51218_DRVL_VTT
4 3 2 1
5 6 7 8
1.05V_VTT 10KR2F-2-GP PR4906 2 1
SIR460DP-T1-GE3-GP
R1
PC4910 SC330P50V2KX-3GP
VTT_SENSE 20KR2F-L-GP
PR4908
R2
Frequency setting 470K -->290KHz 200K -->340KHz 100K -->380KHz 39K -->430KHz
Vout=0.704V*(R1+R2)/R2
B
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L Inductor: 1uH FDUE1040D-1R0M=P3 TOKO DCR:2.35mohm Isat =17.9Arms 68.1R01B.10A O/P cap: 220U 2V EEFCX0D221R 15mOhm 2.7Arms PANASONIC/ 79.22719.20L H/S: SI7686DP-T1-E3/11mohm/ 14mOhm@4.5Vgs/ 84.07686.037 L/S: SIR460DP-T1-GE3-GP/4.5mOhm/6.1mohm@4.5Vgs/ 84.00460.037
84K5R2F-GP 51218_1.05VTT_TRIP 2 +1.05V_EN 1 2 VTT_SENSE PR4907 120KR2J-GP 51218_1.05VTT_CCM 1 2 PD4902 PR4904 CH751H-40PT-GP 470KR2F-GP
PR4905 PC4907 SC1U6D3V2KX-GP
2D2R5J-1-GP
TPS51218DSCR-GP-U1
51218_DRVL_VTT
PC4909
1 2 3 4 5
PGOOD TRIP EN VFB RF
GND VBST DRVH SW V5IN DRVL
11 10 9 8 7 6
51218_VBST_VTT
1 PR4903 2 51117B_LL1_VTT 2 1R3F-GP

+5V_ALW
4 3 2 1
PU4903
A00
Design Current = 13.7A 21.55A<OCP<25.47A

PL4901 +1.05VTT_PWR SC4D7U6D3V5KX-3GP PC4908 Do Not Stuff
51218_DRVH_VTT 51218_SW_VTT
1 2 IND-1UH-80-GP
PG4919
PC4901
SCD1U16V2KX-3GP
DJ1
Wistron Corporation
TPS51218_+1.05V_VCCP
5 4 3 2
Rev
DJ1 Montevina UMA

Sheet
1
A00
49 of 88
SSID = PWR.Plane.Regulator_1p5v0p75v
+5V_ALW PR5002 5D1R3J-GP +5V_ALW
PR5015 1 11KR2F-L-GP
2 2
51116_VDD PC5004 SC1U10V3KX-3GP
+5V_ALW
+3.3V_ALW
PC5002 SC1KP50V2KX-1GP
1 2
DY
2
PD5001 Do Not Stuff
16
14
15 VDDP
ILIM
VDDP
PR5005 20KR2J-L2-GP
PU5002 PR5007 1
RT: Non_ASM TI: ASM
+5116_PWR_SRC 41 S3_PWRGD
13
BST DH
22 TPS51116_VBST1 21 TPS51116_UGT
2 TPS51116_VBST
PGD NC#12 EN/PSV VTTEN VTTIN DL NC#7 19 TPS51116_LGT LX 20 TPS51116_PHS
0R3J-0-U-GP
PR5006 1 22,37,41 PM_SLP_S4# R5017 1
DY
2
C5022
2 Do Not Stuff
SCD1U16V2KX-3GP
12 11
0D75V_EN 10
10KR2J-3-GP
+1.5V_SUS_P +PWR_SRC 22,37,42,49 PM_SLP_S3# 22,37,41 PM_SLP_S4# +5116_PWR_SRC PG5003 1
+1.5V_SUS_P
+1.5V_SUS PG5002 2
23 1 7 2 1 4
+5V_ALW +1.5V_SUS_P
PC5005 PR5008 SC1U10V3KX-3GP 1 2 Do Not Stuff
1 PR5003 2 Do Not Stuff

PR5004 1
0D75V_EN
DY
TPS51116RGER-GP-U
PGND2 TON VDDQS 24 2 VTT VTTS VSSA GND VCCA REF FB PGND1 PGND1 18 17 8 9 6 1
TPS51116_VDDQSNS 51116_VDDQSET +5V_ALW PR5010
DY
2 Do Not Stuff
DY
2
PC5001 Do Not Stuff
Do Not Stuff PG5004 1 2 Do Not Stuff PG5005 1 2 Do Not Stuff PG5007 1 2 Do Not Stuff PG5009 1 2 Do Not Stuff PG5010 1 2 Do Not Stuff PG5011 1 2
1 PR5009 2
Do Not Stuff PC5006 +0D75V_DDR_P Do Not Stuff
DY
DY
+5116_PWR_SRC
Do Not Stuff Do Not Stuff PC5012 SC4D7U25V5KX-GP PC5009 SC10U25V6KX-1GP PC5010 SC10U25V6KX-1GP PC5011 SCD1U50V3KX-GP
25
1 PR5011 2 Do Not Stuff

+V_DDR_REF
DY PC5007
5 6 7 8
Design Current = 0.7A

+0D75V_DDR_P
PU5003 FDS8880-NL-GP S S S G G
Design Current = 9.82A 15.43A<OCP< 18.24A
D D D D D
Do Not Stuff PG5012 1 2 Do Not Stuff PG5013 1 2
PC5013 SCD1U10V2KX-5GP
SC10U6D3V5KX-1GP PC5014
+0D75V_DDR_P +0.75V_DDR_VTT PG5014 1 2 Do Not Stuff PG5016 1 2 Do Not Stuff
4 3 2 1
+1.5V_SUS_P TPS51116_UGT TPS51116_VBST 1 PL5001
TPS51116_PHS
Do Not Stuff PG5015 1 2 Do Not Stuff

B
PC5019 SCD1U10V2KX-5GP
PG5017 Do Not Stuff
PTC5002 Do Not Stuff
PC5018 SC4D7U6D3V5KX-3GP
1 2 IND-1D5UH-55-GP
5 6 7 8
DY
2 1
PR5012 Do Not Stuff
DY
2
1 2
D D D D D S S S G G
PU5001 FDS6676AS-GP
TPS51116_PHS_SET
20100118
State S0 S3 S4/S5
S3 Hi Lo Lo
S5 Hi Hi Lo
VDDR On On Off
VTTREF On On Off On
VTT Off(Hi-Z) Off

TPS51116_LGT
DY PC5020 Stuff Do Not

1
TPS51116_VDDQSNS PR5013 30KR2F-GP 51116_VDDQSET
4 3 2 1
DY
1 2 2 2
1
PC5021 Do Not Stuff PR5014 30KR2F-GP
VDDQSET GND
A
VDDQ (V) 2.5 1.8 Adjustable
VTTREF and VTT VVDDQSNS/2 VVDDQSNS/2 VVDDQSNS/2
NOTE DDR DDR2 1.5 V < VVDDQ < 3 V
V5IN FB Resistors
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L Inductor: 1.5UH FDVE1040-1R5M=P3 DCR:4.6mohm Isat =13.7Arms TOKO/ 68.1R51A.10G O/P cap: 330U 2.5V EEFCX0E331QR 15mOhm 2.7Arms PANASONIC/ 79.3371V.20L H/S: FDS8880 SO-8/9.6mohm/ 12mOhm@4.5Vgs/ 84.08880.037 L/S: FDS6676AS/ 5.9mOhm/7.25mohm@4.5Vgs/ 84.06676.A37 Switching freq-->400KHz

DJ1
A
Wistron Corporation
TPS51116_+1.5V_SUS
5 4 3 2
Rev
DJ1 Montevina UMA

Sheet
1
A00
50 of 88
(Blanking)
DJ1
Wistron Corporation
5 4 3 2
Document Number
(Reserved)
Sheet
1
Rev
DJ1 Montevina UMA

A00
(Blanking)
DJ1
Wistron Corporation
5 4 3 2
Document Number
Reserved
Sheet
1
Rev
DJ1 Montevina UMA

A00
(Blanking)
DJ1
Wistron Corporation
5 4 3 2
Document Number
Reserved
Sheet
1
Rev
DJ1 Montevina UMA

A00
SSID = VIDEO
LVDS CONNECTOR
GFX_PW R_SRC LCD1
D
SSID = Inverter
INVERTER POWER
RN5401 LCD_CBL_DET#_C LCD_TST_C BLON_OUT_C LCD_DET_G C5404 SC1U6D3V2KX-GP
+LCDVDD
49
SCD1U10V2KX-5GP C5401 2 1
47
LCD_BRIGHTNESS LCD_CBL_DET#_C BLON_OUT_C LCD_TST_C
+3.3V_RUN
R5417
2 100R2J-2-GP
LBKLT_CTL 13
45
LCD_DET_G
LDDC_CLK 13 LDDC_DATA 13 VGA_TXAOUT0- 13 VGA_TXAOUT0+ 13 VGA_TXAOUT1- 13 VGA_TXAOUT1+ 13 VGA_TXAOUT2- 13 VGA_TXAOUT2+ 13 VGA_TXACLK- 13 VGA_TXACLK+ 13
R5418 100KR2J-1-GP
44
46
43
42
51 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 50
1 2 3 4
8 7 6 5
LCD_CBL_DET# 37 LCD_TST 37 BLON_OUT 37
GFX_PW R_SRC F5401
+PW R_SRC
SRN100J-4-GP
2 1 2
POLYSW -1D1A24V-GP-U C5403 SCD1U50V3KX-GP
USB_CAMERA# USB_CAMERA +3.3V_CAMERA
Do Not Stuff
1 R5409 1 R5412
2 2
Do Not Stuff
USB_PN11 21 USB_PP11 21
2010/01/05
SSID = VIDEO
+3.3V_RUN
41 48
IPEX-CONN40-2R-GP-U 20.F1093.040
LCD POWER
Q5401 1 D 2 D 3 G D 6 D 5 S 4 +LCDVDD
+15V_ALW
1 C5411 1 R5415
2 FPVCC_CTL1 SCD068U50V-GP
R5413 120R3J-2-GP
330KR2J-L1-GP 2 R5414 1
SI3456DDV-T1-GE3-GP
DY
2 Do Not Stuff 4 5 6
Q5402
3 2 1
2N7002EDW -GP
LCDVDD_1
13
LCDVDD_EN D4102 BAT54C-U-GP +3.3V_ALW Q4103
1 R5416 3 OUT
2 47KR2J-2-GP
FPVCC_CTL3
ENVDD_D
2 IN
R1 R2
1 GND
DDTC144EUA-7F-GP
37
LCD_TST_EN
X01
A
Camera Power
+3.3V_RUN R5411 +3.3V_CAMERA
LBKLT_CTL LCD_TST EC5405 Do Not Stuff EC5406 Do Not Stuff DJ1

A
2 1 1
Wistron Corporation
3 2
EC5403 Do Not Stuff
DY
Do Not Stuff
DY
DY
Document Number
LCD/Inverter Connector
DJ1 Montevina UMA
Sheet
1
Rev
For EMI request

5 4
A00
of 88
54
SSID = VIDEO
+5V_CRT_RUN CRT1
16
CRT_R RN5501 SRN2K2J-1-GP CRT_G CRT_B +5V_CRT_RUN 13 DDC_DATA_CON 13 DDC_CLK_CON DDC_DATA_CON DDC_CLK_CON
6 1 7 2 8 3 9 4 10 5 17
1 2
11 12 13 14 15
DDC_DATA_CON JVGA_HS JVGA_VS DDC_CLK_CON Do Not Stuff C5515 Do Not Stuff C5516 2 1
D
Layout Note: *Pi-filter & 150 Ohm pull-down resistors should be as close as to CRT CONN. * RGB signal will hit 75 Ohm first, then pi-filter, finally CRT CONN.
4 3
1 1
2 2
C5514 SC22P50V2JN-4GP
L5501 13 M_RED
BLM15BB220SS1D-GP
AFTP5501 AFTP5508 AFTP5503 AFTP5506 AFTP5507 AFTP5504 CRT_R TP5505 TP5509 CRT_G
1 1 1 1 1 1 1 1
+5V_CRT_RUN DDC_DATA_CON DDC_CLK_CON CRT_R CRT_G CRT_B JVGA_HS JVGA_VS
1
L5502
2
BLM15BB220SS1D-GP
13
M_GREEN
1
L5503
2
BLM15BB220SS1D-GP
2010/01/15
2
C5507 SC8P250V2CC-GP C5508 SC8P250V2CC-GP CRT_B C5509 SC8P250V2CC-GP
C
13
C
M_BLUE C5504 Do Not Stuff C5505 Do Not Stuff R5501 150R2F-1-GP R5502 150R2F-1-GP R5503 150R2F-1-GP C5506 Do Not Stuff
1 1 1 1 1 1 1
DY
DY
DY
AFTP5502
VIDEO-15-127-GP-U 20.20401.015
DY
DY
+5V_CRT_RUN
+5V_RUN D5502
A00
+5V_CRT_RUN D5501
+5V_RUN
+5V_CRT_RUN C5511 SCD01U16V2KX-3GP
A
RB551V-30-2GP
14
CRT_R C5512 Do Not Stuff
Hsync & Vsync level shift

14 13
DY
DY
1
DY
7
Do Not Stuff D5503 U5501D
U5501A Do Not Stuff
2
HSYNC_5 CRT_G
13 GMCH_HSYNC
12 14
DY
7
11
DY
1
+5V_CRT_RUN
Do Not Stuff RN5502 VSYNC_5 Do Not Stuff
U5501B
13 GMCH_VSYNC
DY
7
3 4
DY
2 1
JVGA_HS JVGA_VS D5504
14
10
Do Not Stuff Do Not Stuff CRT_B
DJ1
2 3
DY
7
DY
1
U5501C Do Not Stuff Title
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
1 R5506
2 Do Not Stuff
Do Not Stuff
A00
5 4 3 2
CRT Connector
Size Date: Document Number Rev
DJ1 Montevina UMA

Friday, February 26, 2010 Sheet
1
A00
of 88
55
(Blanking)
DJ1
Wistron Corporation
5 4 3 2
Document Number
Reserved
Sheet
1
Rev
DJ1 Montevina UMA

A00
(Blanking)
DJ1
Wistron Corporation
5 4 3 2
Document Number W ednesday, February 24, 2010
HDMI
Sheet
1
Rev
DJ1 Montevina UMA

57 of 88
A00
SSID = User.Interface
ITP Connector
D
+3.3V_RUN DEBUG1 R5801 LPC_LAD0_IN LPC_LAD1_IN LPC_LAD2_IN LPC_LAD3_IN LPC_LFRAME#_IN R5802 1 R5804 1 1 R5805
H_CPURST# use pull-up Resistor close ITP connector 500 mil ( max ), others place near CPU side.
1 DY 2Do Not Stuff LPC_LAD0 LPC_LAD1 DY 2Do Not Stuff 1 R5803 DY 2Do Not Stuff LPC_LAD2 Do LPC_LAD3 2 Not Stuff DY 2 LPC_LFRAME# 20,37 DYDo Not Stuff 1 2 DYDo Not Stuff PLT_RST# 11,21,37,76 R5806
PCLK_FW H 7
DY
1 2 3 4 5 6 7 8 9 10 11 12
LPC_LAD[0..3]
20,37
Do Not Stuff Do Not Stuff
CPU
TCK(PIN AC5)
ITP Connector
TCK(PIN 5) FBO(PIN 11)
SSID = Thermal
Fan Connector
B B
3
FAN1 39 EMC2102_FAN_TACH_1 39 EMC2102_FAN_DRIVE EMC2102_FAN_TACH_1 AFTP5801 EMC2102_FAN_DRIVE
5 3 2 1 4
FOX-CON3-6-GP-U 20.D0210.103
*Layout* 20 mil
K 1
D5801 C5801 RB551V-30-2GP SC10U6D3V5KX-1GP
AFTP5802 AFTP5803
1 1
EMC2102_FAN_TACH_1 EMC2102_FAN_DRIVE
DJ1
Wistron Corporation
5 4 3 2
Document Number
ITP/Fan Connector
Sheet
1
Rev
DJ1 Montevina UMA

A00
SSID = SATA
SATA HDD Connector

D D
+3.3V_RUN
1
1
C5901 Do Not Stuff
DY
HDD1
P1 P2 P3
+5V_RUN
V33 V33 V33 V5 V5 V5 V12 V12 V12 A+ AB+ B-
23 24 NP1 NP2
23 24 NP1 NP2
P7 P8 P9 P13 P14 P15 S2 S3
20 20 20 SATA_RXP0_C 20 SATA_RXN0_C
C
SATA_TXP0 SATA_TXN0 SCD01U50V2KX-1GP SCD01U50V2KX-1GP
1 1
2 C5904 2 C5905
SATA_RXP0 SATA_RXN0
S6 S5
GND GND GND GND GND GND GND GND DAS/DSS
S1 S4 S7 P4 P5 P6 P10 P12 P11

C
SKT-SATA7P-15P-23-GP
ODD Connector
B B
ODD1
8 NP1 S1 S2 S3 S4 S5 S6 S7 P1 P2 P3 P4 P5 P6 NP2 9
SKT-SATA7P-6P-4-GP SATA_TXP1_DJ2 SATA_TXN1_DJ2 SATA_RXN1 SATA_RXP1
A00
Do Not Stuff 1 R5901 2 1 R5902 2 Do Not Stuff SCD01U50V2KX-1GP SCD01U50V2KX-1GP SATA_TXP1 SATA_TXN1 20 20
1 1
2 C5907 2 C5908
SATA_RXN1_C 20 SATA_RXP1_C 20
SATA_RX- and SATA_RX+ Trace Length match within 20 mil

+5V_RUN
SCD1U10V2KX-5GP 2 1
22.10300.811 2010/01/05
A
C5909
DJ1
Wistron Corporation
5 4 3 2
HDD/ODD
Sheet
1
Rev
DJ1 Montevina UMA

59 of 88
A00
SSID = AUDIO
Speaker Connector
D
LINE1 OUT
D
SPK1 LINEOUT1 30 AUD_HP1_JD# 30 AUD_HP1_JACK_L 30 AUD_HP1_JACK_R AUD_HP1_JD# L6001
30 30 30 30
AUD_SPK_LAUD_SPK_L+ AUD_SPK_RAUD_SPK_R+ EC6001 Do Not Stuff EC6002 Do Not Stuff EC6003 Do Not Stuff EC6004 Do Not Stuff
1 2 3 4
FOX-CON4-19-GP 20.F0711.004
EC6005 SCD01U16V2KX-3GP
DY
DY
DY
DY
EC6006 SCD01U16V2KX-3GP
1 R6012 60D4R2F-GP 1 R6011 60D4R2F-GP
2 2
AUD_HP1_JACK_L2 AUD_HP1_JACK_R2
1 1
L6002
BLM15BD601SS1D-GP 2 BLM15BD601SS1D-GP 2
AUD_HP1_JACK_L1 AUD_HP1_JACK_R1
8 7 3 1 4 2 5 6 1
1
AFTP6002 AFTP6003 AFTP6004 AFTP6005
C
1 1 1 1
AUD_SPK_LAUD_SPK_L+ AUD_SPK_RAUD_SPK_R+
1 1 1
AUD_HP1_JD# AUD_HP1_JACK_L1 AUD_HP1_JACK_R1

C
600ohm 100MHz 200mA 0.5ohm DC
2010/01/08
Internal Microphone
MIC IN
C6001 SC1U10V3KX-3GP 30 AUD_VREFOUT_B
2 1
RN6001 SRN4K7J-8-GP
3 4
30 INT_MIC_L_R
1 1 2
MIC1 Do Not Stuff Do Not Stuff AUD_EXT_MIC_L C6002
A00
B
EC6010 SC1KP50V2KX-1GP
AFTP6009
PHONE-JK383-GP 22.10133.K31
MICIN1
30 AUD_EXT_MIC_L
1 SC1U10V3KX-3GP
MIC_IN_L_2
R6009 1 2 Do Not Stuff R6010
MIC_IN_L_C
8 7 3 1 4 2 5 6
PHONE-JK383-GP 22.10133.K31
30 AUD_EXT_MIC_R AUD_AGND
AUD_EXT_MIC_R C6003
1 SC1U10V3KX-3GP
MIC_IN_R_2
1 2 Do Not Stuff
MIC_IN_R_C
30 EXT_MIC_JD# EC6008 SC100P50V2JN-3GP 2 1 EC6009 SC100P50V2JN-3GP
AFTP6006 G6001 AFTP6007
1 1 1
MIC_IN_L_C MIC_IN_R_C EXT_MIC_JD#
2
Do Not Stuff
A
AFTP6008
AUD_AGND
DJ1
AFTP6001
Wistron Corporation
5 4 3 2
Document Number
Audio Jack/Mic/Speaker
DJ1 Montevina UMA
Sheet
1
Rev
A00
60 of 88
(Blanking)
DJ1
Wistron Corporation
5 4 3 2
Document Number
Reserved
Sheet
1
Rev
DJ1 Montevina UMA

A00
SSID = Flash.ROM
SPI FLASH ROM (16M bits) for KBC
+KBC_PW R +KBC_PW R C6203 SCD1U16V2KX-3GP
DY
RN6201 SRN100KJ-6-GP
4 3
R6202 Do Not Stuff
DY
2 1 2
EC_SPI_HOLD#
C6202 Do Not Stuff
U6201 37 EC_SPI_CS# 37 EC_SPI_DI 37 EC_SPI_W P#_R R6201 1 R6203 1
+KBC_PW R
2 33R2J-2-GP 2 1
EC_SPI_CS# EC_SPI_DI_R EC_SPI_W P#
Do Not Stuff R6209 100KR2J-1-GP R6210 10KR2J-3-GP
1 2 3 4
CS# SO/SIO1 WP#/ACC GND
VCC HOLD# SCLK SI/SIO0
8 7 6 5 1
Do Not Stuff 2 1 EC6202
EC_SPI_DO_R EC6203 Do Not Stuff
EC_SPI_CLK 37 EC_SPI_DO_R 37
EC6201 Do Not Stuff
DY
2
MX25L1605DM2I-12G-GP
72.25165.A01
2nd 72.25016.D01 A00
DY DY
SSID = RBATT
RTC Connector
+3.3V_RTC_LDO +RTC_CELL D6203
2 3
A
+RTC_VCC R6208
RTC1
1
RTC_PW R
2
TP6201
1KR2J-1-GP SDMG0340LC7F-GP-U
Width=20mils
1 2 NP1 NP2
PWR GND NP1 NP2

BAT-CON2-1-GP-U
DJ1
Wistron Corporation
2
2010/01/15
TP6202
62.70001.011
1
+RTC_VCC
2010/01/05
Flash/RTC
Sheet
1
Rev
DJ1 Montevina UMA

62 of 88
A00
SSID = USB
IO Board USB Power
+5V_ALW U6302
D
+5V_USB1
at least 80 mil
37 USB_PW R_EN# C6306 SCD1U10V2KX-5GP
1 2 3 4
GND VIN VIN EN#
VOUT#8 VOUT#7 VOUT#6 OC#
8 7 6 5
at least 80 mil
D
1
USB_OC#0_1 21
UP7534BRA8-15-GP
74.07534.079 2nd 74.09715.079 20100111
USB Socket
+5V_USB2 USB1
Right USB Power

+5V_ALW U6301 +5V_USB2 C6301 SCD1U10V2KX-5GP C6302 SC1U10V3KX-3GP
5 1
USB_P2USB_P2+
7
C
R6301 Do Not Stuff
37 USB_PW R_EN# C6303 SCD1U10V2KX-5GP
GND VIN VIN EN#
VOUT#8 VOUT#7 VOUT#6 OC#
TC6301 ST100U6D3VBML1GP
at least 80 mil
1
1 2 3 4
8 7 6 5
at least 80 mil
1 1 1 1
2 3 4 6
SKT-USB8-29-GP 22.10254.451
USB_OC#2_3 21
74.07534.079
2nd 74.09715.079 20100111
UP7534BRA8-15-GP
DY
+5V_USB2
USB3
5 1
USB_P3USB_P3+
21 21
USB_PN2 USB_PP2
USB_PN2 USB_PP2
Do Not Stuff 1 R6302 2
2 3 4 6
SKT-USB8-29-GP 22.10254.451
USB_P2+5V_USB2 USB_P2+ D6301 1
4
B
2010/01/05
21 21 USB_PN3 USB_PP3 USB_PN3 USB_PP3 Do Not Stuff 1 R6304 2 USB_P3USB_P3+ USB_P2+
DY
2
Do Not Stuff
USB_P2-
AFTP6304 AFTP6302 AFTP6301 AFTP6306 AFTP6305
1 1 1 1 1
+5V_USB2 USB_P2USB_P2+ USB_P3USB_P3+
+5V_USB2 D6302
DY
USB_P3+
A
2
Do Not Stuff
USB_P3DJ1
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
USB
Size Date:
5 4 3 2
Document Number
Rev
DJ1 Montevina UMA

Friday, February 26, 2010 Sheet
1
A00
of 88
63
(Blanking)
DJ1
Wistron Corporation
5 4 3 2
Document Number
Reserved
Sheet
1
Rev
DJ1 Montevina UMA

A00
(Blanking)
DJ1
Wistron Corporation
5 4 3 2
Document Number
Reserved
Sheet
1
Rev
DJ1 Montevina UMA

A00
SSID = LED
Power LED
PDTA144VT-GP PW R_LED# +5V_ALW LED-W -27-GP K A R2 Q6605
Power button LED

D
E C
PW R_LED_R
83.01221.R70
Battery LED
White
LED-OW -3-GP Q6601 37 BATCHG R6601
+5V_ALW
R1
C E
LED_BATCHG#
1 1
BATCHG_LED_B
3 1 2
LED1
330R2J-3-GP EC6601 Do Not Stuff
R2 PDTC124EU-1-GP
DY
83.00326.G70
R6602 Q6602
B
Amber
2
BAT_LED_B
B
37 BATLOW _LED
R1
C E
LED_BAT#
1 1
330R2J-3-GP EC6602 Do Not Stuff
R2 PDTC124EU-1-GP
HDD LED
PDTA144VT-GP SATA_LED#
+5V_RUN LED-W -27-GP K A
E C
SATA_LED_R
DY
Q6604
R1
20
SATA_LED#
R6604
SATA_LED_B
330R2J-3-GP
LED2
83.01221.R70
Title Size A3 Date:
4 3 2
R1
37
PW R_LED#
R6605
PW R_LED_B
330R2J-3-GP
LED3
R2 R2
DJ1
Wistron Corporation
LED
Sheet
1
Rev
DJ1 Montevina UMA

66 of 88
A00
(Blanking)
DJ1
Wistron Corporation
5 4 3 2
Document Number
Reserved
Sheet
1
Rev
DJ1 Montevina UMA

A00
SSID = KBC
SSID = Touch.Pad
Internal KeyBoard Connector

KB1
TouchPad Connector
+5V_RUN
1 31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 32
ACES-CON30-3-GP KROW 7 KROW 6 KROW 4 KROW 2 KROW 5 KROW 1 KROW 3 KROW 0 KCOL5 KCOL4 KCOL7 KCOL6 KCOL8 KCOL3 KCOL1 KCOL2 KCOL0 KCOL12 KCOL16 KCOL15 KCOL13 KCOL14 KCOL9 KCOL11 KCOL10
AFTP6831 KB_DET# 37 C6802 SCD1U16V2KX-3GP TP1
1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
AFTP6827 AFTP6825 AFTP6824 AFTP6822 AFTP6823 AFTP6820 AFTP6821 AFTP6819 AFTP6817 AFTP6818 AFTP6816 AFTP6814 AFTP6812 AFTP6813 AFTP6815 AFTP6810 AFTP6808 AFTP6809 AFTP6806 AFTP6807 AFTP6804 AFTP6805 AFTP6803 AFTP6801 AFTP6802
+5V_RUN
KROW [0..7] KCOL[0..16]
37 37 37 37 TPCLK TPDATA
RN6801 SRN10KJ-5-GP
1 2
5 4 3 1 2 3 4
C
AFTP6811
2 2
6
ACES-CON4-10-GP-U 20.K0320.004
1 1 1
+5V_RUN TPCLK TPDATA
20.K0421.030 2nd 20.K0461.030
DJ1
Wistron Corporation
5 4 3 2
Document Number
Key Board/Touch Pad

Sheet
1
Rev
DJ1 Montevina UMA

A00
+3.3V_ALW
Hall switch
2
HSC1
VDD VSS OUT
LID_CLOSE#_1
S-5711ACDL-M3T1S-GP
20100114
+3.3V_ALW
A00 DY R6902 100KR2J-1-GP

2
B
1
LID_CLOSE#
37
LID_CLOSE#
1 R6901
2 10R2J-2-GP
LID_CLOSE#_1
C6901 SCD047U16V2KX-1-GP
DJ1
Wistron Corporation
5 4 3 2
Hall Sensor
Sheet
1
Rev
DJ1 Montevina UMA

69 of 88
A00
(Blanking)
DJ1
Wistron Corporation
5 4 3 2
Document Number
Reserved
Sheet
1
Rev
DJ1 Montevina UMA

A00
SSID = SDIO
SD/XD/MS Card Reader

D
+3.3V_RUN_CARD
DY
DY
DY
C7101 Do Not Stuff
C7102 Do Not Stuff
C7103 Do Not Stuff
2010/01/15
TP7112 TP402 TP403 TP404 TP405 TP406 TP407 TP408 TP409 TP410 TP411 TP412 TP413 TP414 TP415 TP416 TP417 XD_CD# XD_RDY/SD_W P/MS_CLK XD_RE#/MS_INS# XD_CE#/SD_D1 XD_CLE/SD_D0/MS_D7 XD_ALE/SD_D7/MS_D3 XD_W E#/SD_CD# XD_W P/SD_D6/MS_D6 XD_D0/SD_CLK/MS_D2 XD_D1/SD_D5/MS_D0 XD_D2/SD_CMD XD_D3/SD_D4/MS_D4 XD_D4/SD_D3/MS_D1 XD_D5/SD_D2/MS_D5 XD_D6/MS_BS XD_D7 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
+3.3V_RUN_CARD
CARD1
23 14 33 8 9 26 27 28 30 31 32 1 2 3 4 5 6 7 34 NP1 NP2
SD_VCC MS_VCC XD_VCC XD_D0 XD_D1 XD_D2 XD_D3 XD_D4 XD_D5 XD_D6 XD_D7 XD_R/B XD_RE XD_CE XD_CLE XD_ALE XD_WE XD_WP XD_CD_SW NP1 NP2
CARDBUS36P-1-GP
SD_DAT0 SD_DAT1 SD_DAT2 SD_DAT3 SD_CMD SD_CLK SD_CD_SW SD_WP_SW MS_DATA0 MS_DATA1 MS_DATA2 MS_DATA3 MS_BS MS_INS MS_SCLK 4IN1_GND 4IN1_GND 4IN1_GND 4IN1_GND
25 29 10 11 12 24 36 35 19 20 18 16 21 17 15 13 22 38 37
XD_CLE/SD_D0/MS_D7 32 XD_CE#/SD_D1 32 XD_D5/SD_D2/MS_D5 32 XD_D4/SD_D3/MS_D1 32 XD_D2/SD_CMD 32 XD_D0/SD_CLK/MS_D2 32 XD_W E#/SD_CD# 32 XD_RDY/SD_W P/MS_CLK 32 XD_D1/SD_D5/MS_D0 32 XD_D4/SD_D3/MS_D1 32 XD_D0/SD_CLK/MS_D2 32 XD_ALE/SD_D7/MS_D3 32 XD_D6/MS_BS 32 XD_RE#/MS_INS# 32 XD_RDY/SD_W P/MS_CLK
XD_D0/SD_CLK/MS_D2 XD_D1/SD_D5/MS_D0 XD_D2/SD_CMD XD_D3/SD_D4/MS_D4 XD_D4/SD_D3/MS_D1 XD_D5/SD_D2/MS_D5 XD_D6/MS_BS XD_D7
XD_RDY/SD_W P/MS_CLK XD_RE#/MS_INS# XD_CE#/SD_D1 XD_CLE/SD_D0/MS_D7 XD_ALE/SD_D7/MS_D3 XD_W E#/SD_CD# XD_W P/SD_D6/MS_D6 XD_CD#
32
TP7124
2010/01/15
20.I0109.001
2010/01/15
DJ1
Wistron Corporation
5 4 3 2
Document Number
CARD Reader Connector

DJ1 Montevina UMA
Sheet
1
Rev
A00
71 of 88
(Blanking)
DJ1
Wistron Corporation
5 4 3 2
Document Number
RESERVED
Sheet
1
Rev
DJ1 Montevina UMA

A00
SSID = User.Interface
BT1 AFTP7319 76 37,76 BLUETOOTH_EN_L W LAN_ACT AFTP7311 AFTP7308 AFTP7318 AFTP7316 BLUETOOTH_DET#
1 1 1 1 1
1 3 5 7 9 11 13
15 NP1 2 4 6 8 10 12 14 NP2 16
HRS-CONN14D-GP-U 20.F0987.014
+3.3V_RUN BT_ACT 76
BT_LED BLUETOOTH_GPIO3 BLUETOOTH_GPIO5
USB_PP4 21 USB_PN4 21
1 2 1
AFTP7313 C7303 SC2D2U6D3V3KX-GP
C
76 BT_ACT 37,76 BLUETOOTH_EN_L 76 W LAN_ACT
BT_ACT BLUETOOTH_EN_L W LAN_ACT
AFTP7314 AFTP7309 AFTP7315 AFTP7312 AFTP7310 AFTP7317
1 1 1 1 1 1
W LAN_ACT BLUETOOTH_EN_L BT_ACT +3.3V_RUN USB_PP4 USB_PN4
EC7306 Do Not Stuff 2 1
R7304 10KR2J-3-GP
R7305 Do Not Stuff
DY
DY
DJ1
Wistron Corporation
5 4 3 2
Bluetooth
Sheet
1
Rev
DJ1 Montevina UMA

73 of 88
A00
(Blanking)
DJ1
Wistron Corporation
5 4 3 2
Document Number
Reserved
Sheet
1
Rev
DJ1 Montevina UMA

A00
(Blanking)
DJ1
Wistron Corporation
5 4 3 2
Document Number
Reserved
Sheet
1
Rev
DJ1 Montevina UMA

A00
SSID = PWR.Support
IOBD1
NP2
65
+PW R_SRC
+PW R_SRC
64 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 63 62 NP1
66 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 61
BATT SMBUS WLAN SMBUS WLAN CLK

C
37 BAT_SDA 37 BAT_SCL 7,18,19,22 ICH_SMBDATA 7,18,19,22 ICH_SMBCLK 7 CLK_PCIE_MINI1# 7 CLK_PCIE_MINI1 21 21 21 21 21 21 PCIE_RXN2 PCIE_RXP2 PCIE_TXN2 PCIE_TXP2 USB_PN6 USB_PP6
CLK_PCIE_MINI1# CLK_PCIE_MINI1 PCIE_RXN2 PCIE_RXP2 PCIE_TXN2 PCIE_TXP2 USB_PN6 USB_PP6
+5V_ALW +KBC_PW R +3.3V_ALW E51_RXD 37 E51_TXD 37 BAT_IN# 37 AC_IN# 37 PSID_DISABLE# 37 PSID_EC 37 AD_IA 37 W IFI_RF_EN 37 MINI1_CLKREQ# 7 PCIE_W AKE# 22 PLT_RST# 11,21,37,58 PM_LAN_ENABLE 37 KBC_PW RBTN# 37 BT_ACT 73 BLUETOOTH_EN_L 37,73 W LAN_ACT 73 +3.3V_RUN +1.5V_RUN +5V_USB1
WLAN PCIE WLAN PCIE WLAN USB LAN CLK LAN PCIE LAN PCIE USB Port
7 CLK_PCIE_LAN# 7 CLK_PCIE_LAN 21 PCIE_RXN3 21 PCIE_RXP3 21 21 21 21 PCIE_TXN3 PCIE_TXP3 USB_PN0 USB_PP0 USB_PN0 USB_PP0
ACES-CONN60C-1-GP-U 20.F1563.060
Close to IOBD Conn

+5V_USB1
A
+3.3V_RUN C7603 SCD1U16V2KX-3GP
+3.3V_ALW C7604 SCD1U16V2KX-3GP
+KBC_PW R C7605 SCD1U16V2KX-3GP
+5V_ALW C7606 SCD1U16V2KX-3GP
+PW R_SRC C7607 SCD1U50V3KX-GP
+1.5V_RUN DJ1
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date: Document Number
IO Board Connector
Sheet
1
DJ1 Montevina UMA

76 of
Rev
A00
88
(Blanking)
DJ1
Wistron Corporation
5 4 3 2
Document Number
Reserved
Sheet
1
Rev
DJ1 Montevina UMA

A00
(Blanking)
DJ1
Wistron Corporation
5 4 3 2
Document Number
Reserved
Sheet
1
Rev
DJ1 Montevina UMA

A00
SSID = Mechanical
H21 Do Not Stuff H22 Do Not Stuff H23 Do Not Stuff SPR1 SPRING-51-GP HBT1 STF237R115H123-GP HMI2 STF217R128H83-GP
34.4F822.002
1 1 1 1 1
D
34.4A902.001
1
34.4Y702.001
+PW R_SRC SCD1U50V3KX-GP
+PW R_SRC SCD1U50V3KX-GP SCD1U50V3KX-GP

D
2nd 34.4H103.201
2
EC7906
EC7901 EC7901
EC7902
EC7903 EC7903
EC7904
EC7905
H3 Do Not Stuff
H2 Do Not Stuff
H6 Do Not Stuff
H1 Do Not Stuff
H7 Do Not Stuff
+PW R_SRC Do Not Stuff
+PW R_SRC Do Not Stuff
2
EC7924 EC7924
EC7907 EC7907
EC7908
EC7909 EC7909
EC7910
EC7911
EC7925
EC7926
EC7922
EC7923
DY
1
DY
1
Do Not Stuff
+1.5V_SUS_P Do Not Stuff
H4 Do Not Stuff
H13 Do Not Stuff
+1.05V_VCCP Do Not Stuff
H18 Do Not Stuff
H8 Do Not Stuff
H20 Do Not Stuff
EC7912 EC7912 EC7921
EC7913
EC7914 EC7914 +1.05V_VCCP Do Not Stuff +5V_RUN SCD1U50V3KX-GP +5V_RUN SCD1U50V3KX-GP SCD1U50V3KX-GP +5V_RUN SCD1U50V3KX-GP
DY
2
EC7929
EC7915 EC7915
EC7916 EC7916
EC7917
EC7927 EC7927
EC7928
DY
2
DY
1
DY
1
DY
1
+3.3V_RUN
B
+3.3V_RUN SCD1U50V3KX-GP
+3.3V_RUN
B
EMI Request
G6002 G6003 G6004
2
Do Not Stuff
2
Do Not Stuff
2
Do Not Stuff +5V_ALW SCD1U50V3KX-GP +5V_ALW SCD1U50V3KX-GP +5V_ALW SCD1U50V3KX-GP +5V_ALW SCD1U50V3KX-GP +5V_ALW Do Not Stuff Do Not Stuff
DJ1
DY
SCD1U50V3KX-GP
SCD1U50V3KX-GP
2010/01/07
EC7938 EC7938
EC7918 EC7918 EC7930 EC7930
EC7919 EC7919 EC7931 EC7931
EC7920 EC7933 EC7933 Title Size A3 Date:
EC7936 EC7936
EC7937
EC7932 EC7932
UNUSED PARTS/EMI Capacitors

Document Number
DJ1 Montevina UMA

W ednesday, February 24, 2010 Sheet
1
EC7934
A
Wistron Corporation
Rev
A00
of 88
79
(Blanking)
DJ1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Document Number
(Reserved)
Sheet
1
Rev
A3
Date:
5 4 3 2
DJ1 Montevina UMA

W ednesday, February 24, 2010 80 of
A00
88
(Blanking)
DJ1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Document Number
(Reserved)
Sheet
1
Rev
C
Date:
5 4 3 2
DJ1 Montevina UMA

Wednesday, February 24, 2010 81 of
A00
88
(Blanking)
DJ1
Wistron Corporation
(Reserved)
Size Document Number Rev
A2
Date:
5 4 3 2
DJ1 Montevina UMA

1
A00
82 of 88
Sheet
(Blanking)
DJ1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Document Number
(Reserved)
Sheet
1
Rev
C
Date:
5 4 3 2
DJ1 Montevina UMA

Wednesday, February 24, 2010 83 of
A00
88
(Blanking)
DJ1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Date:
5 4 3 2
Document Number
(Reserved)
Sheet
1
Rev
Custom
DJ1 Montevina UMA

84 of
A00
88
(Blanking)
DJ1
Wistron Corporation
5 4 3 2
(Reserved)
Sheet
1
Rev
DJ1 Montevina UMA

85 of 88
A00
(Blanking)
DJ1
Wistron Corporation
5 4 3 2
Document Number
(Reserved)
Sheet
1
Rev
DJ1 Montevina UMA

A00
(Blanking)
DJ1
Wistron Corporation
5 4 3 2
Document Number
(Reserved)
Sheet
1
Rev
DJ1 Montevina UMA

A00
Item
1
D
Page#
20 54 37 59
Date
2010/01/04 2010/01/04 2010/01/04 2009/01/06
Request By Wistron Wistron Wistron Wistron
Issue description
R2018.R2019 to J accurity D4102 Change MB version chang to X01 ME change ODD&RTC Conn
Solution Description
Change R2018 R2019 to 63.33434.1DL D4102 change to 83.00054.Q81 Change R3722 pop,R3727 dummy. Change ODD Conn to 22.10300.811 Change RTC Conn to 62.70001.011 Add EC7927 EC7928 EC7929 EC7936 EC7937 EC7938 EC7930 EC7931 EC7932 EC7933 EC7934 POP EC7913 EC7912 EC7925 EC7922 EC7926 PC4610 PC4615 Del TR5401 TR3201 TR6301 TR6302 Change R5409 R5412 R3211 R3210 R6302 R6303 R6304 R6305 to 0ohm Change R4210 to 10K 63.10334.1DL EC6005 EC6006 change to 0.01u 78.10321.2FL Change U6301 U6302 to 74.07534.079 POP U3702 74.00690.I7B Add C3721 close KBC Pin AD_IA Change HSC1 layout symbol to Seiko 74.05711.07B
Rev.
X01 X01 X01 X01
2 3 4
79
2009/01/07
Wistron
EMI Request
X01
6
C
54 32 63
2010/01/07
Wistron
USB layout change
X01
C
7 8 9 10 11 12
B
42 60 63 37 37 69 47 49 50 46 37 37 20 37 55 37 69
2010/01/07 2010/01/08 2010/01/11 2010/01/12 2010/01/12 2010/01/14 2010/01/16 2010/01/18 2010/02/10 2010/02/10 2010/02/24 2010/02/24 2010/02/25
Wistron IDT Wistron Wistron DELL Wistron Wistron Wistron Wistron Wistron Wistron DELL Wistron
Change R4210 for POP noise IDT Request change EMI CAP to 0.01u USB power switch change Prevent BIOS damage Add one capacitor for IPCC function SMT issue Power team request Power team request U3702 reset timing is too long Change PCB version from X01 to A00 Change 0ohm to short pad. Add one FET for RCID function Do not stuff R6902
X01 X01 X01 X01 X01 X01

B
13 14 15 16 17 18
A
change PC4740 PC4741 PC4910 PC5020to 78.33124.2FL DY PTC4603.change PTC5001 PTC4602 DY U3702 DY R3722 and R3728, stuff R3727 and R3723 Change R2014 R3725 R3748 R5505 R5506 R3012 R3014 R3018 RN5901 R6009 R6010 Reserve Q3706 Reserve R6902
DJ1
X01 X01 A00 A00 A00 A00 A00

A
19
Wistron Corporation
5 4 3 2
Document Number
Change History
Sheet
1
Rev
DJ1 Montevina UMA

Thursday, February 25, 2010 88 of 88
A00

DELL Inspiron N4020

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DELL Inspiron N4020

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5

DJ1 Montevina UMA Schematics Document uFCPGA Mobile Penryn

Intel GM45+ICH9M 2010-02-10 REV : A00

DJ1 Montevina UMA

DJ1 Montevina UMA Block Diagram

Clock Generator SLG8SP513VTR

Intel Mobile CPU Penryn Socket P

Project code : 91.4EK01.001 PCB P/N : 48.4EK06.0SA Revision : 09275-SA

DDRIII 800/1066 Channel A

DDRIII 800/1066 DDRIII 800/1066

DDRIII 800/1066 Channel B

I/O Board Connector

Left Side: USB x 1

Internal Analog MIC

Right Side: USB x 2

2CH SPEAKER HDD

Flash ROM 2MB 62

DJ1 Montevina UMA

DJ1 Montevina UMA Power Block Diagram

+PWR_SRC TPS51125 Charger BQ24745

Power Block Diagram

DJ1 Montevina UMA

ICH SMBus Block Diagram

KBC SMBus Block Diagram

KBC_SCL1 2N7002DW-1-GP KBC_SDA1

SRN100J-3-GP PBAT_SMBCLK1 PBAT_SMBDAT1

SMBUS Block Diagram

DJ1 Montevina UMA

Wednesday, February 24, 2010

Thermal Block Diagram

Audio Block Diagram

HP0_PORT_A_L HP0_PORT_A_R VREFOUT_A_OR_F

Put between CPU and NB

EMC2102_DP3 PMBS3904-1-GP SC470P50V3JN-2GP

PORTC_L PORTC_R VREFOUT_C

Thermal/Audio Block Diagram

Wednesday, February 24, 2010

ICH9M Functional Strap Definitions

ICH9 EDS 642879 Comment

ICH9 Integrated pull-up and pull-down Resistors

Cantiga chipset and ICH9M I/O controller Hub strapping configuration

GNT2#/ GPIO53 GPIO20 GNT1#/ GPIO51

ITPM Host Interface

Intel Management engine crypto strap

PCIE Graphics Lane

Top-Block Swap override. Rising Edge of PWROK.

Boot BIOS Destination Selection 1, Rising Edge of PWROK.

SPI_MOSI SPI_MISO SPKR TACH[3:0] TP3 USB[11:0][P,N]

PULL-DOWN 20K PULL-UP 20K

PULL-DOWN 20K PULL-UP 20K PULL-UP 20K PULL-DOWN 15K

Local Flat Panel (LFP) Present Digital Display Present

PCI Express Lane Reversal (Lanes 1-4). Rising Edge of PWROK.

MiniCard WLAN LAN

No Reboot, Rising Edge of PWROK.

XOR Chain Entrance. Rising Edge of PWROK.

SPI_MOSI (Moble Only)

DJ1 Montevina UMA

Wednesday, February 24, 2010

CLK_XTAL_IN X701 CLK_XTAL_OUT

VDD_IO VDD_PLL3_IO VDD_SRC_IO VDD_SRC_IO VDD_SRC_IO VDD_CPU_IO

VDD_REF VDD_48 VDD_PCI VDD_SRC VDD_CPU VDD_PLL3

CLK_CPU_BCLK CLK_CPU_BCLK# CLK_MCH_BCLK CLK_MCH_BCLK#

CLK_CPU_BCLK 8 CLK_CPU_BCLK# 8 CLK_MCH_BCLK 10 CLK_MCH_BCLK# 10

+3.3V_RUN R706 C713 SC1U10V3KX-3GP