EECS140 ANALOG CIRCUIT DESIGN

INTRODUCTION

EECS140 ANALOG CIRCUIT DESIGN

INTRODUCTION

I-1
University of California Berkeley
College of Engineering Department of Electrical Engineering and Computer Science

EECS 140 ANALOG INTEGRATED CIRCUITS

Robert W. Brodersen, 2-1779, 402 Cory Hall, rb@eecs.berkeley.edu
This course will focus on the design of MOS analog integrated circuits with extensive use of Spice for the simulations. In addition, some applications of analog integrated circuits will be covered which will include RF amplification and discrete and continuous time filtering. Though the focus will be on MOS implementations, comparison with bipolar circuits will be given.

Robert W. Brodersen EECS140

Analog Circuit Design

Required Text
Analysis and Design of Analog Integrated Circuits, 4th Edition, P.R. Gray, P. Hurst, S. Lewis and R.G. Meyer, John Wiley and Sons, 2001

Supplemental Texts
B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001. Thomas Lee, The Design of CMOS Radio Frequency Integrated Circuits, Cambridge University Press, 1998 The SPICE Book, Andre Vladimirescu, John Wiley and Sons, 1994

Prerequisites
EECS 105: Microelectronic Devices and Circuits

ROBERT W. BRODERSEN

LECTURE 1

ROBERT W. BRODERSEN

LECTURE 1

EECS140 ANALOG CIRCUIT DESIGN

INTRODUCTION

EECS140 ANALOG CIRCUIT DESIGN

LECTURES ON MOS DEVICE MODELS

IC Design Course Structure at Berkeley EE40

I-2
University of California Berkeley
College of Engineering Department of Electrical Engineering and Computer Science

EE105 Robert W. Brodersen

EECS140

EE140 Linear/Analog Linear Design

EE142 Non-Linear

EE141 Digital

Analog Circuit Design

Sensors, Transducers

Interface Circuits

Digital Processing Amplifiers, Filters, A/D & D/As

Lectures on MOS DEVICE MODELS

ROBERT W. BRODERSEN

LECTURE 1

ROBERT W. BRODERSEN

LECTURE 2

EECS140 ANALOG CIRCUIT DESIGN

LECTURES ON MOS DEVICE MODELS

EECS140 ANALOG CIRCUIT DESIGN

LECTURES ON MOS DEVICE MODELS

M-1 Assumed Knowledge a) KCL, KVL - Kirchoff Laws

Vs Rs

i in
+

2-Port Equivalent Circuit (Voltage in - Voltage out) io u t in

R in R out +

M-2 in R i n = ----ii n R out

RL iout 0

+ -

b) Voltage, Current Dividers c) Thevenin, Norton Equivalents d) 2-Port Equivalents e) Phasors, Frequency Response
Vs

+ a i n

out
RL

out = ------i out

R S = i n = 0

out A = ------in

RL

i in
+

i out in1
Rin1

+ -

out1 in2 + a 1 i n 1
-

R out1

R out2 Rin2

+ a 2 in2

out
-

R in2 o u t = a 2 i n 2 = a 2 o u t 1 = a 2 a 1 i n 1 ------------------------ R out1 + R in2

ROBERT W. BRODERSEN LECTURE 2 ROBERT W. BRODERSEN LECTURE 2

EECS140 ANALOG CIRCUIT DESIGN

LECTURES ON MOS DEVICE MODELS

EECS140 ANALOG CIRCUIT DESIGN

LECTURES ON MOS DEVICE MODELS

MOS Large Signal Equations

n-channel D I DS B VGS S G Cutoff VDS n p n S L NMOS

M-3 Cutoff :
V GS < V T

MOS Large Signal Equations (Cont.)

M-4

V DSAT I DS Saturation

Linear :
V GS > V T V D S < V D S A T = VG S V T VD I D S = k' W V G S V T -------S V D S --2 L

Linear

Saturated :
V GS > V T V D S > V D S A T = VG S V T

ID S = k' W ( V G S V T ) 2 ( 1 + V D S ) --- --2 L

ROBERT W. BRODERSEN LECTURE 2

ROBERT W. BRODERSEN

LECTURE 2

EECS140 ANALOG CIRCUIT DESIGN

LECTURES ON MOS DEVICE MODELS

EECS140 ANALOG CIRCUIT DESIGN

LECTURES ON MOS DEVICE MODELS

MOS Large Signal Equations (Cont.)

2 2 V T = V T o + [ ( 2 f + V S B ) ( 2 f) ] 1 -1 -

M-5

MOS Large Signal Equations (Cont.) Body Effect :

V T o + VS B
1 2

M-6

(VSB > 0 ) V T o Threshold Voltage @ V S B = 0 f Fermi Potential 0.3 Body Effect Factor Short Channel Effect W Width of Device L Length k' = C ox
Oxide Capacitance mobility E VBS E = V DS/L VT S n G ++++++++ n D

1 = ------ C ox

2 q NA
VTo
0

ROBERT W. BRODERSEN

LECTURE 2

ROBERT W. BRODERSEN

LECTURE 2

EECS140 ANALOG CIRCUIT DESIGN

LECTURES ON MOS DEVICE MODELS

EECS140 ANALOG CIRCUIT DESIGN

LECTURES ON MOS DEVICE MODELS

MOS Large Signal Equations (Cont.) Short Channel Effect ():

M-7

MOS Large Signal Equations (Cont.)

I (DA ) = k' -------- ( V G S V T ) 2 --- W 2 LEFF

M-8

Modeled as
k' W I (DB) = --- --- ( V G S V T )2 ( 1 + V D S) -2 L

XJ = Junction Depth XD L drawn L D = Lateral Diffusion ~ 0.75 X J

I (DB) = I DS V DS
( A) k' W ID 2 dL = --- -------- ( V G S V T ) E F F VD S 2 L2 FF d VD S E

L = L drawn 2 L D LE F F = L X D X D = f ( VD S )

I (DA ) ID = -------- dX D = I D V DS L EFF dV DS

ROBERT W. BRODERSEN

LECTURE 2

ROBERT W. BRODERSEN

LECTURE 3

EECS140 ANALOG CIRCUIT DESIGN

LECTURES ON MOS DEVICE MODELS

EECS140 ANALOG CIRCUIT DESIGN

LECTURES ON MOS DEVICE MODELS

MOS Large Signal Equations (Cont.)

1 dX 1 dX = -------- D -- D L E F F d V D S L d V D S

MOS Large Signal Equations (Cont.)

G

M-9

Weak function of VDS

XD 2 ( V D S VD S A T ) ------------------------------------------q NA
1 2

I DS Ideal

I D S

S
Longer Channel (Increasing L)

W L

Fixed = Dielectric constant of silicon

V DS

W/L is the parameter of interest

N A = Substrate doping dX D 1 2 1 = - ------------- ------------------------ d VD S 2 q N A V D S V D S A T

1 2 1 2

C G W L COX

ROBERT W. BRODERSEN

LECTURE 3

ROBERT W. BRODERSEN

LECTURE 3

EECS140 ANALOG CIRCUIT DESIGN

LECTURES ON MOS DEVICE MODELS

EECS140 ANALOG CIRCUIT DESIGN

LECTURES ON MOS DEVICE MODELS

MOS Small Signal Model (Low Frequency) IDS G + V GS S +

ID S =

M-10 M-11

MOS Small Signal Model (Cont.) In Saturation :

M-12

gm gs gmbs bs V SB B ro

gm =

dID S W = k' --- ( V G S V T ) ( 1 + V D S ) d VG S L

1 -

2 W W W g m k' --- ( V G S V T ) = k' --- V D S A T = 2 k' --- I D S -- L L L

What is VDSAT ? G bs + dI D S ds dV DS k' I D S = --- W ( V G S V T ) 2 = k' W V 2 S A T ------ ---D 2 L 2 L W g m = k' --- V D S A T so, -L 2 ID S 2 V D S A T = -------------------- k' W L
LECTURE 3
1 -

and from above,

gm
ROBERT W. BRODERSEN

gmbs
LECTURE 3

dID S dID S gs + d VG S d V BS

+ S

1/ro

V G S = VT + V D S A T

ROBERT W. BRODERSEN

EECS140 ANALOG CIRCUIT DESIGN

LECTURES ON MOS DEVICE MODELS

EECS140 ANALOG CIRCUIT DESIGN

LECTURES ON MOS DEVICE MODELS

MOS Small Signal Model (Cont.) gmbs calculation :

gmbs = gmb = dI D S = k ' W ( V G S V T ) ( 1 + V D S ) dV T ---dV BS L d V BS

M-13

MOS Small Signal Model (Cont.) C ox 0.23

gmbs ------- = gm
S n n G

M-14

dV T = ----------------------------------------- dV BS 2 ( 2 f + V S B) 0.5 W -g mbs = k' --- ( V G S V T ) ( 1 + V D S ) L gm = ----------------------------------------2 (2 f + V S B )0.5

0.1 -5V V BS = 0.5 f = 0.3 k = 90e-6 = 0.01 V To=0.7

ROBERT W. BRODERSEN LECTURE 3

C js 0V
Q c h a n n e lduetovgs C o x g s Q c h a n n e ld u e t o v b s C j s b s C js = -----C ox

g mbs ------- = gm

ROBERT W. BRODERSEN

LECTURE 3

EECS140 ANALOG CIRCUIT DESIGN

LECTURES ON MOS DEVICE MODELS

EECS140 ANALOG CIRCUIT DESIGN

LECTURES ON MOS DEVICE MODELS

MOS Small Signal Model (Cont.) ro calculation :

1 dI --- = g m d s = D S = d k' W ( V G S V T ) 2 ( 1 + V D S ) --- --- dV DS dV DS 2 L ro 1 --- = k' W ( V G S V T ) 2 --- ---ro 2 L 1 --- = I D S ro 1 r 0 = ------------ ID S

M-15

MOS Small Signal Model (Cont.) Comparison with Spice Level 1:

VTO = V T o 0.5 1.0V P H I = 2 f 0.6 G A M M A = 0.05 0.5 L A M B D A = 0.01 0.1 A K P = k' = C o x n m o s 50 100 ---V2 pmos 1 nmos -3

M-16

ROBERT W. BRODERSEN

LECTURE 3

ROBERT W. BRODERSEN

LECTURE 3

EECS140 ANALOG CIRCUIT DESIGN

LECTURES ON SPICE

EECS140 ANALOG CIRCUIT DESIGN

LECTURES ON SPICE

MOS Small Signal Model (Cont.) Summary:

2 2 I DS W W --g m 2 k' --- ID S = k' --- V D S A T = ------------ VD S A T L L 1

University of California Berkeley

College of Engineering Department of Electrical Engineering and Computer Science

gmbs = gm = ----------------------------------------2 ( 2 f + V S B) 0.5 1 r 0 = ------------ ID S I DS ----- = V G S V T = V D S A T --------------------------gm 2 2 VDSAT 2 ID S = -------------------- k' W L

1 2

V D S A T = VG S V T VGS 2 I DS 2 = V T + -------------------- k' W L

1 -

Robert W. Brodersen
EECS140

Analog Circuit Design

ID S = k' W ( V G S V T )2 --- ---2 L VT = V T o + [ ( 2 f + VS B ) ( 2 f ) ]

1 -2 1 -2

Lectures on SPICE

ROBERT W. BRODERSEN

LECTURE 4

ROBERT W. BRODERSEN

LECTURE 4

EECS140 ANALOG CIRCUIT DESIGN

LECTURES ON SPICE

EECS140 ANALOG CIRCUIT DESIGN

LECTURES ON SPICE

SP-1 Spice Transistor Model : M1 1 2 3 4 nch L=1 W=10 AD=( ) AS=( ) PD=( ) PS=( ) NRD=( ) parasitic resistors
G

SPICE Initial Operationg Point DC currents and Voltages Linearize Around OP Point Solve Eqn. New Operating Point No DC Converge? Yes Increment Time No End of Time Interval
LECTURE 4

SP-2

area of drain 1

Analysis Types : DC op point .op DC sweeps AC & Transient

S L

2 3

Yes

STOP

ROBERT W. BRODERSEN

LECTURE 4

ROBERT W. BRODERSEN

EECS140 ANALOG CIRCUIT DESIGN

LECTURES ON SPICE

EECS140 ANALOG CIRCUIT DESIGN

LECTURES ON SPICE

4 + R4 1 I1 + VB R1

VA I4 G i = 1/Ri 3 R2 R3

SP-3 G 1+G 4 -G 1 0 -G 4 1 0 -G1 0 -G 4 G1 +G 2+G 3 -G 3 0 -G3 -G 3 0 0 0 -G 4 0 0 0 0 -1 1 1 0 0 0 0 0 0 0 -1 1 0 0 V1 V2 V3 V4 I1 I4 0 0 0 = 0 VB VA

SP-4

Node 1 : Node 2 : Node 3 : Node 4 :

( G 1 + G 4 ) V1

G1 V 2

G 4 V 4 + I1 = 0
= 0

G 1 V 1 + ( G 1 + G 2 + G 3 ) V2 G 3 V3 G 3 V2 + G 3 V3 G4 V 1 V1 V 3 V 4

Current src G B F R V = I E C Total # of EQNS N=n + n v + nl n = # of circuit nodes nv= # of independent voltage srcs nl= # of inductors
LECTURE 4

I4 = 0 G 4 V 4 + I4 = 0
= VB = VA

Votlage src
ROBERT W. BRODERSEN

ROBERT W. BRODERSEN

LECTURE 4

EECS140 ANALOG CIRCUIT DESIGN

LECTURES ON SPICE

EECS140 ANALOG CIRCUIT DESIGN

LECTURES ON SPICE

SP-5 Matrix Solution

A x = b

SP-6 Then eliminate a32

(2 ) (1) e1 = e1 (1) (2 ) e2 = e2 (1) a 32 (1 ) e (32 ) = e 3 ------) e 2 1 a (22 (1)

(1) x x x 0 x x 0 0 x Upper triangular matrix can be solved

we need Solve by Gaussian Elimination

(0) denotes iteration step
0 0 e (10) a (101) a (12 ) a (13) x 1 ( 0) (0 ) (0 ) (0) e 2 a 2 1 a 22 a 23 x 2 = ( 0) 0 0 e 3 a (301) a (32 ) a (33) x 3

b (10 ) b2
(0)

(2) (2) (2) a 1 1 a 1 2 a 13 x 1 (2) (2) 0 a 2 2 a 23 x 2 = (2) 0 0 a 33 x 3

b (10 ) b2
(1 )

b (32 )

b (30 )

Eliminate a 21,a 31
e (11 ) = e (10) a e (21) = e (20) ------) e (10 ) (0 a 11
(0 ) 21

a e (31) = e (30) ------) e (10 ) (0 a 11

(0 ) 31

x x x 0 x x 0 x x

b (32 ) x 3 = ------) a (323 1 ( b (21 ) a (23 ) x 3 ) x 2 = --------------------------------1 a (22 ) ( b 1 a 1 3 x 3 a 12 x 2 ) x 1 = -----------------------------------------------------a (101)

(0 ) (0 ) ( 0)

Solution

ROBERT W. BRODERSEN

LECTURE 4

ROBERT W. BRODERSEN

LECTURE 4

EECS140 ANALOG CIRCUIT DESIGN

LECTURES ON SPICE

EECS140 ANALOG CIRCUIT DESIGN

LECTURES ON SPICE

Accuracy Cant divide by 0 or small numbers, so pivoting is used to reorder eqns (Basically renumbering nodes). Puts maximum values on diagonal. R 1 =1
1 1 1 1.0001 V1 = V2 1 0
1 1 - --------- = G 1 + G 2 1 10 k

SP-7 To control accuracy .options PIVTOL = <values> (1018) This sets the allowable range of conductance values. *ERROR* : Maximum entry ......at STEP ....... is less than PIVTOL -Probably means you have an incorrect element or floating node

SP-8

1A

R 2=10k

If the computer only has 4 digits of precision then we get,

1 1 V 1 = 1 1 V 2 1 0 V1 V2 = 1 V1 + V 2 = 0 V 1, V 2 =

Actually,
V 1 = 10 , 001V V 2 = 10 , 000V
ROBERT W. BRODERSEN

LECTURE 4

ROBERT W. BRODERSEN

LECTURE 4

EECS140 ANALOG CIRCUIT DESIGN

LECTURES ON SPICE

EECS140 ANALOG CIRCUIT DESIGN

LECTURES ON SPICE

SP-9 Solution of the DC equations with non-linear models

ID = IS e IG = G V
VD --------V TH

SP-10 Newton-Raphson Iteration : - Make guess of next operation point in iteration Start at initial guess and linearize diode eqn.

+ IA G VD IG ID ID,G

IA

IG

Need to find this point IA ID G G D0

+ V D(0) ID0

ROBERT W. BRODERSEN

LECTURE 4

ROBERT W. BRODERSEN

LECTURE 4

EECS140 ANALOG CIRCUIT DESIGN

LECTURES ON SPICE

EECS140 ANALOG CIRCUIT DESIGN

LECTURES ON SPICE

SP-11 Convergence Keep iterating until all voltages and currents are within a a tolerance value.
V (ni) = node voltage n at iteration i Vn = R E L ( V ) m a x ( V (ni + 1 ) , V (ni) ) + A B S ( V)

SP-12

Current value I D0 ID VD Solve for V D, becomes VD (1)

Solution finds this point Slope of GD0

The convergence check is :

V (ni + 1) V (ni) Vn R E L ( V ) 10 4 (Default 10 3 )

Linearize at this point Find new point

A B S ( V ) 10 6 (Default 50V )

ABS(V) should be at least two orders of magnitude below required accuracy. These values would give 1 part in 104 accuracy down to 100V resolution
ROBERT W. BRODERSEN LECTURE 4

ROBERT W. BRODERSEN

LECTURE 4

EECS140 ANALOG CIRCUIT DESIGN

LECTURES ON MOS DEVICE MODELS

SP-13 Current convergence is broken into two types; MOS and NOT MOS
MOS A B S M O S A B S O L U T E ( 10 6 ) R E L M O S RELATIVE ( 0.5 ) ABSI A B S O L U T E ( 10 9) R E L I RELATIVE ( 0.01 )

NOTMOS

ITL = # of steps in iteration (200) When you get *ERROR* no convergence in DC analysis and the last node voltages Then it hasnt converged in 200 times - something is probably wrong with your netlist
ROBERT W. BRODERSEN LECTURE 2