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Introduction / Objective Design Description Testing Methodology
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Introduction / Objectives
This design is a time keeping digital alarm clock that displays time in hours and minutes. The goal of this design is to implement all of the basic features that one would normally expect to find on a standard digital alarm clock. Features such as standard twelve-hour time, clock/alarm setting functionality, an alarm snooze feature, and an alarm alert indicator.
The design has been implemented on a Spartan-3 FPGA development board. The following diagram shows the physical alarm clock interface.
( Figure 1 )
How to use:
A user should be able to set the clock by holding down the clock set button and incrementing the appropriate hour/minute buttons.
Design Description
This design is implemented on a Digilent Spartan-3 development board. The development board contains many inputs and outputs that aid an engineer in learning how to use the Spartan-3 FPGA. The following I/O were used for this design: a onboard 50 MHz crystal oscillator clock, three slide switches, four momentary-contact push button switches, two individual LEDs, and a four-character, seven-segment display. The pin locations of the I/O that an engineer wants to implement must be defined in a constraint file. These pin location values are listed in the Spartan-3 Starter Kit Board User Guide. This user guide can be accessed online at the manufactures website. See the references section for more details. The constraint file for this design is located at the end of the report. See p.10 in the Appendices. Below is the VHDL entity that describes the same design I/O that is in the constraint file. entity clock is port ( clk50in: in std_logic; -- 50 Mhz XTAL btn_in: in std_logic_vector(3 downto 0); -- 4 pushbutton inputs sw_in: in std_logic_vector(7 downto 0); -- 8 switch inputs digit_out: out std_logic_vector(3 downto 0); -- digit drivers led_out: out std_logic_vector(7 downto 0); -- 8 board mounted LEDs seg_out: out std_logic_vector(7 downto 0)); -- segment drivers end clock; A full list of the inputs and output and their purpose is displayed below. This list corresponds with the entity above, the design constraint file located on p.10 in the Appendices and Figure 1.
Inputs:
1. Momentary Push Buttons: a. Alarm Set { btn(3) } b. Time Set { btn(2) } c. Hours { btn(1) } d. Minutes { btn(0) } Slide Switch: a. Alarm on/off b. Snooze c. Reset
2.
Outputs:
1. 2. 3. 4. 5. 6. Seven-Segment Display AM/PM indicator LED led(7) Alarm on/off indicator led(0) Blinking LED second indicating decimal point Blinking Board mounted second indicated LEDs Alarm Alert ( LED / Sound)
Synthesis:
The designs synthesis report accurately displays the hardware I wanted to infer (see p.16-p.18 in the Appendices).
State Machines:
Testing Methodology
Hardware Testing:
The primary means of testing for this design was using hardware. The design was implemented by synthesizing the VHDL code, then generating a bit file using Xilinx ISE tools. This bit file was downloaded to the Spartin-3 development using Xilinx iMPACT. To complete the program download, I had to power the FPGA board by plugging it into an electrical outlet and hooking it up on end of the JTAG cable to the FPGA board and the other end to the computers parallel port.
Results
The design performs as to be expected. The clocks display is fully functional. It is capable of using all four digits of the seven-segment display and the board mounted am/pm LED indicator. The reset switch works and the state machine does change state when the user presses the push buttons (btn2 btn1 and btn0). This is indicated by LED0, LED1, and LED2.
Analysis
Overall, the design performs the basic clock functions well. Sometimes the clock freezes while the user presses the momentary pushbuttons. This might be caused by unintentional signals generated by a noisy digital contact as the switch is pressed. To eliminate this problem, one would have to de-bounce the push buttons in the software.
Design Simulation:
The VHDL test bench simulated by using the ModelSim by Xilinx. Software test vectors for the state machine were not required because I did not get far enough in the design process, and the results were already seen in previous hardware tests.
Results
This simulation confirmed what the hardware tests were showing. Page 13 in the Appendix is a zoomed out view of the clock wave forms. From this view, the repetitive patterns of each waveform can be observed. Page 14 and 15 offer more detail by displaying the binary values of the signals in different states. One can observe the signals h2,h1,m2,m1 at the expected initial starting value of 12:01, the board mounted LED will be powered by the led_out signal, the digit of seven-segment display is controlled by the digit_out signal, and the corresponding seven-segment decoder output signal seg_out for each digit. One can also observer the alternating decimal point signal dp.
Analysis
The simulation results did not prove to be as useful as I would have liked. Since the clock device operates in real time, it makes the simulations very long. The more interesting events happen every 60 seconds, which is an extremely long time to run a simulation. This simulation provided waveform data that is located at the end of the report. (see p.13-p.15 in the Appendices).
Discussion
Lessons Learned:
Much was learned while developing this project. I learned how to implement hardware using VHDL code. This includes learning about implementation of constraint file, input buffers, and output buffers. I learned how to use the development boards display by multiplexing the digit signal to the 7-segment decoder. I learned how to divide down the boards internal clock so I could use it in my design. For the first time, I learned about and used some programming constructs that I was unfamiliar with such as generate and shared variables. While working on this design, I referenced many VHDL sources including websites, course notes, course book, and the Spartan-3 Starter Kit Board User Guide.
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If I had more time to work on this project, I would consider doing the following tasks.
To Do:
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. Figure out how to store and pass time data between processes. Create an up_hour process Figure out how to set the clocks minutes and hours by storing them in a register Fix am/pm problem ( could use led(7) as a control signal for time counter) Write processes for each state. (i.e. set_time, up_minutes, up_hours ) Make use of newly freed up board mounted LEDs to display alarm on/off indicator. Continue to refine code comments Develop alarm FSM and functionality Might rewrite the time algorithms Confirm the clock is keeping accurate time. Debounce the board mounted push buttons
My lack of time and knowledge has prevented me from completing this design. I have a suspicion that there exists much simpler design approaches. I think an FPGA microprocessor based emulation might offer a better solution path. If I were to continue this project, I would re-evaluate the entire design method
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by increasing my knowledge of VHDL, logic design techniques, clock designs, and computer architecture. These tools would give me the ability to create a logical design. Although the project is incomplete, it has afforded me with much more knowledge about this particular problem. My knowledge of the VHDL language has improved vastly.
References
Digilent Inc.
http://www.digilentinc.com/
http://www.xilinx.com/products/boards/DO-SPAR3-DK/reference_designs.htm
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Appendices
Equipment
1.
IBM PC compatible unit: computer box, monitor, mouse, keyboard, running Windows XP Professional.
2. Hardware Device:
a) Device
b) Device:
c) Package: pq208
3.
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