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Memory
Chapter Overview
Memory Classification Memory Architectures The Memory Core Periphery Reliability
Memory
Random Access
SRAM DRAM
Memory
SN-2 SN_1
Input-Output (M bits)
Input-Output (M bits)
Row Decoder
Word Line
Column Decoder
Global Data Bus Control Circuitry Block Selector Global Amplifier/Driver I/O Advantages: 1. Shorter wires within blocks 2. Block address activates only 1 block => power savings
Digital Integrated Circuits Memory Prentice Hall 1995
Memory
CAS
RAS-CAS timing
BL[0]
Digital Integrated Circuits
BL[1]
Memory
BL[2]
BL[3]
Prentice Hall 1995
Only 1 layer (contact mask) is used to program memory array Programming of the memory can be delayed to one of last process steps
Digital Integrated Circuits Memory Prentice Hall 1995
WL[3]
WL[1]
WL[2]
WL[3]
No contact to VDD or GND necessary; drastically reduced cell size Loss in performance compared to NOR ROM
Digital Integrated Circuits Memory Prentice Hall 1995
WL cword
rword
BL Cbit
Word line parasitics Resistance/cell: (7/2) x 10 /q = 35 Wire capacitance/cell: (7 2) (0.6)2 0.058 + 2 (7 0.6) 0.043 = 0.65 fF Gate Capacitance/cell: (4 2) (0.6)2 1.76 = 5.1 fF. Bit line parasitics: Resistance/cell: (8.5/4) x 0.07 /q = 0.15 (which is negligible) Wire capacitance/cell: (8.5 4) (0.6)2 0.031 + 2 (8.5 0.6) 0.044 = 0.83 fF Drain capacitance/cell: ((3 4) (0.6)2 0.3 + 2 3 0.6 0.8) 0.375 + 4 0.6 0.43 = 2.6 fF
Memory
rword
cbit
Memory
Bit line delay Assume a (2.4/1.2) pull-down device and a (8/1.2) pull-up transistor. The bit line switches between 5 V and 2.5 V. Cbit = 512 (2.6 + 0.8) fF = 1.7 pF IavHL = 1/2 (2.4/0.9) (19.6 10 -6)((4.25)2/2 + (4.25 3.75 - (3.75) 2/2)) 1/2 (8/0.9) (5.3 10-6 ) (4.25 1.25 - (1.25)2/2) = 0.36 mA tHL = (1.7 pF 1.25 V) / 0.36 mA = 5.9 nsec The low-to-high response time can be computed using a similar approach. tLH = (1.7 pF 1.25 V) / 0.36 mA = 5.9 nsec
Digital Integrated Circuits Memory Prentice Hall 1995
WL
K cells
BL[0] BL[1]
BL[2] BL[3]
PMOS precharge device can be made as large as necessary, but clock driver becomes harder to design.
Digital Integrated Circuits Memory Prentice Hall 1995
Gate D Drain
Substrate
10 V 5 V S
20 V
5V S
0V
2.5 V S
5V
Avalanche injection.
Memory
FLOTOX EEPROM
Floating gate Source 20-30 nm n+ n+ 10 nm Gate Drain 10 V 10 V Substrate p VGD I
WL
VDD
Flash EEPROM
Control gate Floating gate
erasure n+ source
programming p-substrate
Memory
Flash
Digital Integrated Circuits
Courtesy Intel
Memory
EPROM
Prentice Hall 1995
Memory
DYNAMIC (DRAM)
Periodic refresh required Small (1-3 transistors/cell) Slower Single Ended
Digital Integrated Circuits Memory Prentice Hall 1995
M1
M3
BL
BL
Memory
kn
,M6 (
DD
2 2 VDD VDD VDD VDD VTn )----------- ----------- = k p M4 VDD VTp )----------- ----------- ( , 2 2 8 8
Memory
VDD Cbit
V DD
VDD C bit
(W/L)n,M5 10 (W/L)n,M1
Digital Integrated Circuits
6T-SRAM Layout
VDD
M2 M4
Q
M1 M3
GND
M5 M6
WL
BL
Digital Integrated Circuits Memory
BL
Prentice Hall 1995
Static power dissipation -- Want RL large Bit lines precharged to VDD to address t p problem
Digital Integrated Circuits Memory Prentice Hall 1995
No constraints on device ratios Reads are non-destructive Value stored at node X when writing a 1 = VWWL -VTn
Digital Integrated Circuits Memory Prentice Hall 1995
3T-DRAM Layout
BL2 BL1 GND
RWL
M3 M2
WWL
M1
Memory
VDD VT VDD
BL CBL VDD /2
sensing
VDD /2
Write: CS is charged or discharged by asserting WL and BL. Read: Charge redistribution takes places between bit line and storage capacitance
CS V = VBL V PRE = ( V BIT V PRE )-----------------------C S + CBL
M1 word line
(a) Cross-section
(b) Layout
Memory
Cell Plate Si
Transfer gate Isolation Storage electrode
Capacitor Insulator
Refilling Poly
Trench Cell
Digital Integrated Circuits Memory
Stacked-capacitor Cell
Prentice Hall 1995
Periphery
Decoders Sense Amplifiers Input/Output Buffers Control / Timing Circuitry
Digital Integrated Circuits Memory Prentice Hall 1995
Row Decoders
Collection of 2M complex logic gates Organized in regular and dense fashion (N)AND Decoder
NOR Decoder
Memory
Dynamic Decoders
Precharge devices GND GND VDD WL3 WL3 VDD WL2
VDD
VDD
WL1
WL0
V DD
A0
A0
A1
A1
A0
A0
A1
A1
WL 0
A1 A 0
A0
A1
A3 A2
A2
A3
Splitting decoder into two or more logic layers produces a faster and cheaper implementation
Digital Integrated Circuits Memory Prentice Hall 1995
A0
A1
Advantage: speed (t pd does not add to overall memory access time) only 1 extra transistor in signal path Disadvantage: large transistor count
Digital Integrated Circuits Memory Prentice Hall 1995
D Number of devices drastically reduced Delay increases quadratically with # of sections; prohibitive for large decoders Solutions: buffers progressive sizing combination of tree and pass transistor approaches
Digital Integrated Circuits Memory Prentice Hall 1995
Memory
Sense Amplifiers
t C V = ---------------p I av large make V as small as possible
small
s.a. output
Prentice Hall 1995
BL
EQ
(b) Doubled-ended Current Mirror Amplifier VDD SRAM cell i y Diff. Sense x x Amp y y D D x SE y x
SE
Initialized in its meta-stable point with EQ Once adequate voltage gap created, sense amp enabled with SE Positive feedback quickly forces output to a stable operating point.
Digital Integrated Circuits Memory Prentice Hall 1995
Single-to-Differential Conversion
WL BL x Diff. S.A. x
+ _
cell
Vref
CS
... CS
CS
SE
CS
... CS
CS
dummy cell
dummy cell
Memory
V (Volt)
6.0
0.00
Vcasc
WLC
WL
Memory
DRAM Timing
Memory
A0
DELAY td
ATD
ATD
A1
DELAY td
Memory
Memory
WL1 BL CBL C
WL0 WL D CWBL
CWBL
WLD
WL 0
WL1 BL
Sense C C Amplifier C C C
CBL
Memory
Folded-Bitline Architecture
WL1
WLD
WL D y Sense C EQ Amplifier x y
x C C
BL
CBL CWBL
Memory
Transposed-Bitline Architecture
BL BL BL BL" (a) Straightforward bitline routing. BL BL BL BL" (b) Transposed bitline architecture.
Digital Integrated Circuits Memory Prentice Hall 1995
Ccross SA
Ccross SA
Alpha-particles
-particle WL BL n+ SiO2
VDD
Yield
Redundancy
Row Address Redundant rows : Redundant columns Memory Array Row Decoder Fuse Bank
Column Decoder
Column Address
Prentice Hall 1995
Memory
Memory
AND PLANE
x0x1 x2
OR PLANE
f0 x0 x1 x2
f1
Memory
Pseudo-Static PLA
GND GND GND GND VDD GND
GND
GND
VDD
x0
x0
x1
x1
x2
x2
f0
f1
AND-PLANE
Digital Integrated Circuits Memory
OR-PLANE
Prentice Hall 1995
Dynamic PLA
AND GND VDD OR
AND V DD x0 x0 x1 x1 x2 x2
OR f0 f1 GND
AND-PLANE
Digital Integrated Circuits Memory
OR-PLANE
Prentice Hall 1995
AND
AND AND
Dummy AND Row
OR
OR
PLA Layout
VDD And-Plane Or-Plane GND
x0 x0 x1 x1 x2 x2 Pull-up devices
Memory
f0 f1 Pull-up devices
Increasing die size factor 1.5 per generation Combined with reducing cell size factor 2.6 per generation
Memory
Memory