EE 2730 Fall 2010

Latches & Flip-Flops

Chapter 7.1 7.7

EE 2730 - Fall 2010

Combinational-Sequential

EE 2720 Combinational Logic

No feedback

EE 2730 Sequential Logic

Feedback

No memory Present o/p depends on present i/p Telephone dialer TV remote channel no. Money changer

Remembers the past Present o/p depends on present and past i/p Telephone redial TV remote channel up/dn Vending machine

State part of the past needed to produce present outputs

EE 2730 - Fall 2010

A Simple Memory

0 1 0

Stable Configuration

feedback

1 0 1

No control No practical use

EE 2730 - Fall 2010

A Controlled Memory Element

Load

d Data TG1

q Output

TG2

EE 2730 - Fall 2010

A Controlled Memory Element

Load

d Data TG1

q Output

TG2

EE 2730 - Fall 2010

A Controlled Memory Element

Load

d Data TG1

d Output

TG2

EE 2730 - Fall 2010

Control of an Alarm System

Sensor Reset Set Memory element On Off Alarm

Activated sensor sets alarm on Even when sensor ceases to be activated, alarm is on Need to reset alarm to turn it off Alarm remembers that sensor was triggered after it was last reset
EE 2730 - Fall 2010

Basic (SR) Latch

Reset Set Q

Qa

Qb

Qa and Qb often called Q and Q or Q and /Q

EE 2730 - Fall 2010

Basic (SR) Latch Function

R
Qa

S R 0 0 1 0 1 0 1

Qa Qb 0/1 1/0 0 1 0 1 0 0 no change reset set ?

Qb

EE 2730 - Fall 2010

Basic (SR) Latch --- no change

R

0 q q 0

q
Qa

S R 0 0 0 1 0 1

Qa Qb 0/1 1/0 0 1 0 1 0 0 no change reset set ?

q
Qb

1 1

q
Qa

q
Qb

EE 2730 - Fall 2010

Basic (SR) Latch --- reset

R

0
Qa

S R 0 0 0 1 0 1

Qa Qb 0/1 1/0 0 1 0 1 0 0 no change reset set ?

1
Qb

EE 2730 - Fall 2010

Basic (SR) Latch --- set

R

1 1

0
Qa

S R 0 0 1 0 1 0 1

Qa Qb 0/1 1/0 0 1 0 1 0 0 no change reset set ?

0 0
1 1 1 0

Qb

Qa

0 0 1

Qb

EE 2730 - Fall 2010

Basic (SR) Latch --- ?

R

0
Qa

S R 0 0 1 0 1 0 1

Qa Qb 0/1 1/0 0 1 0 1 0 0 no change reset set ?

0
0
S Qb

EE 2730 - Fall 2010

Basic (SR) Latch ---Timing

R Qa S Qb 1 t1 t2 t3 t4 t5 t6 t7 t8 t9 t 10

R
0 1 S 0 S R 0 0 1 1 0 1 0 1 Qa Qb 0/1 0 1 0 1/0 1 0 0 no change reset set ? 1 Qa 0 1 Qb 0 Time ? ?

EE 2730 - Fall 2010

Basic (SR) Latch --- with delay

1
R
1 ns

Qa

1 0 0
1 ns

0
t1 1 t2 t3 t4 t5 t6 t7 t8 t9 t 10

Qb

1
R
0 1 S 0

S R 0 0 1 1 0 1 0 1

Qa Qb 0/1 0 1 0 1/0 1 0 0 no change reset set ?

1 Qa 0 1 Qb 0
1 ns

Time

Not in text
EE 2730 - Fall 2010

Basic (SR) Latch --- with delay (t1)

1 0
R
1 ns

Qa

1 0 0
1 ns

0
t1 1

no change
t2 t3 t4 t5 t6 t7 t8 t9 t 10

Qb

1
R
0 1 S 0

S R 0 0 1 1 0 1 0 1

Qa Qb 0/1 0 1 0 1/0 1 0 0 no change reset set ?

1 Qa 0 1 Qb 0
1 ns

Time

Not in text
EE 2730 - Fall 2010

Basic (SR) Latch --- with delay (t2)

0
R
1 ns

Qa

1 0 1 0
1 ns

0
t1 1 t2 t3 t4 t5 t6 t7 t8 t9 t 10

Qb

0 1
R
0 1 S 0

S R 0 0 1 1 0 1 0 1

Qa Qb 0/1 0 1 0 1/0 1 0 0 no change reset set ?

1 Qa 0 1 Qb 0
1 ns

Time

Not in text
EE 2730 - Fall 2010

Basic (SR) Latch --- with delay (t2)

0
R
1 ns

Qa

0 0 1
1 ns

0 1
t1 1

set
t2 t3 t4 t5 t6 t7 t8 t9 t 10

Qb

0
R
0 1 S 0

S R 0 0 1 1 0 1 0 1

Qa Qb 0/1 0 1 0 1/0 1 0 0 no change reset set ?

1 Qa 0 1 Qb 0
1 ns

Time

Not in text
EE 2730 - Fall 2010

Basic (SR) Latch --- with delay (t3)

0
R
1 ns

Qa

0 1 1 0
1 ns

1
t1 1

no change
t2 t3 t4 t5 t6 t7 t8 t9 t 10

Qb

0
R
0 1 S 0

S R 0 0 1 1 0 1 0 1

Qa Qb 0/1 0 1 0 1/0 1 0 0 no change reset set ?

1 Qa 0 1 Qb 0
1 ns

Time

Not in text
EE 2730 - Fall 2010

Basic (SR) Latch --- delay (t4)

0 1
R
1 ns

Qa

0 1 0
1 ns

1 0
t1 1 t2 t3 t4 t5 t6 t7 t8 t9 t 10

Qb

0
R
0 1 S 0

S R 0 0 1 1 0 1 0 1

Qa Qb 0/1 0 1 0 1/0 1 0 0 no change reset set ?

1 Qa 0 1 Qb 0
1 ns

Time

Not in text
EE 2730 - Fall 2010

Basic (SR) Latch --- delay (t4)

1
R
1 ns

Qa

0 0 0
1 ns

0
t1 1

reset
t2 t3 t4 t5 t6 t7 t8 t9 t 10

Qb

0 1
R
0 1 S 0

S R 0 0 1 1 0 1 0 1

Qa Qb 0/1 0 1 0 1/0 1 0 0 no change reset set ?

1 Qa 0 1 Qb 0
1 ns

Time

Not in text
EE 2730 - Fall 2010

Basic (SR) Latch --- delay (t5)

1
R
1 ns

Qa

1 0 0 1
1 ns

0
t1 1 t2 t3 t4 t5 t6 t7 t8 t9 t 10

Qb

1 0
R
0 1 S 0

S R 0 0 1 1 0 1 0 1

Qa Qb 0/1 0 1 0 1/0 1 0 0 no change reset set ?

1 Qa 0 1 Qb 0
1 ns

Time

Not in text
EE 2730 - Fall 2010

Basic (SR) Latch --- delay (t6-t9)

1
R
1 ns

Qa

0 0 1
1 ns

0
t1 1 t2 t3 t4 t5 t6 t7 t8 t9 t 10

Qb

0
R
0 1 S 0

S R 0 0 1 1 0 1 0 1

Qa Qb 0/1 0 1 0 1/0 1 0 0 no change reset set ?

1 Qa 0 1 Qb 0
1 ns

Time

Not in text
EE 2730 - Fall 2010

Basic (SR) Latch --- delay (t10)

1
R
1 ns

Qa

1 0 0
1 ns

0
t1 1 t2 t3 t4 t5 t6 t7 t8 t9 t 10

Qb

1
R
0 1 S 0

S R 0 0 1 1 0 1 0 1

Qa Qb 0/1 0 1 0 1/0 1 0 0 no change reset set ?

1 Qa 0 1 Qb 0
1 ns

Time

Not in text
EE 2730 - Fall 2010

Basic (SR) Latch --- problems?

1 0
R
1 ns

Qa

0 0 0 1
1 ns

0 1
t 10 1

Qb

0 1
R
0 1 S 0

S R 0 0 1 1 0 1 0 1

Qa Qb 0/1 0 1 0 1/0 1 0 0 no change reset set ?

1 Qa 0 1 Qb 0
1 ns

Time

Not in text
EE 2730 - Fall 2010

Basic (SR) Latch --- problems?

0
R
1 ns

Qa

1 0 0 1 0
1 ns

1 0
t 10 1

Qb

1 0
R
0

1
S R 0 0 1 1 0 1 0 1 Qa Qb 0/1 0 1 0 1/0 1 0 0 no change reset set ?

1 S 0 1 Qa 0 1 Qb 0
1 ns

Time

Not in text
EE 2730 - Fall 2010

Basic (SR) Latch --- problems?

1 0
R
1 ns

Qa

0 0

0
t 10 1

0 1

1 ns

Qb

0
R
0 1 S 0

S R 0 0 1 1 0 1 0 1

Qa Qb 0/1 0 1 0 1/0 1 0 0 no change reset set ?

1 Qa 0 1 Qb 0
1 ns

Time

Not in text
EE 2730 - Fall 2010

Basic (SR) Latch --- Oscillation

1 0
R
1 ns

Qa

0 0

0
t 10 1

O/p depends on gate speed Unpredictable Undefined mode

0 1

1 ns

Qb

0
R
0 1 S 0

S R 0 0 1 1 0 1 0 1

Qa Qb 0/1 0 1 0 1/0 1 0 0 no change reset set ?

1 Qa 0 1 Qb 0
1 ns

Time

Not in text
EE 2730 - Fall 2010

Timing Diagram

See Solved Example 7.17 page 473 of text

EE 2730 - Fall 2010

Gated SR Latch

S R 0 0 1 1 0 1 0 1

Q Q 0/1 0 1 0 1/0 1 0 0 no change reset set ?

S, R Bad notation

EE 2730 - Fall 2010

Gated SR Latch

Alternate graphical symbol

EE 2730 - Fall 2010

S R Latch
S
Q

S R 0 0 0 1 1 0 1 1

Q(t+1) 1 0 Q(t) undefined mode set reset no change

EE 2730 - Fall 2010

S-R Gated Latch with NAND Gates

S R
S

Q(t+1) 1 0 Q(t) Q(t+1) 1 0 Q(t) undefined mode set reset no change undefined mode set reset no change

S
Q

Clk

0 0 0 1 1 0 1 1 S R 1 1 0 0 1 0 1 0

Q
R

When Clk = 1 Graphical symbol Same as before

EE 2730 - Fall 2010

Gated D Latch

S R

Q(t+1)

1 1 0 0

1 0 1 0

1 0 Q(t)

undefined mode set reset no change

S = R Undefined mode not possible

EE 2730 - Fall 2010

Setup (tsu) and Hold (th) Times

t su th Clk D Q

Minimum times around falling edge of clock when D should be stable Figure does not show propagation delay
EE 2730 - Fall 2010

Edge Triggering
clk

Level triggering

Edge triggering
clk

positive edge triggering negative edge triggering

EE 2730 - Fall 2010

Master-Slave D Flip-Flop
Master D Clock D Q Qm Slave D Q Qs Q Q Clk Q Clk Q

One way to implement an edge-triggered flip-flop Uses level triggered device (latch)
EE 2730 - Fall 2010

Master-Slave D Flip-Flop
Master D Clock D Q Qm Slave D Q Qs Q Q Clk Q Clk Q

Clock

EE 2730 - Fall 2010

Master-Slave D Flip-Flop
Master D Clock D Q Qm Slave D Q Qs Q Q Clk Q Clk Q

Clock

D
Qm

EE 2730 - Fall 2010

Master-Slave D Flip-Flop
Master D Clock D Q Qm Slave D Q Qs Q Q Clk Q Clk Q

Notice the negative edge-triggering Operates as a D flip-flop

Clock

D
Qm Q = Qs

EE 2730 - Fall 2010

Master-Slave D Flip-Flop
Master D Clock D Q Qm Slave D Q Qs Q Q D D Q Q Q Q Clk Q Clk Q

Clock

Dynamic indicator Can make it positive edge-triggered Needs 8 NAND gates

D
Qm Q = Qs

EE 2730 - Fall 2010

Edge-Triggered D Flip-Flop
Recall the S-R latch
S
Q

S R 0 0 0 1 1 0 1 1

Q(t+1) 1 0 Q(t) undefined mode set reset no change

If R = (S) = x, then Q(t+1) = R = x and Q(t+1) = S = x

EE 2730 - Fall 2010

Edge-Triggered D Flip-Flop
1 P3

D
P1 5 Q

Clock

Clock P2 6 Q

P4

Output changes to value of D when clock changes from 0 to 1 No change in output at any other time Positive edge triggered D Flip-Flop

EE 2730 - Fall 2010

Edge-Triggered D Flip-Flop
1 P3

D
P1 5 Q

Clock

Clock

D
3 P2 6 Q 0 1

Q (t + 1 ) 0 1

Characteristic Table
D 4 P4

Characteristic Equation: Q(t+1) = D

EE 2730 - Fall 2010

Edge-Triggered D Flip-Flop (Clock = 0)

d
1 P3

P1

1 0
Clock

no change

1
3

P2

no change

d
D

Setup time : time needed to get values at P3 and P4 = sum of delays of gates 4 and 1
4 P4

d
EE 2730 - Fall 2010

Edge-Triggered D Flip-Flop (Clock 0 1)

d
1 P3

P1

1 0
Clock

d
d
3 P2 6 Q

d
D

P4

d
EE 2730 - Fall 2010

Edge-Triggered D Flip-Flop (Clock = 1)

1 d
1 P3

Suppose D changes when Clock = 1

P1 5 Q

1 0
Clock

d
d
3 P2 6 Q

d d d
D 4 P4

Hold time : time needed to get a d at P2 = delay of gate 3

d 1
EE 2730 - Fall 2010

Edge-Triggered D Flip-Flop (Clock 1 0)

x d or 1
1 P3

d x
P1

d 1

no change d

1 0
Clock

1 d
3

1 d

P2

no d change

d x or d
D

P4

d or 1 x
EE 2730 - Fall 2010

Level/Edge Positive/Negative
Clock D Q Qc D Q Qc D Q Qb Clk Q Qa D Q Qa

Q Qb

Clock D Qa Qb Qc
EE 2730 - Fall 2010

Level/Edge Positive/Negative
Clock D Q Qc D Q Qc D Q Qb Clk Q Qa D Q Qa

Q Qb

Clock D Qa Qb Qc
EE 2730 - Fall 2010

Level/Edge Positive/Negative
Clock

Q Qc

D Q Qc

Q Qb

D Q Qb

Clk

what if ?
D Q Qa

Q Qa

Clock D Qa

EE 2730 - Fall 2010

Preset and Clear

Preset, when activated, causes

Clear, when activated, causes

Q1 Q 0 Q0 Q 1

Asynchonous causes change at any time (regardless of the triggering edge of the clock) Synchronoues causes change only at the triggering edge of the clock
EE 2730 - Fall 2010

Preset and Clear

Preset Preset D Clock Q Q Clear Q D

Clear

When (Preset) = 0, show that Q = 1 and Q = 0 When (Clear) = 0, show that Q = 0 and Q = 1 When (Preset) = (Clear) = 1, show that there is no effect of these inputs
EE 2730 - Fall 2010

Preset and Clear

Preset

1
D Clock

1
Q

Preset D

Q
Q

Clear

Clear

When (Preset) = 0, show that Q = 1 and Q = 0 When (Clear) = 0, show that Q = 0 and Q = 1 When (Preset) = (Clear) = 1, show that there is no effect of these inputs
EE 2730 - Fall 2010

Preset and Clear

Preset D Clock Q Q Clear

Preset

1
Q D Q

1
Clear

When (Preset) = 0, show that Q = 1 and Q = 0 When (Clear) = 0, show that Q = 0 and Q = 1 When (Preset) = (Clear) = 1, show that there is no effect of these inputs
EE 2730 - Fall 2010

Preset and Clear

See Figure 7.14 (a), (b) from text

Synchronous clear

Clear
D Clock D Q Q

EE 2730 - Fall 2010

Flip-Flop Timing Parameters

Not respecting set-up and hold times can cause metastability Propagation time has max and min
EE 2730 - Fall 2010

T-Flip-Flop
T D T Q Q Q Q Q Q

Clock

T 0 1

Q(t + 1) Q(t ) Q(t )

Clock

no change toggle

T Q

Characteristic Table Characteristic Equation : Q(t+1) = Q(t) + T

EE 2730 - Fall 2010

T-Flip-Flop
T D T Q Q Q Q Q Q

Clock

T 0 1

Q(t + 1) Q(t ) Q(t )

no change toggle

Characteristic Equation : Q(t+1) = D = TQ(t) + TQ(t) = Q(t+1) = Q(t) + T

Characteristic Table

EE 2730 - Fall 2010

JK Flip-Flop
J D Q Q Q Q J Q

K
Clock

J K Q ( t + 1) 0 0 1 1 0 1 0 1

Characteristic Equation: Q(t+1) = JQ(t) + KQ(t)

Q (t) 0 1 Q (t )

EE 2730 - Fall 2010