Hi guys.

Im Naman Gupta, from ECE-07 batch and these are the few placement papers of the companies for which I sat, just for your reference before you sit down to start preparing for your placements. I strongly feel that it should give you a good idea of what to expect and how to go about your preparation. In case you feel the need to ask about the books or to even get the material we all gathered from our seniors or anything else, please feel free to reach me at palindrome1989@gmail.com. I request you all to add your placement papers and pass them to your juniors. It will really help. Wishing you all the best for your placements! A few placement papers:
-Atrenta

Placement Paper, NSIT, August 6, 2010..

The paper had 3 sections. First was the Programming section with questions in basic C, Data Structures and one question on C++

Section 1: Programming:
1)

How would you interchange the value stored in two variables without using a temporary variable.

2) One question based on the padding used in structures, where the the structure in the question had one char, one int and one float in different order and hence the size of structure and the pointer variables to these structures was asked. 3) Simple questions on strings.. (2 such questions, make sure you play around with pointers and strings). 4) Program to find mirror image of a tree. 5) Implementation of Stack. 6) Some simple questions picked up straight from crack_the_interview pdf.. Make sure you do that well.. 7) Hashing (Interview)

Section 2: Digital Circuits and Systems:

1)

Make a 5:1 MUX USING 4 2:1 MUXs..

2) How many MUXs would be required to make any general n:1 MUX and hence 7:1 MUX? 3) Counter decoding.. Where a counter circuit (using gates and FFs is given) and you are required to decode the circuit and probably tell the mod number of that counter.. 4) Simple problem statements were given and we were required to make an appropriate digital circuit just by solving K-maps. (2 such questions) 5) A combinational circuit was given and we were asked to minimize the number of gates in that circuit. 6) Two ways to generate a clock signal.. (Interview) 7) Binary to Gray and Gray to Binary Conversion..using FFs.. (Interview) 8) 2 ways to convert Gray back into binary (tricky).. (Interview)

9) SOP to POS.. (Interview)

Section 3: Aptitude:

Aptitude was pretty tricky. But not impossible at all. In the end 14 were shortlisted for the interview and 4 (2ECE, 2 COE) were selected.

NVIDIA

Placement Paper, NSIT, Sept 7, 2010..

1)Divisible by 5 FSM.. 2)FIFO Buffer.. Certain writing frequency, certain reading frequency and there were wait or idle states between any two successive reads and we were asked to find the minimum size of the FIFO buffer required to prevent any loss of data. 3)Questions from Chapter 10, Sedra and Smith where one is supposed to realize an arbitrary boolean expression using NMOS and PMOS..and also vice versa i.e. Boolean expression from any given NMOS or PMOS network or to derive NMOS network from given PMOS network or vice-versa.. 4)2 ways to make an inverter out of a NAND gate..which one would be better in terms of power dissipation and switching speed.. 5)Setup and Hold time.. 6)Delay Theory.. (2-3 questions) 7)Pipelining.. 8)Number of bits required for the Cache Memory.. (You may refer to the book by Patterson). 9) o, t, t, f, f, s, s, e, n, ___ What should be in this blank? 10)Changing the clock frequency would affect: Hold Time or Setup time or both or none? 11)A program to find factorial of a number was implemented with and without using recursion. Using which of the above two methods would you be able to find the factorial of a larger number and why? 12)One simple question on C++ (Provided you know the basics, which unfortunately I didnt). 5 were shortlisted for the interviews and in the end two made it. In the interview, they didnt ask much. I was expecting a 1 hour of a grilling interview but it lasted for just 15 minutes for each candidate.

Cosmic

Circuits Placement Paper:

Total of 15 questions in 60 or probably 90 minutes.. 1) One question on maximum clock frequency of a digital circuit. 2) An op-amp circuit was given with positive as well as negative feedback resistors but the value of these was unknown and we were asked to choose the appropriate value so that the circuit is stable. 3) Level Shifter circuit using two MOS and two capacitors. (This was a tricky question) 4) Controlled Voltage/Current Sources- Choose which controlled source does the circuit represent. 5) Output impedance of n cascaded Common Gate amplifiers. 6) Square wave of1KHz frequency passed through an LPF of cut off frequency 2KHz. Find the maximum amplitude of the output. 7) MOSFET with an inductor connected in its drain and then the inductor to VDD. Source was grounded and a square wave was applied at the input and we had to plot the output waveform. Output was taken across the drain and the source.. 8) One question based on ADCs and DACs. I didnt even understand the question! 9) One simple question on clampers.. 10) 2 questions from LIC where we had to find the T/F of the op-amp based circuit. 11) One question on circuit resistance noise, where we had to find the component values such that the total circuit noise is less than a certain value.. In the interview, they asked the same questions from the test. Cosmic Circuits repeated the last year paper (which unfortunately many people had) and on the top of that, they went to DCE the next day, and again took the same paper! :P So, Id suggest that you do this paper thoroughly, because you never know what will happen next year!

Kritikal Solutions Placement Paper, NSIT, Sept 28, 2010..

The paper had 3 sections.. First was basic C, 2nd Aptitude and final electronics.. COE people had Algorithms instead of Electronics.. Questions in the programming section (common for all) were pretty simple and any book by Yashwant Kanetkar would suffice for that. Questions asked were pretty common and a look through the placement papers of different companies would be more than enough (if youre an ECE person). 1) Setup and hold time.. 2)Zener Diode.. 3)Divisible by 3 FSM.. 4)EX-OR gate using 4 NAND gates and EX-NOR gate using 4 NOR gates.. 5)AND and OR gates using Diodes.. 6)How would you double the clock frequency using combinational circuits.. 7) Analog Differentiator. 8) FSM for y(t)=x(t-2); Serial Adder, Pattern Detector. 9) Log Amplifier 10) Voltage Regulator Aptitude Section was fun to solve, had around 7-8 questions. In the end 3 from ECE and 1 from COE were selected..

Electronics Section:

 Freescale Placement Paper: Decemeber 17, 2010.. N.S.I.T..

The paper had 15 sections, 13 from Digital Electronics, 1 from Analog and 1 was an objective MCQ question containing 5 parts.. 1) A simple question on clippers where one diode was clipping the positive side of the waveform and other was clipping the negative side of the waveform. We were asked to draw that very waveform. Just go through the basic clipper circuits that you studied in 3rd sem. 2) One simulation result with clock input, input to the circuit and the circuit output were given and we were asked to decipher what the circuit was doing and make the circuit to realize that. The circuit was basically that whenever thered be a change in the input signal, the output would go high for one clock cycle. (I solved this question using FSMs). 3) A simple question to realize a digital logic function (given in form of minterms and dont cares) and we simply had to solve the Karnaugh Map and make the circuit. 4) Another question where the terms were this time given in POS form and we had to solve the Kmap in SOP form and make the circuit. 5) Realize all basic gates (NOT, OR, AND,NAND, NOR) using 2:1 MUX. 6) Realize a given digital function (with 4 input variables) using only 2:1 MUX. Idea was to basically do it using 8:1 MUX and replace that multiplexer with 7 2:1 MUXs. 7) Digital Circuit to replicate the input clock at the output. (Many possible solutions, I probably did it using FSMs). 8) Another waveform was given, where the output was like 1 0 0 0 1 0 0 0 1 0 0 0 . Where the changes obviously happened at clock edges. And we had to realize the circuit. 9) An arbitrary 5 input digital function something like: Y= (A.B)+(A.C.E)+(B.E)+(C.D.E) and we had to make a fully static CMOS circuit using only 10 transistors. (Clueless how to do it in just 10!) 10) One question on stuck-at-0 fault and the test vector required to detect that fault. 11) One question on setup and hold time and the maximum clock frequency. 12) Minimum combinational circuit to detect whether two 8-bit numbers are equal or not. 13) Minimizing a given digital circuit to realize the same function. 14) Aptitude question. 15) Cant recall one last question.. In the interview, I was asked about A lot of stuff from CMOS, Digital Electronics- Flip Flops, Counters, Basic stuff from Analog Communication, VHDL etc.. One technical was followed by 2 HRs. In the end 6 were selected.