LOW POWER VLSI DESIGN Sub Code : 08EC047 Max. Marks: 100 Question No.

1-34 carries 1Marks each Question No. 35-42 carries 2Marks each Question No. 43 carries 3 Marks each Question No. 44-46 carries 4 Marks each Question No. 47-53 carries 5Marks

1) Power is the rate at which energy is delivered or exchanged. a) True b) False 2) The low power VLSI design problems are classified in to two _______ &_________ a) Optimization , Analysis b) Estimation , Identification c) Power, Energy d) All the above 3) Increased operating frequency and processing capacity per chip results in __________power dissipation. a) b) c) d) decreased increased no effect none

4) Low power chips are needed because a) increased demand for portable devices b) increased computational complexities c) increased power dissipation d) Environmental concern e)All of the above a) b) c) d) 5) Dynamic power dissipation is due to switching activity of the circuit high operating frequency charging and discharging of the capacitor All

a) b)

6) Higher operating frequency results in Increased power dissipation Reduced power dissipation

7) Capacitors are fabricated intentionally for a) non digital operations b) digital operations c) both a & b d) none 8) The energy stored in capacitor is a) CV2 b) CV2 /2 c) 2 CV2 d) none 9) Delay in a circuit is minimized when a. p/ n =2.2 b. p/ n >6 c. p/n =1.5 d. None of the above 10) SPICE stands for____________ a. Simulation program with Inter-digital Circuit Emphasis b. Specification program with Integrated Circuit Emphasis c. Summation of program with Integrated Circuit Emphasis d. Simulation program with Integrated Circuit Emphasis 11) Transmission gate amplifies the signal a) True b) False 12) The effect of data correlation on power dissipation depends on ----------representation of the digital system. a) Digital b) numerical c) both d) none 13) If the LSB BIT toggle at approximately half the maximum frequency, then it is called as a) sign bit b)uniform white noise c) noise bit d)none 14) In probabilistic analysis, a logical signal is viewed as a random zero-one process with certain __________characteristic. a. dynamical b. Statistical c. both d. none

15) The probabilistic approach is mainly been developed for ______________ and above. a. circuit level abstraction b. Gate level abstraction c. architectural level abstraction d. none 16) In both continues and discrete signal model, the switching frequency of a digital signal is defined as _______ the number of transition per unit time. a. twice b. same c. Half d. thrice 17) For an AND gate, If the static probabilities of the inputs are p1 and p2 respectively and two signals are statistically uncorrelated, the output static probability is ______ a. p1p2 b. p1+p2 c. p1/p2 d. p1-p2 18) In grey area, the toggle frequency changes from sign bit to white noise. (True/ False) 19) In lag-one signal model, how many independent variables are required for charactizing the logic signal? a. Zero b. one c. two d. three

20) What is the expected maximum frequency of a memoryless random? a) 0.50 b. 0.75 c. 0.25 d. 1 21) By increasing the output capacitance increases the short-circuit power dissipation but the sum of capacitive and short-circuit power increases. a) True b) False 22) The ______________are used for controlling the timing of computations in synchronous systems. a) Flip-Flop b) Latch c) Both d) None 23) Edge triggered flip-flops are made up of __________________ a. Two CMOS latches b. Two CMOS flip-flops c. Two CMOS latches d. Two CMOS flip-flops

24) Bus invert coding is suitable for a set of ___________signals. a) Parallel synchronous b) Parallel asynchronous c) Synchronous d) Serial synchronous 25) Objective function of F. S. M. a) Minimize the transition b) Maximize the transition c) Decreases the no of bits d) None of these 26) In precomputation logic, due to the nature of function f(X), there may be some conditions under which the output of f(X) is ______________of logic value of R2. a) Independent b) Dependent c) Un defined d) None 27) The important component of the algorithm inherent dissipation is the ______________ Power, a) memory b) circuit c) gate d) none 28) Buffers have to be used to drive the _______ load capacitance on a clock. a) b) c) d) small large single all the above

29) Most techniques used for skew minimization are based on adjusting the interconnect_______. e) length

f) width g) length and width h) none

30) The process of matching a given algorithm onto particular architecture style is called architecture synthesis. a) True b) False 31) In filp chip Technology , The flip-chip has i) j) k) l) Highest IO density Smallest chip size Lowest inductance All the above

32) Moores law predicts __________ a. growth rate of integrated circuits b. number of transistors c. size of the chip d. Both a and b 33) Every 0.1 V reduction in the Vt raises the I static by __________. c) d) e) f) 10 times. 20 times. 100 times. 200 times.

34) Architecture level abstraction is also called as ______________. a) Block level b) Macro level c) Both d) None 35) For the power minimization in a clock tree, _______ buffers scheme is preferred over the _______ buffer schemes. a) Single , distributed b) Distributed, single c) Double single

d) Multiple, many 36) In positive correlation, LSB bits of the data bus toggle _____ while the MSB are ______. a. frequently, relatively quiet b. irregularly, relatively quiet c. seldom, relatively quiet d. infrequently, unchanged 37) The duration of the short circuit current is _________ on the output capacitance because it depends on the _______ signal slope only. dependent, input independent, input independent, output dependent, input 38) Reverse biase leakage current and subthreshold leakage current are ------------on temperature and --------------of operating voltage a)dependent , independent b) independent, dependent c) dependent, dependent d) independent, independent 39) Switching factor for 2 input clocked 2 input NAND gate is given by a) b) c) 3/16 d) none 40) Give the three steps for Monte Carlo Power Simulation. a. calculate N, evaluate and S2 of pi, check N for calculated value. b. assume N and simulate pi, evaluate and S2, check for the inequality for Nif no, increase N. c. calculate pi, evaluate and S2, find the value of N. d. none of the above. 41) The total number of transitions in a 6-bit binary counters is________________. a. 124 b. 125 c. 126 d. 120

a. b. c. d.

42) Calculate the expectation of switching per transition for the following state diagram:

a. 1

b. 2

c. 3

d. 4

43) Match the following 1. Information Content a. Ci Vdd2 fs 2. Entropy of the signal b. i=1m Pi 3. Power dissipation in circuit c. log2(1/Pi) a) b) c) d) cba abc bac cab

44) Match the following 1. Latches 2. Flip-flops 3. Faster 4. Slower a) b) c) d) abdc bacd adcb abcd a. Edge sensitive b. Level sensitive c. Latches d. Flip-flops

45) Match the following 1. Circuit simulation 2. Logic simulation 3. Behavioral-level simulation 4. Gate-level simulation a. performed to refine the initial estimate b. offers rapid analysis with less accuracy c. cannot be applied to full chip analysis d. can handle full chip analysis

a) b) c) d)

cdba cdab daba dcba

46) Match the following 1. Continues 2. discrete 3. lag-n signal model 4. lag-one signal model a. accurate characterization of random signals. b. reflect the precise time of signal transition c. simplicity of signal representation and processing d. n+1 degree of freedom.

a) b) c) d)

bcda abdc cdba dcab

47) A 32 bit off chip bus operating at 5 v and 66 MHz clock rate is driving a capacitance of 25 pF/bit. Each bit is estimated to have a toggling probability of 0.25 at each clock cycle.What is the power dissipation in operating the bus? a) 330mw b) 440mw c) 220mw d) none 48) Find the output static probability P(y), in terms of the input static probabilities P(a), P(b), and P(c), using Shannons Decomposition Method. The Boolean function is y = a + bc. a) P(y) = P(b) + P(b).P(c) P(a)P(b)P(c) b) P(y) = P(a) + P(b).P(c) P(a)P(b)P(c) c) P(y) = P(a) + P(a).P(c) P(a)P(b)P(c) d)None of the above 49) Compute the transition density of y = a + bc, given P(a) = 0.4, P(b) = 0.3, P(c) = 0.2. D(a) = 3, D(b) = 2 and D(c) = 1 a. D(y) = 4.32 b. D(y) = 2.34

c. D(y) = 3.24 d. D(y) = 1.23 50) Match the following 1. F S.M a. By Designer 2. Vrilog & VHDL b. Determined by Encoding 3. Quality c. gate level circuit 4. Transition graph d. For Synthesis state machine 5. Synthesis System e. Reducing power dissipation. a) abced b) adbce c) adbac d) dbcae

51) Match the following 1. Pint 2. Pstat 3. Pcap 4. SPICE a.(1/2)CV2 b.KVL c. = neti CiV2fi d. = g s P(g.s). T(g.s) T e.= g e E(g.e) f(g.e) a) b) c) d) edcba edabc edcab abcde

5. ES

52) The chip size of a CPU is 15mm x 25mm with clock frequency of 300MHz operating at 3.3V. The length of the clock routing is estimated to be twice the circumference of the chip. Assume that the clock signal is routed on a metal layer with width of 1.2m and the parasitic capacitance of the metal layer is 1fF/ m2. What is the power dissipation of the clock signal? a. 625mW b. 620mW c. 600mW d. 627mW

53) Match the following 1.synchronous 2. asynchronous 3.Single driver 4.distrubuted buffer a) b) c) d) dcba dcab dabc abcd a. Intermediate buffer b. Single strong buffer c. Independs on the clock d. Depends on the clock