II N I DUNG

1. T ng quan v ASIC
1.1 ASIC l g?
- ASIC l vi t t t c a c m t application-specific integrated circuit trong ti ng Anh, l m t thu t ng ch cc vi m ch tch h p chuyn d ng trong i n t h c . - ASIC l m t vi m ch c thi t k dnh cho m t ng d ng c th . ASIC ngy nay c ng d ng h u nh kh p m i n i, v d nh vi x l c a i n tho i di ng, hay chip x l trong cc my mc t ng, cc ph ng ti n truy n thng, xe c , tu v tr , cc h th ng x l, cc dy chuy n cng nghi p... - Khi ni m ASIC l m t khi ni m t ng i r ng v lin quan n cng ngh thi t k s n xu t IC ch khng ph i g n v i m t dng s n ph m hay thi t b c th . i l p v i ASIC l cc vi m ch tch h p cho m c ch chung nh 7400 series v 4000 series nh ng vi m ch ny c th lin k t t o ra nhi u ng d ng khc nhau. Ngoi ra v tnh t ng i c a vi c phn lo i theo m c ch s d ng m cn c thm khi ni m Application Specific Standard Product (ASSP) thi t b chu n cho ng d ng c bi t, ch n nh ng vi m ch n m gi a hai khi ni m ASIC v vi m ch tch h p cho m c ch chung.

1.2 Cc lo i ASIC
 Full-custom ASIC (ASIC c ch hon ton)  Semi-custom ASIC (ASIC c ch bn ph n) o Standard-Cell-Based ASIC: ASIC d a trn cc t bo chu n. o Gate-Array-Based ASIC: ASIC d a trn m ng c ng lgc  Progammable ASIC (ASIC l p trnh c) o Programmable Logic Devices (PLD): Thi t b logic c th l p trnh c. o Field-Programmable Gate Array (FPGA): M ng c ng lgc c th l p trnh c theo tr ng/mi n. 1.2.1 Full-custom ASIC Trong m t full-custom ASIC, ng i k s thi t k m t s ho c t t c cc cell logic, cc m ch ho c layout m t cch c th cho m t ASIC i u ny c ngh a l ng i k s t b ph ng php s d ng cc cell c m t tr c v c ki m tra tr c cho t t c ho c m t ph n c a thi t k . i u ny c ngh a ph ng php ny ch c ngh a n u khng s n c cc th vi n cell hi n hnh thch h p, cc th vi n ny c th c s d ng cho ton b thi t k . i u ny c th do cc th vi n cell hi n hnh khng nhanh ho c cc cell logic khng nh ho c tiu th nhi u cng su t. Ta c th c n s d ng thi t k full-custom n u cng ngh ASIC l m i ho c chuyn d ng n m c khng c cc th vi n hi n hnh no ho c do ASIC chuyn d ng n m c m t s m ch ph i c thi t k tu thu c vo khch hng. Ngy cng t cc fullcustom IC c thi t k do c nhi u v n v i cc thnh ph n c bi t ny

c a ASIC Tuy nhi n c m t thnh vi n c a h ny ang l n m nh, ASIC h n h t ng t

1.2.2 Standard-Cell-Based ASIC C c ASIC d a t n cell ased IC (CBIC m t t thng d ng Nh t B n) s d ng cc l gic cell thi t k s n ( c ng AND, c ng OR, multi lexers, v c g i l standard cells. Chng ta c th s d ng thu t ng CBIC fli fl s) cho t t c cc IC s d ng cell, nh ng thng th ng cell ased ASIC ho c CBIC c ngh a l standard cells-based ASIC. Cc vng standard cells (hay cn g i l flexible blocks) trong CBIC c t o nn t nhi u hng c a standard cells-gi ng nh b c t ng xy t cc vin g ch. Cc standard cells c th s d ng k t h v i cc cells l n c c thi t k s n, c th l b vi i u khi n ho c ngay c l b vi x l , bi t nh l megacell. Megacell cn c g i l megafunction, full-custom block, system-level macros (SLMs), fixed blocks, cores, or unctional Standard Blocks ( SBs). Ng i thi t k ASIC ch nh ngh a v tr c a standard cells v interconnect trong 1 CBIC. Tuy nhin, standard cells c th c tb tk u trn silicon, i u ny c ngh a l t t c cc mask layers c a CBIC c thi t k theo yu c u v l duy nh t i v i t ng khch hng. Thu n l i c a CBIC l ng i thi t k s ti t ki m c th i gian, ti n b c, v gi m r i ro c ki m tra b ng vi c s d ng th vi n standard-cell thi t k s n v tr c.thm vo , m i standard-cell c th c xem xt m t cch ring l . Trong qu trnh thi t k th vi n cell, t ng transitor trong m i standard-cell c th c ch n n t c c c i hay di n tch t i thi u,v d v y. B t l i c a CBIC l th i gian hay chi ph thi t k ho c mua th vi n standard-cell l r t cao v th i gian c n ch t o t t c layers c a ASIC cho m i thi t k m i l r t di. Cc tnh ch t quan tr ng c a ASIC lo i ny: - T t c cc mask layer u ty thu c vo khch hng cc transistor v cc interconnect. - Cc kh i ty thu c vo khch hng c th c nhng(embedded). - Th i gian s n xu t kho ng 8 tu n l .

Hnh: khun c a ASIC d a trn cell (CBIC) c m t mi n cell chu n duy nh t (kh i linh ho t) cng v i 4 kh i c nh

Standard-cell area: mi n cell chu n. ixed blocks: cc kh i c nh.

1.2.3 Gate-Array-Based ASIC Trong m t d i c ng GA (gate array) ho c ASIC d a trn d i c ng (gate array based ASIC), cc transsitor c xc nh trn mi ng silic.Bi u xc nh tr c cc transsitor trn m t d i c ng l d i n n (base array), v thnh ph n nh nh t c t o b n sao th c hi n d i n n l cell n n (base cell), gi ng nh cc vin g ch trn sn nh (th nh tho ng c g i l cell s c p (primitive cell)). Ch vi l p kim lo i trn nh, cc l p ny xc nh lin k t n i gi a cc transsitor, c xc nh b i ng i thi t k b ng cch s d ng cc m t n tu thu c vo khch hng (custom mask). phn bi t lo i d i c ng ny v i cc lo i d i c ng khc, d i c ng ny th ng c g i l d i c ng c l p m t n MGA (masked gate array). Ng i thi t k ch n cc cell logic c thi t k tr c v c m t tr c t th vi n d i c ng. Cc cell logic trong m t th vi n d i c ng th ng c g i l cc macro. L do cho vi c g i ny l cc layout cell nn (base-cell layout) gi ng nhau cho m i m t cell logic, v ch c lin k t n i (bn trong cc cell v gi a cc cell) l tu thu c vo khch hng, sao cho c m t t ng ng gi a cc macro d i c ng v macro c a ph n m m. Bn trong IBM, cc macro d i c ng c g i l cc book (do v y cc book l ph n c a th vi n), nh ng th t khng may thu t ng m t ny khng cs d ng ph bi n bn ngoi IBM. Ta c th hon t t cc b c kh ch tn t o thnh cc transsitor v k n d tr cc mi ng silic ( i khi ta g i m t d i c ng l m t d i c kh ch tn tr c (prediffused array) do b i l do ny. V ch c cc lin k t n i cc kim lo i l duy nh t i v i MGA, ta c th s d ng cc mi ng silic c d tr cho nhi u khch hng khc nhau khi c n n. Vi c s d ng cc mi ng silic c s n xu t tr c cc b c kim lo i ho lm gi m th i gian c n thi t ch t o m t MGA, th i gian thay i hon ton (turnaround), cn vi ngy ho c t i a l hai tu n. Gi thnh cho t t c cc b c ch t o ban u i v i MGA c chia s cho m i m t khch hng v i u ny lm gi m gi thnh c a MGA so v i thi t k full-custom ASIC ho c ASIC d a trn cell chu n. Ta c cc lo i MGA ho c ASIC d a trn d i c ng khc nhau sau y: D i c ng c chia knh (channeled gate-array). D i c ng khng chia knh (channeless gate-array). D i c ng c c u trc (structured gate-array).

a. D i c ng c chia knh c i m quan tr ng c a lo i MGA ny l : - Ch c lin k t n i l ty bi n.

- Lin k t n i s d ng cc kho ng tr ng xc nh tr base cell. - Th i gian s n xu t 2 ngy n 2 tu n.

c gi a cc hng c a

Hnh: Khun c a d i c ng c chia knh. Cc kho ng cch gi a cc hng cell n n c dnh cho lin k tn i

Base cell: cell n n. b. D i c ng khng chia knh D i c ng khng chia knh (cn g i l d i c ng knh t do[channel-free gate array], d i nhi u c ng[sea-of-gate array] ho c d i SO ). Cc tnh ch t quan tr ng: o Ch c m t s l p m t n ty thu c vo khch hng lin k t n i. o Th i gian s n xu t t 2 ngy n 2 tu n.

Hnh: Khun d i c ng khng chia knh. Di n tch li

c a die l p y hon ton b i m ng c a base cell (the base array) Base cell:cell n n. Array of base cells (not all show): d i cc cell n n (khng

c trnh by)

S khc bi t gi a channelless gate array v channeled gate array l khng c vng di n tch no nh ngh a s n dnh cho routing gi a cell trn 1 channelless gate array. Thay v v y ta ph i nh v trn nh c a thi t b .chng ta c th lm i u ny b i v chng ta ty bi n contact layer ( nh ngh a s k t n i gi a metal1, l p kim lo i u tin v transistor). c. D i c ng c c u trc D i c ng c nhng (embedded gate array) ho c d i c ng c c u trc (structured gate array) k t h p m t s tnh ch t c a CBIC v m t s tnh ch t c a MGA. M t trong nh ng i m b t l i c a MGA l cell n n d i c ng c b nc nh. i u ny lm cho vi c th c hi n, th d , b nh s kh kh n v khng hiu qu .Trong m t d i c ng c nhng ta d tr m t vng no

 trong IC v dnh ring vng ny cho ch c n ng c th . Vng c nhng ny ho c c th ch a m t cell n n khc thch h p h n i v i vi c xy d ng cc cell nh , ho c c th ch a m t kh i m ch hon ch nh, ch ng h n nh m t b vi i u khi n. Cc tnh ch t quan tr ng c a lo i MGA ny nh sau: o Ch c lin k t n i tu thu c vo khch h ng. o Cc kh i tu thu c vo khch hng (gi ng nhau cho m i m t thi t k ) c th c nhng. o Th i gian s n xu t t 2 ngy 2 hai tu n.
Hnh: Khun c a d i c ng c nhng ho c c c u trc trnh by m t kh i nhng gc trn bn tri. Ph n cn l i c a khun c lm y b ng d i cc cell chu n.

Embeded block: kh i nhng. Array of base cells (not all show): d i cc cell n n (khng by).

c trnh

1.2.4 Programmable Logic Devices (PLD) c PLD (programmable logic device) l cc IC Cc linh ki n logic l p trnh chu n c s n d i d ng cc c u hnh chu n t sch tra c u cc linh ki n v c bn v i s l ng l n n nhi u khch hng khc nhau.Tuy nhin, cc PLD c th c c u hnh ho c c l p trnh t o ra ph n tu thu c khch hng cho m t ng d ng c th , v do v y chng c ng thu c vo h cc ASIC. Cc PLD s d ng cc cng ngh khc nhau cho php ta l p trnh chip. Hnh sau trnh by m t PLD v cc tnh ch t quan tr ng m t t c cc PLD u c: - Khng c l p m t n ho c cc cell logic no ty thu c vo khch hng. - Th i gian thi t k nhanh. - Kh i lin k t n i l p trnh c l n, duy nh t. - Ma tr n microcell logic th ng bao g m m ch logic d i l p trnh cPAL(programmable array logic), theo sau b i m t flipflop ho c b ch t.

Hnh Khun c a chip logic l p trnh c PLD. Cc macrocell i n hnh bao g m m ch logic d i l p trnh c PAL c theo sau b i m t flipflop ho c b ch t. Cc macrocell c k t n i b ng cch s d ng kh i lin k t n i l p trnh c l n.

1.2.5 Field-Programmable Gate Array (FPGA) Trn PLD m t b c v ph c t p l d i c ng l p trnh c d ng tr ng PGA.S khc bi t gi a PGA v PLD l PGA l n h n v ph c t p h n so v i PLD. PGA l thnh vin m i trong h ASIC v ang pht tri n r t nhanh chng, thay th TTL trong h thng vi i n t . Hnh sau minh h a cc c tnh ch y u c a m t PGA - Khng c l p m t n no ty thu c vo khch hng. - Ph ng php l p trnh cc cell logic c b n v lin k t n i. - Li l d i c h th ng cc cell logic c b n l p trnh c, c th th c hi n h t h p c ng nh h tu n t . - Ma tr n lin k t n i l p trnh c bao quanh cc cell logic c b n. - Cc cell I/O l p trnh c bao quanh li. - Th i gian thi t k ch m t vi gi .
Hnh: Khun c a d i l p trnh c PGA. T t c cc PGA u ch a m t c u trc c h th ng cc cell logic c b n l p trnh c, c bao quanh b i cc lin k t n i l p trnh c.Lo i, kch th c v s cell logic l p trnh c b n c bi n thin r t l n.

Programmable basic logic cell: cell logic c b n l p trnh Programmable interconnect: lin k t n i l p trnh c.

c.

2. Qui trnh thi t k ASIC

2.1 Qui trnh thi t k chung

Hnh 2.1: ASIC design flow 1. M t bi ton: s d ng ngn ng m t p h n c ng HDL (VHDL hay Verilog). 2. T ng h p logic: dng HDL v cng c t ng h p logic xy d ng netlist l s m t cc t bo (cell), cc kh i (block) v k t n i (interconnect) gi a chng. 3. Phn chia h th ng:chia h th ng l n thnh cc ph n thch h p. 4. M ph ng ti n layout:ki m tra tnh ng n c a thi t k (ti n layout = s m ch logic ch g n ng v i th c t ). 5. S p x p cc kh i trn chip:s p x p cc kh i c a netlist trn chip. Nn xem xt c kha c nh v t l v logic khi thi t k b c ny. 6. B tr cell: nh v cell bn trong kh i. 7. Thi t k tuy n:k t n i gi a cc cell v cc kh i. 8. Ki m tra tnh h p l c a b c 7:tnh ton tr khng v dung khng l p interconnect. 9. M ph ng h u layout:ki m tra kh n ng lm vi c n nh c a ton b thi t k trong tr ng h p c thm t i t l p interconnect (h u layout = s m ch th ct ).

Trong : Cc b Cc b

c thi t k 1 - 5: logic. c thi t k 5 9 : v t l.

2.2 Qui trnh thi t k c th :

Hnh 2.2: Quy trnh thi t k ASIC

2.2.1 Thi t k ki n trc (Architecture design)

ASIC v i ngh a l IC cho m t ng d ng ring bi t, nn xu t pht t m i ng d ng trong th c ti n cu c s ng, s l b c t ra yu c u ph i thi t k nn IC th a mn c ny c nhi m v ti p nh n cc yu i th c c m t cch t ng quan thi t k c ton b t t nh t nh ng yu c u c a ng d ng . Thi t k ki n trc(Architecture design) u tin c a quy trnh thi t k , b c u c a thi t k v xy d ng nn ki n trc t ng qut c a thi t k . Ng hi n thi t k ki n trc ph i l ng v ph i l ng cc b Cc b in mb t i nhn nh n c kh n ng c a cng ngh , am hi u

c thi t k xuyn su t qui trnh. c t ng quan c a m t qui trnh Thi t K Ki n Trc: c ny, t nh ng yu c u c a thi t k v d a trn i thi t k ki n trc s xy d ng nn ton c ny ng i thi t k ki n

- Define overall chip: Trong b

kh n ng c a cng ngh hi n c, ng trc ph i m t c nh ng v n

b ki n trc t ng quan cho thi t k .Ngh a l trong b sau :  Thi t k c nh ng kh i no ?  M i kh i c ch c n ng g ?  Ho t thi t k . - Initial Floorplan : B ng c a thi t k v c a m i kh i ra sao ?

 Phn tch cc k thu t s d ng trong thi t k v cc cng c , softwave h tr c ti p theo trong thi t k ki n trc l vi c phn y chnh l b n ch t l c nh hnh cho t on b nh.

b , s p x p cc kh i c trong thi t k . Ki n trc c a thi t k h ng n cc b nh h

thi t k . Vi c phn b , s p x p cc kh i ph i theo nh ng nguyn t c nh t ng r t l n

ng c a thi t k v nh

c sau c a quy trnh cho nn vi c phn b ki n trc ph i lm c ny s d ng ngn ng m t ph n c ng ho c ng c a thi t k . Nh m m c ch ki m c ny cn c ngh a m t c th h n, thi t k v c thu n l i h n . ng ng v m t ch c n ng ch a, n u ch a ng c trn. B c sau ny

sao cho thi t k t i u nh t . - RTL or C model: B ngn ng C tra s b xem thi t k c ho t th ph i ch nh s a l i cc b vi c th c hi n thi t k b m ph ng t ng th ho t

lm r rng h n cho ki n trc c a thi t k , gip cho vi c n m b t

2.2.2 Thi t k logic (Logic Design)

Thi t k logic l b m t thi t k .Ng circuit, Cc b c m ph ng t ng th cc ch c n ng logic v t i u ki m tra ton b thi t k , bin d ch netlist i thi t k t o ra m t HDL behavioral model cho nh ng custom

nh ngh a nh ng b vector

v t i u ha thi t k . c t ng quan c a m t qui trnh thi t k logic: i v i cc - Behavioral verilog Thi t k c th g m nhi u kh i standard v custom k t h p v i nhau. kh i standard cells c th dng RTL code c thi t k d khng th dng RTL code ti t tnh n ng c a cc kh i . - Logic simulation Sau khi th c hi n xong cng o n behavioral verilog, ng ph ng t ng th thi t k m c cao nh t (top-level) i thi t k c n m ki m tra thi t k c ho t m t . Tuy nhin i v i cc kh i m t chi

i d ng custom (v d : b nh nhng embeded memory) th c m ph i dng Behavioral verilog

ng ng v i cc tnh n ng yu c u.N u ch a ng ph i ki m tra l i cc kh i standard cell ho c custom circuit. - Logic Synthesis (t ng h p logic) T ng h p logic l qu trnh t ng h p cc RTL code thnh netlist. Qu trnh chia thnh 2 b c: chuy n i cc RTL code thnh m t d i d ng cc bi u th c i s Boolean, d a trn cc bi u th c ny k t h p v i th vi n standard cells s n c t ng h p nn m t thi t k t i u. - Datapath Schematic Nh p netlist v cc rng bu c v timing vo m t cng c phn tch timing. Cng c phn tch timing s tch r i t t c cc path c a design, tnh th i gian tr c a cc path d a trn cc rng bu c. D a trn k t qu phn tch (report) c a cng c phn tch, ta xc d n nh cc path khng th a mn v timing. Ty theo nguyn nhn n khng th a mn m ta c th vi t l i m RTL v ti n hnh l i t ng h p

logic ho c hi u ch nh l i cc rng bu c. Sau khi t t c cc vi ph m timing b lo i b ti n hnh placement v routing.

2.2.3Thi t k m ch (Circuit design)

Sau b c thi t k logic l b c trn, b t v t c thi t k m ch, b c ny xy d ng nn s c th c hi n m ch th c s c a thi t k .D a vo cc yu c u v ch c n ng, tnh n ng thi t l p ra t b nh ng ch c n ng C hai ph - Ph c ny xy d ng nn cc m ch th c s c nh ng tnh n ng thi t k m ch: y l ph ng php ti p ng php ny, h u c yu c u.

ng php ti p c n

ng php ty bi n (custom methodology): c u c th c hi n th cng v

c n thi t k cho m t lo i thi t k v c u hnh c th . V i ph nh m i b i m c a ph ng php ny l t o ra

c t i u ha hon ton. u thi t k ch m v kh y l m t ph ng php

c m t thi t k g n nh t i u ha hon c i m l t c

ton, nh ng b l i, n c ng c nh ng nh n ng ti s d ng l r t th p. - Ph

ng php bin d ch (compiler methodology):

c tnh h th ng cho php xy d ng m t h cc c u hnh c a m t lo i thi t k . Vi c thi t k c th c hi n b ng s xy d ng cc t bo m ch (leaf-cell library t o thnh m t s p x p cc t bo u i mc a ng php ny, c nhi u c u hnh ng trnh bin d ch (Mega Compiler), hay mega-cell library), m i t bo m ch l m t thnh t c s kh i bn trong. Sau , s d ng m t ch v i ph m ch theo m t trnh t xc ng php ny l t c u vo l cc c u hnh mong mu n v th vi n t bo, thi t k r t nhanh, c th t o ra

nh v c u thnh c u hnh cho thi t k . c i m v t i u thi t k .V i ph c t i u nh t.

cng lc, nh ng n c ng c nh vi c t i u thi t k ch Cc b trung gian bn trong d i s khng

c th c hi n trn cc c u hnh bin, v v y cc c u hnh

c t ng quan c a m t qui trnh thi t k m ch: v nn cc b n v m ch. Ph n ny bao g m

- Xy d ng b n v (Circuit schematic): Dng cc cng c xy d ng m ch nh l Power View, Cadence5, nh ng b c nh sau:

 T o cc mega cell: Ty thu c vo m i lo i thi t k , th vi n mega-cell c a chng s khc. Th vi n mega-cell c a m i lo i ch a nh ng t bo m ch c s t o nn c u hnh c a thi t k , v v y chng ta s thay . i ty thu c vo ch c n ng v yu c u c a thi t k t o ra cc mega-cell, c th s d ng

l i cc c u trc m ch chu n c s n nh l bit cell 6T circuit, S.A circuit, decoder circuit v t o thm cc m ch c n thi t khc cho thi t k .  Xy d ng s c u hnh m u s t c nguyn l cho cc c u hnh m u: B c ny t o ra m t s c u hnh m u, y l cc c u hnh bin c a m t d i cho php c a thi t k . Cc c m ph ng, ki m tra v cc yu c u nh l ch c n ng, c t i u ha, nh m mb o nh th cc c u hnh , cng su t tiu th , di n tchv s

r ng n u cc c u hnh ny th a mn m t s yu c u xc t o ra t Mega Compiler ho t c u. M i c u hnh s c xy d ng m t s s

ng trong d i cho php s th a mn yu nguyn l khc nhau,

nh m ph c v cho nh ng m c tiu m ph ng v ki m tra khc. V d , s nguyn l ton c u hnh (full configuration) ch c n ng thi t k v cng su t tiu, s path) c xy d ng cho vi c ki m tra t c c trn), b c xy d ng cho vi c ki m tra thi t k nguyn l nguyn l rt g n thi t k (critical

- M ph ng m ch i n (Circuit simulation): Sau khi cc s c xy d ng ( b cc trnh m ph ng cng nghi p v i ph ng g n nh th c t ,

c ny s th c hi n m ph ng chng b ng chnh xc cao, v i cc i u ki n m

ki m tra s v n hnh t ng th c a m ch. Qu trnh m th c hi n c a thi t k . c th c hi n m ch ng v cng su t

ph ng v ki m tra bao g m cc cng o n nh sau :  M ph ng b ng cng c HSPICE: Ki m tra t c N ut c ho t ng ch a ti p t c t i u.  M ph ng b ng cng c HSIM: Ki m tra ch c n ng ho t tiu th c a m ch. Vi c ki m tra ch c n ng s tr n l n cc ch c n ng l ng vo nhau, l i v m t ch c n ng. N u pht hi n hi n m ch s a ch a. m b o thi t k th a mn c yu c u v m t di n c s a ch a m ch t c. c th c hi n b ng cch cho m b o r ng thi t k khng b c th c t yu c u, s quay l i b

thi t k th c hi n t t c cc ch c n ng c a n, v i nhi u l n lin t c, v nhi u c l i ph i l p t c quay v b

 Xy d ng phc th o hnh d ng v c u trc c a layout cho cc mega cell v tnh ton ph ng on v m ph ng tr l i, nh m tch. N u di n tch qu l n so v i yu c u, ph i quay l i b

m b o m i yu c u c a thi t k l

- Xy d ng kh i v c u hnh (Mega cell block): B c ny s d ng trnh bin d ch c ny, l nh ng c u hnh t o cc c u hnh.Cc c u hnh trnh by c t o ra ng trong b c l a ch n ty trong cc d i cho php, trn, ph

nh m m c ch ki m tra ng u nhin thi t k . Nh bin, v v y vi c ki m tra ph i c u hnh n m bn trong cc d i, v b o m thi t k t yu c u.

php thi t k theo ki u bin d ch ch cho php t i u ha trn nh ng c u hnh c th c hi n m t cch ng u nhin trn cc cc tnh ki m tra c trong su t (transparency)

2.2.4 Thi t k v t l cho cc cells

sang s m ch v t l t

c tr ng (Mask Design)
m ch lu n l c quy nh s n xu t s cc l p m u

Mask design hay layout design l m t qu trnh thi t k t s nh trn c s cc m t n (mask layers) mong mu n. t

c cc l p v t l bi u th cc c m t m ch tch h p i thi t k bu c

transistor, cc c ng logic v cc k t n i gi a chng ph i tun theo cc quy k v b i cc yu c u ng th c. c tch h p trn cng m t phi n

c i u th trong qu trnh layout, ng c ch ra trong m ph ng m ch

nh rng bu c b i qu trnh s n xu t, b i quy trnh thi t m ch c th ho t

M ch IC CMOS l m t m ch r t ph c t p bao g m nhi u transistor v i kch c c c k nh v nhi m v c a layout sao cho t l v bi u di n cc l p bn d n c ng nh cc l p kim lo i v th c hi n k t n i cc transistor c ng nh cc cell lin quan l i v i nhau trn phi n c kch th c th ho t c t i u nh t theo yu c u c a khch hng m v n ng t t nh thi t k ban m b o m ch

u. Do trong layout i h i ph i tun c ki m tra l i DRC

th nghim ng t cc lu t thi t k c ng nh cc yu c u trong thi t k . Vi c thi t k layout ph i Cc b m b o khng c l i sau khi qua cc b (design rule check), LVS (layout vesus schematic). c t ng quan c a m t qui trnh thi t k layout : Nhi m v c a b cc khu v c s kch th c ny l v ch ra k ho ch cho vi c thi t k , xem xt nh - Layout & Floorplan: t linh ki n, cc khu v c m tn hi u s ch y qua, xc

c c a cc kh i v phn ph i cc cell, s p x p cc l p, cc linh ki n

cho ph h p nh ng ph i th a mn yu c u v di n tch v v nh ng cell c b n trong thi t k (cell c b n l nh ng cell nh , c th dng l i nhi u l n trong thi t k ). B s ti t ki m c ny r t quan tr ng, n u ta c m t floorplan h p l th vi c th c c th i gian. c hi n s d dng h n v vi c ch nh s a v tr cc l p trong cell s t h n nh v y - Assemble Cell library: Sau khi th c hi n floorplan cho ton m ch v v cc cell nh , b ny s th c hi n thi t k cc kh i m ch l n h n b ng cch k t n i cc cell c b n l i v i nhau v ch y dy gi a chng theo cc k ho ch s p x p trong ph n floorplan. V i b b c floorplan t t, vi c th c hi n s d dng. Trong b c ny bao g m c vi c t o th vi n v th c hi n thi t k cho cc b n v c th . c ny th c hi n ch y cc ph n m m CALIBRE ho c HERCULES c xem xt, ki m tra v o ki m tra l i DRC, LVS cho cc cell, v i cc cell quan tr ng nh cc bitcell l cell l u tr d li u s mb o - Plot: Sau khi hon thnh b ng v m ch, ng b ng v so v i m ch lu n l ban d ng gds2 Sau khi ng a xu ng cho b u b o i thi t k s ki m tra l i thi t k m ch c n ng, c u trc m ch. i ta s th c hi n trch file nh so v i lu t thi t k c a nh s n xu t (Design Rules Check - DRC) v ki m tra Sau khi th c hi n ch y t t cc ki m tra, ng c cc i n tr , i n dung c cc yu c u thi t k .

c th c hi n ti p theo. c bi t c a chip

1.3.5Thi t k v t l (Physical Design)

i thi t k hon thnh giai o n layout nh ng m ch cs p th cc m ch t v k t n i v i nhau, ho c v i cc kh i ch c n ng nh d a vo thi t k lu n l c a chip (gatec sau: t t cc IO u vo, xc nh kch th c cc kh i v

khc trn m t vng di n tch nh t - Floorplan: chu n b d li u

level netlist). Quy trnh ny g i l Place and Route v g m cc b

chng vo cc v tr t i u cho vi c ch y dy. S p x p cc vng VDD, VSS cho cc kh i

cells, cc power pad, standard cells. L p k ho ch cho vi c cung c p ngu n

- Place & Route: b trn cng

c ny

c th c hi n vi c

t v n i dy cc cell

t ng

c g i l chip level nh cc ph n m m h tr .

th c hi n vi c k t

ny, chng ta c n c cc thng tin sau:  Cc thng tin v t l v th vi n cell: v d kch th n i, nh th i, cc tr ng i trong khi ch y dy. c t ng h p s ch ra chi ti t cc instance v m i quan h k t ng d n b h n ch trong thi t k . ng, cc  M t netlist c cell, cc i m

n i bao g m c cc

 T t c cc yu c u c a ti n trnh cho cc l p k t n i, bao g m cc lu t thi t k cho cc l p ch y dy, tr khng v i n dung, tiu th n ng l lu t v s d n i n trong m i l p. - Post Route View, Edit v plot: b ch nh s a sau khi th c hi n ch y dy xu t, c ny th c hi n xem xt, ki m tra, v m b o ton b yu c u c a nh s n i n

m b o l cc k t n i hon ch nh v th c hi n ki m tra cc gi tr nh d ng file gds2( Graphic Design System II).

tr v i n dung sau khi ch y dy. Sau khi hon t t vi c ki m tra, ta s th c hi n bin d ch sang - DRC (design rule check), LVS (layout vesus Schematic), ERC (Electrical Rules Check): sau khi bin d ch sang d ng file gds2, ta s th c hi n ki m tra DRC, LVS trn ton b chip. K t thc b trn c ki m tra, n u c l i xu t hi n ta ph i quay l i cc b n khi vi c ki m tra c th c hi n ch nh s a c m b o hon t t m khng

cn l i. Sau khi hon t t vi c bin d ch sang file gds2 m khng cn l i no n a, file c a chip ny s a xu ng nh s n xu t v th c hi n cc cng o n ch t o thnh m t chip thnh ph m.

3. Gi i thi u ph n m m m ph ng ModelSim dng trong thi t k ASIC:

3.1 Gi i thi u
ModelSim l mi tr ng m ph ng v ki m th (debug) ph n c ng c a bin d ch v m hng Mentor Graphics, l m t cng c r t thng d ng dng nay.

ph ng cng o n thi t k logic (s d ng ngn ng m t ph n c ng HDL) hi n

3.2 Ci
B

t
ti n hnh ci tb nl nl t th c hi n cc b c sau: tt i c 1:N u b n ch a c file ci t th c th down load file ci

https://www.altera.com/support/software/download/eda_software/modelsim/ms m-index.jsp B c 2: Sau khi c file ci t s xu t hi n. t b n nh p p chu t vo file ny. C a s ci

c 3: B n nh n Next

ti p sang b

c k ti p.

c 4: B n nh n Yes

ch p nh n cc yu c u v license c a Altera

B th

c 5: Ti p theo b n nh n Browse th m c m c

l a ch n

ng d n ci

t m i ho c c

nh. Sau nh n Next

c 6: Ti p t c b n nh n Next, ho c nh p tn th m c m i vo.

c 7: Trong c a s hi n th thng tin th m c ci t. Thanh process s xu t hi n

t b n ch n Next

th c t

hi n qu trnh ci ph n m m

cho bi t ti n trnh ci

c 8: Sau khi qu trnh ci

t k t thc m t b n thng bo s xu t hi n. c l i n u ch a c file ny th b n ch n No v ng d n sau

N u b n c file license.dat th ch n Yes v b qua quy trnh download file license t trang web altera. Ng sau ti n hnh download file license t altera, theo h

B B

c 9: c10:

download file license, tr

c tin b n vo trang ch

https://www.altera.com

ng k account, sau b n vo trang web sau:

https://www.altera.com/support/software/download/eda_software/modelsim/dnlmsim-61g.jsp ti n hnh download. Trong trang web ny b n ch n phin b n Windows (ModelSim-Altera Web Edition) v nh p vo link requires a license. Trang web s yu c u b n login vo h th ng, b n login vo account t o ra (n u ch a c th download. Tr ng k m i m t account) s au vo l i trang ny ng h p login thnh cng th b n s th y trang web nh sau:

trang web ny b n nh p a ch card m ng c a my mnh vo khung NIC number. ng th i l a ch n option Yes, include a free ModelSim-Altera Web Edition License v Academic: Only for academic/education/hobby purposes. Sau nh n Continue n nh.M t email t server s c g i vo email c a b n, vo mail v download file license. B c 12.Sau khi download file license b n s a tn file l i thnh license.dat v l u trong th m c C:\ModelSim. B c 13. bi t c a ch card m ng c a mnh th b n vo Start-> Run, g vo cmd v nh n enter. Trong c a s m i xu t hi n b n g l nh ipconfig /all a ch card m ng c a my s c hi n th nh hnh v :
B c 11.

ng ch n v tr c a file license. u tin b n nh p chu t ph i vo Mycomputer (trn desktop) ch n Properties. Trong c a s properties b n ch n tab advanced
B

c 14.Sau khi c file license b n ti p t c t o 2 bi n mi tr

B c 15. Ti p t c b n nh p nt vo nt Environment Variables, c a s ch a cc bi n mi tr ng s c hi n th nh hnh v

B tr

c 16. Trong c a s user variables b n ch n nt New ng m i. C a s t o m i s xu t hi n

t o m t bi n mi

B c 17:Ti p b n nh p tn bi n l LM_LICENSE_FILE v gi tr bi n l C:\ModelSim\license.dat, sau nh n OK n nh. T ng t b n t o thm m t bi n khc c tn l MGLS_LICENSE_FILE v gi tr l C:\ModelSim\license.dat. n y th vi c ci c hon t t, ch y ch ng trnh b n ch c n nh p p vo icon c a ModelSim trn desktop.

3.3 H
D

ng d n s d ng

i y s l quy trnh so n th o mt project v i ModelSim. B c 1.Nh p p vo icon c a ModelSim trn mn hnh desktop.C a s lm vi c c a ModelSim s xu t hi n nh hnh v .

c 2:

t o m i m t project b n vo File -> New -> Project (xem hnh).

B c 3.Trong c a s t o m i project b n nh p tn c a project, l a ch n n i l u tr project sau nh n OK t o m i project.

c 4.K

, m t c a s cho php t o thm cc file vo project xu t hi n

c 5.B n ch n Create New File, h p tho i t o m i m t file s xu t hi n

B c 6.Ti p theo b n nh p tn file, ch n Browse ch n n i l u tr file ny v ch n ki u file s t o ra (ch n Verilog, nh trn hnh v ). Sau khi t o xong b n ch n close ng c a s thm file vo project. B c 7.Nh p p vo file m i t o ti n hnh so n th o.

B c 8.Hnh v trn ch a code verilog hi n th c m t c ng AND 2 ng bin nh p.Sau khi g xong code verilog b n nh p vo nt trn thanh cng c d ch ch ng trnh.C a s l nh s cho bi t ch ng trnh bin d ch c thnh cng hay khng (xem hnh). B c 9.Ti p theo ki m th ta ph i hi n th c thm file testbench. File TestBench ny s s d ng ch ng trnh chnh (c ng AND) nh l m t linh ki n th vi n, v nhi m v chnh c a file testbench l lm sao t o ra y cc kh n ng c th ki m tra tnh ng n c a linh ki n test. Cc b c ti p theo y s l quy trnh t o ra file testbench. B c 10.T o m i m t file b n vo File->New->Source->Verilog t o m i file verilog (xem hnh).

B c 11.C a s c a file m i t o s xu t hi n, b n nh n Ctrl + S. Khi c a s Save As xu t hi n b n nh p tn file vo sau nh n Save l u tr file B c 12.K ti p b n thm file m i t o ny vo project c a mnh b ng cch ch n File->Add to Project->Existing File.

B c 13.Trong c a s thm file vo project, b n ch n Browse tm v tr c a file c n thm vo. Trong khung c a s ki u file (add file as type) b n ch n lo i file c n thm vo (verilog), nh n OK n nh. B c 14.Ti p theo b n nh p p vo file v a m i thm vo bn c a s project, v nh p hi n th c code cho file ny.

B c 15.Bin d ch file testbench sau nh p vo tab Library. Ton b file trong project s c bin d ch vo th vi n word. B n m th vi n ny s th y cc file v a m i t o (xem hnh).

B c 16.Nh p chu t ph i vo file Testbench v ch n Simulate trnh simulate (m ph ng) file testbench.

th c hi n qu

B c 17.C a s Object s xu t hi n, trong c a s ny b n gi phm Ctrl v nh p chu t tri ch n nh ng tn hi u s c v trn gi n th i gian.

B c 18.Ti p theo trong c a s l nh b n g l n run 199 (nh h n th i gian simulate 1 n v ch ng trnh v n ch a d ng l i).

c 19. C a s v gi n

th i gian s xu t hi n

B c 20. Simulate.

k t thc qu trnh simulate b n c th vo Simulate -> End