EXPERIMENT NO 1

AIM:- To design and verify the operation of a 2X4 DECODER (using when else) circuit.

SOFTWARE USED: ModelSIM

THEORY:-

A binary code of n bits is capable of representing upto 2ⁿ distinct elements of coded information .
A Decoder is a combinational circuit that converts binary information from n input
lines to a maximum of 2ⁿ unique output lines.If the n-bit decoded information has unused or don’t-
care combinations,the decoder output will have fewer than 2ⁿ outputs.

TRUTH TABLE:-

Truth table of a 2-to-4 line Decoder

A B E O/P
0 0 1 Z0
0 1 1 Z1
1 0 1 Z2
1 1 1 Z3

VHDL CODE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are

-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity decoder is
Port ( a : in std_logic_vector(0 to 1) ;
o : out std_logic_vector(3 downto 0));
end decoder;

architecture Behavioral of decoder is

begin
o<= "0001" when a="00" else
"0010" when a="01" else
"0100" when a="10" else
"1000" when a="11";

end Behavioral;

BLOCK DIAGRAM:
WAVEFORM
 EXPERIMENT NO 2

AIM:- To design and verify the operation of a 2X4 DECODER (using select) circuit.

SOFTWARE USED: ModelSIM

THEORY:-

A binary code of n bits is capable of representing upto 2ⁿ distinct elements of coded information .
A Decoder is a combinational circuit that converts binary information from n input
lines to a maximum of 2ⁿ unique output lines.If the n-bit decoded information has unused or don’t-
care combinations,the decoder output will have fewer than 2ⁿ outputs.

TRUTH TABLE:-

Truth table of a 2-to-4 line Decoder

A B E O/P
0 0 1 Z0
0 1 1 Z1
1 0 1 Z2
1 1 1 Z3

VHDL CODE

entity dec_s is
Port ( z : out std_logic_vector(3 downto 0));
end dec_s;

architecture Behavioral of dec_s is

signal s:std_logic_vector(1 downto 0);
begin
with s select
z<="0001" when "00",
"0010" when "01",
"0100" when "10",
"1000" when "11",
"1111" when others;

end Behavioral;

BLOCK DIAGRAM
WAVEFORM
 EXPERIMENT NO 3

AIM: To design and verify the operation of FULL ADDER circuit using half adder with behavioral
model

SOFTWARE USED: ModelSIM

THEORY:-

A full adder is a combinational circuit that forms the arithmetic sum of three input bits.It consist of
three inputs and two outputs.Two of the input variables ,denoted by x and y, represent the two
significant bits to be added.The third input, z ,represent
The carry from the previous lower significant position.The two outputs are designated
by the symbols S for sum and C for carry.

S = x`y`z + x`yz`+ xy`z`+xyz

C= xy + yz + yz

TRUTH TABLE:-

x y z C S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

VHDL CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are

-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity habe is
Port ( a : in std_logic;
b : in std_logic;
cin : in std_logic;
s : out std_logic;
cout : out std_logic);
end habe;

architecture Behavioral of habe is

signal s1,c1,c2: std_logic;
begin
ha1:process (a,b)
begin
s1<=a xor b;
c1<=a and b;
end process ha1;

ha2:process (s1,c1)
begin
s<=s1 xor c1;
c2<=c1 and s1;
end process ha2;

or1:process (c2,c1)
begin
cout<=c2 or c1;
end process or1;

end Behavioral;

BLOCK DIAGRAM
WAVEFORM
 EXPERIMENT NO 4

Aim:- To design and verify the operation of MUX using when –else statement.

SOFTWARE USED: ModelSIM

THEORY:- The multiplexer drawn here is based on NAND gates. The circuit has 3 kinds of
inputs, the STROBE, the Select lines A and B and the Data inputs I1, I2, I3, I4. The circuit is
capable of transferring the input from any one of the input lines to the single output line. Which of
the inputs is selected depends on the status of the select inputs. The importance of the strobe
input, also known as the enable input is that without the strobe being 0, the circuit will not select
any of the inputs and its output will be 0. The working of the circuit is explained by the truth table
given below.

TRUTH TABLE:-

Select inputs Strobe Output

A B
0 0
0 1
1 0
1 1
X X
Z I1/I2/I3/I4/0
0 I1
0 I2
0 I3
0 I4
1 0

VHDL CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are

-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity mux is
Port ( a : in std_logic_vector(3 downto 0);
s : in std_logic_vector(1 downto 0);
z : out std_logic);
end mux;

architecture Behavioral of mux is

begin
z <= a(0) when s ="00" else
a(1) when s ="01" else
a(2) when s ="10" else
a(3) when s ="11";

end Behavioral;
BLOCK DIAGRAM

WAVEFORM
 EXPERIMENT NO 5

Aim:- To design and verify the operation of PRIORITY ENCODER using don’t care condition.

SOFTWARE USED: ModelSIM

THEORY:- An encoder is a digital function that produces a reverse operation from that of a
decoder. An encoder has 2ⁿ( or less) input lines and ª output lines. The output lines generate the
binary code for 2ⁿ input variables.
If more then two inputs are active simultaneously, the output is unpredictable or rather it is not
what we expect it to be.This ambiguity is resolved if priority is established so that only one input is
encoded, no matter how many inputs are active at given point of time. Priority encoder is the one
which includes the priority function. The operation of the priority encoder is such that if two or
more inputs are active at the same time, the input having the highest priority will take the
precedence.These encoders establish an input priority to ensure that only the highest priority line
is encoded.

TRUTH TABLE:-

D3 D2 D1 D0 Y2 Y1 Y0
0 0 0 0 0 0 0
0 0 0 1 0 0 1
0 0 1 X 0 1 0
0 1 X X 0 1 1
1 X X X 1 0 0

VHDL CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are

-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity proenc is
Port ( a : in std_logic_vector(3 downto 0);
y : out std_logic_vector(1 downto 0);
valid : out std_logic);
end proenc;

architecture Behavioral of proenc is

begin
y <= "00" when a="0001" else
"10" when a="001-" else
"01" when a="01--" else
"11" when a="1---" else
"00" ;
valid <= '1' when a(0) ='1' or a(1) ='1' or a(2) ='1' or a(3) ='1' else '0';
end Behavioral;
BLOCK DIAGRAM:-

WAVEFORM
 EXPERIMENT NO 6

AIM: To design and veriy the operation of 9 bit parity( odd/even) generator.

SOFTWARE USED: ModelSIM

THEORY: When binary data is transmitted from one place to another noise or other disturbances
can cause an error in the digital signal. BCD (5) 0101 encounters noise during LSB and
becomes (4) 0100.If parity checking is used this error would be detected at the receiver,
and an error condition signaled. RX could request RE-Transmit of data. Parity systems are either
ODD or EVEN parity. They require an extra bit of information. If 4 bit data, then 5 bits are
required. If seven bit as in ASCII, the 8th bit is for parity. Parity (ODD or EVEN) reflects the data
number sent.If even parity is used, 10100 would generate a 1 in the 5 th bit. If 00101 parity bit is
0. The sum of all bits must be even. The parity bit is inserted to make the total even. Could be
MSB or LSB.
A Parity generator creates the parity bit on the transmission side. On Receiving end a parity
checker determines is the 5th bit reflects the correct parity.

TRUTH TABLE:

Number of Outputs
HIGH Inputs I0–
∑Even ∑Odd
I8
0, 2, 4, 6, 8 H L
1, 3, 5, 7, 9 L H

VHDL CODE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are

-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity pg is
Port ( d : in std_logic_vector(8 downto 0);
odd : out std_logic;
even : inout std_logic);
end pg;

architecture Behavioral of pg is
Component XOR
port(x,y:in std_logic;z:out std_logic);
end component;
 component NOT
port(a:in std_logic;b:out std_logic);
end component;

signal f: std_logic_vector(3 downto 0);

g:std_logic_vector(1 downto 0);
h:std_logic;
begin
X1 <= XOR port map (d(0),d(1),f(0));
X2 <= XOR port map (d(2),d(3),f(1));
X3 <= XOR port map (d(4),d(5),f(2));
X4 <= XOR port map (d(6),d(7),f(3));
X5 <= XOR port map (f(0),f(1),g(0));
X6 <= XOR port map (f(2),f(3),g(1));
X7 <= XOR port map (g(0),g(1),h);
X8 <= XOR port map (h,d(8),e);
X9 <= NOT port map (e,o);
end Behavioral;

BLOCK DIAGRAM
WAVEFORM:-
 EXPERIMENT NO 7

AIM: To design and verify the operation of FULL ADDER circuit using 2 half adder with dataflow
model

SOFTWARE USED: ModelSIM

THEORY:-

A full adder is a combinational circuit that forms the arithmetic sum of three input bits.It consist of
three inputs and two outputs.Two of the input variables ,denoted by x and y, represent the two
significant bits to be added.The third input, z ,represent the carry from the previous lower
significant position.The two outputs are designated by the symbols S for sum and C for carry.

S = x`y`z + x`yz`+ xy`z`+xyz

C= xy + yz + yz

TRUTH TABLE:-

x y z C S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

VHDL CODE:-

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are

-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity full_adder is
port(
a,b,c: in std_logic;
s,cout:out std_logic
);
end full_adder;

architecture full_adder_arch of full_adder is

begin
s<=(a xor b) xor c;
cout<=((a and b) or (b and c) or (a and c));
end full_adder_arch;

BLOCK DIAGRAM:-
WAVEFORM:-
 EXPERIMENT NO 8

AIM: To design and verify the operation of RS flip flop USING behavioral model.

SOFTWARE USED: ModelSIM

THEORY: The clocked SR flip-flop shown in Figure consists of a basic NOR flip-flop and two
AND gates. The outputs of the two AND gates remain at 0 as long as the clock pulse (or CP) is 0,
regardless of the S and R input values. When the clock pulse goes to 1, information from the S
and R inputs passes through to the basic flip-flop. With both S=1 and R=1, the occurrence of a
clock pulse causes both outputs to momentarily go to 0. When the pulse is removed, the state of
the flip-flop is indeterminate, ie., either state may result, depending on whether the set or reset
input of the flip-flop remains a 1 longer than the transition to 0 at the end of the pulse.

TRUTH TABLE:

VHDL CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are

-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity dk473 is
Port ( j : in std_logic;
clk : in std_logic;
k : in std_logic;
pr : in std_logic;
clr : in std_logic;
Q : inout std_logic);
end dk473;

architecture Behavioral of dk473 is

begin
process(clk,pr,clr)
begin
if(pr='0') then
Q <= '1';
else if(clr='0') then
Q <= '0';
 else if(clk 'event and clk='1') then
if(j='0' and k='0') then
Q <= Q;
else if(j='0' and k='1') then
Q <='0';
else if(j='1' and k='0') then
Q <= '1';
else if(j='1' and k='1') then
Q <= not(Q);
end if;
end if;
end if;
end if;

end if;
end if;
end if;
end process;

end Behavioral;

BLOCK DIAGRAM:-
WAVEFORM:-
 EXPERIMENT NO 9

AIM: To design and verify the operation JK flip flop using behavioral model.

SOFTWARE USED: ModelSIM

THEORY: A JK flip-flop is a refinement of the SR flip-flop in that the indeterminate state of the R
type is defined in the JK type. Inputs J and K behave like inputs S and R to set and clear the flip-
flop (note that in a JK flip-flop, the letter J is for set and the letter K is for clear). When logic 1
inputs are applied to both J and K simultaneously, the flip-flop switches to its complement state,
ie., if Q=1, it switches to Q=0 and vice versa.
A clocked JK flip-flop is shown in Figure 6. Output Q is ANDed with K and CP inputs so that the
flip-flop is cleared during a clock pulse only if Q was previously 1. Similarly, ouput Q' is ANDed
with J and CP inputs so that the flip-flop is set with a clock pulse only if Q' was previously 1.

TRUTH TABLE:

VHDL CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are

-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity dk473 is
Port ( j : in std_logic;
clk : in std_logic;
k : in std_logic;
pr : in std_logic;
clr : in std_logic;
Q : inout std_logic);
end dk473;

architecture Behavioral of dk473 is

begin
process(clk,pr,clr)
begin
if(pr='0') then
Q <= '1';
else if(clr='0') then
Q <= '0';
else if(clk 'event and clk='1') then
if(j='0' and k='0') then
Q <= Q;
else if(j='0' and k='1') then
Q <='0';
else if(j='1' and k='0') then
Q <= '1';
else if(j='1' and k='1') then
Q <= not(Q);
end if;
end if;
end if;
end if;

end if;
end if;
end if;
end process;

end Behavioral;

BLOCk DIAGRAM

WAVEFORM
 EXPERIMENT NO 10

AIM: To design and verify the operation D flip flop using behavioral model.

SOFTWARE USED: ModelSIM

THEORY:-The D FLIP FLOP is constructed using Nand gates.The circuit hence

obtained samples the input and changes its output only at the negative edge of the
controlling clock.To eliminate undesirable condition of the indeterminate state in S-R FF
we use D FF.D FLIP FLOP has two inputs-D(data) and control input(E).D input goes
directly to S input and its invert is applied to the R input.
If D=0 output goes to 0 placing the circuit in reset state else if D=1 then its in
set state.E should always be equal to one.

TRUTH TABLE:-

E D Next state of Q
0 X No change
1 0 Q=0,reset state
1 1 Q=1,set state

VHDL CODE:-

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are

-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity D_FF is
Port ( D : in std_logic;
CLK : in std_logic;
Q : out std_logic);
end D_FF;

architecture Behavioral of D_FF is

begin
p0:process is
begin
wait until (clk='1');
q<=d;
end process p0;

end Behavioral;

BLOCK DIAGRAM:-

WAVEFORM:-
 EXPERIMENT NO 11

AIM: To design and verify the operation of HALF ADDER circuit using dataflow model.

SOFTWARE USED: ModelSIM

THEORY:- Half Adder is an arithmetic circuit which performs addition operation of two
bits and provides their sum and carry generated by the addition of those
two bits.The input variables designate the augend and addend bits;the
output variables produce the sum and carry.We arbitrarily assign symbols
x and y to the inputs and S (for sum) and C (for carry) to the outputs.

S = x`y + xy`
C = xy

TRUTH TABLE:

A(n) B(n) Sum(n) Carry

0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

VHDL CODE:-

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are

-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity abcd is
Port ( a : in std_logic;
b : in std_logic;
c : out std_logic;
d : out std_logic);
end abcd;
architecture Behavioral of abcd is

begin
c<= a xor b ;
d<= a and b ;

end Behavioral;

BLOCK DIAGRAM:-
WAVEFORM:-
 EXPERIMENT NO 12

AIM:- To design and verify the operation of DECADE COUNTER.

SOFTWARE USED: ModelSIM

THEORY:- A decade counter requires resetting to 0 when the count reaches decimal 10. In the
case of the ripple counter this corresponds to triggering a CLEAR signal to all 4 flip-flops when
the state 1010bin is reached.
It is therefore necessary to take action when all of the following are true

* Qa = 0
* Qb = 1
* Qc = 0
* Qd = 1

In principle this would require the logical AND of the outputs Qb and Qd and the complements of
Qa and Qc. In practise however, from the mod-16 counter truth table it can be seen that decimal
10 corresponds to the first time that Qb and Qd are 1 and so the logic is simplified.

TRUTH TABLE:-

Reset Clock Enable Load Mode Count

0 - - - - 0
1 ^ 1 - - Count
1 ^ 0 0 - Data
1 ^ 0 1 0 Count + 1 (binary)
1 ^ 0 1 1 Count + 1 (decade)

VHDL CODE

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity COUNTER is
port (Clock : in Std_logic;
Reset : in Std_logic;
Enable: in Std_logic;
Load : in Std_logic;
Mode : in Std_logic;
Data : in Std_logic_vector(7 downto 0);
Count : out Std_logic_vector(7 downto 0));
end;

architecture Model_Solution of Counter is

constant nibble_max : std_logic_vector(3 downto 0) := "1111";
constant decade_max : std_logic_vector(3 downto 0) := "1001";
constant zero_nibble : std_logic_vector(3 downto 0) := "0000";
constant zero_byte : std_logic_vector(7 downto 0) := "00000000";
signal Q : Std_logic_vector(7 downto 0);
begin
process (Clock, Reset)
begin
if Reset = '0' then
 Q <= zero_byte;
elsif Clock'event and Clock = '1' then
if Enable = '0' then
if Load = '0' then
Q <= Data;
elsif (Mode = '0' and Q(3 downto 0) /= nibble_max) or
(Mode = '1' and Q(3 downto 0) /= decade_max) then
Q(3 downto 0) <= Q(3 downto 0) + '1';
else
Q(3 downto 0) <= zero_nibble;
if (Mode = '0' and Q(7 downto 4) /= nibble_max) or
(Mode = '1' and Q(7 downto 4) /= decade_max) then
Q(7 downto 4) <= Q(7 downto 4) + '1';
else
Q(7 downto 4) <= zero_nibble;
end if;
end if;
end if;
end if;
end process;

Count <= Q;

end;