Laptop Schematic Diagram (Intel Montevina Mobile Platform)

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PILLAR ROCK Montevina Mobile Platform Fab 3
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CUSTOMER REFERENCE BOARD Rev. 1.0
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Table of Contents
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Page Description
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1 TITLE PAGE Merom
D 2 NOTES D
3 Penryn (1 of 2)
4 Penryn (2 of 2)
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5 CPU Thermal Sensor
6 CANTIGA (1 OF 6)
7 CANTIGA (2 OF 6)
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8 CANTIGA (3 OF 6)
9 CANTIGA (4 OF 6)
10 CANTIGA (5 OF 6)
11 CANTIGA (6 OF 6)
12 CANTIGA STRAP & CAMARILLO
13 DDR2 SODIMM 0
14 DDR2 SODIMM 1
15 DDR2 TERMINATION
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16 CRT
17 LVDS
18 TVO
19 PCIE GRAPHICS
20 XDP
21 ICH9M (1 of 4)
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22 ICH9M (2 of 4)
23 ICH9M (3 of 4)
24 ICH9M (4 of 4)
25 PCI-E Slots (1 & 2)
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C 26 PCI-E Slots (3,4 & 5) C
27 High Definition Audio
28 HDA Power Supply
29 USB 1.1/2.0
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30 SATA (1 of 3)
31 SATA (2 and 3 of 3)
32 PCI Edge Connector(Gold finger)
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33 LAN Boaz
34 LAN Docking and SPI
35 CK505
36 DB800 & Buffers
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37 FWH and I/O Port Expander
38 SIO
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39 Legacy Support
40 H8 2116 KBC(1 of 2)
41 H8 2116 KBC(2 of 2)
42 PS2
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43 LPC Slot, TPM Header,
44 DOCKING
45 TPS51120 SYSTEM POWER VR
46 DDR2 VR
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47 CANTIGA VR
48 DDR VREF
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49 GRAPHICS CORE VR
50 SYSTEM CHARGER VR
B 51 SYSTEM CHARGER BATTERY B
52 IMVP-6 CONTROLLER
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53 IMVP-6 DRIVERS&FETS
54 CPU Decoupling
55 DISCHARGE CIRCUITS
56 Start Up Sequence
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57 Sleep control
58 POWER SEQUENCING
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A
Pillar Rock Intel Confidential A
Title
TITLE PAGE
Size Document Number Rev

A 355659
1.0
Date: Tuesday, August 28, 2007 Sheet 1 of 58
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MONTEVINA CUSTOMER REFERENCE PLATFORM
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SCHEMATIC ANNOTATIONS AND BOARD INFORMATION
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D D
Jumper / Switch Settings Changes for Pillar Rock with PM GMCH SKU
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2
Voltage Rails I C / SMB Addresses
POWER PLANE VOLTAGE ACTIVE IN DESCRIPTION Device Address Hex Bus Jumper Default Description Page SL No NO_STUFF STUFF
Clock Generator 1101 001x D2 SMB_ICH_M3
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+VBATA 6V-14.1V S0/M0, (S3-S5)/M1, (S3-S5)/M-off Battery Rail in Mobile Power Mode DB800 Clock Buffer 1101 110x DC SMB_ICH_M3 J1G1 1-2 BSEL2 35 1 U6E2, U6E3, U6E4
+VBAT 6V-14.1V S0/M0, (S3-S5)/M1, (S3-S5)/M-off Battery Rail in Mobile Power Mode SO-DIMM0 1010 000x A0 SMB_ICH_M2 J1G3 1-2 BSEL1 35
+VBATS 6V-14.1V S0/M0 Battery Rail in Mobile Power Mode SO-DIMM1 1010 010x A4 SMB_ICH_M2 J1G5 1-2 BSEL0 35 2 L5F1
+V12S 12V S0/M0 Only on in DT Power Mode SO-DIMM0 Thermal Sensor 0011 000x 30 SMB_ICH_M2 J2B2 All OPEN CPU CORE VID 52
-V12A -12V S0/M0, (S3-S5)/M1, (S3-S5)/M-off Only on in DT Power Mode SO-DIMM1 Thermal Sensor 0011 010x 34 SMB_ICH_M2 J2G1 1-X Force Shutdown 56 3 R5E5, R5F9, R5T16, R5E4, R5T5, R5T8,
-V12S -12V S0/M0 Only on in DT Power Mode DDR Thermal Sensor 0100 110x 4C SMB_ICH_M2 J2H2 All OPEN GFX CORE VID 49 R5U3, R5U11, R5U14, R5T9, R5T10,
+V5A 5V S0/M0, (S3-S5)/M1, (S3-S5)/M-off I2C Bus Expander 0011 xxxx 3x SMB_ICH J3C1 1-2, 3-4 CPU thermal sensor 5 R5U21, R6V1 R5T12, R5T17
+V5 5V S0/M0, S3/M1, S3/M-off Ambient Lighr Sensor 0111 001x 72 ALS J3J2 1-X Power ON Latch 56
+V5S 5V S0/M0 EMA Display 0011 110x 3C EMA J4H1 1-X No ME G3 to M1 support 56 4 C5E8, C5E9, C5E11, C5E8,C5E9,C5T13,C5U3
+V3.3A 3.3V S0/M0, (S3-S5)/M1, (S3-S5)/M-off CPU Thermal Sensor 1001 100x 98 SMB_THRM J4J2 1-2 SATA Power Enable 31 C5E12, C5E13, C5E14, with 0 Ohm 0402 size res
+V3.3M 3.3V S0/M0, (S3-S5)/M1, S3/(M-off w/WOL_EN) LAN IMVP6 Amb. Temp. Sensor 1001 101x 9A SMB_THRM J5G1 1-X SRTC RST 21 C5E15, C5T12, C5T13, IPN A93549-001
a
+V3.3M_CK505 3.3V S0/M0, (S3-S5)/M1 Clock, MCH Battery A 0001 110x 1C SMB_BS J5H2 1-X CMOS Clear 21 C5U1, C5U2, C5U3
+V3.3 3.3V S0/M0, S3/M1, S3/M-off Battery B 0001 111x 1E SMB_BS J7A1 1-2 In-circuit SMC Programming 39
+V3.3S 3.3V S0/M0 Board ID Port Expander 0011 000x 30 SMB_BS J7E1 1-2 SIO Reset 38 5 FB5F1, FB5F2, FB5T1
+V1.8 1.8V S0/M0, (S3-S5)/M1, S3/M-off DDR core Docking Port Expander 0011 001x 32 SMB_BS J7H1 1-2 SATA interlock switch for port0 30
+V1.5S 1.5V S0/M0 Skin Temperature Sensor 1001 100x 98 SMB_BS J7H2 1-X TPM PHYSICAL PRESENCE 23 6 J2G1(3 4), J2G1(5 6), J2G1(1 2), J2G1(13 14)
+V1.05M 1.05V S0/M0, (S3-S5)/M1 H8 TBD TBD SMB_ME J8B1 1-2 PM Lan enable 40 J2G1(7 8)
+V1.05S 1.05V S0/M0 GMCH, ICH core, and FSB rail PCI-Slot3 TBD TBD SMB_ICH_A1 J8B2 1-2 In-circuit SMC Programming 39
+V0.9 0.9V S0/M0, (S3-S5)/M1, S3/M-off DDR command & control pull up. PCI-Gold Finger TBD TBD SMB_ICH_A1 J8C1 1-X SELCETING SPI0 or SPI1 TO BE PROGRAMMED 34
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+VCC_CORE 0.35V-1.5V S0/M0 CPU core rail PCI-Express Slot1-5 TBD TBD SMB_ICH_A1 J8F2 1-X BIOS recovery 23
+VCC_GFXCORE 0.7V-1.25V S0/M0 GMCH Graphics core rail Docking TBD TBD SMB_ICH_A1 J8G1 1-X SV Setup 63
PCIe x16 Slot (PEG) TBD TBD SMB_ICH_S4 J8G3 1-X SMC MD2 40
TPM Header TBD TBD SMB_ICH_S4 J8G4 1-X CRB/SV Detect 64
ITP-XDP TBD TBD SMB_ICH_S4 J8G5 1-2 SMC MD1 40
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J8G6 1-X KBC disable 40
C J8H1 1-2 Boot BIOS Strap 31 C
J9C1 1-X PROGRAMMING SPI1 34
J9D1 1-X PROGRAMMING SPI0 34
J9F1 1-2 KSC Enable 40
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J9G2 1-2 Boot Block Programming 42
J9H1 1-X NMI 42
J9H2 1-2 SATA interlock switch for port1 31
J9H3 1-X LID Position 41 LEDs and Switches
Buses labeled SMB_ICH_xx come out of ICH, via an I2C expander.
J9H4 1-X Virtual Battery 41
The rest come out of EC.
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LED Page Reference
xTA Activity 21 CR7H1
VID0 39 CR1B1
PCI Devices VID1 39 CR1B2
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VID2 39 CR1B3
VID3 39 CR1B4
Device IDSEL # REQ/GNT # Interrupts VID4 39 CR1B5
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Slot 3 AD18 2 2 D, C, A, B VID5 39 CR1B6
VID6 39 CR1B7
LAN (AD24 internal) Num Lock 40 CR9G1
Scroll Lock 40 CR9G3
Caps Lock 40 CR9G2
S3 57 CR5H6
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M0/M1 57 CR5H3
Net Naming Conventions S4 57 CR5H7
S5 57 CR5H5
S0 57 CR5H4
Suffix System Power Good 57 CR7H3
to
# = Active Low Signal LT Status 64 CR8G1
Prefix
H = Host
M = DDR Memory
TP = Test Point (does not connect anywhere else)
B B
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Switch Default Description Page
Power States SW9H1 1 - 2 Virtual Docking 41
SW9H3 1 - 2 Virtual Battery 41
SW9H2 1 - 2 LID Switch 41
SLP_S3# S4_STATE# SLP_S4# SLP_S5# SLP_M# +V*A +V3.3M_WOL +V1.05M +V3.3M +V1.8/+V0.9 +V5/+V3.3 +V*S Clocks SW7J1 1 - 2 Hybrid GFX switch 41
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S0 (Full on)/M0 HIGH HIGH HIGH HIGH HIGH ON ON ON ON ON ON ON ON
SW1C1 Power Button 56
S3 (Suspend to RAM)/M1 LOW HIGH HIGH HIGH HIGH ON ON ON ON ON ON OFF only MCH BCLK SW1C2 Reset Button 56
SW8E1 Net Detect 56
S3 (Suspend to RAM)/Moff LOW HIGH HIGH HIGH LOW ON OFF OFF OFF ON ON OFF OFF
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S3 (Suspend to RAM)/Moff w/WOL_EN LOW HIGH HIGH HIGH LOW ON ON OFF OFF ON ON OFF OFF
S4 (Suspend to Disk)/M1 LOW LOW HIGH HIGH HIGH ON ON ON ON ON OFF OFF only MCH BCLK
S5 (Soft Off)/M1 LOW LOW HIGH LOW HIGH ON ON ON ON ON OFF OFF only MCH BCLK PCB Footprints
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S4 (Suspend to Disk)/Moff LOW LOW LOW HIGH LOW ON OFF OFF OFF OFF OFF OFF OFF
S5 (Soft Off)/Moff LOW LOW LOW LOW LOW ON OFF OFF OFF OFF OFF OFF OFF SOT-23 SOT23-5
1 1 5
3 As seen from top 2
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Wake Events 2 3 4
Wake Events State Supported

RI# from serial port S3
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A PME# from PCI, mini PCI slot/device, LPC slot/device S3 A
PCI Express, mini PCI Express, Express-card wake event
Wake on LAN
S3
S3/M1
Pillar Rock Intel Confidential
LID switch attached to SMC S3
USB S3 Title
HDA wake on ring
SmLink for AOLII
S3
S3 NOTES
Hot Key from Scan matrix keyboard S3
PS/2 Keyboard/mouse S3
PWRBTN#
Netdetect
S3
S3, S4, S5 / M1
A 355659 1.0
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4,20,35,39,43,52,54 +V1.05S_CPU
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6 H_A#[35:3]
U2E1A
H_A#3 J4 H1 R2H2
A[3]# ADS# H_ADS# 6
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ADDR GROUP_0
H_A#4 L5 E2 56 Connect H_IERR# with no
A[4]# BNR# H_BNR# 6 stub to the connector
H_A#5 L4 G5
A[5]# BPRI# H_BPRI# 6 J2H1 and then connect
H_A#6 K5
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H_A#7 A[6]# to the 56 ohm pull up
M3 H5 H_DEFER# 6
D H_A#8 N2
A[7]# DEFER#
F21 Resistor R2H2. D
A[8]# DRDY# H_DRDY# 6
H_A#9 J1 E1
A[9]# DBSY# H_DBSY# 6
H_A#10 N3
H_A#11 A[10]#
P5 F1
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A[11]# BR0# H_BREQ# 6
H_A#12 P2 R2H3
A[12]#
CONTROL
H_A#13 L2 D20 H_IERR#_R
A[13]# IERR# H_IERR#
H_A#14 P4 B3
A[14]# INIT# H_INIT# 21
H_A#15 P1 56
H_A#16 A[15]# Place testpoint on
R1 H4
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A[16]# LOCK# H_LOCK# 6 H_IERR# with a GND
6 H_ADSTB#0 M1 ADSTB[0]# H_CPURST# 6,20
C1 0.1" away
6 H_REQ#[4:0] RESET# H_RS#[2:0] 6
H_REQ#0 K3 F3 H_RS#0
H_REQ#1 REQ[0]# RS[0]# H_RS#1
H2 REQ[1]# RS[1]# F4
H_REQ#2 K2 G3 H_RS#2
H_REQ#3 REQ[2]# RS[2]#
J3 REQ[3]# TRDY# G2 H_TRDY# 6
H_REQ#4 L1 REQ[4]# NO_STUFF
6 H_A#[35:3] HIT# G6 H_HIT# 6
H_A#17 Y2 E4 TP1F1
A[17]# HITM# H_HITM# 6
H_A#18 U5
H_A#19 A[18]#
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R3 A[19]# BPM[0]# AD4 XDP_BPM#0 20
ADDR GROUP_1
H_A#20 W6 AD3
A[20]# BPM[1]# XDP_BPM#1 35
H_A#21 U4 AD1
A[21]# BPM[2]# XDP_BPM#2 35
H_A#22 Y5 AC4
A[22]# BPM[3]# XDP_BPM#3 35
XDP/ITP SIGNALS
H_A#23 U1 AC2
A[23]# PRDY# XDP_BPM#4 20
H_A#24 R4 AC1
A[24]# PREQ# XDP_BPM#5 20
H_A#25 T5 AC5
A[25]# TCK XDP_TCK 20
H_A#26 T3 AA6
A[26]# TDI XDP_TDI 20
H_A#27 W2 AB3 4,20,35,39,43,52,54 +V1.05S_CPU
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A[27]# TDO XDP_TDO 20
H_A#28 W5 AB5
A[28]# TMS XDP_TMS 20
H_A#29 Y4 AB6
Layout note: A[29]# TRST# XDP_TRST# 20
H_A#30 U2 C20
A[30]# DBR# XDP_DBRESET# 20
no stub on H_STPCLK TP. H_A#31 V4 R1R4 TP1D1 Place TP1D1 close
H_STPCLK# to be routed in daisy A[31]# to CPU. 6 H_D#[63:0] H_D#[63:0] 6
H_A#32 W3 68 U2E1B
chain fashion from ICH to LPC slot H_A#33 A[32]# 5% H_D#0 H_D#32
THERMAL
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AA4 A[33]# NO_STUFF E22 D[0]# D[32]# Y22
and then to CPU. H_A#34 AB2 H_D#1 F24 AB24 H_D#33
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C H_A#35 AA3
A[34]#
D21 H_PROCHOT#_D R1D1 H_D#2 E26
D[1]# D[33]#
V24 H_D#34 C
A[35]# PROCHOT# H_PROCHOT# 52 D[2]# D[34]#
DATA GRP 0
V1 A24 0 H_D#3 G22 V26 H_D#35
DATA GRP 2
6 H_ADSTB#1 ADSTB[1]# THERMDA H_THERMDA 5 D[3]# D[35]#
B25 H_D#4 F23 V23 H_D#36
THERMDC H_THERMDC 5 D[4]# D[36]#
A6 . H_D#5 G25 T22 H_D#37
H_STPCLK#_R 21 H_A20M# A20M# H_PROCHOT#_D D[5]# D[37]#
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ICH
A5 C7 H_D#6 E25 U25 H_D#38

21 H_FERR# FERR# THERMTRIP# PM_THRMTRIP# 7,21 PM_THRMTRIP# should connect D[6]# D[38]#
NO_STUFF TP2F1 C4 H_D#7 E23 U23 H_D#39
21 H_IGNNE# IGNNE# to ICH9 and GMCH without D[7]# D[39]#
H_D#8 K24 Y25 H_D#40
R2U11 T-ing (No stub) H_D#9 D[8]# D[40]# H_D#41
D5 STPCLK# G24 D[9]# D[41]# W22
0 C6 H CLK H_D#10 J24 Y23 H_D#42
21,43 H_STPCLK# 21 H_INTR LINT0 D[10]# D[42]#
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B4 A22 H_D#11 J23 W24 H_D#43
21,43 H_NMI LINT1 BCLK[0] CLK_CPU_BCLK 35 D[11]# D[43]#
A3 A21 H_D#12 H22 W25 H_D#44
21,43 H_SMI#. SMI# BCLK[1] CLK_CPU_BCLK# 35 D[12]# D[44]#
H_D#13 F26 AA23 H_D#45
TP_CPU_RSVD01 H_D#14 D[13]# D[45]# H_D#46
M4 RSVD[01] K22 D[14]# D[46]# AA24
Layout Note: TP_CPU_RSVD02 N5 H_D#15 H23 AB25 H_D#47
RSVD[02] D[15]# D[47]#
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TP2F1 should be placed TP_CPU_RSVD03 T2 J26 Y26
close to J1G7 RSVD[03] 6 H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 6
TP_CPU_RSVD04 V3 H26 AA26
RSVD[04] 6 H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 6
RESERVED
TP_CPU_RSVD05 B2 H25 U22

RSVD[05] 6 H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 6
CPU_RSVD06 D2 RSVD[06] 6 H_D#[63:0] H_D#[63:0] 6
TP_CPU_RSVD07 D22
TP_CPU_RSVD08 D3 RSVD[07] 4,20,35,39,43,52,54 +V1.05S_CPU H_D#16 H_D#48
RSVD[08] N22 D[16]# D[48]# AE24
F6 H_D#17 K25 AD24 H_D#49
CPU_RSVD09 RSVD[09] D[17]# D[49]#
H_D#18 P26 AA21 H_D#50
H_D#19 D[18]# D[50]# H_D#51
R23 D[19]# D[51]# AB22
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R1R16 H_D#20 L23 AB21 H_D#52
1K D[20]# D[52]#
DATA GRP 1
H_D#21 M24 AC26 H_D#53
DATA GRP 3
1% D[21]# D[53]#
Penryn_Ball-out_Rev_1p0 . H_D#22 L22 AD20 H_D#54
H_D#23 D[22]# D[54]# H_D#55
M23 D[23]# D[55]# AE22
H_D#24 P25 AF23 H_D#56
H_GTLREF D[24]# D[56]# Layout note:
H_D#25 P23 AC25 H_D#57
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H_D#26 D[25]# D[57]# H_D#58 Comp0,2 connect with Zo=27.4ohm, make
P22 D[26]# D[58]# AE21
Layout note: Zo=55 ohm, R1R17 H_D#27 T24 AD21 H_D#59 trace length shorter than 0.5".
0.5" max for GTLREF. 2K H_D#28 D[27]# D[59]# H_D#60 Comp1,3 connect with Zo=55ohm, make
t
1%
R24 D[28]# D[60]# AC22
H_D#29 L25 AD23 H_D#61 trace length shorter than 0.5".
. D[29]# D[61]#
H_D#30 T25 AF22 H_D#62
H_D#31 D[30]# D[62]# H_D#63
N25 D[31]# D[63]# AC23
B L26 AE25 B
6 H_DSTBN#1 DSTBN[1]# DSTBN[3]# H_DSTBN#3 6
6 H_DSTBP#1 M26 DSTBP[1]# DSTBP[3]# AF24 H_DSTBP#3 6
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6 H_DINV#1 N24 DINV[1]# DINV[3]# AC20 H_DINV#3 6
AD26 R26 COMP0 R2R3 27.4 1%
4,20,35,39,43,52,54 +V1.05S_CPU GTLREF COMP[0] COMP1 R2R2 54.9 1%
CPU_TEST1 C23 TEST1 MISC COMP[1] U26
D25 AA1 COMP2 R2U1 27.4 1%
C1T1 CPU_TEST2 TEST2 COMP[2]
C24 Y1 COMP3 R2U2 54.9 1%
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CPU_TEST3 TEST3 COMP[3]
XDP_TMS R2U4 54.9 CPU_TEST4 AF26
1% TEST4
CPU_TEST5 AF1 TEST5 DPRSTP# E5 H_DPRSTP# 7,21,43
0.1uF A26 B5
CPU_TEST6 TEST6 DPSLP# H_DPSLP# 21,43
XDP_TDI R2U3 54.9 10% C3 D24
CPU_TEST7 TEST7 DPWR# H_DPWR# 6
1% NO_STUFF B22 D6
Layout Note: Place R1U6 close to 35 CPU_BSEL0 BSEL[0] PWRGOOD H_PWRGD 21,43
B23 D7 R1U15
CPU with stub length <200mils. 35 CPU_BSEL1 BSEL[1] SLP# H_CPUSLP# 6,43 1K H_PWRGD_XDP 20
XDP_BPM#5 R1U6 54.9 C21 AE6
35 CPU_BSEL2 BSEL[2] PSI# PSI# 52 5%
1% TP3E2 .
Place C1T1 close to the CPU_TEST4 pin. Penryn_Ball-out_Rev_1p0
Make sure CPU_TEST4 routing is reference
XDP_TCK R1T2 54.9 to GND and away from other noisy signals. NO_STUFF Place Series Resistor
1K
1K
1% Layout: Connect on H_PWRGD_XDP Without
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XDP_TRST# R1T3 test point TP3E2 Stub
NO_STUFF
NO_STUFF
649 with no stub
1%
R3P5
R3P6
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Size
Pillar Rock
Penryn (1 of 2)
Document Number
Custom 355659
Intel Confidential
Rev
1.0
A

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53,54,55 +VCC_CORE 53,54,55 +VCC_CORE
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U2E1C
A7 VCC[001] VCC[068] AB20
A9 AB7
.
VCC[002] VCC[069]
A10 AC7
D A12
VCC[003] VCC[070]
AC9 D
VCC[004] VCC[071]
A13 VCC[005] VCC[072] AC12
A15 VCC[006] VCC[073] AC13
A17 AC15
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VCC[007] VCC[074]
A18 VCC[008] VCC[075] AC17
A20 VCC[009] VCC[076] AC18
B7 VCC[010] VCC[077] AD7
B9 VCC[011] VCC[078] AD9
B10 AD10 U2E1D
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VCC[012] VCC[079]
B12 VCC[013] VCC[080] AD12 A4 VSS[001] VSS[082] P6
B17 VCC[016] VCC[083] AD17 A14 VSS[004] VSS[085] R2
B18 VCC[017] VCC[084] AD18 A16 VSS[005] VSS[086] R5
B20 VCC[018] VCC[085] AE9 A19 VSS[006] VSS[087] R22
C9 VCC[019] VCC[086] AE10 A23 VSS[007] VSS[088] R25
C10 VCC[020] VCC[087] AE12 AF2 VSS[008] VSS[089] T1
C12 VCC[021] VCC[088] AE13 B6 VSS[009] VSS[090] T4
a
C17 VCC[024] VCC[091] AE18 B13 VSS[012] VSS[093] U3
C18 VCC[025] VCC[092] AE20 B16 VSS[013] VSS[094] U6
D9 VCC[026] VCC[093] AF9 B19 VSS[014] VSS[095] U21
D10 AF10 R3T2 is for test purpose only. B21 U24
VCC[027] VCC[094] VSS[015] VSS[096]
D12 VCC[028] VCC[095] AF12 B24 VSS[016] VSS[097] V2
D14 VCC[029] VCC[096] AF14 C5 VSS[017] VSS[098] V5
D15 VCC[030] VCC[097] AF15 C8 VSS[018] VSS[099] V22
D17 AF17 9,10,24,47,55 +V1.05S C11 V25
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VCC[031] VCC[098] NO_STUFF VSS[019] VSS[100]
D18 VCC[032] VCC[099] AF18 C14 VSS[020] VSS[101] W1
E7 AF20 TP3E1 3,20,35,39,43,52,54 +V1.05S_CPU C16 W4
VCC[033] VCC[100] VSS[021] VSS[102]
E9 VCC[034] C19 VSS[022] VSS[103] W23
E10 VCC[035] VCCP[01] G21 CPU_G21 R3T2 R3U2 2 1 C2 VSS[023] VSS[104] W26
E12 V6 0 NO_STUFF C22 Y3
VCC[036] VCCP[02] C2U2 0 VSS[024] VSS[105]
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E13 VCC[037] VCCP[03] J6 C25 VSS[025] VSS[106] Y6
E15 K6 . 270uF R3U1 2 1 D1 Y21
C E17
VCC[038] VCCP[04]
M6
20% NO_STUFF D4
VSS[026] VSS[107]
Y24 C
VCC[039] VCCP[05] . VSS[027] VSS[108]
E18 J21 0 D8 AA2
VCC[040] VCCP[06] VSS[028] VSS[109]
E20 VCC[041] VCCP[07] K21 D11 VSS[029] VSS[110] AA5
F7 VCC[042] VCCP[08] M21 D13 VSS[030] VSS[111] AA8
h
F9 VCC[043] VCCP[09] N21 D16 VSS[031] VSS[112] AA11
F10 VCC[044] VCCP[10] N6 D19 VSS[032] VSS[113] AA14
F12 VCC[045] VCCP[11] R21 D23 VSS[033] VSS[114] AA16
F14 VCC[046] VCCP[12] R6 D26 VSS[034] VSS[115] AA19
F15 T21 10,11,24,28,47,55,57 +V1.5S E3 AA22
VCC[047] VCCP[13] VSS[035] VSS[116]
c
F17 VCC[048] VCCP[14] T6 E6 VSS[036] VSS[117] AA25
F18 VCC[049] VCCP[15] V21 E8 VSS[037] VSS[118] AB1
F20 VCC[050] VCCP[16] W21 E11 VSS[038] VSS[119] AB4
AA7 VCC[051] E14 VSS[039] VSS[120] AB8
AA9 B26 +VCCA_PROC R3R13 0.01 E16 AB11
VCC[052] VCCA[01] VSS[040] VSS[121]
s
AA10 C26 1% E19 AB13
VCC[053] VCCA[02] 53,54,55 +VCC_CORE C3R3 C3R2 VSS[041] VSS[122]
AA12 VCC[054] E21 VSS[042] VSS[123] AB16
AA13 AD6 0.01uF 10uF Layout Note: E24 AB19
VCC[055] VID[0] H_VID0 52 Place C3R3 near pin-B26 VSS[043] VSS[124]
10% 20%
-
AA15 VCC[056] VID[1] AF5 H_VID1 52 . F5 VSS[044] VSS[125] AB23
AA17 AE5 . F8 AB26
VCC[057] VID[2] H_VID2 52 VSS[045] VSS[126]
AA18 VCC[058] VID[3] AF4 H_VID3 52 F11 VSS[046] VSS[127] AC3
AA20 VCC[059] VID[4] AE3 H_VID4 52 F13 VSS[047] VSS[128] AC6
AB9 VCC[060] VID[5] AF3 H_VID5 52 F16 VSS[048] VSS[129] AC8
AC10 AE2 R1T16 F19 AC11
VCC[061] VID[6] H_VID6 52 VSS[049] VSS[130]
p
AB10 100 F2 AC14
VCC[062] 1% VSS[050] VSS[131]
AB12 VCC[063] . F22 VSS[051] VSS[132] AC16
AB14 AF7 Layout Note: F25 AC19
VCC[064] VCCSENSE VCCSENSE 52 Route VCCSENSE and VSSSENSE traces at VSS[052] VSS[133]
AB15 VCC[065] G4 VSS[053] VSS[134] AC21
AB17 27.4 Ohms with 50 mil spacing. G1 AC24
VCC[066] Place PU and PD within 1 inch of CPU. VSS[054] VSS[135]
AB18 AE7 G23 AD2
o
VCC[067] VSSSENSE VSSSENSE 52 VSS[055] VSS[136]
G26 VSS[056] VSS[137] AD5
Penryn_Ball-out_Rev_1p0 R1T14 H3 AD8
100 VSS[057] VSS[138]
t
. 1%
H6 VSS[058] VSS[139] AD11
. H21 VSS[059] VSS[140] AD13
H24 VSS[060] VSS[141] AD16
J2 VSS[061] VSS[142] AD19
B J5 AD22 B
VSS[062] VSS[143]
J22 VSS[063] VSS[144] AD25
p
J25 VSS[064] VSS[145] AE1
K1 VSS[065] VSS[146] AE4
K4 VSS[066] VSS[147] AE8
K23 VSS[067] VSS[148] AE11
K26 VSS[068] VSS[149] AE14
L3 AE16
l. a
VSS[069] VSS[150]
L6 VSS[070] VSS[151] AE19
L21 VSS[071] VSS[152] AE23
L24 VSS[072] VSS[153] AE26
M2 VSS[073] VSS[154] A2
M5 VSS[074] VSS[155] AF6
M22 VSS[075] VSS[156] AF8
M25 VSS[076] VSS[157] AF11
N1 VSS[077] VSS[158] AF13
N4 VSS[078] VSS[159] AF16
N23 VSS[079] VSS[160] AF19
N26 VSS[080] VSS[161] AF21
P3 A25
w
VSS[081] VSS[162]
VSS[163] AF25
Penryn_Ball-out_Rev_1p0
.
w w Pillar Rock
Title
Size
Custom
Penryn (2 of 2)
Document Number
355659
Intel Confidential
Rev
1.0
A

5 4 3 2 1
5 4 3 2 1
7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57 +V3.3S
o m
c
CPU Thermal Sensor
7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57 +V3.3S
.
D Layout Note: R3B19
10K
R3N22
10K
R3N19
10K
D
Route H_THERMDA and C3N10
H_THERMDC on same layer w/ 0.1uF 5% 5% 5%
10 mil trace & 10 mil . . .
R3N21 20%
s
spacing. Route away from 10K .
noise sources with ground 5% U3B3
guard tracks on each side. NO_STUFF SMB_THRM_CLK 12,40,43
1 VDD 8
C3N11 SMBCLK
it c
J3C1 THERM_DXP R3N27 ADT_THERM_DXP 2 7
0 D+ SMBDAT
1 2 SMB_THRM_DATA 12,40,43
3 H_THERMDA 1000pF ADT_THERM_DXN
3 4 3 6
3 H_THERMDC THERM_DXN R3N26 5% D- OS#/A0
2X2HDR . 0 ADT_THM# 4 5 THRM_ALERT# R3N20
T_CRIT# GND PM_THRM# 12,23,40,43
NO_STUFF 0
LM95245C
. NO_STUFF
a
J4A1 NOTE : R3N27, R3N26, C3N11 are placeholders for Note: No-Stuff R3N20 for normal operation, No
3Pin_Recepticle the new thermal sensor (NS LM95245). Stuff (R9G11, Sheet 40) if R3N20 is stuffed
2 1
THERMDP THERMDN
GND0 GND2 NO_STUFF
m
GND1 3 4 5 6 GND3
e
Thermal Diode Connector
C C
J3C1
h
Connects the Internal CPU
1-2 3-4 Thermal sensor to the
ADT7461A (Default)
c
Connect an external
1-X 3-X Thermal sensor to the
ADT7461A
- s
p
CPU Fan Power Control
11,12,16,17,18,24,28,30,31,32,39,48,49,52,55,56,57 +V5S
t o
C3N4 C3N6 7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57 +V3.3S
0.1uF 4.7uF
10% 10%
B . . B
p
12
10
11
1
EU3B1 R2N6
1K
1%
V+ .
8 _ 2
TF
l. a
EN VOUT_OPAMP
OPA567 OUT
R3N14 OPA567_POSIN 9 3
40,43 CPU_PWM_FAN 15K + IS IF
HS CPU_TACHO_R_FAN R2N4
1% V- CPU_TACHO_FAN 40,43
. 3 0
C3B5 . .
4
5
13
6
7
1uF CR2N2
10% BAT54 Note: No-Stuff R2N4 to Disable PWM control of FAN
OPA567_ISIN_R
.
1
3
2
1
w
R3N8
3
2
1
1.74K J2B3
1%
.
OPA567_NEGIN CONN3_HDR
.
w
R3N10
R3N6 3.32K
20K 1%
5% .
.
w
A A
Title
CPU Thermal Sensor & Fan

A 355659 1.0
5 4 3 2 1
5 4 3 2 1
U5E1A
H_A#3
H_A#[35:3] 3
o m
c
3 H_D#[63:0] A14
H_D#0 H_A#_3 H_A#4
F2 C15
H_D#1 H_D#_0 H_A#_4 H_A#5
G8 F16
H_D#_1 H_A#_5
.
H_D#2 F8 H13 H_A#6
H_D#_2 H_A#_6
D H_D#3 E6
H_D#_3 H_A#_7
C18 H_A#7 D
H_D#4 G2 M16 H_A#8
H_D#5 H_D#_4 H_A#_8 H_A#9
H6 J13
H_D#6 H_D#_5 H_A#_9 H_A#10
H2 P16
s
H_D#7 H_D#_6 H_A#_10 H_A#11
F6 R16
10 +VCCP_GMCH H_D#8 H_D#_7 H_A#_11 H_A#12
D4 N17
H_D#9 H_D#_8 H_A#_12 H_A#13
H3 M13
H_D#10 H_D#_9 H_A#_13 H_A#14
M9 E17
H_D#_10 H_A#_14
it c
H_D#11 M11 P17 H_A#15
R4E8 H_D#12 H_D#_11 H_A#_15 H_A#16
J1 F17
221 H_D#13 H_D#_12 H_A#_16 H_A#17
1%
J2 H_D#_13 H_A#_17 G20
. H_SWING H_D#14 N12 B19 H_A#18
H_D#15 H_D#_14 H_A#_18 H_A#19
J6 H_D#_15 H_A#_19 J16
H_D#16 P2 E20 H_A#20
H_SWING H_D#17 H_D#_16 H_A#_20 H_A#21
L2 H_D#_17 H_A#_21 H16
H_D#18 R2 J20 H_A#22
H_D#19 H_D#_18 H_A#_22 H_A#23
N9 H_D#_19 H_A#_23 L17
H_D#20 L6 A17 H_A#24
a
R4E5 C4F1 H_D#21 H_D#_20 H_A#_24 H_A#25
M5 H_D#_21 H_A#_25 B17
100 0.1uF H_D#22 H_A#26
1% J3 H_D#_22 H_A#_26 L16
. 20% H_D#23 N2 C21 H_A#27
. H_D#24 H_D#_23 H_A#_27 H_A#28
R1 H_D#_24 H_A#_28 J17
H_D#25 N5 H20 H_A#29
H_D#26 H_D#_25 H_A#_29 H_A#30
N6 H_D#_26 H_A#_30 B18
H_D#27 P13 K17 H_A#31
H_D#28 H_D#_27 H_A#_31 H_A#32
N8 B20
m
H_D#29 H_D#_28 H_A#_32 H_A#33
L7 H_D#_29 H_A#_33 F21
H_D#30 N10 K21 H_A#34
H_D#31 H_D#_30 H_A#_34 H_A#35
M3 H_D#_31 H_A#_35 L20
H_RCOMP H_D#32 Y3
H_D#33 H_D#_32
AD14 H12
e
H_D#_33 H_ADS# H_ADS# 3
H_D#34 Y6 B16
H_D#_34 H_ADSTB#_0 H_ADSTB#0 3
C R4E2 H_D#35 Y10 H_D#_35 H_ADSTB#_1 G17 H_ADSTB#1 3
C
24.9 H_D#36 Y12 A9
1% H_D#_36 H_BNR# H_BNR# 3
. H_D#37 Y14 F11
H_D#_37 H_BPRI# H_BPRI# 3
H_D#38 Y7 G12
HOST
h
H_D#_38 H_BREQ# H_BREQ# 3
H_D#39 W2 E9
H_D#_39 H_DEFER# H_DEFER# 3
H_D#40 AA8 B10
H_D#_40 H_DBSY# H_DBSY# 3
H_D#41 Y9 AH7
H_D#_41 HPLL_CLK CLK_MCH_BCLK 35
H_D#42 AA13 AH6
H_D#_42 HPLL_CLK# CLK_MCH_BCLK# 35
H_D#43
c
AA9 J11 H_DPWR# 3
H_D#44 H_D#_43 H_DPWR#
AA11 F9 H_DRDY# 3
H_D#45 H_D#_44 H_DRDY#
AD11 H9 H_HIT# 3
H_D#46 H_D#_45 H_HIT#
AD10 E12 H_HITM# 3
H_D#47 H_D#_46 H_HITM#
AD13 H11
s
H_D#48 H_D#_47 H_LOCK# H_LOCK# 3
AE12 C9 H_TRDY# 3
H_D#49 H_D#_48 H_TRDY#
AE9
H_D#50 H_D#_49
AA2
H_D#_50
-
H_D#51 AD8
H_D#52 H_D#_51
AA3
H_D#53 H_D#_52
AD3 J8 H_DINV#0 3
H_D#54 H_D#_53 H_DINV#_0
AD7 L3 H_DINV#1 3
H_D#55 H_D#_54 H_DINV#_1
AE14 Y13 H_DINV#2 3
H_D#_55 H_DINV#_2
p
H_D#56 AF3 Y1
H_D#_56 H_DINV#_3 H_DINV#3 3
H_D#57 AC1
H_D#58 H_D#_57
AE3 L10 H_DSTBN#0 3
H_D#59 H_D#_58 H_DSTBN#_0
AC3 M7 H_DSTBN#1 3
H_D#60 H_D#_59 H_DSTBN#_1
AE11 AA5 H_DSTBN#2 3
H_D#_60 H_DSTBN#_2
to
H_D#61 AE8 AE6
H_D#_61 H_DSTBN#_3 H_DSTBN#3 3
H_D#62 AG2
H_D#63 H_D#_62
AD6 L9 H_DSTBP#0 3
H_D#_63 H_DSTBP#_0
M8 H_DSTBP#1 3
H_DSTBP#_1
AA6 H_DSTBP#2 3
H_SWING H_DSTBP#_2
C5 AE5 H_DSTBP#3 3
B H_RCOMP E3
H_SWING H_DSTBP#_3 B
H_RCOMP H_REQ#[4:0] 3
B15 H_REQ#0
p
H_REQ#_0 H_REQ#1
K13
H_REQ#_1 H_REQ#2
F13
H_REQ#_2 H_REQ#3
B13
H_REQ#_3 H_REQ#4
3,20 H_CPURST# C12 B14
H_CPURST# H_REQ#_4
3,43 H_CPUSLP# E11 H_RS#[2:0] 3
H_CPUSLP#
la
10 +VCCP_GMCH B6 H_RS#0
H_RS#_0 H_RS#1
F12
H_RS#_1 H_RS#2
C8
H_RS#_2
A11
R4E7 H_AVREF
B11
.
1K H_DVREF
1%
. CANTIGA_1p2
H_AVREF
w
NO_STUFF
R4E4 C4E12
2K 0.1uF
1% R4E6 10%
.
0
w
H_DVREF
H_VREF & H_DVREF

Default= R4E6(STUFF)
w
A R4E3, R4F1(NO_STUFF) on Sheet # 65 A
H_AVREF & H_DVREF shorted togther (same voltage divider)
For EV= R4E6(NO_STUFF)
R4E3, R4F1 (STUFF) on Sheet # 65
Title
H_AVREF & H_DVREF can be schoomed independently for EV
CANTIGA (1 OF 6)
(separate voltage divider)

A 355659 1.0
5 4 3 2 1
5 4 3 2 1
U5E1B
m
M36 RSVD1
MCH_RSVD_1
N36 AP24
DDR CLK/ CONTROL/COMPENSATION

MCH_RSVD_2 RSVD2 SA_CK_0 M_CLK_DDR0 13
R33 AT21 U5E1C
MCH_RSVD_3 RSVD3 SA_CK_1 M_CLK_DDR1 13
T33 RSVD4 SB_CK_0 AV24 M_CLK_DDR3 14
MCH_RSVD_4 10 +VCC_PEG
AH9 AU20 M_CLK_DDR4 14
o
MCH_RSVD_5 RSVD5 SB_CK_1
AH10 RSVD6
MCH_RSVD_6
AH12 RSVD7 SA_CK#_0 AR24 M_CLK_DDR#0 13 L32 L_BKLT_CTRL
MCH_RSVD_7 17 L_BKLT_CTRL PEG_COMP R5T3 49.9
AH13 RSVD8 SA_CK#_1 AR21 M_CLK_DDR#1 13 G32 L_BKLT_EN PEG_COMPI T37
MCH_RSVD_8 TP_MCH_RSVD9 17 L_BKLT_EN
K12 RSVD9 SB_CK#_0 AU24 M_CLK_DDR#3 14 17,20 L_CTRL_CLK M32 L_CTRL_CLK PEG_COMPO T36
c
AV20 M_CLK_DDR#4 14
SB_CK#_1
17,20 L_CTRL_DATA M33 PEG_RX#[15:0] 19
L_CTRL_DATA PEG_RX#0
BC28 M_CKE0 13,15 17 LVDS_DDC_CLK K33 H44
SA_CKE_0 L_DDC_CLK PEG_RX#_0
.
AY28 J33 J46 PEG_RX#1
SA_CKE_1 M_CKE1 13,15 17 LVDS_DDC_DATA L_DDC_DATA PEG_RX#_1
D MCH_RSVD_14
T24
RSVD14 SB_CKE_0
AY36 M_CKE3 14,15 PEG_RX#_2
L44 PEG_RX#2 D
BB36 L40 PEG_RX#3
SB_CKE_1 M_CKE4 14,15 PEG_RX#_3
RSVD
TP_MCH_RSVD15 B31 R5U18 L_VDD_EN_R M29 N41 PEG_RX#4
RSVD15 17 LVDS_VDD_EN 0 L_VDD_EN PEG_RX#_4 PEG_RX#5
BA17 C44 P48
s
SA_CS#_0 M_CS#0 13,15 LVDS_IBG LVDS_IBG PEG_RX#_5
TP_MCH_RSVD17 M1 AY16 NO_STUFF LVDS_VBG B43 N44 PEG_RX#6
RSVD17 SA_CS#_1 M_CS#1 13,15 LVDS_VBG PEG_RX#_6
AV16 TP5F1 . E37 T43 PEG_RX#7
SB_CS#_0 M_CS#2 14,15 LVDS_VREFH PEG_RX#_7
AR13 E38 U43 PEG_RX#8
SB_CS#_1 M_CS#3 14,15 LVDS_VREFL PEG_RX#_8
LVDS
TP_MCH_RSVD20 AY21 R5T11 C41 Y43 PEG_RX#9
RSVD20 17 LVDSA_CLK# LVDSA_CLK# PEG_RX#_9
it c
BD17 2.37K C40 Y48 PEG_RX#10
SA_ODT_0 M_ODT0 13,15 17 LVDSA_CLK LVDSA_CLK PEG_RX#_10
AY17 1% B37 Y36 PEG_RX#11
SA_ODT_1 M_ODT1 13,15 . 17 LVDSB_CLK# LVDSB_CLK# PEG_RX#_11
B2 BF15 A37 AA43 PEG_RX#12
MCH_RSVD_21 RSVD21 SB_ODT_0 M_ODT2 14,15 17 LVDSB_CLK LVDSB_CLK PEG_RX#_12
TP_MCH_RSVD22 BG23 AY13 9,10 +V1.8_GMCH AD37 PEG_RX#13
RSVD22 SB_ODT_1 M_ODT3 14,15 PEG_RX#_13
TP_MCH_RSVD23 BF23 H47 AC47 PEG_RX#14
RSVD23 SM_RCOMP 17 LVDSA_DATA#0 LVDSA_DATA#_0 PEG_RX#_14 PEG_RX#15
MCH_RSVD_24 BH18 RSVD24 SM_RCOMP BG22 E46 LVDSA_DATA#_1 PEG_RX#_15 AD39
SM_RCOMP# 17 LVDSA_DATA#1
MCH_RSVD_25 BF18 RSVD25 SM_RCOMP# BH21 G40 LVDSA_DATA#_2 PEG_RX[15:0] 19
R5R4 17 LVDSA_DATA#2 PEG_RX0
A40 LVDSA_DATA#_3 PEG_RX_0 H43
GRAPHICS
1K 17 LVDSA_DATA#3
SM_RCOMP_VOH BF28 SM_RCOMP_VOH 1% PEG_RX_1 J44 PEG_RX1
BH28 SM_RCOMP_VOL H48 L43 PEG_RX2
a
SM_RCOMP_VOL NO_STUFF 17 LVDSA_DATA0 LVDSA_DATA_0 PEG_RX_2 PEG_RX3
SM_PWROK 46 D45 LVDSA_DATA_1 PEG_RX_3 L41
17 LVDSA_DATA1 PEG_RX4
SM_VREF AV42 M_VREF_MCH 46,48 F40 LVDSA_DATA_2 PEG_RX_4 N40
17 LVDSA_DATA2 PEG_RX5
SM_PWROK AR36 B40 LVDSA_DATA_3 PEG_RX_5 P47
SM_REXT R4R7 499 NOTE:SM_DRAMRST# Would be 17 LVDSA_DATA3 PEG_RX6
SM_REXT BF17 PEG_RX_6 N43
BC36 TP_SM_DRAMRST#
. 1% R5R5 needed for DDR3 only A41 T42 PEG_RX7
SM_DRAMRST# 1K 17 LVDSB_DATA#0 LVDSB_DATA#_0 PEG_RX_7 PEG_RX8
1% H38 LVDSB_DATA#_1 PEG_RX_8 U42
17 LVDSB_DATA#1 PEG_RX9
DPLL_REF_CLK B38 DREFCLK 35 NO_STUFF G37 LVDSB_DATA#_2 PEG_RX_9 Y42
17 LVDSB_DATA#2 PEG_RX10
A38 J37 W47
m
DPLL_REF_CLK# DREFCLK# 35 17 LVDSB_DATA#3 LVDSB_DATA#_3 PEG_RX_10
E41 Y37 PEG_RX11
DPLL_REF_SSCLK DREFSSCLK 35 PEG_RX_11
F41 B42 AA42 PEG_RX12
DPLL_REF_SSCLK# DREFSSCLK# 35 NOTE: All LVDS data 17 LVDSB_DATA0 LVDSB_DATA_0 PEG_RX_12
G38 AD36 PEG_RX13
17 LVDSB_DATA1 LVDSB_DATA_1 PEG_RX_13
ME JTAG
F43 signals/and its compliments F37 AC48 PEG_RX14
CLK PEG_CLK CLK_PCIE_3GPLL 35 SHOULD BE ROUTED 17 LVDSB_DATA2 LVDSB_DATA_2 PEG_RX_14
PCI-EXPRESS
AL34 E43 K37 AD40 PEG_RX15
e
15 MCH_TCK ME_JTAG_TCK PEG_CLK# CLK_PCIE_3GPLL# 35 DIFFERENTIALLY 17 LVDSB_DATA3 LVDSB_DATA_3 PEG_RX_15
PEG_TX#[15:0] 19
C AK34 ME_JTAG_TDI PEG_TX#_0 J41 PEG_TX#0 C
15 MCH_TDI PEG_TX#1
DMI_TXN[3:0] 22 PEG_TX#_1 M46
AN35 AE41 DMI_TXN0 R5U9 0 5% MCH_TVA_DAC F25 M47 PEG_TX#2
15 MCH_TDO ME_JTAG_TDO DMI_RXN_0 18 TVA_DAC TVA_DAC PEG_TX#_2
AE37 DMI_TXN1 R5U8 0 5% MCH_TVB_DAC H25 M40 PEG_TX#3
h
DMI_RXN_1 18 TVB_DAC TVB_DAC PEG_TX#_3
AM35 AE47 DMI_TXN2 R5U5 0 . 5% MCH_TVC_DAC K25 M42 PEG_TX#4
15 MCH_TMS ME_JTAG_TMS DMI_RXN_2 18 TVC_DAC TVC_DAC PEG_TX#_4
TV
AH39 DMI_TXN3 . R48 PEG_TX#5
DMI_RXN_3 R5U4 150 1% PEG_TX#_5 PEG_TX#6
DMI_TXP[3:0] 22 . H24 N38
DMI_TXP0 R5U7 150 1% TV_RTN PEG_TX#_6 PEG_TX#7
35 MCH_BSEL0 AE40 T40
DMI_RXP_0 DMI_TXP1 PEG_TX#_7 PEG_TX#8
c
T25 AE38 R5U6 150 1% U37
35 MCH_BSEL1 CFG_0 DMI_RXP_1 PEG_TX#_8
R25 AE48 DMI_TXP2 U40 PEG_TX#9
35 MCH_BSEL2 CFG_1 DMI_RXP_2 PEG_TX#_9
P25 AH40 DMI_TXP3 C31 Y40 PEG_TX#10
12 MCH_CFG_[17:3] CFG_2 DMI_RXP_3 18 TV_DCONSEL0_MCH TV_DCONSEL_0 PEG_TX#_10
MCH_CFG_3 P20 E32 AA46 PEG_TX#11
CFG_3 DMI_RXN[3:0] 22 Layout Note: 18 TV_DCONSEL1_MCH TV_DCONSEL_1 PEG_TX#_11
MCH_CFG_4 P24 AE35 DMI_RXN0 AA37 PEG_TX#12
-s
MCH_CFG_5 CFG_4 DMI_TXN_0 Place 150 Ohm termination resistors PEG_TX#_12
C25 AE43 DMI_RXN1 AA40 PEG_TX#13
MCH_CFG_6 CFG_5 DMI_TXN_1 close to GMCH PEG_TX#_13
N24 AE46 DMI_RXN2 AD43 PEG_TX#14
MCH_CFG_7 CFG_6 DMI_TXN_2 PEG_TX#_14
M24 AH42 DMI_RXN3 AC46 PEG_TX#15
MCH_CFG_8 CFG_7 DMI_TXN_3 PEG_TX#_15
E21 DMI_RXP[3:0] 22 PEG_TX[15:0] 19
CFG_8
CFG
MCH_CFG_9 AD35 DMI_RXP0 Layout Note: PEG_TX0

DMI
C23 16 CRT_BLUE E28 J42

MCH_CFG_10 CFG_9 DMI_TXP_0 Place 150 Ohm termination CRT_BLUE PEG_TX_0
C24 AE44 DMI_RXP1 L46 PEG_TX1
MCH_CFG_11 CFG_10 DMI_TXP_1 resistors close to GMCH PEG_TX_1
N21 AF46 DMI_RXP2 16 CRT_GREEN G28 M48 PEG_TX2
MCH_CFG_12 CFG_11 DMI_TXP_2 CRT_GREEN PEG_TX_2
P21 AH43 DMI_RXP3 M39 PEG_TX3
CFG_12 DMI_TXP_3 PEG_TX_3
p
MCH_CFG_13 T21 J28 M43 PEG_TX4
CFG_13 16 CRT_RED CRT_RED PEG_TX_4
VGA
MCH_CFG_14 R20 R5T4 150 1% R47 PEG_TX5
MCH_CFG_15 CFG_14 R5T5 150 1% PEG_TX_5 PEG_TX6
M20 G29 N37
MCH_CFG_16 CFG_15 R5T6 150 1% CRT_IRTN PEG_TX_6 PEG_TX7
L21 T39
MCH_CFG_17 CFG_16 PEG_TX_7 PEG_TX8
H21 16 CRT_DDC_CLK_MCH H32 U36
CFG_17 CRT_DDC_CLK PEG_TX_8
o
P29 J32 U39 PEG_TX9
GRAPHICS VID
MCH_CFG_18 CFG_18 16 CRT_DDC_DATA_MCH CRT_DDC_DATA PEG_TX_9

R28 J29 Y39 PEG_TX10
12 MCH_CFG_19 R5F10 MCH_CFG_20_R CFG_19 R5U10 30.1 HSYNC CRT_HSYNC PEG_TX_10 PEG_TX11
T28 B33 E29 Y46
t
12,19 MCH_CFG_20 CFG_20 GFX_VID_0 GFXVR_VID_0 49 16 CRT_HSYNC CRT_TVO_IREF PEG_TX_11
0 B32 R5T7 . 1.02k CRTIREF L29 AA36 PEG_TX12
GFX_VID_1 GFXVR_VID_1 49 CRT_VSYNC PEG_TX_12
TP5F2 NO_STUFF G33 0.5% . AA39 PEG_TX13
GFX_VID_2 GFXVR_VID_2 49 PEG_TX_13
. F33 R5U11 30.1 VSYNC AD42 PEG_TX14
B GFX_VID_3 GFXVR_VID_3 49 16 CRT_VSYNC PEG_TX_14 B
R5F13 PM_SYNC#_R R29 E33 . AD46 PEG_TX15
23 PM_SYNC# PM_SYNC# GFX_VID_4 GFXVR_VID_4 49 PEG_TX_15
0 R4T2 PM_DPRSTP#_R B7
p
3,21,43 H_DPRSTP# PM_DPRSTP#
0 N33
40 PM_EXTTS#0_EC PM_EXT_TS#_0
. R5P2 PM_EXTTS#1_R P32 CANTIGA_1p2 R5U13 10K CLK_MCH_OE#
13,14 TS#_DIMM0_1 PM_EXT_TS#_1
PM
23 DELAY_VR_PWRGOOD .0 AT40
PWROK GFX_VR_EN
C34 GFXVR_EN 49
9,10 +V1.25S_1.05M_CANTIGA
R4R11
. 100 RST_IN#_MCHAT11 5,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57 +V3.3S R5U12 10K PM_EXTTS#0_EC
R4T3 0 THRMTRIP#_R T20 RSTIN#
THERMTRIP#
l. a
3,21 PM_THRMTRIP# R5U31 0 DPRSLPVR_R R32 9,10 +V1.8_GMCH R5P5 10K
23,43,52 PM_DPRSLPVR DPRSLPVR PM_EXTTS#1_R 15
R5D10 R5D5
. AH37 1K 1K
CL_CLK CL_CLK0 23 1% 0.10%
. AH36 CL_DATA0 23
TP_MCH_NC1 CL_DATA
BG48 AN36 MPWROK 23,46
PLT_RST# 19,22,25,26,38,41,57
TP_MCH_NC2 NC_1 CL_PWROK R5D11 SM_RCOMP_VOH
BF48 AJ35 CL_RST#0 23
NC_2 CL_RST# EV_VCC_V1.05_CLVREF0
ME
TP_MCH_NC3 BD48 AH34 MCH_CLVREF_R 0

TP_MCH_NC4 NC_3 CL_VREF NO_STUFF C5R2 C5R4
BC48
TP_MCH_NC5 NC_4 R5D8 0.01uF 2.2uF
BH47 MCH_CLVREF NO_STUFF
TP_MCH_NC6 NC_5 0 R5D9 C5D3 R5D12 3.01k 10% 10%
BG47
TP_MCH_NC7 NC_6 0.1uF 511 1% 402 .
BE47 N28 DDPC_CTRLCLK 19
NC_7 DDPC_CTRLCLK
w
TP_MCH_NC8 BH46 M28 10%
. 1%
NC_8 DDPC_CTRLDATA DDPC_CTRLDATA 19
TP_MCH_NC9 BF46 G36 .
NC_9 SDVO_CTRLCLK SDVO_CTRLCLK 19
NC
TP_MCH_NC10 BG45 E36

NC_10 SDVO_CTRLDATA SDVO_CTRLDATA 19
TP_MCH_NC11 BH44 K36 SM_RCOMP_VOL
NC_11 CLKREQ# CLK_MCH_OE# 35
TP_MCH_NC12
TP_MCH_NC13
BH43
BH6
NC_12 ICH_SYNC#
H36 MCH_ICH_SYNC# 23
****
MISC
NC_13 MCH_TSATN# 41
TP_MCH_NC14 BH5 R7V4 33 NO_STUFF R5D6 C5R1 C5R3
w
9,10 +V1.8_GMCH TP_MCH_NC15 NC_14 R7V3 33 NO_STUFF HDA_BIT_CLK 21,27 1K 0.01uF 2.2uF
BG4 B12
TP_MCH_NC16 NC_15 TSATN# R7V8 33 NO_STUFF HDA_RST# 21,27 0.10% 10% 10%
BH3
TP_MCH_NC17 NC_16 R7V23 33 NO_STUFF HDA_SYNC 21,27 402 .
BF3
TP_MCH_NC18 NC_17 R5F9 0 NO_STUFF HDA_SDOUT 21,27
BH2 HDA_SDIN3 21,27
TP_MCH_NC19 NC_18 HDA_CODEC_BCLK
BG2 B28
TP_MCH_NC20 NC_19 HDA_BCLK HDA_CODEC_RST#
BE2 B30
NC_20 HDA_RST#
.
NO_STUFF
TP_MCH_NC21 HDA_SDIN
w
BG1 B29
A R5D1 R5D4 TP_MCH_NC22 BF1
NC_21 HDA_SDI
C29 HDA_CODEC_SDATAOUT A
20 80.6 TP_MCH_NC23 BD1
NC_22 HDA_SDO
A28 HDA_CODEC_SYNC Pillar Rock Intel Confidential
HDA
TP_MCH_NC24 NC_23 HDA_SYNC IMPORTANT NOTE:

BC1 NC_24
1% 1%
SM_RCOMP
TP_MCH_NC25 F1 NC_25
When the Resistors R8E7, R7H3 (Page-28) are mounted, then the
resistors R7V4, R7V3, R7V8, R7V23, R5F9 should be NO_STUFF.
Title
SM_RCOMP# CANTIGA (2 OF 6)
CANTIGA_1p2
.
R5R1
1%
80.6
20
NO_STUFF
R5D3
1% A 355659 1.0
5 4 3 2 1
5 4 3 2 1
o m
c
13 M_A_DQ[63:0] 14 M_B_DQ[63:0]
.
U5E1D U5E1E
D M_A_DQ0 AJ38
SA_DQ_0 SA_BS_0
BD21 M_A_BS0 13,15
M_B_DQ0 AK47
SB_DQ_0 SB_BS_0
BC16 M_B_BS0 14,15 D
M_A_DQ1 AJ41 BG18 M_B_DQ1 AH46 BB17
SA_DQ_1 SA_BS_1 M_A_BS1 13,15 SB_DQ_1 SB_BS_1 M_B_BS1 14,15
M_A_DQ2 AN38 AT25 M_B_DQ2 AP47 BB33
SA_DQ_2 SA_BS_2 M_A_BS2 13,15 SB_DQ_2 SB_BS_2 M_B_BS2 14,15
M_A_DQ3 AM38 M_B_DQ3 AP46
s
M_A_DQ4 SA_DQ_3 M_B_DQ4 SB_DQ_3
AJ36 BB20 M_A_RAS# 13,15 AJ46
M_A_DQ5 SA_DQ_4 SA_RAS# M_B_DQ5 SB_DQ_4
AJ40 BD20 M_A_CAS# 13,15 AJ48 AU17 M_B_RAS# 14,15
M_A_DQ6 SA_DQ_5 SA_CAS# M_B_DQ6 SB_DQ_5 SB_RAS#
AM44 AY20 M_A_WE# 13,15 AM48 BG16 M_B_CAS# 14,15
M_A_DQ7 SA_DQ_6 SA_WE# M_B_DQ7 SB_DQ_6 SB_CAS#
AM42 AP48 BF14 M_B_WE# 14,15
SA_DQ_7 SB_DQ_7 SB_WE#
it c
M_A_DQ8 AN43 M_B_DQ8 AU47
AN44 AU46
AU40 SA_DQ_10 M_A_DM[7:0] 13 BA48 SB_DQ_10
M_A_DQ11 AT38 AM37 M_A_DM0 M_B_DQ11 AY48
SA_DQ_11 SA_DM_0 SB_DQ_11 M_B_DM[7:0] 14
M_A_DQ12 AN41 AT41 M_A_DM1 M_B_DQ12 AT47 AM47 M_B_DM0
M_A_DQ13 SA_DQ_12 SA_DM_1 M_A_DM2 M_B_DQ13 SB_DQ_12 SB_DM_0 M_B_DM1
AN39 SA_DQ_13 SA_DM_2 AY41 AR47 SB_DQ_13 SB_DM_1 AY47
M_A_DQ14 AU44 AU39 M_A_DM3 M_B_DQ14 BA47 BD40 M_B_DM2
AU42 SA_DQ_15 SA_DM_4 BB12 BC47 SB_DQ_15 SB_DM_3 BF35
M_A_DQ16 AV39 AY6 M_A_DM5 M_B_DQ16 BC46 BG11 M_B_DM4
AY44 AT7 BC44 BA3
a
SA_DQ_17 SA_DM_6 SB_DQ_17 SB_DM_5
A
M_A_DQ18 BA40 AJ5 M_A_DM7 M_B_DQ18 BG43 AP1 M_B_DM6
B
M_A_DQ19 SA_DQ_18 SA_DM_7 M_B_DQ19 SB_DQ_18 SB_DM_6 M_B_DM7
BD43 SA_DQ_19 M_A_DQS[7:0] 13 BF43 SB_DQ_19 SB_DM_7 AK2
M_A_DQ20 AV41 AJ44 M_A_DQS0 M_B_DQ20 BE45
SA_DQ_20 SA_DQS_0 SB_DQ_20 M_B_DQS[7:0] 14
M_A_DQ21 AY43 AT44 M_A_DQS1 M_B_DQ21 BC41 AL47 M_B_DQS0
M_A_DQ22 SA_DQ_21 SA_DQS_1 M_A_DQS2 M_B_DQ22 SB_DQ_21 SB_DQS_0 M_B_DQS1
BB41 BA43 BF40 AV48
SA_DQ_22
MEMORY SA_DQS_2 SB_DQ_22 SB_DQS_1
M_A_DQ23 M_A_DQS3 M_B_DQ23 M_B_DQS2
MEMORY
BC40 SA_DQ_23 SA_DQS_3 BC37 BF41 SB_DQ_23 SB_DQS_2 BG41
M_A_DQ24 AY37 AW12 M_A_DQS4 M_B_DQ24 BG38 BG37 M_B_DQS3
BD38 BC8 BF38 BH9
m
AV37 SA_DQ_26 SA_DQS_6 AU8 BH35 SB_DQ_26 SB_DQS_5 BB2
M_A_DQ27 AT36 AM7 M_A_DQS7 M_B_DQ27 BG35 AU1 M_B_DQS6
SA_DQ_27 SA_DQS_7 M_A_DQS#[7:0] 13 SB_DQ_27 SB_DQS_6
M_A_DQ28 AY38 AJ43 M_A_DQS#0 M_B_DQ28 BH40 AN6 M_B_DQS7
SA_DQ_28 SA_DQS#_0 SB_DQ_28 SB_DQS_7 M_B_DQS#[7:0] 14
M_A_DQ29 BB38 AT43 M_A_DQS#1 M_B_DQ29 BG39 AL46 M_B_DQS#0
M_A_DQ30 SA_DQ_29 SA_DQS#_1 M_A_DQS#2 M_B_DQ30 SB_DQ_29 SB_DQS#_0 M_B_DQS#1
AV36 BA44 BG34 AV47
e
AW36 SA_DQ_31 SA_DQS#_3 BD37 BH34 SB_DQ_31 SB_DQS#_2 BH41
C M_A_DQ32 BD13 SA_DQ_32 SA_DQS#_4 AY12 M_A_DQS#4 M_B_DQ32 BH14 SB_DQ_32 SB_DQS#_3 BH37 M_B_DQS#3 C
M_A_DQ33 AU11 BD8 M_A_DQS#5 M_B_DQ33 BG12 BG9 M_B_DQS#4
BC11 SA_DQ_34 SA_DQS#_6 AU9 BH11 SB_DQ_34 SB_DQS#_5 BC2
M_A_DQ35 BA12 AM8 M_A_DQS#7 M_B_DQ35 BG8 AT2 M_B_DQS#6
SYSTEM
h
M_A_DQ36 SA_DQ_35 SA_DQS#_7 M_B_DQ36 SB_DQ_35 SB_DQS#_6 M_B_DQS#7
SYSTEM
AU13 SA_DQ_36 M_A_A[14:0] 13,15 BH12 SB_DQ_36 SB_DQS#_7 AN5
M_A_DQ37 AV13 BA21 M_A_A0 M_B_DQ37 BF11
SA_DQ_37 SA_MA_0 SB_DQ_37 M_B_A[14:0] 14,15
M_A_DQ38 BD12 BC24 M_A_A1 M_B_DQ38 BF8 AV17 M_B_A0
M_A_DQ39 SA_DQ_38 SA_MA_1 M_A_A2 M_B_DQ39 SB_DQ_38 SB_MA_0 M_B_A1
BC12 BG24 BG7 BA25
c
BB9 BH24 BC5 BC25
BA9 BG25 BC6 AU25
AU10 BA24 AY3 AW25
AV9 BD24 AY1 BB28
BA11 BG27 BF6 AU28
s
BD9 BF25 BF5 AW28
AY8 AW24 BA1 AT33
BA6 BC21 BD3 BD33
SA_DQ_47 SA_MA_10 SB_DQ_47 SB_MA_9
-
M_A_DQ48 M_A_A11 M_B_DQ48 M_B_A10
DDR
AV5 BG26 AV2 BB16

DDR
AV7 BH26 AU3 AW33
AT9 BH17 AR3 AY33
AN8 AY25 AN2 BH15
M_A_DQ52 SA_DQ_51 SA_MA_14 M_B_DQ52 SB_DQ_51 SB_MA_13 M_B_A14
AU5 AY2 AU33
SA_DQ_52 SB_DQ_52 SB_MA_14
p
M_A_DQ53 AU6 M_B_DQ53 AV1
AT5 AP3
AN10 AR1
AM11 AL1
AM5 AL2
SA_DQ_57 SB_DQ_57
o
M_A_DQ58 AJ9 M_B_DQ58 AJ1
AJ8 AH1
AN12 AM2
t
AM13 AM3
AJ11 AH3
AJ12 AJ3
B SA_DQ_63 SB_DQ_63 B
CANTIGA_1p2 CANTIGA_1p2
l. a p
w w
w
A A
Title
CANTIGA (3 OF 6)

A 355659 1.0
5 4 3 2 1
5 4 3 2 1
49 +VGFX_CORE
o m
c
U5E1G 10,15,35,47,55 +V1.05M +VCC_GMCH
.
7,10 +V1.8_GMCH
D D
AP33 W28 R5U3 0.002 U5E1F
VCC_SM_1 VCC_AXG_NCTF_1 1%
AN33 V28
VCC_SM_2 VCC_AXG_NCTF_2
BH32 W26
s
VCC_SM_3 VCC_AXG_NCTF_3 C5U4 C5T3 C5R11 C5T1 C5T4
BG32 V26
VCC_SM_4 VCC_AXG_NCTF_4 270uF 22uF 0.22uF 0.22uF 0.1uF
BF32 W25 AG34
VCC_SM_5 VCC_AXG_NCTF_5 20% 20% 20% 20% 10% VCC_1
BD32 V25 AC34
VCC_SM_6 VCC_AXG_NCTF_6 SMC7343 SMC0805
. SMC0603 SMC0603 SMC0402
. VCC_2
BC32 W24 AB34
VCC_SM_7 VCC_AXG_NCTF_7 VCC_3
it c
BB32 V24 AA34
BA32 W23 Y34
VCC_SM_9 VCC_AXG_NCTF_9 Place close to VCC_5
AY32 VCC_SM_10 VCC_AXG_NCTF_10 V23 V34 VCC_6
AW32 AM21 the GMCH Cavity Capacitors U34
AV32 VCC_SM_12 VCC_AXG_NCTF_12 AL21 AM33 VCC_8
AU32 VCC_SM_13 VCC_AXG_NCTF_13 AK21 AK33 VCC_9
AT32 VCC_SM_14 VCC_AXG_NCTF_14 W21 AJ33 VCC_10
AR32 VCC_SM_15 VCC_AXG_NCTF_15 V21 AG33 VCC_11
AP32
AN32
VCC_SM_16 POWER VCC_AXG_NCTF_16 U21
AM20 49 +VCC_GFXCORE 7,10 +V1.25S_1.05M_CANTIGA
AF33 VCC_12
a
VCC_SM_17 VCC_AXG_NCTF_17
BH31 VCC_SM_18 VCC_AXG_NCTF_18 AK20 AE33 VCC_13
VCC CORE
BG31 VCC_SM_19 VCC_AXG_NCTF_19 W20 AC33 VCC_14
BF31 U20 +V1.25S_1.05M_CANTIGA AA33
VCC_SM_20 VCC_AXG_NCTF_20 R3F1 For Teenah STUFF: R3F1 VCC_15
BG30 VCC_SM_21 VCC_AXG_NCTF_21 AM19 2 1 Y33 VCC_16
BH29 AL19 0.002 NO_STUFF: R4F6 W33
VCC_SM_22 VCC_AXG_NCTF_22 NO_STUFF For Cantiga STUFF: R4F6 VCC_17
BG29 VCC_SM_23 VCC_AXG_NCTF_23 AK19 V33 VCC_18
BF29 AJ19 10,15,35,47,55 +V1.05M NO_STUFF: R3F1 U33
VCC_SM_24 VCC_AXG_NCTF_24 R4F6 VCC_19
BD29 AH19 2 1 AH28
m
VCC SM
BC29 AG19 0.002 AF28

Pins BA36, BB24, BD16, VCC_SM_26 VCC_AXG_NCTF_26 . VCC_21
BB29 VCC_SM_27 VCC_AXG_NCTF_27 AF19 AC28 VCC_22
BB21, AW16, AW13, AT13 BA29 AE19 AA28
could be left NC for VCC_SM_28 VCC_AXG_NCTF_28 VCC_23
AY29 VCC_SM_29 VCC_AXG_NCTF_29 AB19 AJ26 VCC_24
DDR2 boards AW29 AA19 49 +VCC_GFXCORE 49 +VGFX_CORE AG26
e
AV29 VCC_SM_31 VCC_AXG_NCTF_31 Y19 AE26 VCC_26
C AU29 VCC_SM_32 VCC_AXG_NCTF_32 W19 AC26 VCC_27
C
AT29 V19 R3F2 0.002 NO_STUFF AH25
VCC_SM_33 VCC_AXG_NCTF_33 1% VCC_28 +VCC_GMCH
AR29 VCC_SM_34 VCC_AXG_NCTF_34 U19 AG25 VCC_29
1
AP29 AM17 + C4T7 + C4T5 C4R9 C4T2 C4T6 C5T2 C4T4 C5T10 AF25
h
VCC_SM_35 VCC_AXG_NCTF_35 4,10,24,47,55 +V1.05S 330uF 330uF C4T3 1uF 10uF 22uF 0.1uF 0.1uF 1.0uF VCC_30
VCC_AXG_NCTF_36 AK17 3 20%
3 20%
AG24 VCC_31
VCC_SM_36 BA36 AH17 0.47uF 20% 20% 20% 10% 10% 20% AJ23
2
VCC_SM_37 VCC_SM_36/NC VCC_AXG_NCTF_37 smc7343_TAK smc7343_TAK SMC0603 SMC0603
. SMC0805
. SMC0805
. SMC0402
. SMC0402
. 402 VCC_32
BB24 AG17 AH23
VCC_SM_38 VCC_SM_37/NC VCC_AXG_NCTF_38 R4U5 0.002 VCC_33
POWER
BD16 AF17 AF23
VCC_SM_38/NC VCC_AXG_NCTF_39 VCC_34
c
BB21 AE17 1% AM32
VCC_SM_40 VCC_SM_39/NC VCC_AXG_NCTF_40 Place close to VCC_NCTF_1
AW16 AC17 NO_STUFF T32 AL32
VCC_SM_40/NC VCC_AXG_NCTF_41 the GMCH Cavity Capacitors VCC_35 VCC_NCTF_2
AW13 AB17 AK32
VCC_SM_42 VCC_SM_41/NC VCC_AXG_NCTF_42 VCC_NCTF_3
AT13 Y17 AJ32
VCC_SM_42/NC VCC_AXG_NCTF_43 R4U5 TO BE STUFFED ONLY VCC_NCTF_4
W17 AH32
s
+VGFX_CORE VCC_AXG_NCTF_44 AS BACKUP OPTION FOR +VGFX_CORE VCC_NCTF_5
V17 AG32
VCC GFX NCTF
VCC_AXG_NCTF_45 VCC_NCTF_6
AM16 AE32
VCC_AXG_NCTF_46 VCC_NCTF_7
Y26 AL16 AC32
VCC_AXG_1 VCC_AXG_NCTF_47 VCC_NCTF_8
-
AE25 AK16 AA32
AB25 AJ16 Y32
VCC_AXG_3 VCC_AXG_NCTF_49 R5T1 is used for internal R5T1 VCC_NCTF_10
AA25 AH16 W32
VCC_SM_36
VCC_SM_37
VCC_SM_38
VCC_SM_40
VCC_SM_42
VCC_AXG_4 VCC_AXG_NCTF_50 test purpose only 0 VCC_NCTF_11
AE24 AG16 U32
AC24 AF16 AM30
p
AA24 AE16 . AL30
Y24 AC16 AK30
VCC_AXG_8 VCC_AXG_NCTF_54 +VCC_MCH_35 VCC_NCTF_15
AE23 AB16 AH30
VCC_AXG_9 VCC_AXG_NCTF_55 C5R12 C4R10 C4R11 C4R12 C4R13 VCC_NCTF_16
AC23 AA16 AG30
VCC_AXG_10 VCC_AXG_NCTF_56 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF VCC_NCTF_17
AB23 Y16 AF30
o
AA23 W16 10% 10% 10% 10% 10% AE30
AJ21 V16 AC30
VCC_AXG_13 VCC_AXG_NCTF_59 NO_STUFF VCC_NCTF_20
AG21 U16 AB30
t
AE21 AA30
VCC_AXG_15 +V1.8 10,13,14,46,48,55,57 VCC_NCTF_22
AC21 Y30
VCC_AXG_16 +V1.8_GMCH 7,10 VCC_NCTF_23
AA21 W30
B VCC_AXG_17 VCC_NCTF_24 B
VCC NCTF
Y21 V30
VCC_AXG_18 R5C6 0.002 VCC_NCTF_25
AH20 U30
p
VCC_AXG_19 1% VCC_NCTF_26
AF20 AL29
VCC_AXG_20 VCC_NCTF_27
AE20 AK29
VCC_AXG_21 C5C7 C5C8 C5D2 C5D1 C5R13 VCC_NCTF_28
AC20 AJ29
VCC_AXG_22 Place C5C7 where LVDS 0.1uF 330uF 22uF 22uF 0.1uF VCC_NCTF_29
AB20 AH29
VCC_AXG_23 and DDR2 taps. 10% 20% 20% 20% 10% VCC_NCTF_30
AA20 AG29
l. a
T17 SMC0402
. SMC7343_75h SMC0805
. SMC0805
. AE29
VCC_AXG_25 NO_STUFF VCC_NCTF_32
T16 AC29
AM15 AA29
AL15 Y29
VCC_AXG_28 PLACE ON THE EDGE VCC_NCTF_35
AE15 W29
AJ15 V29
AH15 AL28
AG15 AK28
AF15 AL26
AB15 AK26
AA15 AK25
w
VCC GFX
Y15 AK24
V15 AK23
U15
VCC_AXG_38
AN14
VCC_AXG_39
AM14
VCC_AXG_40 +VCCSM_LF1
U14 AV44
VCC_AXG_41 VCC_SM_LF1
VCC SM LF
T14 BA37 +VCCSM_LF2
w
VCC_AXG_42 VCC_SM_LF2 +VCCSM_LF3
AM40
VCC_SM_LF3 +VCCSM_LF4 CANTIGA_1p2
AV21
VCC_SM_LF4 +VCCSM_LF5
AY5
AM10
BB13
VCC_SM_LF7
C4R4 C4R8 C5R7 C5R8
w
A 49 VCC_AXG_SENSE AJ14 0.1uF 0.1uF C4R5 C4R6 C5R10 1.0uF 1.0uF A
49 VSS_AXG_SENSE AH14
VCC_AXG_SENSE
VSS_AXG_SENSE
10% 10% 0.22uF 0.22uF 0.47uF 20% 20% Pillar Rock Intel Confidential
SMC0402
. SMC0402
. SMC0402 SMC0402 SMC0402 SMC0402 SMC0402
Title
Route VCC_AXG_SENSE and
VSS_AXG_SENSE
CANTIGA (4 OF 6)
differentially

CANTIGA_1p2
A 355659 1.0
5 4 3 2 1
5 4 3 2 1
7,9 +V1.25S_1.05M_CANTIGA
+V3.3S_A_TV_CRT_BG +V3.3S_A_CRT_DAC
m
R5F2
1
1 2
.
R5F14 0.002
o
0.002 C5E12 C5E17
0.1uF 0.01uF R5E5 U5E1H 6 +VCCP_GMCH 4,9,24,47,55 +V1.05S
+V1.05M_DPLLA 10% 10% 0
R4F5
2
L5F1 10uH SMC0402

. SMC0402 U13 1 2
VTT_1 0.002
c
1 2 NO_STUFF VTT_2
T13
10% B27 U12 C4E9 C4E7 C4E10 C4F2
+V1.05M_MCH_PLL
201005-548 + C5U7 C5E8 VCCA_CRT_DAC_1 VTT_3 C4E6 2.2uF 4.7uF 4.7uF 270uF
A26 T12 20%
VCCA_CRT_DAC_2 VTT_4
.
220uF 0.1uF U11 0.47uF 10% 10% 10%
10% VTT_5
D . 10%
R5F6 VTT_6
T11 SMC0603 .
SMC0805 .
SMC0805 .
SMC0805 SMC7343 D
SMC0402
. 1 2 +V3.3S_A_DAC_BG A25 U10
CRT
0.002 VCCA_DAC_BG VTT_7
B25 T10
+V1.05M_DPLLB C5E13 C5E16 VSSA_DAC_BG VTT_8
U9
s
L6F1 10uH 0.1uF 0.01uF R5E6 VTT_9
T9
10% 10% 0 +V1.05M_DPLLA VTT_10
1 2 VTT_11
U8
10% SMC0402
. SMC0402 F47 T8
201005-548 + C5F1 C5E5 +V1.05M_DPLLB VCCA_DPLLA VTT_12
NO_STUFF U7
VTT
220uF VTT_13
it c
0.1uF L48 T7
10% 10% +V1.05M_HPLL VCCA_DPLLB VTT_14
. U6
SMC0402
. VTT_15
AD1 T6
PLL
+V3.3S +V1.05M_MPLL VCCA_HPLL VTT_16
VTT_17 U5
AE1 T5 +V1.05M_AXF
+V1.8_TXLVDS VCCA_MPLL VTT_18 7,9 +V1.25S_1.05M_CANTIGA
VTT_19 V3
U3 R4F2 0
VTT_20 R4F4
+V1.25S_1.05M_CANTIGA J48 V2 1 2 +V1.05M_AXF_R 1 2
R5D13 VCCA_LVDS VTT_21 0.002
U2
A LVDS
VTT_22
NO_STUFF
4,11,24,28,47,55,57 +V1.5S 0 C5E7 J47 T2 C4E14 C4E15 SMR1210 .
a
VSSA_LVDS VTT_23
1
.
NO_STUFF 1000pF V1 1.0uF 10uF

R4D6 +VCCA_PEG_BG 10% VTT_24 20% 20%
VTT_25 U1
0.002 .SMC0402 SMC0402 SMC0805
R6E1
1 2 AD48
+V1.05M_HPLL 0.002 VCCA_PEG_BG
2
R4E9 . C5E2
0.1uF +V1.05M_PEGPLL
A PEG
+V1.05M_MCH_PLL2
10%
m
.
0 C4E3
7,9 C4E4
+V1.25S_1.05M_CANTIGA SMC0402
. AA48 +V1.8_SM_CK
0.1uF 4.7uF VCCA_PEG_PLL 7,9 +V1.8_GMCH
10% 10% C5R7:Cavity Cap L4D1
R4R1 R4D1
SMC0402
. SMC0603
. 1 2 +V1.05M_A_SM_R R4R3 +V1.05M_A_SM AR20 1 2 +V1.8_SM_CK_RR 1 2
VCCA_SM_1
NO_STUFF
0.002 0 AP20 1uH 0.002
e
+V1.05M_MPLL . SMR0603 C4R1 C4R2 C4R3 C4R7 VCCA_SM_2 C4D2 R4D2 30%
AN20 VCCA_SM_3
POWER
1
C FB4E1 + . 22uF 22uF 4.7uF 1.0uF AR17 VCCA_SM_4

0.1uF +V1.8_SMCK_RC SML0805
46 +V1.8_LDO C
SMF0603 C4E2 20% 20% 10% 20% AP17 10% 1% 1.00
VCCA_SM_5
NO_STUFF
100uF SMC0805 SMC0805
. SMC0603
. SMC0402 AN17 SMC0402
. SMR0402
2
VCCA_SM_6
2
120ohm@100MHz C4E1 SMC7343 AT16 C4D1
h
0.1uF VCCA_SM_7 10uF R5F3
AR16
A SM
C4R3: Edge Cap VCCA_SM_8
R4E1 0.51 10% AP16 20% 0.002
1% SMC0402
. VCCA_SM_9 SMC0805
.
+V1.05M_MPLL_RC SMR0402
1
c
+V1.8_TXLVDS
C4T1 7,9 +V1.25S_1.05M_CANTIGA
22uF 9,13,14,46,48,55,57 +V1.8
20%
R4R2 R5F4
SMC0805
. 1 2 +V1.05M_A_SM_CK_R R5R3 +V1.05M_A_SM_CK AP28 1 L5E1 2 +V_TXLVDS_PM 1 2
-s
0 VCCA_SM_CK_1 0.10uH 0.002
0.002 AN28 B22
VCCA_SM_CK_2 VCC_AXF_1
NO_STUFF
C5R5 C5R6 C5R9 AP25 B21 R5E4 C5E6 C5E15 20%
AXF
. 2.2uF 22uF 0.1uF VCCA_SM_CK_3 VCC_AXF_2 0 1000pF 22uF
. AN25 A21
SMR0603 10% 20% 10% VCCA_SM_CK_4 VCC_AXF_3 5% 10% 20% SML0805
AN24 NO_STUFF .
SMC0603 SMC0805
. SMC0402
. VCCA_SM_CK_5 .SMC0402 SMC0805
.
AM28
VCCA_SM_CK_NCTF_1
AM26
A CK
VCCA_SM_CK_NCTF_2
AM25
VCCA_SM_CK_NCTF_3
AL25 BF21
VCCA_SM_CK_NCTF_4 VCC_SM_CK_1
p
AM24 BH20 7 +VCC_PEG 9,15,35,47,55 +V1.05M
SM CK
VCCA_SM_CK_NCTF_5 VCC_SM_CK_2 R5E3 0
AL24 BG20 R6E3
5 +V3.3S_TVDAC +V3.3S_A_TV_CRT_BG +V3.3S_A_TV_DAC VCCA_SM_CK_NCTF_6 VCC_SM_CK_3 +V1.05M_PEG_LR 1
AM23 BF20 1 2 2
VCCA_SM_CK_NCTF_7 VCC_SM_CK_4 0.002
R4F3 AL23
VCCA_SM_CK_NCTF_8
.
FB4F1 1 2 C5E4 C5E3 + C6E11 SMR1210 .
220uF
o
0.002 4.7uF 22uF
180ohm@100MHz C5E18 C5E14 R5E7 +V3.3S_A_TV_DAC 10% 20% 10% 4,9,24,47,55 +V1.05S
K47
0.1uF 0.01uF 0 VCC_TX_LVDS .
SMC0805 SMC0805
. SMC7343 NO_STUFF
SMF0603 B24
t
10% 10% VCCA_TV_DAC_1 +V3.3S_HV
A24 C35 R6E2
VCCA_TV_DAC_2 VCC_HV_1
TV
SMC0402
. SMC0402 NO_STUFF B35 1 2
+VCC_HDA VCC_HV_2 0.002
A35
HV
B VCC_HV_3 B
NOTE: CAPS USED IN A32
p
VCC_HDA
HDA
+V3.3S_TVDAC should be V48 +VCC_DMI
within 250mils of edge VCC_PEG_1
NO_STUFF
R5T10 U48 7 +VCC_PEG

of MCH 0 VCC_PEG_2 R5E1
V47
PEG
5% +V1.5S_TVDAC VCC_PEG_3
U47 1 2
VCC_PEG_4
D TV/CRT
M25 U46 0.002
VCCD_TVDAC VCC_PEG_5
l. a
+V1.5S_QDAC C5E1
47,55,57 +V1.5S +V1.5S_TVDAC L28 0.1uF
+V1.05M_MCH_PLL2 VCCD_QDAC 10%
R4U3 AH48
VCC_DMI_1 SMC0402
. To use seperate filters for VCC_PEG & VCC_DMI
1 2 AF1
VCCD_HPLL VCC_DMI_2
AF48
0.002 C5U1 C5T9 +V1.05M_PEGPLL AH47 rails No-Stuff R5E1 and stuff L5D1 ,C5C9 & R5D7
0.1uF 0.01uF C4D3 AA47
DMI VCC_DMI_3
AG47
R4U2 10% 10% 0.1uF VCCD_PEG_PLL VCC_DMI_4
28 +V1.5S_LDO_QDAC 0 SMC0402
. SMC0402 SMC0402 10% C5T6 9,15,35,47,55 +V1.05M
NO_STUFF . Topside Cap 0.1uF M38 +VCC_DMI
VCCD_LVDS_1
LVDS
10% L37 A8 +VTTLF_CAP1 NO_STUFF L5D1

R4U2 to be stuffed & R4U4 to be VCCD_LVDS_2 VTTLF1 R5D7
SMC0402
. L1 +VTTLF_CAP2 +V1.05M_DMI_LR 1 2
VTTLF2
1
w
no_stuffed , if val needs to be
VTTLF
AB2 +VTTLF_CAP3 91nH 0.002

done from switcher +V1.5S_QDAC VTTLF3 C4T8 C4E13 + C5C9 20%
0.002 FB5U1 9,13,14,46,48,55,57 +V1.8 +V1.8_DLVDS 0.47uF C4T9 220uF SML1210-STD NO_STUFF
R4U4 C4E5 C4E8 SMC0402 0.47uF 10% NO_STUFF
R5F8 0.47uF 0.47uF
1 2 CANTIGA_1p2 0.47uF SMC7343
2
+V1.5S_LDO_QDAC_R 180ohm@100MHz C5U3 C5U2 46 +V1.8_LDO 0.002 SMC0402 SMC0402 NO_STUFF

SMF0603 0.1uF 0.01uF R5U2 4,9,24,47,55 +V1.05S
w
10% 10% 0 R5F5 R5T9 C5E9
SMC0402
. SMC0402 2 1 0 1.0uF NO_STUFF
5% 1
NO_STUFF 0.002 20%
NO_STUFF NO_STUFF SMC0402 CR5F1
BAT54
+V1_05S_SD
Pillar Rock
w
A +V1.25S_1.05M_CANTIGA 3 Intel Confidential A
1
+V1.05M_PEGPLL
R5T8
+V1.05M_PEGPLL_R
SMF0805
FB5T1
4,11,24,28,47,55,57 +V1.5S +V3.3S
R5U19
10
Title
1 2
0.002
220ohm_at_100MHz
+VCC_HDA 5% +V3.3S_HV CANTIGA (5 OF 6)
.
R5U1 R5F1
2
1.00 1 2 1 2
+V1.05M_PEGPLL_RC R5T2 10% 0.002 0.002
1% SMC0402
. C5E10 Size Document Number Rev
C5T8
10uF
SMR0402 C5T5
0.1uF
C5E11
0.1uF
0.1uF
10%
A 355659 1.0
20% 10% SMC0402
.
SMC0805
. SMC0402
.
5 4 3 2 1
5 4 3 2 1
m
U5E1I U5E1J
BG21 VSS_199 VSS_297 AH8
AU48 VSS_1 VSS_100 AM36 L12 VSS_200 VSS_298 Y8
AR48 VSS_2 VSS_101 AE36 AW21 VSS_201 VSS_299 L8
o
AL48 VSS_3 VSS_102 P36 AU21 VSS_202 VSS_300 E8
BB47 VSS_4 VSS_103 L36 AP21 VSS_203 VSS_301 B8
AW47 VSS_5 VSS_104 J36 AN21 VSS_204 VSS_302 AY7
AN47 VSS_6 VSS_105 F36 AH21 VSS_205 VSS_303 AU7
AJ47 B36 AF21 AN7
c
VSS_7 VSS_106 VSS_206 VSS_304
AF47 VSS_8 VSS_107 AH35 AB21 VSS_207 VSS_305 AJ7
AD47 AA35 R21 AE7
.
AB47 Y35 M21 AA7
D Y47
VSS_10 VSS_109
U35 J21
VSS_209 VSS_307
N7 D
T47 VSS_12 VSS_111 T35 G21 VSS_211 VSS_309 J7
N47 VSS_13 VSS_112 BF34 BC20 VSS_212 VSS_310 BG6
s
L47 VSS_14 VSS_113 AM34 BA20 VSS_213 VSS_311 BD6
G47 VSS_15 VSS_114 AJ34 AW20 VSS_214 VSS_312 AV6
BD46 VSS_16 VSS_115 AF34 AT20 VSS_215 VSS_313 AT6
BA46 VSS_17 VSS_116 AE34 AJ20 VSS_216 VSS_314 AM6
it c
AY46 VSS_18 VSS_117 W34 AG20 VSS_217 VSS_315 M6
AV46 VSS_19 VSS_118 B34 Y20 VSS_218 VSS_316 C6
AR46 VSS_20 VSS_119 A34 N20 VSS_219 VSS_317 BA5
AM46 VSS_21 VSS_120 BG33 K20 VSS_220 VSS_318 AH5
V46 VSS_22 VSS_121 BC33 F20 VSS_221 VSS_319 AD5
R46 VSS_23 VSS_122 BA33 C20 VSS_222 VSS_320 Y5
P46 VSS_24 VSS_123 AV33 A20 VSS_223 VSS_321 L5
H46 VSS_25 VSS_124 AR33 BG19 VSS_224 VSS_322 J5
F46 VSS_26 VSS_125 AL33 A18 VSS_225 VSS_323 H5
a
BF44 VSS_27 VSS_126 AH33 BG17 VSS_226 VSS_324 F5
AH44 VSS_28 VSS_127 AB33 BC17 VSS_227 VSS_325 BE4
AD44 VSS_29 VSS_128 P33 AW17 VSS_228
AA44 L33 AT17 BC3
Y44
U44
VSS_30
VSS_31
VSS_32
VSS_129
VSS_130
VSS_131
H33
N32
R17
M17
VSS_229
VSS_230
VSS_231
VSS VSS_327
VSS_328
VSS_329
AV3
AL3
T44 K32 H17 R3 4,10,24,28,47,55,57 +V1.5S
VSS_33
VSS VSS_132 VSS_232 VSS_330
m
M44 VSS_34 VSS_133 F32 C17 VSS_233 VSS_331 P3
F44 VSS_35 VSS_134 C32 VSS_332 F3
BC43 VSS_36 VSS_135 A31 BA16 VSS_235 VSS_333 BA2 1
AV43 VSS_37 VSS_136 AN29 VSS_334 AW2
AU43 T29 AU16 AU2 CR3R2
e
VSS_38 VSS_137 VSS_237 VSS_335 BAT54
AM43 VSS_39 VSS_138 N29 AN16 VSS_238 VSS_336 AR2
C J43 K29 N16 AP2 C
VSS_40 VSS_139 VSS_239 VSS_337 NO_STUFF
C43 VSS_41 VSS_140 H29 K16 VSS_240 VSS_338 AJ2
BG42 F29 G16 AH2 3
AY42 A29 E16 AF2
h
VSS_43 VSS_142 VSS_242 VSS_340 V1_5SFOLLOW
AT42 VSS_44 VSS_143 BG28 BG15 VSS_243 VSS_341 AE2
AN42 BD28 AC15 AD2 +V5S 5,12,16,17,18,24,28,30,31,32,39,48,49,52,55,56,57
AJ42 VSS_46 VSS_145 BA28 W15 VSS_245 VSS_343 AC2
1
AE42 AV28 A15 Y2
c
VSS_47 VSS_146 VSS_246 VSS_344 R3R8
N42 VSS_48 VSS_147 AT28 BG14 VSS_247 VSS_345 M2
L42 AR28 AA14 K2 +V5S 5,12,16,17,18,24,28,30,31,32,39,48,49,52,55,56,57 10
VSS_49 VSS_148 VSS_248 VSS_346 5%
BD41 VSS_50 VSS_149 AJ28 C14 VSS_249 VSS_347 AM1 NO_STUFF
AU41 AG28 BG13 AA1
2
-s
AM41 VSS_52 VSS_151 AE28 BC13 VSS_251 VSS_349 P1
AH41 AB28 BA13 H1 R3R9
VSS_53 VSS_152 VSS_252 VSS_350 10K
AD41 VSS_54 VSS_153 Y28 5%
AA41 P28 U24 MCH_VSS_351 R4T4 0
VSS_55 VSS_154 VSS_351 MCH_VSS_352 R5T12 0 10,48,55 +V3.3S_TVDAC
Y41 VSS_56 VSS_155 K28 AN13 VSS_255 VSS_352 U28
U41 H28 AJ13 U25 MCH_VSS_353 R4T5 0 U3D1 SC1563
VSS_57 VSS_156 VSS_256 VSS_353 MCH_VSS_354 R5T13 0
T41 VSS_58 VSS_157 F28 AE13 VSS_257 VSS_354 U29 5 IN
MCH_VSS_355 R4R13 0 V3.3S_TVDAC_R2 R3D2
p
M41 VSS_59 VSS_158 C28 N13 VSS_258 VSS_355 AJ6 OUT 4
G41 BF26 L13 C3D2 1 0.01
1%
VSS_60 VSS_159 VSS_259 1.0uF SHDN
B41 VSS_61 VSS_160 AH26 G13 VSS_260 VSS_NCTF_1 AF32
10% GND ADJ R3R7 C3R1
BG40 VSS_62 VSS_161 AF26 E13 VSS_261 VSS_NCTF_2 AB32
BB40 AB26 BF12 V32 . 17.8K C3D1 0.1uF
PM_SLP_S3_SHDN2
VSS_63 VSS_162 VSS_262 VSS_NCTF_3 2 3 1%
o
AV40 AA26 AV12 AJ30 22uF 10%
VSS_64 VSS_163 VSS_263 VSS_NCTF_4 .
AN40 VSS_65 VSS_164 C26 AT12 VSS_264 VSS_NCTF_5 AM29
TVDAC_ADJ2
t
H40 VSS_66 VSS_165 B26 AM12 VSS_265 VSS_NCTF_6 AF29
E40 BH25 AA12 AB29
VSS NCTF
VSS_67 VSS_166 VSS_266 VSS_NCTF_7

AT39 VSS_68 VSS_167 BD25 J12 VSS_267 VSS_NCTF_8 U26
B AM39 BB25 A12 U23 R3R10 B
VSS_69 VSS_168 VSS_268 VSS_NCTF_9 10K
AJ39 VSS_70 VSS_169 AV25 BD11 VSS_269 VSS_NCTF_10 AL20 1%
p
AE39 VSS_71 VSS_170 AR25 BB11 VSS_270 VSS_NCTF_11 V20
N39 VSS_72 VSS_171 AJ25 AY11 VSS_271 VSS_NCTF_12 AC19
L39 VSS_73 VSS_172 AC25 AN11 VSS_272 VSS_NCTF_13 AL17
B39 VSS_74 VSS_173 Y25 AH11 VSS_273 VSS_NCTF_14 AJ17
BH38 N25 AA17
l. a
VSS_75 VSS_174 VSS_NCTF_15
3
BC38 VSS_76 VSS_175 L25 Y11 VSS_275 VSS_NCTF_16 U17
BA38 J25 N11 Q3D1 R3R11
VSS_77 VSS_176 VSS_276 23,40,43,44,46,47,49,55,57 100
AU38 G25 G11 BH48 BSS138
VSS_78 VSS_177 VSS_277 VSS_SCB_1 5%
AH38 E25 C11 BH1 1
VSS SCB
VSS_79 VSS_178 VSS_278 VSS_SCB_2 PM_SLP_S3# NO_STUFF

AD38 VSS_80 VSS_179 BF24 BG10 VSS_279 VSS_SCB_3 A48
AA38 AD12 AV10 C1
2
VSS_81 VSS_180 VSS_280 VSS_SCB_4
Y38 VSS_82 VSS_181 AY24 AT10 VSS_281
U38 VSS_83 VSS_182 AT24 AJ10 VSS_282 VSS_SCB_6 A3
T38 VSS_84 VSS_183 AJ24 AE10 VSS_283
J38 VSS_85 VSS_184 AH24 AA10 VSS_284 NC_26 E1
w
F38 VSS_86 VSS_185 AF24 M10 VSS_285 NC_27 D2
C38 VSS_87 VSS_186 AB24 BF9 VSS_286 NC_28 C3
BF37 VSS_88 VSS_187 R24 BC9 VSS_287 NC_29 B4
BB37 VSS_89 VSS_188 L24 AN9 VSS_288 NC_30 A5
AW37 VSS_90 VSS_189 K24 AM9 VSS_289 NC_31 A6
AT37 VSS_91 VSS_190 J24 AD9 VSS_290 NC_32 A43
w
AN37 VSS_92 VSS_191 G24 G9 VSS_291 NC_33 A44
AJ37 F24 B9 B45
NC
VSS_93 VSS_192 VSS_292 NC_34

H37 VSS_94 VSS_193 E24 BH8 VSS_293 NC_35 C46
C37 VSS_95 VSS_194 BH23 BB8 VSS_294 NC_36 D47
BG36 VSS_96 VSS_195 AG23 AV8 VSS_295 NC_37 B47
BD36 VSS_97 VSS_196 Y23 AT8 VSS_296 NC_38 A46
w
A AK15 VSS_98 VSS_197 B23 NC_39 F48 A
AU36 VSS_99 VSS_198 A23 NC_40 E48
C48 Pillar Rock Intel Confidential
NC_41
B48
CANTIGA_1p2 NC_42
NC_43 A47 Title
CANTIGA_1p2
CANTIGA (6 OF 6)

A 355659 1.0
5 4 3 2 1
5 4 3 2 1
Layout Note:
m
Location of all MCH_CFG strap resistors
needs to be close to trace to minimize stub 5,7,10,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57 +V3.3S
7 MCH_CFG_7
o
Digital Display Port (SDVO/DP/iHDMI) Concurrent with PCIe
7 MCH_CFG_5 MCH_CFG_20 Low = Only Digital Display Port (SDVO/DP/iHDMI) or R5P7
MCH_CFG_7 ME TLS Confidentiality (Isolation Bypass Enable) PCIE or is operational (Default) 4.02K
DMI X2 Select High = Digital Display Port (SDVO/DP/iHDMI) 1%
R1T9
c
NO_STUFF
Low = AMT Firmware will use TLS cipher suite with no 2.21K and PCIE are operating simultaneously via PEG port
MCH_CFG_5 Low = DMIx2 confidentiality (Isolators are bypassed] 1%
NO_STUFF
.
High = DMIx4 (default) High = AMT Firmware will use TLS cipher suite with
Confidentiality {Isolators are active (Default)}
D R1T11
2.21K 7,19 MCH_CFG_20 D
1%
NO_STUFF
FSB Dynamic ODT

7 MCH_CFG_16
C3P4
GMCH Fan Power Control
5,11,16,17,18,24,28,30,31,32,39,48,49,52,55,56,57
C3C13
+V5S
it c s
a
MCH_CFG_16 Low = Dynamic ODT Disabled 0.1uF 4.7uF
High = Dynamic ODT Enabled (default) 10% 10%
R1E1 . . 5,7,10,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57 +V3.3S
2.21K
1%
12
10
11
NO_STUFF
1
EU4C1
R3P3
m
V+
_ 1K
8 TF 2 1%
EN MCH_TACHO_OP_FAN .
OPA567 OUT
R4P2 OPA567_POSIN_R
40,43 MCH_PWM_FAN 15K
9 + IS IF 3
HS
1% V- MCH_TACHO_R_FAN R3P4
e
. 3 MCH_TACHO_FAN 40,43
0
C C4C19 . CR3P1 C
4
5
13
6
7
1uF BAT54 .
10%
OPA567_ISIN_MCH_R
7 MCH_CFG_9 7 MCH_CFG_6
.
h
1
R1T7
3
2
1
2.21K R3P2
PCI Express Graphics Lane R1U4 1% 1.74K
3
2
1
2.21K . 1%
stuff J1C3 to enable ITPM
c
J3C2
MCH_CFG_9 Low = Reverse Lane (default) 1% MCH_CFG_6_R
.
1
High = Normal operation OPA567_NEGIN_R
J1C3
CONN3_HDR
s
R4C25
2
R4P1 3.32K
20K 1%
5%
-
MCH_CFG_6 (iTPM Host Interface)
Low = iTPM Host Interface is enabled
p
,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57 +V3.3S High = iTPM Host Interface is Disabled (default)
to
DMI Lane Reversal
R5F11 IMVP6 & Amb Thermal sensors
MCH_CFG_19 Low = Normal (default) 4.02K
High = Lanes Reversed 1%
NO_STUFF
5,7,10,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57 +V3.3S
5,7,10,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57 +V3.3S
B B
p
7 MCH_CFG_19
R3B21
10K
NO_STUFF
R3B20 C3B7
10K 0.1uF 1%
1% 20%
la
NO_STUFF
3 7481_D1P_Q R3B16 U3B2

0 1 10
.
VDD SCLK SMB_THRM_CLK 5,40,43
Q3C3 1 C3N9 7481_D1P 2 9
D1+ SDATA SMB_THRM_DATA 5,40,43
2N3904 . 1000pF 7481_D1N 3 8 7481_THRM2# R3N24
7 MCH_CFG_10 D1- ALRT#/THM2#
10% 4 7 7481_D2P 7481_D2P_Q
R3B15 3 0
2 7481_D1N_Q R3B18 THM# D2+ 0 NO_STUFF
5 6
0 GND D2- C3N8 Q3B1
7 MCH_CFG_12 1
Place in IMVP_6 ADT7481ARMZ-1 TEMP MON 1000pF . 2N3904
w
Hot Spot . 10%
7481_D2N R3B17 7481_D2N_Q 2
7 MCH_CFG_13 PM_THRM# 5,23,40,43
0
Spare sensor, For
. Amb. temp sensor
Place ADT7481 near Air inlet not under SODIMM
w
R1T12 R1T15 R1T17
2.21K 2.21K 2.21K Design Note: 7481_THRM# R3N23
1% 1% 1% Only one of the CFG10/CFG12/CFG13 straps can be 0
NO_STUFF NO_STUFF NO_STUFF enabled at any time NO_STUFF
w
A A
XOR / ALLZ / Clock Un-gating
MCH_CFG_13 MCH_CFG_12 Configuration
0 0 Reserved
Title
1
0
0
1
XOR Mode Enabled
All-Z Mode Enabled
CANTIGA STRAPPING
1 1 Normal Operation (Default)
MCH_CFG_10 (PCIE Loopback enable) Size Document Number Rev

Low = Enabled
High = Disabled (Default) A 355659 1.0
5 4 3 2 1
5 4 3 2 1
o m
. c
D D
s
M_A_DQ[63:0] 8
it c
J5P1A CON200_DDR2-SODIMM-STAN
8,15 M_A_A[14:0]
M_A_A0 102 M_A_DQ0
M_A_A1 A0 DQ0 5 M_A_DQ1
101 A1 DQ1 7
M_A_A2 100 M_A_DQ2
99 A3 DQ3 19
M_A_A4 98 M_A_DQ4
97 A5 DQ5 6
M_A_A6 94 M_A_DQ6
M_A_A7 A6 DQ6 14 M_A_DQ7 +V1.8_DIMM0 J5P1B CON200_DDR2-SODIMM-STAN
92 A7 DQ7 16
M_A_A8 93 M_A_DQ8
DQ8 23
a
M_A_A9 A8 M_A_DQ9
91 A9 DQ9 25 112 VDD1 VSS16 18
M_A_A10 105 M_A_DQ10
M_A_A11 A10/AP DQ10 35 M_A_DQ11
111 VDD2 VSS17 24
90 A11 DQ11 37 117 VDD3 VSS18 41
M_A_A12 89 M_A_DQ12
M_A_A13 A12 DQ12 20 M_A_DQ13
96 VDD4 VSS19 53
116 A13 DQ13 22 95 VDD5 VSS20 42
M_A_A14 86 M_A_DQ14
A14 DQ14 36 M_A_DQ15
118 VDD6 VSS21 54
84 A15 DQ15 38 81 VDD7 VSS22 59
85 M_A_DQ16
DQ16 43 82 65
m
8,15 M_A_BS2 A16_BA2 VDD8 VSS23
M_A_DQ17 14,15,23,35,55,57 +V3.3M
DQ17 45 M_A_DQ18
87 VDD9 VSS24 60
8,15 M_A_BS0 107 BA0 DQ18 55 103 VDD10 VSS25 66
106 M_A_DQ19
8,15 M_A_BS1 BA1 DQ19 57 M_A_DQ20 R4C1 0.022 +V3.3M_DIMM0
88 VDD11 VSS26 127
7,15 M_CS#0 110 S0# DQ20 44 104 VDD12 VSS27 139
115 M_A_DQ21 C3C7 C4C7
DQ21 46 128
e
7,15 M_CS#1 S1# VSS28
30 M_A_DQ22 To connect TS on DIMM0&1 o/p to H8, 0.1uF 2.2uF
C 7 M_CLK_DDR0 CK0 DQ22 56 M_A_DQ23
199 VDDSPD VSS29 145
C
7 M_CLK_DDR#0 32 CK0# DQ23 58 stuff R5P3 and no-stuff R5P1 .10% 10%
VSS30 165
164 M_A_DQ24 .
7 M_CLK_DDR1 CK1 DQ24 61 M_A_DQ25
83 NC1 VSS31 171
7 M_CLK_DDR#1 166 CK1# DQ25 63 120 NC2 VSS32 172
79 M_A_DQ26
DQ26 73 50 177
h
7,15 M_CKE0 CKE0 7,14 TS#_DIMM0_1 EVENT# VSS33
80 M_A_DQ27
7,15 M_CKE1 CKE1 DQ27 75 M_A_DQ28 +V3.3S
69 NC4 VSS34 187
8,15 M_A_CAS# 113 CAS# DQ28 62 163 NCTEST VSS35 178
108 M_A_DQ29
DQ29 64
8,15 M_A_RAS# 190
RAS# M_A_DQ30 R5P1 10K VSS36
109
DQ30 74
8,15 M_A_WE# 1 9
SA0_DIM0 WE# M_A_DQ31 VREF VSS37
c
198 R5P3
DQ31 76
21
SA1_DIM0 SA0 M_A_DQ32 15,40 PM_EXTTS#0_DIMM0_1 NO_STUFF 0 VSS38
200
DQ32 123
201 33
SA1 M_A_DQ33 GND0 VSS39
197
DQ33 125
14,15,23 SMB_CLK_M2 48 M_VREF_DIMM0 202 155
SCL M_A_DQ34 GND1 VSS40
195
DQ34 135
14,15,23 SMB_DATA_M2 34
Note: SDA M_A_DQ35 C6P2 C6P1 VSS41
DQ35 137
132
s
SO-DIMM0 SPD Address is 0xA0 R3C5 R3C6 M_A_DQ36 0.1uF 2.2uF VSS42
114
DQ36 124
7,15 M_ODT0 47 144
SO-DIMM0 TS Address is 0x30 10K 10K ODT0 M_A_DQ37 VSS1 VSS43
7,15 M_ODT1 119
ODT1 DQ37 126 .10% 10% 133
VSS2 VSS44
156
5% 5% M_A_DQ38 .
DQ38 134
8 M_A_DM[7:0] 183 168
VSS3 VSS45
-
M_A_DM0 10 M_A_DQ39 +V1.8_DIMM0
DQ39 136
. . 77 2
M_A_DM1 DM0 M_A_DQ40 VSS4 VSS46
26
DQ40 141
12 3
52
DQ41 143
48 15
67
DQ42 151
184 27
M_A_DM4 DM3 M_A_DQ43 C4C8 C4C9 C4C10 C5C5 VSS7 VSS49
130
DQ43 153
78 39
DM4 VSS8 VSS50
p
M_A_DM5 147 M_A_DQ44 0.1uF 0.1uF 0.1uF 0.1uF
DQ44 140
71 149
M_A_DM6 DM5 M_A_DQ45 10% 10% 10% 10% VSS9 VSS51
170
DQ45 142
72 161
M_A_DM7 DM6 M_A_DQ46 . . . . VSS10 VSS52
185
DQ46 152
121 28
DM7 M_A_DQ47 VSS11 VSS53
DQ47 154
122 40
8 M_A_DQS[7:0] M_A_DQS0 M_A_DQ48 VSS12 VSS54
13
DQ48 157
196 138
DQS0 VSS13 VSS55
o
M_A_DQS1 31 M_A_DQ49
DQ49 159
193 150
M_A_DQS2 DQS1 M_A_DQ50 VSS14 VSS56
51
DQ50 173
8 162
M_A_DQS3 DQS2 M_A_DQ51 Layout Note: Place these Caps near SO-DIMM0. VSS15 VSS57
70
DQ51 175
t
M_A_DQS4 DQS3 M_A_DQ52
131
M_A_DQS5 DQS4 DQ52 158 M_A_DQ53
148
M_A_DQS6 DQS5 DQ53 160 M_A_DQ54
169
B M_A_DQS7 DQS6 DQ54 174 M_A_DQ55 B
188
8 M_A_DQS#[7:0] M_A_DQS#0 DQS7 DQ55 176 M_A_DQ56
11
DQ56 179
p
M_A_DQS#1 DQS#0 M_A_DQ57
29
M_A_DQS#2 DQS#1 DQ57 181 M_A_DQ58
49
68
129
146
DQS#5 DQ61 182
l. a
M_A_DQS#6 167 M_A_DQ62
186
DQS#7 DQ63 194
Layout Note: Place these Caps near SO-DIMM0.
9,10,14,46,48,55,57 +V1.8
+V1.8_DIMM0
R5C3 0.002
1%
C5C1 C4C13 C5C3 C4C12 C5C4 C4C11

330uF
w
2.2uF 2.2uF 2.2uF 2.2uF 2.2uF
20% 10% 10% 10% 10% 10%
2.5V . . . . .
w w Pillar Rock
Title
Size
A
DDR2 SODIMM 0
Document Number
355659
Intel Confidential
Rev
1.0
A

5 4 3 2 1
5 4 3 2 1
o m
. c
D D
s
M_B_DQ[63:0] 8
J5N1A CON200_DDR2-SODIMM-REV
8,15 M_B_A[14:0]
M_B_A0 102 M_B_DQ0
A0 DQ0 5
it c
M_B_A1 101 M_B_DQ1
M_B_A2 A1 DQ1 7 M_B_DQ2
100
99 A3 DQ3 19
M_B_A4 98 M_B_DQ4
97 A5 DQ5 6
M_B_A6 94 M_B_DQ6 +V1.8_DIMM1 J5N1B CON200_DDR2-SODIMM-REV
92 A7 DQ7 16
M_B_A8 93 M_B_DQ8
112 VDD1 VSS16 18
91 A9 DQ9 25 111 VDD2 VSS17 24
M_B_A10 105 M_B_DQ10
DQ10 35 117 41
a
M_B_A11 A10/AP M_B_DQ11 VDD3 VSS18
90 A11 DQ11 37 96 VDD4 VSS19 53
M_B_A12 89 M_B_DQ12
M_B_A13 A12 DQ12 20 M_B_DQ13
95 VDD5 VSS20 42
116 A13 DQ13 22 118 VDD6 VSS21 54
M_B_A14 86 M_B_DQ14
A14 DQ14 36 M_B_DQ15
81 VDD7 VSS22 59
84 A15 DQ15 38 82 VDD8 VSS23 65
85 M_B_DQ16
8,15 M_B_BS2 A16_BA2 DQ16 43 M_B_DQ17
87 VDD9 VSS24 60
DQ17 45 M_B_DQ18 13,15,23,35,55,57 +V3.3M
103 VDD10 VSS25 66
107 DQ18 55 88 127
m
8,15 M_B_BS0 BA0 VDD11 VSS26
106 M_B_DQ19
8,15 M_B_BS1 BA1 DQ19 57 M_B_DQ20
104 VDD12 VSS27 139
7,15 M_CS#2 110 S0# DQ20 44 VSS28 128
115 M_B_DQ21 R4B23 0.022 +V3.3M_DIMM1
7,15 M_CS#3 S1# DQ21 46 M_B_DQ22
199 VDDSPD VSS29 145
7 M_CLK_DDR3 30 CK0 DQ22 56 VSS30 165
32 M_B_DQ23 C3B8 C3B9
DQ23 58 83 171
e
7 M_CLK_DDR#3 CK0# NC1 VSS31
164 M_B_DQ24 0.1uF 2.2uF
C 7 M_CLK_DDR4 CK1 DQ24 61 M_B_DQ25
120 NC2 VSS32 172
C
7 M_CLK_DDR#4 166 CK1# DQ25 63 .10% 10% 50 EVENT# VSS33 177
13,15,23,35,55,57 +V3.3M 79 M_B_DQ26 .
7,15 M_CKE3 CKE0 DQ26 73 M_B_DQ27
69 NC4 VSS34 187
7,15 M_CKE4 80 CKE1 DQ27 75 163 NCTEST VSS35 178
113 M_B_DQ28
DQ28 62 190
h
8,15 M_B_CAS# CAS# 7,13 TS#_DIMM0_1 VSS36
108 M_B_DQ29
8,15 M_B_RAS# RAS# DQ29 64 M_B_DQ30
48 M_VREF_DIMM1 1 VREF VSS37 9
8,15 M_B_WE# 109 WE# DQ30 74 VSS38 21
SA0_DIM1 198 M_B_DQ31 C6N10 C6N11
DQ31 76
201 33
R3B23 SA1_DIM1 SA0 M_B_DQ32 0.1uF 2.2uF GND0 VSS39
200
DQ32 123
202 155
SA1 M_B_DQ33 GND1 VSS40
c
10K
5% 197 .10% 10%
DQ33 125
13,15,23 SMB_CLK_M2 34
SCL M_B_DQ34 . VSS41
195
DQ34 135
13,15,23 SMB_DATA_M2 132
Note: SDA M_B_DQ35 +V1.8_DIMM1 VSS42
DQ35 137
. 47 144
SO-DIMM1 SPD Address is 0xA4 M_B_DQ36 VSS1 VSS43
114
DQ36 124
7,15 M_ODT2 133 156
SO-DIMM1 TS Address is 0x34 ODT0 M_B_DQ37 VSS2 VSS44
119
DQ37 126
7,15 M_ODT3 183 168
s
ODT1 M_B_DQ38 VSS3 VSS45
DQ38 134
8 M_B_DM[7:0] 77 2
M_B_DM0 M_B_DQ39 C4B22 C4B20 C4B19 C4B23 VSS4 VSS46
10
DQ39 136
12 3
R4B24 M_B_DM1 DM0 M_B_DQ40 0.1uF 0.1uF 0.1uF 0.1uF VSS5 VSS47
26
DQ40 141
48 15
DM1 VSS6 VSS48
-
10K M_B_DM2 52 M_B_DQ41 10% 10% 10% 10%
DQ41 143
184 27
5% M_B_DM3 DM2 M_B_DQ42 . . . . VSS7 VSS49
67
DQ42 151
78 39
M_B_DM4 DM3 M_B_DQ43 VSS8 VSS50
130
DQ43 153
. 71 149
147
DQ44 140
72 161
170
DQ45 142
121 28
DM6 VSS11 VSS53
p
M_B_DM7 185 M_B_DQ46
DQ46 152
122 40
DM7 M_B_DQ47 VSS12 VSS54
DQ47 154
196 138
8 M_B_DQS[7:0] M_B_DQS0 M_B_DQ48 Layout Note: Place these Caps near SO-DIMM1. VSS13 VSS55
13
DQ48 157
193 150
M_B_DQS1 DQS0 M_B_DQ49 VSS14 VSS56
31
DQ49 159
8 162
M_B_DQS2 DQS1 M_B_DQ50 VSS15 VSS57
51
DQS2 DQ50 173
o
M_B_DQS3 70 M_B_DQ51
M_B_DQS4 DQS3 DQ51 175 M_B_DQ52 +V1.8_DIMM1
131
M_B_DQS5 DQS4 DQ52 158 M_B_DQ53 9,10,13,46,48,55,57 +V1.8
148
DQ53 160
t
M_B_DQS6 DQS5 M_B_DQ54
169
M_B_DQS7 DQS6 DQ54 174 M_B_DQ55 R5B6 0.002
188
8 M_B_DQS#[7:0] M_B_DQS#0 DQS7 DQ55 176 M_B_DQ56 1%
11
B M_B_DQS#1 DQS#0 DQ56 179 M_B_DQ57 B
29
M_B_DQS#2 DQS#1 DQ57 181 M_B_DQ58 C5B4 C4B21 C4B18 C5B6 C4B17 C5B5
49
DQ58 189
p
M_B_DQS#3 DQS#2 M_B_DQ59 2.2uF 2.2uF 2.2uF 2.2uF 2.2uF 330uF
68
M_B_DQS#4 DQS#3 DQ59 191 M_B_DQ60 10% 10% 10% 10% 10% 20%
129
M_B_DQS#5 DQS#4 DQ60 180 M_B_DQ61 . . . . .
146
M_B_DQS#6 DQS#5 DQ61 182 M_B_DQ62
167
M_B_DQS#7 DQS#6 DQ62 192 M_B_DQ63
186
DQS#7 DQ63 194
l. a
Layout Note: Place these Caps near SO-DIMM1.
SO-DIMM1 is placed farther from

the GMCH than SO-DIMM0
w w
w
A A
Title
DDR2 SODIMM 1

A 355659 1.0
5 4 3 2 1
5 4 3 2 1
m
+V0.9 46,55
Layout Note:
Place Q5N2 R5C1 56
under DIMM0 On Board DDR2 Thermal Sensor R5C4 56 M_CKE0 7,13
o
R5B4 56 M_CKE1 7,13
R5B7 56 M_CKE3 7,14
M_CKE4 7,14
DDR_THERM1 +V3.3M 13,14,23,35,55,57 R4C22 56
R4C12 56 M_ODT0 7,13
c
R4B34 56 M_ODT1 7,13
2 M_ODT2 7,14
U5P1 R4B22 56
M_ODT3 7,14
.
Q5N2 1 1 8
VDD SCLK SMB_CLK_M2 13,14,23
D 2N3904 R4C13 56
M_A_BS0 8,13 D
DDR_THERM2 2 7 R4C20 56
3 D+ SDATA SMB_DATA_M2 13,14,23 M_A_BS1 8,13
R5C2 56
PM_EXTTS#0_D R5P6 M_A_BS2 8,13
3 6
s
D- ALERT# PM_EXTTS#0_DIMM0_1 13,40
0 R4C9 56
R5P4 PM_EXTTS#1_D NO_STUFF R4C10 56 M_A_WE# 8,13
7 PM_EXTTS#1_R 4 5
0 THERM# GND R4C21 56 M_A_CAS# 8,13
ADM1032AR M_A_RAS# 8,13
it c
. R4B14 56
R4B31 56 M_B_BS0 8,14
Layout Note: M_B_BS1 8,14
Place U5P1 R5B5 56
M_B_BS2 8,14
under DIMM1
R4B15 56
Layout note: Place one cap close to every 2 pullup resistors terminated to +V0.9 R4B21 56 M_B_WE# 8,14
+V0.9 46,55 R4B32 56 M_B_CAS# 8,14
M_B_RAS# 8,14
R4C23 56
R4C11 56 M_CS#0 7,13
a
R4B33 56 M_CS#1 7,13
R4B16 56 M_CS#2 7,14
C4C3 C4C15 C4C1 C4C5 C4B25 C4B16 C4B12 C4B26 C4B27 C4B14 C4C6 C4C4 C4B11 C4C14 M_CS#3 7,14
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% R4C19 56 M_A_A0 M_A_A[14:0] 8,13
. . . . . . . . . . . . . . R4C7 56 M_A_A1
R4C18 56 M_A_A2
R4C6 56 M_A_A3
m
R4C17 56 M_A_A4
C5C6 C4B29 C4B24 C4B15 C4B28 C4C18 C4C17 C4C16 C5B3 C4C2 C5C2 C4B9 C4B10 R4C4 56 M_A_A5
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF R4C16 56 M_A_A6
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% R4C15 56 M_A_A7
. . . . . . . . . . . . . R4C5 56 M_A_A8
e
R4C2 56 M_A_A9
C R4C8 56 M_A_A10 C
R4C14 56 M_A_A11
R4C3 56 M_A_A12
R4C24 56 M_A_A13
h
R5C5 56 M_A_A14
Voltage Buffer Translator for MCH ME JTAG
13,14,23,35,55,57 +V3.3M R4B30 56 M_B_A0 M_B_A[14:0] 8,14
M_B_A1
c
R4B13 56
R4B28 56 M_B_A2
R4B19 56 M_B_A3
R4B29 56 M_B_A4
R6M7 R4B11 56 M_B_A5
s
R6M4 13,14,23,35,55,57
10K +V3.3M R4B27 56 M_B_A6
9,10,35,47,55 +V1.05M 2.37K R4B26 56 M_B_A7
1% . J5A2 R4B12 56 M_B_A8
-
GTL2005_JTAG_DIR1 ME_JTAG_TCK_BUFFER 1 R4B17 56 M_B_A9
ME_JTAG_TMS_BUFFER 2 R4B20 56 M_B_A10
GTL2005_JTAG_REF ME_JTAG_TDI_BUFFER 3 R4B25 56 M_B_A11
. R6A4 C6M7 ME_JTAG_TDO_BUFFER 4 R4B18 56 M_B_A12
MCH_RSVD_10 JTAG_TCK 1K 1K 1K R6A3 C6A1 10K 0.1uF 10K 10K 10K 5 R4B35 56 M_B_A13
p
MCH_RSVD_11 JTAG_TDI 806 0.1uF 20% 6 R5B8 56 M_B_A14
MCH_RSVD_12 JTAG_TDO 1% 20% NO_STUFF NO_STUFF
MCH_RSVD_13 JTAG_TMS RJ-11_JACK_Vertical-Mount
. . .
R6M9
R6M5
R6M3
R6A6
R6A5
R6A2
.
U6M1
o
1 14
R6M8 100 MCH_TDI_R DIR VCC ME_JTAG_TDI_BUFFER
2 13
7 MCH_TDI R6M6 100 MCH_TCK_R A0 B0 ME_JTAG_TCK_BUFFER
3 12
t
7 MCH_TCK A1 B1
4 11
R6M2 100 MCH_TMS_R GTLREF GND3 ME_JTAG_TMS_BUFFER
5 10
7 MCH_TMS TP_GTL2005_JTAG_A3 A2 B2 GTL2005_JTAG_B3 R6M1
6 9
B 7
A3 B3
8 1K B
GND1 GND2 R6A19 R6A18 R6A17 5%
.
p
GTL2005
10K 10K 10K NO_STUFF
5% 5% 5%
13,14,23,35,55,57 +V3.3M
l. a
R6A13 13,14,23,35,55,57 +V3.3M
R6A8 10K
3.24K NO_STUFF
1%
.
GTL2005_JTAG_DIR2 C6M2
GTL2005_JTAG_REF2 0.1uF
20%
R6A12 R6M12
w
R6M10 C6M5 10K 10K
1K 0.1uF
5%
. . NO_STUFF
U6M2
1 14
DIR VCC ME_JTAG_TDO_BUFFER_R R6M11 22 ME_JTAG_TDO_BUFFER
2 13
w
7 MCH_TDO A0 B0
GTL2005_JTAG_A1 3 12 TP_GTL2005_JTAG_B1
A1 B1
4 11
GTL2005_JTAG_A2 GTLREF GND3 TP_GTL2005_JTAG_B2
5 10
GTL2005_JTAG_A3 A2 B2 TP_GTL2005_JTAG_B3
6 9
A3 B3
22.1K
7 8 C6M6
GND1 GND2
1K
1K
1K
220PF
GTL2005
w
A 5% 5% 5% A
R6A10
R6A11
. . .
R6A9
R6A7
Title
DDR2 TERMINATION, THERMAL SENSOR AND ME JTAG

A 355659 1.0
5 4 3 2 1
5 4 3 2 1
5,7,10,12,13,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57 +V3.3S
m
C2N3
0.1uF
20%
+V3.3S
8
U2M2
VP
c
R6T5 CRT_L2_RED 1 10
10K CRT_L2_BLUE I/O1 I/O8
2 9
I/O2 I/O7
.
CRT_L2_GREEN 3 7
I/O3 I/O6
D NO_STUFF CRT_Q_HSYNC 4
I/O4 I/O5
6 CRT_Q_VSYNC D
R6T3 DOCK_CRT_EN#_R
s
41 DOCK_CRT_EN#
0
VN
.
ESD DIODE ARRAY
5
it c
R6T4
1K
NO_STUFF
a
5,11,12,17,18,24,28,30,31,32,39,48,49,52,55,56,57 +V5S
19,27,30,31,55,57 +VBATS +V5S_F_DAC

F2A1
+1 2
m
+V3.3S R2N1 1.1A
1K
2
DDC_GATE1
Q2A1
e
U6E4 R2N2 BSS138
C DOCK_CRT_EN#_R 12 SEL VDD1 1 100K C
4 Note:
3
VDD2 For video bandwidths > 200MHz:
7 CRT_RED 2 Y_A VDD3 9
5 19 C3B1, C3A4, C2B1, C2A5, C2B2, C2N1 = 3.3pF
h
7 CRT_GREEN Y_B VDD4 C3M3, C2A4, C2A6 = No_Stuff
6 FB2M1
7 CRT_BLUE Y_C FB3A1, FB2A4, FB2B1 = Short
8 24 50OHM
7 CRT_VSYNC Y_D I_A0 CRT_RED_DOCK 44
7 CRT_HSYNC 11 22 CRT_GRN_DOCK 44
Y_E I_B0
18 CRT_BLUE_DOCK 44
I_C0 DDC_SRC
c
3 17 CRT_VSYNC_DOCK 44
GND1 I_D0
+V5S_L_DAC
7 14 CRT_HSYNC_DOCK 44
GND2 I_E0
10
GND3 CRT_Q_RED R2M3 R2M4
20 23
GND4 I_A1 CRT_Q_GREEN 2.2K 2.2K
21
-s
I_B1 CRT_Q_BLUE . .
16
I_C1 CRT_Q_VSYNC
15
I_D1 CRT_Q_HSYNC
13
I_E1
CRT_DDC_DATA_ISO
PI3V512QE
CRT_DDC_CLK_ISO
1
p
CR2N1 CR2M1
+V3.3S
FB3B1 FB3A1
CRT_Q_RED CRT_L_RED
2
Clamping-Diode Clamping-Diode
47ohm@100MHz
o
C3B1 C3A4 47ohm@100MHz C3M3
C6E9 C6T5 C6T6 C6T7 R3B1 10pF 22pF 10pF
0.1uF 0.1uF 0.1uF 0.1uF 150 5% 5% 5%
t
20% 20% 20% 20% 1% . . . J2A2B
GND1 19
CRT_L2_RED RED 14 24 NC2
B FB3B2 FB2A4 GND2 18 B
5,7,10,12,13,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57 +V3.3S CRT_Q_GREEN CRT_L_GREEN CRT_L2_GREEN GRN 13 23 DATA
p
GND3 17
47ohm@100MHz BLU
R3B2 C2B1 C2A5 47ohm@100MHz C2A4 CRT_L2_BLUE 12 22 HSYNC
150 10pF 22pF 10pF VCC 16
1% NC1
5% 5% 5% 11 21 VSYNC
C6T3 . . . GND4 15
l. a
0.1uF GND5 10 20 CLK
20% FB2B2 FB2B1
5 CRT_Q_BLUE CRT_L_BLUE 2IN1
U6T1
47ohm@100MHz
R2B1 C2B2 C2N1 47ohm@100MHz C2A6
DOCK_CRT_EN#_R 2 4 CRT_EN# 150 10pF 22pF 10pF
1% 5% 5% 5%
5,11,12,17,18,24,28,30,31,32,39,48,49,52,55,56,57 +V5S . . .
INVERTER
+V3.3S 3
w
CRT_Q_VSYNC
R6T1
2.2K C6T2
U6E1 0.1uF CRT_Q_HSYNC
1 8 20%
1OE# VCC C3M4 C3M5
7 CRT_DDC_DATA_MCH 2 7
1A 2OE# CRT_DDC_DATA_ISO 33pF 33pF
3 6
w
44 CRT_DDC_DATA_DOCK 1B 2B
4 5 5% 5%
GND 2A NO_STUFF NO_STUFF
SN74CBTD3306C
+V3.3S
5,11,12,17,18,24,28,30,31,32,39,48,49,52,55,56,57 +V5S
w
A R6T2 A
2.2K C6T4 Pillar Rock Intel Confidential
U6E3 0.1uF
1 1OE# VCC 8 20% Title
7 CRT_DDC_CLK_MCH 2 1A 2OE# 7
3 1B 2B 6 CRT_DDC_CLK_ISO CRT
4 GND 2A 5
SN74CBTD3306C
44 CRT_DDC_CLK_DOCK
A 355659 1.0
5 4 3 2 1
5 4 3 2 1
m
5,7,10,12,13,16,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57 +V3.3S
o
5,11,12,16,18,24,28,30,31,32,39,48,49,52,55,56,57 +V5S 49,53,55,56,57 +VBAT
+V3.3S_LVDS_DDC +VCC_LVDS_BKLT
R6U19 R6F15
R6U20 0.002 0.002
c
0.002 +V5S_LVDS_BKLT 1% 1%
1%
.
D D
C6U9 C6F6
s
C6U10 0.1uF 0.1uF
0.1uF 20% 10%
20%
it c
a
5,7,10,12,13,16,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57 +V3.3S 5,7,10,12,13,16,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57 +V3.3S
5,11,12,16,18,24,28,30,31,32,39,48,49,52,55,56,57 +V5S +V3.3S
m
C6U2
0.1uF
C7T19 20% +VCC_LVDS_BKLT
0.1uF R7U2
U7E6 20% 10K R6U15
e
LVDS Panel Backlight 5% 10K
38 L_BKLTSEL0# 1 OE1# VCC 8 5%
C BIOS Note: Disable both BKLTSEL
7 L_BKLT_CTRL 2 1A OE2# 7 L_BKLTSEL1# 38
C
lines before enabling one. 3 6 U6F1
1B 2B L_BKLTSEL1#
4 GND 2A 5 L_CTRL_DATA 7,20 1 OE# VCC 5
GMCH_PWM Support +V5S_LVDS_BKLT
h
74CBT3306 7,20 L_CTRL_CLK 2 J6F1
GM_Data_D Support A
1 VDD_BLI
3 4 2
GM_CLK_D Support GND Y VSS_BLI
3
VSS_DBC
c
74CBTLV1G125 4
DBL_CLK VDD_DBC
5
L_BRIGHTNESS DBL_CLK
6
DBL_DATA
7 L_BKLT_EN 7
5,7,10,12,13,16,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57 +V3.3S R6U18 ENA_BL
8
s
100K NC1
9
5,7,10,12,13,16,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57 +V3.3S VDD_ALS
10
VSS_ALS
40 ALS_CLK 11
ALS_CLK
-
40 ALS_DATA 12
ALS_DATA
40 ALS_INTR# 13
For 2.5V panel support, connect an external ALS_INTR
14
NC2
source to net TP_+V2.5. 15
VSS_VDL
R6U25 R6U24 +V3.3S_LVDS_DDC +VDD_VDL_L 16
2.2K 2.2K VDD_VDL1
p
5% 5% 17
VDD_VDL2
18
VDD_VCL
19
RSVD
7 LVDS_DDC_CLK 20
VCL_CLK
7 LVDS_DDC_DATA 21
VCL_DATA
to
7 LVDSA_DATA#0 22
A0M
7 LVDSA_DATA0 23
A0P
24
VSS_SHIELD1
7 LVDSA_DATA#1 25
A1M
7 LVDSA_DATA1 26
5,11,12,16,18,24,28,30,31,32,39,48,49,52,55,56,57 +V5S A1P
27
B 28
VSS_SHIELD2 B
7 LVDSA_DATA#2 A2M
29
p
7 LVDSA_DATA2 A2P
30
VSS_SHIELD3
1
7 LVDSA_DATA#3 31
R6U26 A3M
7 LVDSA_DATA3 32
0.002 A3P
33
+V3.3S VSS_SHIELD4
7 LVDSA_CLK# 34
VDL_CLKAM
la
NO_STUFF NO_STUFF TP6G1 NO_STUFF 35
7 LVDSA_CLK
2
R6V2 0.002 TP_+V2.5 VDL_CLKAP

1 2 36
VSS
1% 0.002 37
7 LVDSB_DATA#0 B0M
R6V4 38
7 LVDSB_DATA0 B0P
39
SI2307DS
.
VSS_SHIELD5
7 LVDSB_DATA#1 40
Q6U3 B1M
7 LVDSB_DATA1 41
B1P
42
+VDD_VDL +VDD_VDL_L VSS_SHIELD6
2 3 7 LVDSB_DATA#2 43
B2M
7 LVDSB_DATA2 44
C6V1 C6F5 C6U1 B2P
45
VSS_SHIELD7
w
R6U28 1000pF 22UF 0.1uF 46
7 LVDSB_DATA#3 B3M
1M 10% 20% 47
7 LVDSB_DATA3
1
B3P
+VDD_VDL STRAPPING 48
VSS_SHIELD8
R6U23 100K L_VDDEN_D# 49
7 LVDSB_CLK# VDL_CLKBM
L_VDDEN#
+V3.3S STUFF R6V2 50

(DEFAULT) NO_STUFF R6U26, R6V4 7 LVDSB_CLK VDL_CLKBP
LVDS,CONN50
w
+V5S STUFF R6U26
NO_STUFF R6V2, R6V4
3
TP_+V2.5 STUFF R6V4

NO_STUFF R6V2, R6U26 Q6F2
BSS138
w
1
A 7 LVDS_VDD_EN A
2
R6V1
Title
100K LVDS

A 355659 1.0
5 4 3 2 1
5 4 3 2 1
Port Value Voltage
m
IO2 IO1 IO0 Format Aspect Ratio Line1 Line2 Line3
0 0 0b 525i (480) 4:3 0V 0V 0V
0 0 1b 525i (480) 16:9 0V 0V 5V
0 0 Xb 525i (480) 4:3 Letterbox 0V 0V 2.2V
0 1 0b 525p (480) 4:3 0V 5V 0V
o
0 1 1b 525p (480) 16:9 0V 5V 5V
0 1 Xb 525p (480) 4:3 Letterbox 0V 5V 2.2V
X 1 0b 750p (720) 4:3 2.2V 5V 0V
X 1 1b 750p (720) 16:9 2.2V 5V 5V
Layout Note: 1 0 0b 1125i (1080) 4:3 5V 0V 0V
c
Place 150 Ohm termination 1 0 1b 1125i (1080) 16:9 5V 0V 5V
5,7,10,12,13,16,17,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57 +V3.3S resistors, ferrite beads and 1 1 0b 1125p (1080) 4:3 5V 5V 0V
.
capicators close to 1 1 1b 1125p (1080) 16:9 5V 5V 5V
connector
D D
5,7,10,12,13,16,17,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57 +V3.3S
U6B1 C2M1
s
12 1 FB2A2 0.1uF
41 DOCK_TV_EN# SEL VDD1
4 DACA DACA_L 20%
VDD2
7 TVA_DAC 2 9
Y_A VDD3
8
5 19 C1A3 150ohm@100MHz C1A1 U2M1
Y_B VDD4
it c
6 R1M2 5.6pF 5.6pF
VP
7 TVB_DAC Y_C 150
8 24 8.9% 8.9%
TV_DACA_OUT_DOCK 44
2
Y_D I_A0 1% . .
7 TVC_DAC 11 Y_E I_B0 22
I_C0 18 TV_DACB_OUT_DOCK 44
3 GND1 I_D0 17
7 14 DACA_L 1 10
GND2 I_E0 TV_DACC_OUT_DOCK 44 I/O1 I/O8
10 DACB_L 2 9
GND3 DACA DACC_L I/O2 I/O7
20 GND4 I_A1 23 3 I/O3 I/O6 7
21 FB2A1 4 6
I_B1 DACB DACB DACB_L I/O4 I/O5
16
a
I_C1
I_D1 15
1
13 DACC C2A3 150ohm@100MHz C2A1
I_E1 R2M2 5.6pF 5.6pF
150 8.9% 8.9% Note:
VN
2
2
PI3V512QE 1% . . ESD Diode Array for the TV
ESD DIODE ARRAY DAC A, DAC B, DAC C signals
5
located on CRT page.
m
+V3.3S FB1A1
DACC DACC_L
e
1
1
C1A4 150ohm@100MHz C1A2
C R1M1 5.6pF 5.6pF J2A1 C
C6N8 C6N6 C6N4 C6N5 150 8.9% 8.9% 1 8
2
0.1uF 0.1uF 0.1uF 0.1uF 1% . . 2 9
20% 20% 20% 20% 3 10 Note:
h
4 11 Pins 12 & 14 are shorted
5 12 inside D-Connector plug.
6 13
7 14
c
CON14_DCONN-CP4120 5,11,12,16,17,24,28,30,31,32,39,48,49,52,55,56,57 +V5S
C2M2
5,11,12,16,17,24,28,30,31,32,39,48,49,52,55,56,57 +V5S 0.1uF
5,11,12,16,17,24,28,30,31,32,39,48,49,52,55,56,57 +V5S 20%
-s
8
U2A2
VP
C2A2
R2A6 1.0uF
10K 10% R2A1 R2A7
1% 5.90K 5.90K 1 10
I/O1 I/O8 DLINE1_IO
p
2 9
I/O2 I/O7 DLINE2_IO
3 7
U2A1 I/O3 I/O6 DLINE3_IO
4 6
R2A2 10K DLINE3 I/O4 I/O5
10 1
I2C_RST#
TV_DCONSEL1_LVL VDD IO_0 R2A4 10K DLINE2

9 2
SDA IO_1
o
TV_DCONSEL0_LVL 8 3 R2M1 10K DLINE1
SCL IO_2
7 4
INT# IO_3
VN
6 5
t
RESET# VSS DLINE3_IO
DLINE2_IO
I2C - PCA9537 ESD DIODE ARRAY
DLINE1_IO
5
R2A3 R2A5
B 4.7K 4.7K B
5,7,10,12,13,16,17,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57 +V3.3S
p
C6T1
0.1uF
l. a
+V3.3S 20%
5 TV-OUT DAC Channel Definition

R6D7 U6R1 Composite Video S-Video Component Video
2.2K Channel A (DACA) CVBS Signal X Chrominance (Pb)
5% DOCK_TV_EN# 2 4 TV_EN# +V5S Channel B(DACB) X Luminance (Y) Luminance (Y)
Channel C (DACC) X Chrominance (C) Chrominance (Pr)
7 TV_DCONSEL1_MCH
INVERTER
3
.
w
R6D6
2.2K
5% C6R1
U6D2 0.1uF
1 8 20%
1OE# VCC
2 7
1A 2OE# TV_DCONSEL1_LVL
3 6
w
44 TV_DCONSEL1_DOCK 1B 2B
4 5
GND 2A +V5S
SN74CBTD3306C
+V3.3S
.
R6D4
w
A R6D5 2.2K A
2.2K 5% Pillar Rock Intel Confidential
5% U6D1 C6D8
1 1OE# VCC 8 0.1uF
20%
Title
7 TV_DCONSEL0_MCH 2 1A 2OE# 7
44 TV_DCONSEL0_DOCK
3 1B 2B 6 TV_DCONSEL0_LVL TV
4 GND 2A 5
SN74CBTD3306C
A 355659 1.0
5 4 3 2 1
5 4 3 2 1
+VBATS_PEG
o m
c
+VBATS_PEG +V3.3S_PEG 23
J6B2
.
23 +V3.3S_PEG
D B1
+12V1 PRSNT1#
A1 DDPC_CTRLCLK 7 D
B2 A2
+12V2 +12V4
B3 A3
+12V3 +12V5
B4 A4
s
GND1 GND6
23,43 SMB_CLK_S4 B5 A5
SMCLK JTAG2 R6N8
23,43 SMB_DATA_S4 B6 A6 PLT_GATED_RST# 41
SMDAT JTAG3 0
B7 A7
21,23,24,25,26,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57 +V3.3A GND2 JTAG4
B8 A8
+3.3V1 JTAG5
it c
B9 A9 NO_STUFF
JTAG1 +3.3V2
B10 A10
3.3VAUX +3.3V3 PEG_SLT_RST# R6N7
23,25,26,44 PCIE_WAKE# B11 WAKE# PWRGD A11 PLT_RST# 7,22,25,26,38,41,57
0
Key
B12 RSVD2 GND7 A12 .
PEG_RSVD2 C6C3
7 PEG_TX[15:0] B13 GND3 REFCLK+ A13 CLK_PCIE_PEG 35 PEG_SLT_RST#
PEG_TX15 0.1uFC6C2 PEG_C_TX15 B14 A14
7 PEG_TX#[15:0] HSOP_0 REFCLK- CLK_PCIE_PEG# 35
PEG_TX#15 10% 0.1uF PEG_C_TX#15 B15 A15
HSON_0 GND8 PEG_RX[15:0] 7
. 10% B16 A16 PEG_RX15
PEG_RX#[15:0] 7
a
. GND4 HSIP_0 PEG_RX#15
7 SDVO_CTRLCLK B17 PRSNT2# HSIN_0 A17
C6C5 B18 A18
PEG_TX14 0.1uFC6C4 PEG_C_TX14 GND5 GND9
B19 HSOP_1 RSVD5 A19 PEG_RSVD5
. 10% HSON_1 GND16 PEG_RX14
B21 GND10 HSIP_1 A21
C6C7. B22 A22 PEG_RX#14
PEG_TX13 0.1uFC6C6 PEG_C_TX13 GND11 HSIN_1
B23 HSOP_2 GND17 A23
m
C6C9. B26 A26 PEG_RX#13
PEG_TX12 0.1uFC6C8 PEG_C_TX12 GND13 HSIN_2
B27 HSOP_3 GND19 A27
B29 A29
e
B30 RSVD3 HSIN_3 A30
C PEG_RSVD3 C
7 SDVO_CTRLDATA B31 PRSNT2#1 GND21 A31
C6C11 B32 A32
PEG_TX11 0.1uFC6C10 PEG_C_TX11 GND15 RSVD6
B33 HSOP_4 RSVD7 A33
h
C6C14. B36 A36 PEG_RX#11
PEG_TX10 0.1uFC6C13 PEG_C_TX10 GND23 HSIN_4 55,57 +VBAT_S4
B37 A37
PEG_TX#10 10% 0.1uF PEG_C_TX#10 HSOP_5 GND31
B38 A38
HSON_5 GND32 PEG_RX10
c
. 10% B39 A39 16,27,30,31,55,57 +VBATS
C6D2. GND24 HSIP_5 PEG_RX#10
B40 A40
PEG_TX9 0.1uFC6D1 PEG_C_TX9 GND25 HSIN_5
B41 A41
B42 A42
. 10% HSON_6 GND34 PEG_RX9 R6N9 R6N6
B43 A43
s
C6D5. GND26 HSIP_6 PEG_RX#9 0.002 0.002
B44 A44
PEG_TX8 0.1uFC6D4 PEG_C_TX8 GND27 HSIN_6 +VBATS_PEG 1% 1%
B45 A45
B46 A46 NO_STUFF
HSON_7 GND36
-
. 10% B47 A47 PEG_RX8
7,12 MCH_CFG_20 B48 A48
C6D7 PRSNT2#2 HSIN_7
B49 A49
PEG_TX7 0.1uFC6D6 PEG_C_TX7 GND29 GND37 C6B5 C6N9
B50 A50
PEG_TX#7 10% 0.1uF PEG_C_TX#7 HSOP_8 RSVD8 C6B6 C6A4 C6B1 C6B3 0.1uF 0.1uF
B51 A51
HSON_8 GND54
p
. 10% B52 A52 PEG_RX7 22UF 22UF 22UF 22UF 10% 10%
C6D10. GND38 HSIP_8 PEG_RX#7 . .
B53 A53
B54 A54
B55 A55
B56 A56
GND40 HSIP_9
to
C6D11. B57 A57 PEG_RX#6
B58 A58
PEG_TX#5 10% 0.1uF PEG_C_TX#5 HSOP_10 GND57 27,32,39,41,42,43,55,57 +V3.3
B59 A59
. 10% HSON_10 GND58 PEG_RX5 5,7,10,12,13,16,17,18,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57 +V3.3S
B60 A60
C6D14. GND42 HSIP_10 PEG_RX#5
B61 A61
GND43 HSIN_10
1
PEG_TX4 0.1uFC6D13 PEG_C_TX4 B62 A62
B PEG_TX#4 10% 0.1uF PEG_C_TX#4 B63
HSOP_11 GND59
A63 For D3 HOT/ D3 ON: R6C1 R6P2 B
. 10% HSON_11 GND60 PEG_RX4 Stuff R6N5, R6P2, and R6N7, 0.002
B64 A64 0.002
p
C6E2. GND44 HSIP_11 PEG_RX#4 unstuff R6N9, R6C1 and R6N6. 23 +V3.3S_PEG 1%
B65 A65 .
PEG_TX3 0.1uFC6E1 PEG_C_TX3 GND45 HSIN_11
B66 A66 NO_STUFF
2
B67 A67
B68 A68
GND46 HSIP_12
1
C6E4. B69 A69 PEG_RX#3 + C6B9 C6B8
GND47 HSIN_12
la
PEG_TX2 0.1uFC6E3 PEG_C_TX2 B70 A70 C6B11 0.1uF 0.1uF
PEG_TX#2 10% 0.1uF PEG_C_TX#2 HSOP_13 GND63 100uF 10% 10%
B71 A71
2
. 10% HSON_13 GND64 PEG_RX2 . .
B72 A72
C6E6. GND48 HSIP_13 PEG_RX#2
B73 A73
PEG_TX1 0.1uFC6E5 PEG_C_TX1 GND49 HSIN_13
B74 A74
.
B75 A75
B76 A76
C6E7. GND50 HSIP_14 PEG_RX#1
B77 A77
PEG_TX0 0.1uFC6E8 PEG_C_TX0 GND51 HSIN_14 21,23,24,25,26,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57 +V3.3A
B78 A78
B79 A79
B80 A80
GND52 HSIP_15
w
. B81 A81 PEG_RX#0
7 DDPC_CTRLDATA PRSNT2#3 HSIN_15
B82 A82 C6B12
PEG_RSVD4 RSVD4 GND69 C6C1 0.1uF
PCIE_X16 22uF 10%
.
w w Pillar Rock
Title
Size
A
PCIE GRAPHICS
Document Number
355659
Intel Confidential
Rev
1.0
A

5 4 3 2 1
5 4 3 2 1
o m
. c
D D
it c s
a
m
XDP
e
C 3 XDP_BPM#5
C
J1F1
3 XDP_BPM#4
1 2
h
GND0 GND1
3 OBSFN_A0 OBSFN_C0 4 XDP_OBS8
5 OBSFN_A1 OBSFN_C1 6 XDP_OBS9
7 8
GND2 GND3 Layout note: R2U5 should
35 XDP_OBS0 9 10 XDP_OBS10
OBSDATA_A0 OBSDATA_C0 connect to H_CPURST# with
c
OBSDATA_A1 OBSDATA_C1 no stub.
13 14
GND4 GND5
R1U1 XDP_OBS3_R OBSDATA_A2 OBSDATA_C2
XDP_OBS3 17 18 XDP_OBS13
0 OBSDATA_A3 OBSDATA_C3
19 20
-s
R1U2 GND6 GND7 3,4,35,39,43,52,54 +V1.05S_CPU +V3.3S
3 XDP_BPM#0 21 22
3,4,35,39,43,52,54 +V1.05S_CPU 0 OBSFN_B0 OBSFN_D0
NO_STUFF 23 24
OBSFN_B1 OBSFN_D1 R1T5
25 26
GND8 GND9 1K
XDP_OBS4. 27 28 XDP_OBS14
OBSDATA_B0 OBSDATA_D0 C1T4
R1T1 OBSDATA_B1 OBSDATA_D1 0.1uF 5% .
31 32
54.9 GND10 GND11 10%
1% OBSDATA_B2 OBSDATA_D2 . R1T4
OBSDATA_B3 OBSDATA_D3
p
37 38 54.9
GND12 GND13 1%
3 H_PWRGD_XDP 39 40 CLK_XDP 35
PWRGOOD/HOOK0 ITPCLK/HOOK4
XDP_OBS20 41 42 CLK_XDP# 35
HOOK1 ITPCLK#/HOOK5
43 44
VCC_OBS_AB VCC_OBS_CD RST_SNS1 R2U5
35 CLK_PCIE_XDP_3GPLL 45 46 H_CPURST# 3,6
HOOK2 RESET#/HOOK6
o
C1T3 47 48 5% 100
35 CLK_PCIE_XDP_3GPLL# HOOK3 DBR#/HOOK7 XDP_DBRESET# 3
0.1uF 49 50
10% GND14 GND15
51 52
t
7,17 L_CTRL_DATA SDA TDO . XDP_TDO 3
. 53 54
7,17 L_CTRL_CLK SCL TRSTN XDP_TRST# 3
55 56 XDP_TDI 3
TCK1 TDI
3 XDP_TCK 57 58 XDP_TMS 3
B 59
TCK0 TMS
60 B
GND16 GND17
p
CONN60_ITP-XDP
l. a
CAD NOTE:
Place the XDP connector on the
primary side of the CRB and place
all components near the
connector.
w w
w
A A
Title
XDP

A 355659 1.0
5 4 3 2 1
5 4 3 2 1
+V3.3A
24 +V3.3A_RTC
m
CR5H1
RTC_RST# 41
1 3
C5W2
BAT54 1uF CMOS Settings J5H2
RTC Circuitry 80% Clear CMOS Shunt
o
Keep CMOS Open
CR5H2 C7F2
BAT_D 1 3 R5W4 20K 10pF
1
BAT54 C5H3 J5H2
c
R5G10 20K 1uF Y7F1 R7U4
R5W5 32.7680KHZ 10M
2
.
1K C5G6 J5G1
1
D 1uF Cap values depend on Xtal D
4
BAT
R5W3 C7F1 U7F1A
1
1M 10pF RTC_X1 C23 K5 24 +V1.05S_ICH_IO
s
RTCX1 FWH0/LAD0 LPC_AD0 38,40,43
1
RTC_X2 C24 K4
J5G1 RTCX2 FWH1/LAD1 LPC_AD1 38,40,43
TPM Settings L6
Clear ME RTC registers Shunt FWH2/LAD2 LPC_AD2 38,40,43
RTC_RST# A25 K2
RTCRST# FWH3/LAD3 LPC_AD3 38,40,43
NO_STUFF
NO_STUFF
Keep ME RTC registers Open
RTC
LPC
BT5H1 SRTC_RST# F20
SRTCRST#
it c
Battery_Holder SM_INTRUDER# C22 K3 R6V5 R7V18 24 +V1.05S_ICH_IO
INTRUDER# FWH4/LFRAME# LPC_FRAME# 38,40,43
56 56
ICH_INTVRMEN B22 J3
INTVRMEN LDRQ0# ICH_DRQ#0 38
A22 J1 ICH_DRQ#1 38
3
LAN100_SLP LDRQ1#/GPIO23
E25 N7 R7V15
33 GLAN_CLK GLAN_CLK A20GATE H_A20GATE 40,43 56
+V3.3S AJ27
A20M# H_A20M# 3
33 LAN_RSTSYNC C13 LAN_RSTSYNC
DPRSTP# AJ25 H_DPRSTP#_R R7V10 0
H_DPRSTP# 3,7,43
F14 AE23 H_DPSLP#_R R6V6 0
LAN / GLAN
33 LAN_RXD0 LAN_RXD0 DPSLP# H_DPSLP# 3,43
a
33 LAN_RXD1 G13 LAN_RXD1
C7H3 D14 AJ26 . H_FERR#_R R7V9 56
33 LAN_RXD2 LAN_RXD2 FERR# H_FERR# 3
R7H7 0.1uF SMC0402 22,24 +V1.5S_PCIE_ICH .
330 10% D13 AD22
33 LAN_TXD0 LAN_TXD0 CPUPWRGD H_PWRGD 3,43
. D12
33 LAN_TXD1 LAN_TXD1
R7H14 E13 AF25
LED_R 33 LAN_TXD2 LAN_TXD2 IGNNE# H_IGNNE# 3
CPU
10K
R6F10 ICH_GPIO56 B10 AE22 24 +V1.05S_ICH_IO
m
GPIO56 INIT# H_INIT# 3
2
CR7H1 . 24.9 AG25

1% INTR H_INTR 3
GREEN . B28 L3
GLAN_COMP GLAN_COMPI RCIN# H_RCIN# 40,43
B27 GLAN_COMPO
5
NMI AF23 H_NMI 3,43

1 ICH_SATA_LED# AF6 AF24 H_SMI#_R R6V9 R6V7
e
7,27 HDA_BIT_CLK H_SMI# 3,43
1
HDA_BIT_CLK SMI# 0 56
56 SATA_LED# 4 7,27 HDA_SYNC AH4 HDA_SYNC
C 2 AH27 H_STPCLK# 3,43
C
. STPCLK#
7,27 HDA_RST# AE7 HDA_RST# .
74AHC1G08 AG26 H_THERMTRIP_R R6V8 54.9
3
THRMTRIP# 1% PM_THRMTRIP# 3,7

U7H1 AF4
h
27 HDA_SDIN0 HDA_SDIN0 Layout note: R6V7 needs to
27 HDA_SDIN1 AG4 HDA_SDIN1 TP12 AG27 ICH_TP8 placed within 2" of ICH9-M,
IHDA
27 HDA_SDIN2 AH3 HDA_SDIN2
AE5 . R6V8 must be placed within 2"
7,27 HDA_SDIN3 HDA_SDIN3 of R6V7 w/o stub.
0 AH11 SATA_RXN4_C C7H1 0.01uF
SATA4RXN SATA_RXN4 31
NO_STUFF R7H8 AJ11 SATA_RXP4_C C7H2 . 0.01uF
c
7,27 HDA_SDOUT AG5
HDA_SDOUT SATA4RXP SATA_RXP4 31
AG12 SATA_TXN4_C C7G9 0.01uF
.
SATA_TXN4 31
SATA4TXN
27,41 HDA_DOCK_EN# AG7 AF12 SATA_TXP4_C C7G8 . 0.01uF
SATA_TXP4 31
HDA_DOCK_EN#/GPIO33 SATA4TXP
27,44 HDA_DOCK_RST# AE8
HDA_DOCK_RST#/GPIO34 SATA_RXN5_C
AH9
SATA5RXN
s
ICH_SATA_LED# AG8 AJ9 SATA_RXP5_C C7W2 0.01uF NO_STUFF
SATALED# SATA5RXP SATA_TXN5_C C7W3 0.01uF NO_STUFF SATA_RXN4_DOCK 44
AE10
C7V17 0.01uF SATA_RXN0_C SATA5TXN SATA_TXP5_C C7V13 0.01uF NO_STUFF SATA_RXP4_DOCK 44
30 SATA_RXN0 AJ16 AF10 SATA_TXN4_DOCK 44
SATA0RXN SATA5TXP
-
C7V18 . 0.01uF SATA_RXP0_C AH16 C7V14 0.01uF NO_STUFF
SATA
30 SATA_RXP0 SATA0RXP SATA_TXP4_DOCK 44
C7V16 . 0.01uF SATA_TXN0_C AF17 AH18
30 SATA_TXN0 SATA0TXN SATA_CLKN CLK_PCIE_SATA# 35
C7V15 . 0.01uF SATA_TXP0_C AG17 AJ18
30 SATA_TXP0 SATA0TXP SATA_CLKP CLK_PCIE_SATA 35
C7V22 0.01uF SATA_RXN1_C AH13 AJ7 SATA_RBIAS_PN
31 SATA_RXN1 SATA1RXN SATARBIAS#
p
C7V21 . 0.01uF SATA_RXP1_C AJ13 AH7
31 SATA_RXP1 SATA1RXP SATARBIAS Layout Note:
C7V19 . 0.01uF SATA_TXN1_C AG14
31 SATA_TXN1 SATA1TXN Short pins AJ7, AH7 and place
C7V20 . 0.01uF SATA_TXP1_C AF14 R7G8
31 SATA_TXP1 SATA1TXP 24.9 R7G1 within 500 mils from them.
ICH9M REV 1.0 1%
.
Distance between the ICH9-M and
to
cap on the "P" signal should be
identical distance between the
ICH9-M and cap on the "N"
signal for same pair.
B SATA_RXN5_C C7H12 0.01uF B

SATA_RXP5_C C7H13 . 0.01uF SATA_RXN5 30 5,7,10,12,13,16,17,18,19,20,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57 +V3.3S
SATA_RXP5 30
p
SATA_TXN5_C C7H11 . 0.01uF
SATA_TXN5 30
SATA_TXP5_C C7H10 . 0.01uF
SATA_TXP5 30
19,23,24,25,26,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57 +V3.3A
H_RCIN# R8U6 10K
la
.
R8U1
10K 24,27,28 +V3.3S_1.5S_HDA_IO
5%
.
ICH_GPIO56
R7G13 XOR Chain Entrance Strap - to be updated
1K ICH_TP3 HDA_SDOUT Description
NO_STUFF 0 0 RSVD
0 1 Enter XOR Chain
1 0 Normal Operation (Default)
w
HDA_SDOUT 1 1 Set PCIE port config bit 1
ICH_TP3 23
R7H18
24 +V3.3A_RTC 1K
w
NO_STUFF
Internal VRM enabled for VccSus1_05, VccSus1_5,
VccCL1_5, VccLAN1_05 and VccCL1_05
R7U8
332K
1%
w
A A
ICH_INTVRMEN
Title
ICH9M (1 of 4)

A 355659 1.0

5 4 3 2 1
5 4 3 2 1
NO_STUFF
R6U29 0
44 PCIE_RXN1_DOCK
R6U27 0
m
44 PCIE_RXP1_DOCK
C6F11 0.1uF
44 PCIE_TXN1_DOCK C6F10 0.1uF
44 PCIE_TXP1_DOCK
R6U22 0
44 PCIE_RXN2_DOCK
R6U21 0
o
44 PCIE_RXP2_DOCK
C6U8 0.1uF
44 PCIE_TXN2_DOCK C6U7 0.1uF
44 PCIE_TXP2_DOCK
U7F1D
c
GLAN_TXP PCI_E_SLOT5_TXN_C R6F19 0 PCIE_RXN1_R DMI_RXN0_R R6F5 0
25 PCIE_RXN1_SLOT1 N29 V27
&TXN towards &TXPC
R6F18 0 PCIE_RXP1_R PERN1 DMI0RXN DMI_RXP0_R R6F6 0 DMI_RXN0 7
GLAN Device (towards PCIe slot5) 25 PCIE_RXP1_SLOT1 N28 V26 DMI_RXP0 7
PERP1 DMI0RXP
Direct Media Interface

C6U12 0.1uF PCIE_TXN1_C DMI_TXN0_R R6U2
P27 U29 . 0
.
25 PCIE_TXN1_SLOT1 PETN1 DMI0TXN DMI_TXN0 7
D C6U11 . 0.1uF PCIE_TXP1_C P26 U28 DMI_TXP0_R R6U1 . 0
D
PCI_E_SLOT6_TXN_C PCI_E_SLOT5_TXN_C 25 PCIE_TXP1_SLOT1 . PETP1 DMI0TXP DMI_TXP0 7
&TXPC &TXPC . .
R6F17 . 0 PCIE_RXN2_R DMI_RXN1_R R6F3
(from ICH) (from ICH) 25 PCIE_RXN2_SLOT2 L29
PERN2 DMI1RXN
Y27 . 0 DMI_RXN1 7
R6F16 0 PCIE_RXP2_R L28 Y26 DMI_RXP1_R R6F4 0
25 PCIE_RXP2_SLOT2 PERP2 DMI1RXP DMI_RXP1 7
C6F9 0.1uF PCIE_TXN2_C DMI_TXN1_R R6U4 . 0
s
M27 W29 DMI_TXN1 7
25 PCIE_TXN2_SLOT2 C6F8 0.1uF PCIE_TXP2_C PETN2 DMI1TXN DMI_TXP1_R R6U3
25 PCIE_TXP2_SLOT2
. M26
PETP2 DMI1TXP
W28 . 0 DMI_TXP1 7
PCIe LANE 6 SELECTION . .
. DMI_RXN2_R R6F7
26 PCIE_RXN3_SLOT3 J29
PERN3 DMI2RXN
AB27 . 0 DMI_RXN2 7
Lane 6 can be connected to LAN or Slot 5 depending 26 PCIE_RXP3_SLOT3 J28 AB26 DMI_RXP2_R R6F8 0
DMI_RXP2 7
PERP3 DMI2RXP
PCI-Express
it c
C6U6 0.1uF PCIE_TXN3_C DMI_TXN2_R R6U6
on the stuffing option described below. 26 PCIE_TXN3_SLOT3
K27
PETN3 DMI2TXN
AA29 . 0 DMI_TXN2 7
Placed the components such that CAP1 (0603)Pad2 & C6U4 0.1uF PCIE_TXP3_C K26 AA28 DMI_TXP2_R R6U5 . 0
26 PCIE_TXP3_SLOT3 PETP3 DMI2TXP DMI_TXP2 7
CAP2 Pad1 are next to each other as shown above. The .
26 PCIE_RXN4_SLOT4 G29 PERN4 DMI3RXN AD27 DMI_RXN3_R R6F1 . 0
Placement is such that a 0603 Capacitor can be placed G28 AD26 DMI_RXP3_R R6F2 0 DMI_RXN3 7 +V1.5S_PCIE_ICH 21,24
there . Similar placement followed for CAP3 and CAP4. 26 PCIE_RXP4_SLOT4 PERP4 DMI3RXP DMI_RXP3 7
C6U5 0.1uF PCIE_TXN4_C H27 AC29 DMI_TXN3_R R6U8 . 0
26 PCIE_TXN4_SLOT4 PETN4 DMI3TXN DMI_TXN3 7
This approach is same for RX Path also. C6U3 0.1uF PCIE_TXP4_C AC28 DMI_TXP3_R R6U7
26 PCIE_TXP4_SLOT4
H26 PETP4 DMI3TXP . 0 DMI_TXP3 7
.
R6F14 0 PCIE_RXN5_SLOT5_R E29 T26 .
26 PCIE_RXN5_SLOT5 PERN5 DMI_CLKN CLK_PCIE_ICH# 35
R6F11 0 PCIE_RXP5_SLOT5_R E28 T25 R6G5
a
26 PCIE_RXP5_SLOT5 PERP5 DMI_CLKP CLK_PCIE_ICH 35 24.9
C6F4 0.1uF PCIE_TXN5_C F27
24,33,34,44,48,55,57 +V3.3M_WOL 26 PCIE_TXN5_SLOT5 C6F2 0.1uF PCIE_TXP5_C PETN5 1%
. F26 PETP5 DMI_ZCOMP AF29 .
26 PCIE_TXP5_SLOT5 .. DMI_IRCOMP_R
DMI_IRCOMP AF28
R9D9 1K SPI_MOSI_R_3.2V R6F12 . 0 GLAN_RXN_R C29
33 GLAN_RXN PERN6/GLAN_RXN
R6F13 0 GLAN_RXP_R C28 AC5
33 GLAN_RXP PERP6/GLAN_RXP USBP0N USB_PN0 29
2
C6F3 0.1uF PCIE_TXN6_C D27 AC4
33 GLAN_TXN PETN6/GLAN_TXN USBP0P USB_PP0 29
J9D2
C6F1 . 0.1uF PCIE_TXP6_C D26 AD3
PETP6/GLAN_TXP USBP1N USB_PN1 29
.
33 GLAN_TXP
. .
m
USBP1P AD2 USB_PP1 29
R7F8 . 15 SPI_CLK_R D23 AC1
34 SPI_CLK USB_PN2 29
1
R7F9 15 SPI_CS#0_R SPI_CLK USBP2N

34 SPI_CS#0 D24 SPI_CS0# USBP2P AC2 USB_PP2 29
R7F7 15 SPI_CS#1_R F23 AA5
34 SPI_CS#1 SPI_CS1#/GPIO58/CLGPIO6 USBP3N USB_PN3 29
USBP3P AA4 USB_PP3 29
R7U11 15 SPI_MOSI_R
e
34 SPI_SI D25 SPI_MOSI USBP4N AB2 USB_PN4 29
SPI
C
34 SPI_SO E23 SPI_MISO USBP4P AB3 USB_PP4 29 C
USBP5N AA1 USB_PN5 29

R8F17 0 N4 AA2
Layout Note: 29 USB_OC#0 OC0#/GPIO59 USBP5P USB_PP5 29
R8G1 0 N5 W5
R7U11,R7F7,R7F8,R7F9 to be placed within 600mils of U7F1 29 USB_OC#1 OC1#/GPIO40 USBP6N USB_PN6 29
R8F19 0 N6 USB W4
h
29 USB_OC#2 OC2#/GPIO41 USBP6P USB_PP6 29
R8G2 0 P6 Y3
29 USB_OC#3 OC3#/GPIO42 USBP7N USB_PN7 29
R8F12 0 M1 Y2
R8F18 0 N2 W1
R8U7 0 M4 W2
c
R8F16 0 M3 V2 USB_PN9 R8G4
29 USB_OC#7 OC7#/GPIO31 USBP9N USB_PN9_R 44
R8U9 0 N3 V3 USB_PP9 0
R8G6
29 USB_OC#8 OC8#/GPIO44 USBP9P USB_PP9_R 44
R7H6 0 N1 U5 0
+V3.3S P5 U4 R8V4
.
29 USB_OC#10 OC10#/GPIO46 USBP10P USB_PP10 29 USB_PP9_R_FPIO 29
P3 U1 0
.
-s
U2 R8V3
USBP11P USB_PP11 29 USB_PN9_R_FPIO 29
Buffer to reduce loading on C7T4 USBRBIAS_PN AG2 0
NO_STUFF
USB_OC#0_R USBRBIAS
PLT_RST#. 0.1uF AG1
USB_OC#1_R USBRBIAS#
20% NO_STUFF
USB_OC#2_R
5
. U8E2 R7G5 ICH9M REV 1.0

USB_OC#3_R
1 PLT_RST# 22.6
USB_OC#4_R
4 1%
40,43 BUF_PLT_RST# USB_OC#5_R
2 USB_OC#6_R
p
USB_OC#7_R
R8T6 74AHC1G08
USB_OC#8_R
3
100K . USB_OC#9_R
o
PCI_GNT#3
A16 swap override Strap/Top-Block
2
Swap Override jumper
U7F1B ICH9M Pullups J8G7
32 PCI_AD[31:0] PCI_GNT#3 Low = A16 swap override/Top-Block
B
PCI_AD0 D11 F1 B
AD0 REQ0# PCI_REQ#0 32 Swap Override enabled
PCI_AD1 C8 PCI G4 PCI_GNT#0 32
1
PCI_AD2 AD1 GNT0# High = Default (Jumper 1-X)
D9 B6
p
AD2 REQ1#/GPIO50 PCI_REQ#1 32
PCI_AD3 E12 A7 +V3.3S
AD3 GNT1#/GPIO51 PCI_GNT#1 32
PCI_AD4 E9 F13
PCI_AD5 AD4 REQ2#/GPIO52 ICH_GPIO52 PCI_FRAME# RP8C1A 8.2K
C9 F12 ICH_GPIO53 1 8
PCI_AD6 AD5 GNT2#/GPIO53 PCI_IRDY# RP8C1B 8.2K
E10 E6 PCI_REQ#3 32 2 7
PCI_AD7 AD6 REQ3#/GPIO54 PCI_TRDY# RP8C1C 8.2K
B7 F6 3 6
l. a
AD7 GNT3#/GPIO55 PCI_GNT#3 32
PCI_AD8 C7 PCI_STOP# RP9D1A 1 8 8.2K
PCI_AD9 AD8 PCI_SERR# RP9D1D 8.2K
C5 D8 PCI_CBE#0 32 4 5
PCI_AD10 AD9 C/BE0# PCI_DEVSEL# RP8C1D 8.2K
G11 B4 PCI_CBE#1 32 4 5
PCI_AD11 AD10 C/BE1# PCI_PERR# RP9D1C 8.2K
F8 D6 PCI_CBE#2 32 3 6
PCI_AD12 AD11 C/BE2# PCI_LOCK# RP9D1B 8.2K PCI_GNT#0 R8F10 1K PCI_GNT#0_R
F11 A5 PCI_CBE#3 32 2 7
PCI_AD13 AD12 C/BE3# PCI_REQ#0 RP9B1A 8.2K 5%
E7 1 8
PCI_AD14 AD13 PCI_REQ#1 RP9C1B 8.2K SPI_CS#1
A3 D3 PCI_IRDY# 32 2 7
PCI_AD15 AD14 IRDY# ICH_GPIO52 RP9C1D 8.2K GNT#0 and SPI_CS#1
D2 E3 PCI_PAR 32 4 5
PCI_AD16 AD15 PAR PCI_REQ#3 RP9C1C 8.2K have a weak
F10 R1 PCI_RST# 32,41 3 6
PCI_AD17 AD16 PCIRST# internal pull up
D5 C6 PCI_DEVSEL# 32
PCI_AD18 AD17 DEVSEL# INT_PIRQA# RP9C1A 8.2K
D10 E4 PCI_PERR# 32 1 8
AD18 PERR#
w
PCI_AD19 B3 C2 INT_PIRQB# RP9B1D 4 5 8.2K
AD19 PLOCK# PCI_LOCK# 32
2
PCI_AD20 F7 J4 INT_PIRQC# RP9B2A 1 8 8.2K Boot BIOS Strap
AD20 SERR# PCI_SERR# 32 PCI_GNT#0 SPI_CS#1 Boot BIOS Location
PCI_AD21 C3 A4 INT_PIRQD# RP9B1C 3 6 8.2K R7F3 J8H1
AD21 STOP# PCI_STOP# 32 0 1 SPI(Default)
PCI_AD22 F3 F5 INT_PIRQE# RP9B2B 2 7 8.2K 1K
AD22 TRDY# PCI_TRDY# 32 1 0 PCI
PCI_AD23 F4 D7 INT_PIRQF# RP9B2C 3 6 8.2K
PCI_FRAME# 32
1
PCI_AD24 AD23 FRAME# INT_PIRQG# RP9B2D 8.2K 1 1 LPC NO_STUFF Default : 1-2
C1 4 5
PCI_AD25 AD24 INT_PIRQH# RP9B1B 8.2K
G7 C14 2 7
w
AD25 PLTRST# PLT_RST# 7,19,25,26,38,41,57
PCI_AD26 H7 D4
AD26 PCICLK CLK_PCIF_ICH 36
PCI_AD27 D1 R2
AD27 PME# PCI_PME# 32,43
PCI_AD28 G5
PCI_AD29 AD28
H6
PCI_AD30 AD29
G1
PCI_AD31 AD30
H3
AD31
w
A
Interrupt I/F Pillar Rock Intel Confidential A
INT_PIRQA# J5 H4
PIRQA# PIRQE#/GPIO2 INT_PIRQE# 32
INT_PIRQB# E1 PIRQB# PIRQF#/GPIO3 K6 INT_PIRQF# 32 Title
32 INT_PIRQC# J6 PIRQC# PIRQG#/GPIO4 F2 INT_PIRQG# 32
INT_PIRQD# C4 PIRQD# PIRQH#/GPIO5 G2 INT_PIRQH# 32 ICH9M (2 of 4)
ICH9M REV 1.0
A 355659 1.0

5 4 3 2 1
5 4 3 2 1
5,7,10,12,13,16,17,18,19,20,21,22,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57
13,14,15,35,55,57 +V3.3M +V3.3A +V3.3S
ICH_GPIO19_R
U7F1C
m
SMB_CLK G16 SMBCLK SATA0GP/GPIO21 AH23 SATA_DET#0 30
A13 AF19 R7V20
SMB_DATA SMBDATA SATA1GP/GPIO19 SATA_DET#1 31
R7U14 10K E17 AE21 0
ICH_GPIO36
SATA
GPIO
LINKALERT#/GPIO60/CLGPIO4 SATA4GP/GPIO36
SMB
34 ICH_GPIO60 40,43 SMB_CLK_ME C17 SMLINK0 SATA5GP/GPIO37 AD20 ICH_GPIO37_R
B18 . No Reboot Strap
o
40,43 SMB_DATA_ME SMLINK1
H1 R8F14
. CLK14 CLK_REF_ICH 35 R7V22 10K HDA_SPKR Low = Default 1K
F19 AF3
Clocks
38,43 PM_RI# RI# CLK48 CLK_USB48 35 High = No Reboot NO_STUFF
R6H1 R6H4 R4 P1 NO_STUFF
38,40,43 PM_SUS_STAT# SUS_STAT#/LPCPD# SUSCLK SUS_CLK 43
c
10K 10K G19
56 PM_SYSRST# SYS_RESET#
C16 SLP_S3#_R R7U24 0
SLP_S3# PM_SLP_S3# 11,40,43,44,46,47,49,55,57
NO_STUFF NO_STUFF M6 E16 SLP_S4#_R R7U23 0 HDA_SPKR
.
7 PM_SYNC# PMSYNC#/GPIO0 SLP_S4# PM_SLP_S4# 46,55
D G17 PM_SLP_S5#_R R7V1 0 D
SLP_S5# PM_SLP_S5# 57
SMB_ALERT# A17
SMBALERT#/GPIO11 PM_S4_STATE#_R R8U2 0
C10 PM_S4_STATE# 32,40,43,44,55,57
R7U15 PM_STPPCI_ICH# S4_STATE#/GPIO26
35,43 PM_STPPCI# A14
R7U25 0 PM_STPCPU_ICH# STP_PCI# PM_ICH_PWROK
SYS GPIO
s
35,43 PM_STPCPU# E19 G20
0 STP_CPU# PWROK
L4 M2 PM_DPRSLPVR_R .
R8F13 0
32,38,40,43 PM_CLKRUN# . CLKRUN# DPRSLPVR/GPIO16 PM_DPRSLPVR 7,43,52
+V3.3S . 13,14,15,35,55,57 +V3.3M
E20 B13 PM_BATLOW#_R R8F4
Power MGT
19,25,26,44 PCIE_WAKE# WAKE# BATLOW# PM_BATLOW# 40,43
it c
M5 0
38,40,43 INT_SERIRQ SERIRQ .
AJ23 R3 R7U13
5,12,40,43 PM_THRM# THRM# PWRBTN# PM_PWRBTN# 40,43 3.24K
. 1%
C7W1 VR_PWRGD_CLKEN D21 D20
0.1uF VRMPWRGD LAN_RST# PM_LAN_ENABLE 33,40,43
10% 5 A20 D22 PM_RSMRST#_R R7U19 0 R6U11
ICH_TP7 TP11 RSMRST# PM_RSMRST# 40,43,56 NO_STUFF EV_V3.3_ICH_CLVREF0
. U6H1 0
R7H4 AG19 R5
100K 38,40,43,44 SMC_EXTSMI# GPIO1 CK_PWRGD CLK_PWRGD 35,36
VR_PWRGD_CLKEN# 2 4 5% ICH_GPIO6 AH21 GPIO6 NO_STUFF
1
AG21 R6 .
a
40,43 SMC_RUNTIME_SCI# GPIO7 CLPWROK MPWROK 7,46
SMC_WAKE_SCI#_R A21 C7U2 R7U18
+V3.3A ICH_GPIO12_R GPIO8 PM_SLP_M#_R 0.1uF 453_1%
INVERTER C12 B16 PM_SLP_M# 40,43,44,47,55,57
3 GPIO12 SLP_M# R7U27 . 0 5% 10%
ICH_GPIO13 C21 GPIO13 .
SV_SET_UP AE18 F24 CL_CLK0 7
2
GPIO17 CL_CLK0
ICH_GPIO18 K1 GPIO18 CL_CLK1 B19 CL_CLK1 26
R7H12 AF8
10K ICH_GPIO20 GPIO20
41 BIOS_REC AJ22 SCLOCK/GPIO22 CL_DATA0 F22 CL_DATA0 7
SATA_PWR_EN#0_R
m
A9 C19
Controller Link
GPIO
GPIO27 CL_DATA1 CL_DATA1 26
SATA_PWR_EN#1_R D19
ICH_GPIO57_J GPIO28 CL_VREF0_ICH_R R6U12 0
35 CLK_SATA_OE# L1 SATACLKREQ#/GPIO35 CL_VREF0 C25 CL_VREF0_ICH
2
TPM PHYSICAL PRESENCE R7H13 J7H2 ICH_GPIO38 AE19 A19 CL_VREF1_ICH_R

J7H2 1-X default 100K SLOAD/GPIO38 CL_VREF1 +V3.3A 19,21,24,25,26,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57
5% MFG_MODE AG22 SDATAOUT0/GPIO39 NO_STUFF
e
CRB_SV_DET_R AF21 SDATAOUT1/GPIO48 CL_RST0# F21 CL_RST#0 7
C DMI_TERM_SEL AH24 D18 C
CL_RST#1 26
1
ICH_GPIO57 GPIO49 CL_RST1# R7U6

A8 GPIO57/CLGPIO5
A16 3.24K
MEM_LED/GPIO24 ICH_GPIO24 34 1%
27,44 HDA_SPKR M7 SPKR GPIO10/SUS_PWR_ACK C18 SUS_PWR_ACK 40,43
R7G15 AJ24 C11 R3J3
h
7 MCH_ICH_SYNC# MCH_SYNC# GPIO14/AC_PRESENT AC_PRESENT 40,43,56 EV_V3.3_ICH_CLVREF1
0 B21 C20 0
21 ICH_TP3 TP3 WOL_EN/GPIO9
TP_ICH_PWM0
MISC
AH20 +V3.3A NO_STUFF
MCH_ICH_SYNC_R# TP8
1
. TP_ICH_PWM1 AJ20
TP_ICH_PWM2 TP9 R7U17 0 C7U3 R7U20
AJ21 CL_VREF1_ICH
TP10
c
0.1uF 453_1%
19 +V3.3S_PEG ICH9M REV 1.0 R7U22 NO_STUFF .10%
10K
2
R416 10K
ICH_GPIO37_R R6C3
-s
+V3.3S 10K NO_STUFF
LAN_WOL_EN 40,43,55,57
ICH_GPIO12_R
. ICH_GPIO12_R
R6C5 R8F20
ICH_GPIO37 ICH_GPIO12 57
R8F8 0 0 +V3.3M 13,14,15,35,55,57 +V3.3A ICH9M Pullups +V3.3A
10K . .
R7D3 10K SMB_CLK_M3 R8C5 10K SMB_CLK_A1
R7D1 10K SMB_DATA_M3 R8D1 10K SMB_DATA_A1
p
J8F2 Default is ICH_GPIO13 R7T22
1-X BIOS_REC 41
R7R10 10K SMB_CLK_M2 +V3.3S 10K 5%
2
for BIOS R7R12 10K SMB_DATA_M2 PM_RI# R7T20 10K

recovery 1-2 J8F2
+V3.3S R7V12 10K ICH_GPIO36 SMB_CLK_ME R7U21 . 10K
o
SMB_DATA_ME R7U12 10K
1
R9A4 10K SMB_CLK_S4

R9A5 10K SMB_DATA_S4 SMB_CLK R7D10 2.2K
t
+V3.3S SMB_DATA R7D11 2.2K
+V3.3S
19,21,24,25,26,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57 +V3.3A SMB_ALERT# R7U9 10K
B TXT Status LED B
R8G11 13,14,15,35,55,57 +V3.3M PCIE_WAKE# R7U1 1K
p
240
+V3.3A PM_BATLOW#_R R8U4 8.2K
C7R2
TXT_STATUS U7D1 0.1uF ICH_GPIO12 R8F5 10K
2
ICH_GPIO38 is used for TXT status indication R7R2 10K CL1 1 20 20%
l. a
CR8G1 R7R4 10K CL2 EXPSCL1 VCC .
2
GREEN R7R5 10K DA1 EXPSCL2 +V3.3S
18 5 SMB_CLK_A1 25,26,32,44
R7R3 10K DA2 EXPSDA1 SCL1
19 6 SMB_DATA_A1 25,26,32,44
EXPSDA2 SDA1
1 3
TXT_STATUS_R
.Q8G1 SMB_CLK 3 8 CLK_SATA_OE# R7F10 10K
SCL0 SCL2 SMB_CLK_M2 13,14,15
BSS138 SMB_DATA 4 9
SDA0 SDA2 SMB_DATA_M2 13,14,15
ICH_GPIO38 1 PM_THRM# R7G7 8.2K
R7R8 10K I2C_EN1 7 12
EN1 SCL3 SMB_CLK_M3 35,36
. R7R11 10K I2C_EN2 11 13 INT_SERIRQ R7T16 10K
SMB_DATA_M3 35,36
2
R8V10 R7R9 10K I2C_EN3 14 EN2 SDA3

10K GPIO49 has a weak internal pull-up DMI_TERM_SEL R7R7 10K I2C_EN4 17 EN3 PM_CLKRUN# R8F9 8.2K
15 SMB_CLK_S4 19,43
5% EN4 SCL4
w
. 10 16 SMB_DATA_S4 19,43
NO_STUFF VSS SDA4 ICH_GPIO6 R7G6 10K
R7V16 is used for testing R7V16 EXP. 5-CH-I2C HUB
purposes only 1K
ALL_SYS_PWRGD R8G5 10K
PM_RSMRST# R9G17 10K
w
+V3.3A 19,21,24,25,26,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57
+V3.3S 5,7,10,12,13,16,17,18,19,20,21,22,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57
C8C1 SMC_WAKE_SCI#_R
SMC_WAKE_SCI#_R
w
0.1uF R8W3
A SMC_WAKE_SCI# 40,43 A
10% R7P3 0
. 2K
1%
.
5
U8C2
1
Title
ALL_SYS_PWRGD 40,43,47
PM_ICH_PWROK 4 ICH9M (3 of 4)
2
DELAY_VR_PWRGOOD 7
R8C4 74AHC1G08
3
10K .
5% SATA_PWR_EN#1_R SATA_PWR_EN#0_R
R8H9
SATA_PWR_EN#1_R
R8W6
SATA_PWR_EN#0_R A 355659 1.0
SATA_PWR_EN#1 31 SATA_PWR_EN#0 30
0 0
. . Date: Tuesday, August 28, 2007 Sheet 23 of 58

5 4 3 2 1
5 4 3 2 1
+V5S 5,11,12,16,17,18,28,30,31,32,39,48,49,52,55,56,57 U7F1E
41 +V1.05S_ICH 4,9,10,47,55 +V1.05S AA26 H5
m
VSS[1] VSS[107]
AA27 VSS[2] VSS[108] J23
21 +V3.3A_RTC AA3 J26
R7U16 U7F1F R7F5 0.002 VSS[3] VSS[109]
AA6 VSS[4] VSS[110] J27
10 A23 A15 AB1 AC22
5% VCCRTC VCC1_05[1] C7U16 C7V2 VSS[5] VSS[111]
B15 AA23 K28
o
+V3.3S C7U5 C7U4 VCC1_05[2] 0.1uF 0.1uF VSS[6] VSS[112]
A6 V5REF VCC1_05[3] C15 AB28 VSS[7] VSS[113] K29
0.1uF 0.1uF D15 10% 10% AB29 L13
10% 10% VCC1_05[4] SMC0402
. SMC0402
. VSS[8] VSS[114]
AE1 V5REF_SUS VCC1_05[5] E15 AB4 VSS[9] VSS[115] L15
1 SMC0402
. SMC0402
. F15 4,10,11,28,47,55,57 +V1.5S AB5 L2
VCC1_05[6] L6G1 VSS[10] VSS[116]
c
AA24 L11 AC17 L26
CR7U1 VCC1_5_B[1] VCC1_05[7] +V1.5S_ICH_VCCDMIPLL +V1.5S_ICH_VCCDMIPLL_R R6G2 VSS[11] VSS[117]
AA25 L12 1 2 AC26 L27
BAT54 VCC1_5_B[2] VCC1_05[8] 1uH 0 VSS[12] VSS[118]
AB24 L14 AC27 L5
VCC1_5_B[3] VCC1_05[9] VSS[13] VSS[119]
.
AB25 L16 C6F13 C6F12 AC3 L7
+V5A VCC1_5_B[4] VCC1_05[10] VSS[14] VSS[120]
D +V5S_ICH_VCC5REF AC24
VCC1_5_B[5] VCC1_05[11]
L17 0.01uF 10uF . AD1
VSS[15] VSS[121]
M12 D
3 AC25 L18 10% 20% 41 +V1.05S_ICH
AD10 M13
+V3.3A C7U8 VCC1_5_B[6] VCC1_05[12] .402 . VSS[16] VSS[122]
AD24 M11 AD12 M14
0.1uF VCC1_5_B[7] VCC1_05[13] VSS[17] VSS[123]
AD25 M18 AD13 M15
s
10% VCC1_5_B[8] VCC1_05[14] FB7V1 VSS[18] VSS[124]
1 AE25 P11 AD14 M16
SMC0402
. VCC1_5_B[9] VCC1_05[15] VSS[19] VSS[125]
AE26 P18 AD17 M17
R8V5 CR8V1 VCC1_5_B[10] VCC1_05[16] C7V3 5ohm@100MHz VSS[20] VSS[126]
AE27 T11 AD18 M23
10 BAT54 VCC1_5_B[11] VCC1_05[17] 4.7uF VSS[21] VSS[127]
AE28 T18 AD21 M28
5% VCC1_5_B[12] VCC1_05[18] VSS[22] VSS[128]
it c
AE29 U11 10% AD28 M29
VCC1_5_B[13]
CORE
VCC1_05[19] . VSS[23] VSS[129]
F25 U18 AD29 N11
3 +V5A_ICH_V5REF_SUS VCC1_5_B[14] VCC1_05[20] VSS[24] VSS[130]
G25 VCC1_5_B[15] VCC1_05[21] V11 AD4 VSS[25] VSS[131] N12
H24 VCC1_5_B[16] VCC1_05[22] V12 21 +V1.05S_ICH_IO
AD5 VSS[26] VSS[132] N13
C7V9 H25 V14 4,9,10,47,55 +V1.05S AD6 N14
0.1uF VCC1_5_B[17] VCC1_05[23] VSS[27] VSS[133]
J24 VCC1_5_B[18] VCC1_05[24] V16 AD7 VSS[28] VSS[134] N15
10% J25 V17 R6V10 0.002 AD9 N16
SMC0402
. VCC1_5_B[19] VCC1_05[25] VSS[29] VSS[135]
K24 VCC1_5_B[20] VCC1_05[26] V18 AE12 VSS[30] VSS[136] N17
K25 C7V5 C7V6 C7V4 AE13 N18
VCC1_5_B[21] 0.1uF 0.1uF 4.7uF VSS[31] VSS[137]
L23 R29 AE14 N26
a
VCC1_5_B[22] VCCDMIPLL 10% 10% 10% VSS[32] VSS[138]
L24 VCC1_5_B[23] AE16 VSS[33] VSS[139] N27
+V1.5S 4,10,11,28,47,55,57 L25 W23 +V1.05S_ICH_DMI SMC0402
. SMC0402
. . AE17 P12
VCC1_5_B[24] VCC_DMI[1] VSS[34] VSS[140]
M24 VCC1_5_B[25] VCC_DMI[2] Y23 AE2 VSS[35] VSS[141] P13
21,22 +V1.5S_PCIE_ICH M25 AE20 P14
FB6G1 VCC1_5_B[26] +V3.3S VSS[36] VSS[142]
N23 VCC1_5_B[27] V_CPU_IO[1] AB23 AE24 VSS[37] VSS[143] P15
R6G3 0.002 +V1.5S_PCIE_R N24 AC23 +V3.3S_DMI_ICH AE3 P16
VCC1_5_B[28] V_CPU_IO[2] VSS[38] VSS[144]
N25 VCC1_5_B[29] AE4 VSS[39] VSS[145] P17
330ohm@100MHz C6G2 C6G3 C6G1 C7U17 P24 AG29 R6G6 0.002 AE6 P2
m
220uF 22uF 22uF 2.2uF VCC1_5_B[30] VCC3_3[1] VSS[40] VSS[146]
P25 VCC1_5_B[31] AE9 VSS[41] VSS[147] P23
VCCA3GP
SMC0603 R24 AJ6 C6V5 AF13 P28
. . . VCC1_5_B[32] VCC3_3[2] 0.1uF VSS[42] VSS[148]
R25 VCC1_5_B[33] AF16 VSS[43] VSS[149] P29
R26 AC10 C7G4 10% AF18 P4
VCC1_5_B[34] VCC3_3[7] 0.1uF SMC0402
. VSS[44] VSS[150]
R27 AF22 P7
e
VCC1_5_B[35] 10% +V3.3S_SATA_ICH R7G9 0.002 VSS[45] VSS[151]
T24 VCC1_5_B[36] VCC3_3[3] AD19 AH26 VSS[46] VSS[152] R11
C T27 AF20 SMC0402
. AF26 R12 C
VCCP_CORE
VCC1_5_B[37] VCC3_3[4] C7V8 VSS[47] VSS[153]
T28 VCC1_5_B[38] VCC3_3[5] AG24 AF27 VSS[48] VSS[154] R13
T29 AC20 0.1uF +V3.3S_VCCPCORE_ICH R7G14 0.002 AF5 R14
+V1.5S 4,10,11,28,47,55,57 VCC1_5_B[39] VCC3_3[6] 10% VSS[49] VSS[155]
U24 AF7 R15
h
+V1.5S_SATA_ICH VCC1_5_B[40] SMC0402
. VSS[50] VSS[156]
U25 VCC1_5_B[41] VCC3_3[8] B9 AF9 VSS[51] VSS[157] R16
L7G1 V24 F9 +V3.3S_PCI_ICH R7F4 0.002 AG13 R17
R7G16 0.002 +V1.5S_APLL_ICH VCC1_5_B[42] VCC3_3[9] VSS[52] VSS[158]
V25 G3 AG16 R18
10uH VCC1_5_B[43] VCC3_3[10] C7U15 C7U7 C7U10 VSS[53] VSS[159]
U23 G6 AG18 R28
VCC1_5_B[44] VCC3_3[11] VSS[54] VSS[160]
c
C7G7 C7G6 W24 J2 0.1uF 0.1uF 0.1uF AG20 T12
10uF 1.0uF VCC1_5_B[45] VCC3_3[12] 10% 10% 10% VSS[55] VSS[161]
W25
PCI
J7 AG23 T13
20% 402 VCC1_5_B[46] VCC3_3[13] SMC0402
. NO_STUFF NO_STUFF VSS[56] VSS[162]
K23 K7 AG3 T14
SMC0805
. . VCC1_5_B[47] VCC3_3[14] SMC0402 SMC0402 VSS[57] VSS[163]
Y24 AG6 T15
VCC1_5_B[48] VSS[58] VSS[164]
Y25 AJ4 AG9 T16
-s
VCC1_5_B[49] VCCHDA 21,27,28 +V3.3S_1.5S_HDA_IO VSS[59] VSS[165]
AH12 T17
+V3.3S_1.5S_HDA_IO_ICH R7V17 0.022 VSS[60] VSS[166]
AJ19 AJ3 AH14 T23
VCCSATAPLL VCCSUSHDA VSS[61] VSS[167]
AH17 B26
VSS[62] VSS[168]
AC16 AC8 TP_VCCSUS1_05_ICH_1 27,28,44 +V3.3A_1.5A_HDA_IO C7V11 AH19 U12
VCC1_5_A[1] VCCSUS1_05[1] VSS[63] VSS[169]
AD15 F17 TP_VCCSUS1_05_ICH_2 0.1uF AH2 U13
C7G5 VCC1_5_A[2] VCCSUS1_05[2] 10% SMC0402 VSS[64] VSS[170]
AD16 AH22 U14
VCC1_5_A[3] VSS[65] VSS[171]
ARX
1.0uF AE15 AD8 TP_VCCSUS1_5_ICH_1 . AH25 U15

402 VCC1_5_A[4] VCCSUS1_5[1] C7V12 VSS[66] VSS[172]
AF15 AH28 U16
VCC1_5_A[5] VSS[67] VSS[173]
p
. AG15 F18 VCCSUS1_5_INT_ICH 0.1uF AH5 U17
VCC1_5_A[6] VCCSUS1_5[2] 10% VSS[68] VSS[174]
AH15 AH8 AD23
VCC1_5_A[7] C7U11 SMC0402
. VSS[69] VSS[175]
AJ15 AJ12 U26
C7G3 VCC1_5_A[8] 0.1uF VSS[70] VSS[176]
A18 AJ14 U27
VCCPSUS
+V1.5S_SATA_ICH 1.0uF VCCSUS3_3[1] 10% SMC0402 VSS[71] VSS[177]

AC11 D16 AJ17 U3
o
402 AD11 D17 . +V3.3A AJ8 V1
. VCC1_5_A[10] VCCSUS3_3[3] VSS[73] VSS[179]
AE11 E22 B11 V13
ATX
AF11 B14 V15
t
VCC1_5_A[12] +V3.3A_ICH R6F9 0.002 VSS[75] VSS[181]
AG10 B17 V23
VCC1_5_A[13] VSS[76] VSS[182]
AG11 AF1 B2 V28
AH10 B20 V29
B +V1.5S_USB_ICH AJ10
VCC1_5_A[15]
T1 B23
VSS[78] VSS[184]
V4 B
VCC1_5_A[16] VCCSUS3_3[6] +V3.3A_USB_ICH R7G1 0.002 VSS[79] VSS[185]
T2 B5 V5
p
R7H1 0.002 VCCSUS3_3[7] VSS[80] VSS[186]
AC9 T3 B8 W26
VCC1_5_A[17] VCCSUS3_3[8] C7V1 C7G1 C7G2 VSS[81] VSS[187]
T4 C26 W27
C7V10 VCCSUS3_3[9] 0.022uF 0.022uF 0.1uF VSS[82] VSS[188]
AC18 T5 C27 W3
0.1uF VCC1_5_A[18] VCCSUS3_3[10] 10% 10% 10% VSS[83] VSS[189]
AC19 T6 E11 Y1
10% VCC1_5_A[19] VCCSUS3_3[11] .402 .402 SMC0402
. VSS[84] VSS[190]
U6 E14 Y28
VCCPUSB
VCCSUS3_3[12] VSS[85] VSS[191]
l. a
SMC0402
. AC21 U7 E18 Y29
V6 E2 Y4
G10 V7 E21 Y5
G9 W6 E24 AG28
W7 E5 AH6
AC12 Y6 E8 AF2
AC13 Y7 F16 B25
AC14 T7 F28
C7V7 VCC1_5_A[25] VCCSUS3_3[20] VSS[93]
F29 A1
0.1uF VCCCL1_05_INT_ICH VSS[94] VSS_NCTF[1]
AJ5 G22 G12 A2
10% VCCUSBPLL VCCCL1_05 C7U12 VSS[95] VSS_NCTF[2]
G14 A28
VSS[96] VSS_NCTF[3]
w
22,33,34,44,48,55,57 +V3.3M_WOL SMC0402
. AA7 G23 VCCCL1_5_INT_ICH 0.1uF G18 A29
VCC1_5_A[26] VCCCL1_5 VSS[97] VSS_NCTF[4]
USB CORE
AB6 10% G21 AH1

VCC1_5_A[27] C7U14 C7U13 SMC0402
. VSS[98] VSS_NCTF[5]
AB7 A24 G24 AH29
R7F2 0.002 +V3.3M_VCCPAUX VCCLAN1_05_INT_ICH VCC1_5_A[28] VCCCL3_3[1] 1UF 0.1uF VSS[99] VSS_NCTF[6]
AC6 B24 G26 AJ1
VCC1_5_A[29] VCCCL3_3[2] 10% VSS[100] VSS_NCTF[7]
AC7 G27 AJ2
C7U9 C7U6 VCC1_5_A[30] NO_STUFF NO_STUFF VSS[101] VSS_NCTF[8]
G8 AJ28
0.1uF 0.1uF SMC0402 VSS[102] VSS_NCTF[9]
A10 H2 AJ29
w
10% 10% VCCLAN1_05[1] VSS[103] VSS_NCTF[10]
A11 H23 B1
SMC0402
. SMC0402
. VCCLAN1_05[2] VSS[104] VSS_NCTF[11]
H28 B29
VSS[105] VSS_NCTF[12]
A12 H29
+V1.5S 4,10,11,28,47,55,57 VCCLAN3_3[1] VSS[106]
B12
L7F1 VCCLAN3_3[2] 22,33,34,44,48,55,57 +V3.3M_WOL ICH9M REV 1.0
R7F1 +V1.5S_ICH_GLANPLL_R 1 2 +V1.5S_ICH_GLANPLL_R_L A27
0 1uH VCCGLANPLL +V3.3M_ICH R7U7 0.002
w
A A
Intel Confidential
GLAN POWER
.
C7F3
10uF
C7F4
2.2uF
D28
D29
VCCGLAN1_5[1]
VCCGLAN1_5[2]
Pillar Rock
21,22 +V1.5S_PCIE_ICH 20% SMC0603 E26
. . E27
VCCGLAN1_5[3]
VCCGLAN1_5[4]
Title
A26 ICH9M (4 of 4)
C6F7 VCCGLAN3_3
4.7uF ICH9M REV 1.0
+V3.3S
10%
.
A 355659 1.0
R6U9 0.002 +V3.3S_GLAN_ICH

5 4 3 2 1
5 4 3 2 1
o m
. c
D D
s
5,7,10,12,13,16,17,18,19,20,21,22,23,24,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57 +V3.3S
it c
+V12S_PCIESLOT1 +V12S_PCIESLOT1 19,21,23,24,26,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57 +V3.3A
+V3.3S_PCIESLOT1
+V3.3S_PCIESLOT1 +V3.3S_PCIESLOT1 R7N5
J6B1 0.002
B1 A1 PCIESLOT1_PRSNT#1 C6B13 C7B10 1% C7B14
19,21,23,24,26,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57 +V3.3A +12V1 PRSNT1# C6B10 0.1uF 0.1uF C7B16 0.1uF
B2 +12V2 +12V3 A2 .
B3 A3 22uF 10% 10% 22uF 10%
RSVD1 +12V4 R6B2 . . .
B4 A4
a
GND1 GND6 0
23,26,32,44 SMB_CLK_A1 B5 SMCLK JTAG2 A5
23,26,32,44 SMB_DATA_A1 B6 SMDAT JTAG3 A6
B7 GND2 JTAG4 A7 .
B8 +3.3V1 JTAG5 A8
+V3.3S_PCIESLOT1 B9 A9 26,30,31,32,43,55,57 +V12S
JTAG +3.3V2
B10 3.3VAUX +3.3V3 A10
B11 WAKE# PWRGD A11 PLT_RST# 7,19,22,26,38,41,57
19,23,26,44 PCIE_WAKE# +V12S_PCIESLOT1
m
Key R7N6
R7C3 B12 A12 0.002
10K RSVD2 GND7 C7B6 C6B4 1%
B13 GND3 REFCLK+ A13 CLK_PCIE_SLOT1 36
5% B14 A14 C7B8 0.1uF 0.1uF .
22 PCIE_TXP1_SLOT1 HSOP_0 REFCLK- CLK_PCIE_SLOT1# 36 22uF 10% 10%
. B15 A15
e
22 PCIE_TXN1_SLOT1 HSON_0 GND8 . .
B16 GND4 HSLP_0 A16 PCIE_RXP1_SLOT1 22
C 36 CLK_SLOT1_OE# B17 PRSNT2# HSLN_0 A17 PCIE_RXN1_SLOT1 22
C
B18 GND5 GND9 A18
h
PCIE_X1
SLOT 1
c
NOTE: SLOTS 1 AND 2
ARE PHYSICALY IN-LINE
-s
5,7,10,12,13,16,17,18,19,20,21,22,23,24,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57 +V3.3S
+V12S_PCIESLOT2 +V12S_PCIESLOT2
19,21,23,24,26,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57 +V3.3A
p
+V3.3S_PCIESLOT2
+V3.3S_PCIESLOT2 +V3.3S_PCIESLOT2 R7R1
J6D1 0.002
B1 A1 PCIESLOT2_PRSNT#1 C7D2 C6D3 1% C7D3
19,21,23,24,26,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57 +V3.3A +12V1 PRSNT1# C7D1 0.1uF 0.1uF C7D4 0.1uF
B2 A2 .
+12V2 +12V3
o
B3 A3 22uF 10% 10% 22uF 10%
RSVD1 +12V4 R7R6 . . .
B4 A4
SMB_CLK_A1 GND1 GND6 0
B5 A5
t
SMB_DATA_A1 SMCLK JTAG2
B6 A6
SMDAT JTAG3
B7 A7 .
GND2 JTAG4
B8 A8
B +V3.3S_PCIESLOT2 B9
+3.3V1 JTAG5
A9 B
JTAG +3.3V2 26,30,31,32,43,55,57 +V12S
B10 A10
p
PCIE_WAKE# 3.3VAUX +3.3V3 PLT_RST#
B11 A11
WAKE# PWRGD +V12S_PCIESLOT2
R7D14 Key R7C20
10K B12 A12 0.002
5% RSVD2 GND7 C6C12 C7C3 1%
B13 A13 CLK_PCIE_SLOT2 36
GND3 REFCLK+
l. a
. B14 A14 C7C1 0.1uF 0.1uF .
22 PCIE_TXP2_SLOT2 HSOP_0 REFCLK- CLK_PCIE_SLOT2# 36 22uF 10% 10%
22 PCIE_TXN2_SLOT2 B15 A15
HSON_0 GND8 . .
B16 A16 PCIE_RXP2_SLOT2 22
GND4 HSLP_0
36 CLK_SLOT2_OE# B17 A17 PCIE_RXN2_SLOT2 22
PRSNT2# HSLN_0
B18 A18
GND5 GND9
PCIE_X1
SLOT 2
w w
w
A A
Title
PCI-E Slots (1 & 2)

355659
1.0
5 4 3 2 1
5 4 3 2 1
PCIe Slot3 VAUX Control
m
+V3.3S +V3.3_PCIE_VAUX_SLOT3
+V12S_PCIESLOT3 +V12S_PCIESLOT3 +V3.3A
o
+V3.3_PCIESLOT3 R7C1 +V3.3_PCIE_VAUX_SLOT3
+V3.3_PCIESLOT3 0.002 8 Q8B1
J8B3 1% IRF7822
7 3
+V3.3_PCIE_VAUX_SLOT3 B1 A1 PCIESLOT3_PRSNT1# . 6 2 .
+12V1 PRSNT1# +V3.3_PCIESLOT3
c
B2 A2 5 1
+12V2 +12V3 R8B5 45,46,47,56,57 +VBATA
B3 A3
RSVD1 +12V4 R8B4 0.002
B4 A4
GND1 GND6
.
B5 A5 0 C8B6 C8B7 1% C8B9
23,25,32,44 SMB_CLK_A1 PCIE_RSVD_1#
4
SMCLK JTAG2
D 23,25,32,44 SMB_DATA_A1 B6
SMDAT JTAG3
A6 C7B17 0.1uF 0.1uF NO_STUFF C8N4 0.1uF D
B7 A7 . 22uF 10% 10% 22uF 10% R8B8 VAUX3_G_SWITCH
GND2 JTAG4 . . . 100K
B8 A8
+V3.3_PCIESLOT3 +3.3V1 JTAG5 R8B7
B9 A9
s
JTAG +3.3V2
3
B10 A10 100K C8B8
3.3VAUX +3.3V3
B11
WAKE# PWRGD
A11 PLT_RST# 7,19,22,25,38,41,57
Q8N1 . 0.01UF
19,23,25,44 PCIE_WAKE# +V3.3A BSS138 10%
R8C1 Key Upham 4 Support: STUFF R8B5 and NO_STUFF R7C1 VAUX3_OK# 1
it c
10K B12 A12 Upham 3 and Conventional PCIe card support(Default): STUFF R7C1 and NO_STUFF R8B5
5% RSVD2 GND7 R8B6
B13 A13 CLK_PCIE_SLOT3 36 .
2
GND3 REFCLK+
3
. 22 PCIE_TXP3_SLOT3 B14 A14 25,30,31,32,43,55,57 +V12S 100K
HSOP_0 REFCLK- CLK_PCIE_SLOT3# 36
B15 A15 Q8N2
22 PCIE_TXN3_SLOT3 HSON_0 GND8
B16 A16 BSS138
GND4 HSLP_0 PCIE_RXP3_SLOT3 22
B17 A17 +V12S_PCIESLOT3 1
CLK_SLOT3_OE# PRSNT2# HSLN_0 PCIE_RXN3_SLOT3 22 41 EC_PCIE_SLOT3_VAUX_ON
B18 A18 R8B2
36 GND5 GND9 0.002 .
2
PCIE_X1 C8B5 C8B3 1%
C8B4 0.1uF 0.1uF .
a
22uF 10% 10%
NOTE: SLOTS 3 AND 4 . .
ARE PHYSICALY IN-LINE SLOT 3
m
+V3.3S +V3.3_PCIE_VAUX_SLOT4
+V12S_PCIESLOT4 +V12S_PCIESLOT4 R8D2

0.002
e
+V3.3_PCIESLOT4 1%
C J8D1
+V3.3_PCIESLOT4 . C
+V3.3_PCIESLOT4 R8D3
+V3.3_PCIE_VAUX_SLOT4 B1 A1 PCIESLOT4_PRSNT1# 0.002
+12V1 PRSNT1# C8D3 C8D2 1% C8D4
B2 A2
h
+12V2 +12V3 R7P13 C8D1 0.1uF 0.1uF C8D5 0.1uF
B3 A3 NO_STUFF
RSVD1 +12V4 0 22uF 10% 10% 22uF 10%
B4 GND1 GND6 A4
SMB_CLK_A1 B5 A5 PCIESLOT4_A5 . . .
+V3.3_PCIESLOT4 SMB_DATA_A1 SMCLK JTAG2 PCIESLOT4_A6
B6 A6 .
SMDAT JTAG3
c
B7 A7 PCIE_RSVD_2#
GND2 JTAG4 PCIESLOT4_A8
B8 A8
+3.3V1 JTAG5 Upham 4 Support: STUFF R8D3 and NO_STUFF R8D2
B9 A9
B10
JTAG +3.3V2
A10 Upham 3 and Conventional PCIe card support(Default): STUFF R8D2 and NO_STUFF R8D3 PCIe Slot4 VAUX Control
B11 A11
-s
WAKE# PWRGD 19,21,23,24,25,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57 +V3.3A
Key
R8D5 B12 A12 +V3.3_PCIE_VAUX_SLOT4
10K RSVD2 GND7 Q7R1
B13 A13 CLK_PCIE_SLOT4 36 8
5% GND3 REFCLK+ 25,30,31,32,43,55,57 +V12S IRF7822
22 PCIE_TXP4_SLOT4 B14 A14 CLK_PCIE_SLOT4# 36 7 3
HSOP_0 REFCLK-
. PCIE_TXN4_SLOT4 B15 A15 6 2 .
22 HSON_0 GND8
B16 A16 PCIE_RXP4_SLOT4 22 5 1
GND4 HSLP_0 +V12S_PCIESLOT4 45,46,47,56,57 +VBATA
36 CLK_SLOT4_OE# B17 A17 PCIE_RXN4_SLOT4 22
PRSNT2# HSLN_0
p
B18 A18 R8C3
GND5 GND9 0.002
4
PCIE_X1 C8C3 C8C4 1%
C8C2 0.1uF 0.1uF . R7P6 VAUX4_G_SWITCH
22uF 10% 10% 100K
SLOT 4 . .
o
19,21,23,24,25,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57 +V3.3A R7P5
3
100K C7R1
Q7P1 . 0.01UF
t
BSS138 10%
R7P4 VAUX4_OK# 1
100K
B . B
2
3
p
Q7P2
BSS138
40 EC_PCIE_SLOT4_VAUX_ON 1
5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,28,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57 +V3.3S
+V12S_PCIESLOT5 +V12S_PCIESLOT5 .
2
l. a
+V3.3S_PCIESLOT5
+V3.3S_PCIESLOT5 +V3.3S_PCIESLOT5
J7B1 R7N4
+V3.3A B1 A1 PCIESLOT5_PRSNT1# 0.002
+12V1 PRSNT1# C7B12 C7B9 1%
B2 A2
+12V2 +12V3 C7B15 0.1uF 0.1uF
B3 A3 .
RSVD1 +12V4 22uF 10% 10%
B4 A4
SMB_CLK_A1 GND1 GND6 R7N3 . .
B5 A5
SMB_DATA_A1 SMCLK JTAG2 0
B6 A6
SMDAT JTAG3
B7 A7
GND2 JTAG4
w
B8 A8 .
+V3.3S_PCIESLOT5 +3.3V1 JTAG5 NOTE: Remove Resistors in case a JTAG-capable PCIE card is to be inserted in Slot 4
B9 A9
JTAG +3.3V2 25,30,31,32,43,55,57 +V12S
B10 A10
B11 A11
WAKE# PWRGD
R7C2 Key +V12S_PCIESLOT5
10K B12 A12 R7N2 PCIESLOT4_A6 R7D20
w
RSVD2 GND7 CL_RST#1 23
5% B13 A13 0.002 PCIESLOT4_A8 R7D12
0
GND3 REFCLK+ CLK_PCIE_SLOT5 36 CL_DATA1 23
. PCIE_TXP5_SLOT5
22 B14 A14 C7B5 C7B7 1% PCIESLOT4_A5 0
R7D13
HSOP_0 REFCLK- CLK_PCIE_SLOT5# 36 CL_CLK1 23
B15 A15 C7B4 0.1uF 0.1uF . 0
.
22 PCIE_TXN5_SLOT5 HSON_0 GND8 22uF 10% 10%
B16 A16 PCIE_RXP5_SLOT5 22 .
GND4 HSLP_0 . .
36 CLK_SLOT5_OE# B17 A17 PCIE_RXN5_SLOT5 22 .
PRSNT2# HSLN_0
B18 GND5 GND9
A18
w
A A
PCIE_X1
SLOT 5 19,21,23,24,25,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57 +V3.3A Title
PCI-E Slots (3,4 & 5)
C7B11
C7B13 0.1uF Size Document Number Rev
22uF 10%
.
355659 1.0
5 4 3 2 1
5 4 3 2 1
m
Layout Toplogy for HDA Clk,Sync,RST,SDout,Enable
* Docking Connector 13x2 Header
o
R7G4 HDA_CODEC_0_1_2_CLK
7,21 HDA_BIT_CLK 0
R7G3 33 HDA_CODEC_3_CLK
. Note: Place the resistors "*" as
**
c
R7V2 HDA_CODEC_0_1_2_RST# Marked in the Diagram
7,21 HDA_RST# 0
***
.
R7G2 33 HDA_CODEC_3_RST#
D . D
R7V6 HDA_CODEC_0_1_2_SYNC
7,21 HDA_SYNC 0
*
s
R7V7 . 33 HDA_CODEC_3_SYNC ICH
7,21 HDA_SDOUT
R7G10 HDA_CODEC_0_1_2_SDATAOUT
0
*
it c
R7G11 33 HDA_CODEC_3_SDATAOUT
.
8x2 Header
HDA_SDIN2 R9N2 HDA_DOCK_SDATAIN
0
NO_STUFF
GMCH
a
+V5 32,42,43,48,52,55,56,57
HDA Header for MDC Interposer
16,19,30,31,55,57 +VBATS
m
19,32,39,41,42,43,55,57 +V3.3 HDA Header for External HDMI Support
19,21,23,24,25,26,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57 +V3.3A 16,19,30,31,55,57 +VBATS
e
R9E7 19,32,39,41,42,43,55,57 +V3.3
C
HDA_CODEC_0_1_2_CLK
** R9D3 33 HDA_MDC_BITCLK
2X8_HDR_KEY12
J9E2
24,28,44 +V3.3A_1.5A_HDA_IO 0 C
16 15 .
HDA_CODEC_0_1_2_RST# R9E6 33 HDA_MDC_RST# 14 13 R6C2
h
HDA_CODEC_0_1_2_SYNC R9D7 33 HDA_MDC_SYNC 12 11 24,28,44 +V3.3A_1.5A_HDA_IO 0
HDA_CODEC_0_1_2_SDATAOUT R9E2 33 HDA_MDC_SDO 10 9 J6C2
8 7 +VBATS_HDA_R1 HDA_CODEC_3_CLK 16 15 .
21 HDA_SDIN0
R9E9 HDA_MDC_SDATAIN1 6 HDA_CODEC_3_RST# 14 13
21 HDA_SDIN1
HDA_MDC_SDATAIN3 HDA_CODEC_3_SYNC
c
R9E12 0 4 3 12 11
7,21 HDA_SDIN3
0 HDA_MDC_SDATAIN2 2 1 HDA_CODEC_3_SDATAOUT 10 9
R9E8 . HDA_SDIN2 R9E14 HDA_SDIN2_R 8 7 +VBATS_HDA_R2
NO_STUFF .0 HDA_AUDIO_PWRDN_NET 1 2 HDA_SPKR_R R9E15 NO_STUFF 0 6
HDA_SPKR 23,44
3 4 0 HDA_SDIN3 R9E13 HDA_SDIN3_R1 4 3
-s
R9E11 5 6 NO_STUFF 0 2 1
21 HDA_SDIN2
0 7 8 HDA_DOCK_EN#_J .R9E17 R9E10 HDA_SDIN3_R2
21,44 HDA_DOCK_RST# HDA_DOCK_EN# 21,41
0 NO_STUFF 0 2X8_HDR_KEY12
. J9E4
R9E16 8Pin HDR .
10K These Resistors need to be Mounted
5% appropriately when SDIN2 & SDIN3 need to get
. tested using the MDC.
p
Layout Note:
Place both headers in-line and
exactly 200 mils from each other, To use iHDMI,
pin-to-pin. Draw one silkscreen Must STUFF: R7V23, R7V8, R7V3, R7V4, R5F9.
box around both parts. Must NO_STUFF: R7G3, R7G2, R7V7, R7G11, R9E13, R9E10, R9E14, R9E12, R9E8,
o
To use eHDMI (on SDIN3)
t
Must NO_STUFF: R7V23, R7V8, R7V3, R7V4, R5F9, R9E14, R9E12, R9E8,
Must STUFF: R7G3, R7G2, R7V7, R7G11, ONE of R9E13 OR R9E10 depending on the add-in-card.
HDA Docking Circuit
B B
p
R9N3
20K
l. a
HDA_SDATAIN_DOCK 44
HDA_DOCK_EN#
+V5 32,42,43,48,52,55,56,57
C9B3
0.1uF
21,24,28 +V3.3S_1.5S_HDA_IO 21,24,28 +V3.3S_1.5S_HDA_IO U9B2 20%
HDA_DOCK_EN# 1 8
21,24,28 +V3.3S_1.5S_HDA_IO OE1# VCC
2 7
1A OE2#
w
C9D4 C9E1 HDA_DOCK_SDATAIN 3 6
0.1uF 0.1uF 1B 2B
4 5
C9D3 U9D2 20% U9E1 20% GND 2A
0.1uF 1 6 1 6 74CBT3306
U9D1 20% OE# VCC OE# VCC
1 6 HDA_CODEC_0_1_2_SYNC 2 5 HDA_CODEC_0_1_2_SDATAOUT 2 5
OE# VCC A NC A NC
w
HDA_CODEC_0_1_2_CLK 2 5 3 4 R9D8 33 3 4 R9E3 33
A NC GND Y HDA_SYNC_DOCK 44 GND Y HDA_SDO_DOCK 44
3 4 R9D4 33 NC7SV125L NC7SV125L HDA_SDO_R
GND Y HDA_BCLK_DOCK 44
HDA_SYNC_R
NC7SV125L HDA_BCLK_R
R9E4
w
A R9E1 20K A
20K Pillar Rock Intel Confidential
R9D6
20K Title
High Definition Audio

A 355659 1.0
5 4 3 2 1
5 4 3 2 1
o m
. c
D D
Power Supply for High Definiton Audio
it c s
19,21,23,24,25,26,27,29,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57 +V3.3A
R8T2
10K
5%
19,21,23,24,25,26,27,29,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57 +V3.3A .
a
+V1.5A_HDA_IO
U8E1 SC1563 10 +V1.5S_LDO_QDAC
5 Q8D1
IN
4 6 SI3442BDV
SC1563_SHDN
C8T1 OUT
1 SHDN 5 4
1.0uF 2
10% GND ADJ R8T1 C8E1 1
2.55K
m
C8T2 0.1uF
2 3 1% 22uF
. 10% +V5S
3
.
HDA_IO_ADJ
3
e
C8D6
C Q8T1 R8T5 R8T4 . 0.01UF C
BSS138 100 10K 10%
1%
45,56 VR_ALW_ENABLE 1
c h
- s
p
Selection of I/O Voltage for the High Definition Audio
to
4,10,11,24,47,55,57 +V1.5S
5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,30,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57 +V3.3S
B +V3.3A +V1.5A_HDA_IO B
p
21,24,27 +V3.3S_1.5S_HDA_IO
la
24,27,44 +V3.3A_1.5A_HDA_IO
NO_STUFF
NO_STUFF
.
R7H2 0.002
R8E8 0.002 1%
1% R7H3 0.002
R8E7 0.002 1%
1%
w
Layout Notes:Place the Two Resistors Next
Layout Notes:Place the Two Resistors Next to each Other
to each Other
w w Pillar Rock
Title
Size
A
Date:
HDA Power Supply
Document Number
355659
Tuesday, August 28, 2007 Sheet 28

Intel Confidential
of 58
Rev
1.0
A
5 4 3 2 1
5 4 3 2 1
19,21,23,24,25,26,27,28,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57 +V3.3A Header-1: FPIO - Port 1, 3
m
+V5A 24,34,38,44,46,47,50,51,56,57
+V5A_L_USBPWR_PN1_PN3
2
RP3B1A RP3B1B J6H4
10K 10K 1 2
o
22 USB_PN1 3 4 USB_PN3 22
R3B3 5 6
22 USB_PP1 USB_PP3 22
7
0.002 7 8
USB_OC#0 22
1% 10 +V3.3A
c
U3N2 USB_2X5-Header
1 8 +V5A 24,34,38,44,46,47,50,51,56,57
+V5A_USBPWR_IN3 GND OC1# +V5A_USBPWR_PN0 FB3N3 50OHM +V5A_L_USBPWR_PN0 Header-1
2 7
.
IN OUT1
2
R3B8 EN1_A 3 6 +V5A_USBPWR_PN2 FB3M1 50OHM +V5A_L_USBPWR_PN2
D C3B4 R3B7 1K EN2_A 4
EN1 OUT2
5 RP5W1A RP5W1B D
1K EN2 OC2# USB_OC#2 22
0.1uF . + C3A3 + C3B2 10K 10K
220uF 220uF USB_OC#1 22
20% . TPS2052B
20% 20% R5W15
s
. .
7
0.002
L3B4 1% U5H4
1 4 1 8 FB6H2
22 USB_PN0 GND OC1#
USBA- +V5A_USBPWR_IN1 2 7 +V5A_USBPWR_PN1_PN3 +V5A_L_USBPWR_PN1_PN3
USBA+ R5W18 EN1_C IN OUT1
2 3 Quadraple USB 3 6
it c
22 USB_PP0 1K EN1 OUT2
R5W19 EN2_C 4 5 50OHM + C6H2
Connector 1K EN2 OC2# USB_OC#3 22 220uF
90@100MHz . C6H3
24,34,38,44,46,47,50,51,56,57 +V5A C5W9 TPS2052B 20% 470PF
U3A4 C3M6
Ports 0,2,4,6 0.1uF
. .
B1 470PF C3N1 J3A1 10%

ESD_CH2 ESD_CH1 A2 470PF .
41 VCC1 TOP GND5 1 Header-2: FPIO - Port 5, 7
A1 V- V+ B2 42 P#0 GND6 2
43 PORT 3
CM1230_02 P0 GND7 +V5A_L_USBPWR_PN5_PN7
44 GND1 GND8 4
L3B3
GND9 5
a
1 4 31 6 J6H2
22 USB_PN2 VCC2 GND10
USBB- 32 1 2
USBB+ P#1 UPPERMIDDLE
22 USB_PP2 2 3 33 P1 22 USB_PN5 3 4 USB_PN7 22
34 PORT 5 6
GND2 22 USB_PP5 USB_PP7 22
90@100MHz U3A3
24,34,38,44,46,47,50,51,56,57 +V5A 7 8
B1 ESD_CH2 ESD_CH1 A2 21 VCC3 10
22 LOWERMIDDLE +V3.3A
P#2 PORT
A1 B2 23 USB_2X5-Header
V- V+ P2
24
m
CM1230_02 GND3 +V5A 24,34,38,44,46,47,50,51,56,57 Header-2
4
L3B2
11 VCC4
12 BOTTOM RP5W1C RP5W1D
C3M2 P#3 PORT 10K 10K
22 USB_PN4 1 4 13 P3
USBC- C3M1 14 GND4
e
2 3 USBC+ 470PF R7H5
22 USB_PP4 USB_OC#5 22
5
470PF QUAD_stack_USB 0.002
C 90@100MHz 24,34,38,44,46,47,50,51,56,57
U3A2 +V5A 1% C
B1 ESD_CH2 ESD_CH1 A2 U6H2
1 8 FB6H1
Layout Note: +V5A_USBPWR_IN2 GND OC1# +V5A_USBPWR_PN5_PN7 +V5A_L_USBPWR_PN5_PN7
A1 B2 2 7
h
V- V+ Place ESD diodes as R6W2 EN1_D IN OUT1
L3B1
3 EN1 OUT2 6
CM1230_02 close to the connector R6W3 1K EN2_D 4 5 50OHM + C6H1 C6W7
as possible. 1K EN2 OC2# USB_OC#7 22 220uF
1 4 C7H5 . 470PF
22 USB_PN6 20%
USBF- 0.1uF TPS2052B
. .
2 3 USBF+ 10%
22 USB_PP6
c
.
Header-3: FPIO - Port 9, 11
90@100MHz
24,34,38,44,46,47,50,51,56,57
U3A1 +V5A +V5A_L_USBPWR_PN9_PN11
19,21,23,24,25,26,27,28,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57 +V3.3A B1 ESD_CH2 ESD_CH1 A2
J6J1
s
A1 V- V+ B2 1 2
3
22 USB_PN9_R_FPIO 3 4 USB_PN11 22
RP3B1C CM1230_02 5 6 USB_PP11 22
-
10K 7 8
USB_OC#4 22 10
U3N1
22 USB_PP9_R_FPIO
6
1 8 FB3N1 USB_2X5-Header
+V5A_USBPWR_IN3 GND OC1# +V5A_USBPWR_PN4 +V5A_L_USBPWR_PN4
2 IN OUT1 7
R3B10 EN1_B 3 6 +V5A_USBPWR_PN6 Header-3
p
R3B9 1K EN2_B EN1 OUT2 50OHM
4 EN2 OC2# 5
C3B3 1K
.
0.1uF . TPS2052B + C3A1 +V3.3A
20% +V3.3A 220uF
20% +V3.3A
.
to
5
R7W2
RP3B1D +V5A 24,34,38,44,46,47,50,51,56,57 10K
5%
10K
R7W4
FB3N2 10K
4
+V5A_L_USBPWR_PN6 5%
B 22 USB_OC#6 B
R7H15 R7W1
0 USB_OC#9 22
50OHM 0.002
p
19,21,23,24,25,26,27,28,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57 +V3.3A 1% 5%
+ C3A2 U7H2 NO_STUFF
220uF 1 8 USB_OC#9_R_2052 FB7H1
20% +V5A_USBPWR_IN4 GND OC1# +V5A_USBPWR_PN9_PN11 +V5A_L_USBPWR_PN9_PN11
. 2 IN OUT1 7
R7W6 EN1_F 3 6
R4A2 R4A3 R7W5 1K EN2_F EN1 OUT2 50OHM + C7J1 C6J1
la
4 EN2 OC2# 5 USB_OC#11 22
10K 10K C7H9 1K 220uF 470PF
5% 5% . 20%
0.1uF . TPS2052B .
10%
.
.
USB_OC#8 22
U4A2
1 8 FB4M1
+V5A_USBPWR_IN3 GND OC1# +V5A_USBPWR_PN8 +V5A_L_USBPWR_PN8
2 IN OUT1 7
R4M6 EN1_E 3 6 +V5A_USBPWR_PN10
C4M5 R4M5 1K EN2_E EN1 OUT2 50OHM + C4A3 C4M3 USB Port Routing Locations
1K
4 EN2 OC2# 5 USB_OC#10 22 220uF
RJ45 1000 with Dual EHCI USB Port Location
0.1uF . 470PF
20% TPS2052B 20% USB Connector USB Port 0 Back of Chassis
w
. .
USB Port 1 FPIO/Duckbay
J5A1B USB Port 2 Back of Chassis
L5B2 USB Port 3 FPIO/Duckbay
1 VCC1
1 4 USBD- 2 0 USB Port 4 Back of Chassis
22 USB_PN8 P0# USB Port 5 FPIO/Duckbay
USBD+ 3 P0 USB Port 6 Back of Chassis LAYOUT NOTE FOR ESD DIODE: CM1230
22 USB_PP8 2 3 4 GND1 USB Port 7 FPIO/Duckbay Need to have minimum of 150mil clearance step down stencil definition around the ESD
USB Port 8 Back of Chassis
w
FB4M2 diodes CM1230 in layout too. Step down stencil area can accomodate other components. If needed,
90@100MHz USB Port 9 Docking/FPIO/Duckbay
+V5A_L_USBPWR_PN10 5 area for step down stencil definition can even be extended to cover other nearby components to avoid
VCC2 1 USB Port 10 Back of Chassis step down area covering the components half way, meaning, if extended
USBE- 6 P1# USB Port 11 FPIO/Duckbay step down area should cover other nearby coponents fullly.
24,34,38,44,46,47,50,51,56,57 +V5A 50OHM + C4A6 C4M7 USBE+ 7
U5B1 220uF 470PF P1
20%
8 GND2
B1 ESD_CH2 ESD_CH1 A2 .
RJ45 1000 WITH DUAL USB
w
A1 B2
A V- V+
Ports 8,10 A
L5B1 CM1230_02
22 USB_PN10 1 4 Pillar Rock Intel Confidential
22 USB_PP10 2 3 Title
90@100MHz USB 1.1/2.0
24,34,38,44,46,47,50,51,56,57 +V5A
U5A1
B1 ESD_CH2 ESD_CH1 A2 Size Document Number Rev
USB FPIO Header to PCIe connector mapping
A1 B2 USB Header USB Port PCIESlot 355659 1.0
V- V+ Header-1 Port 1 & Port 3 Slot 1 & Slot 2
CM1230_02 Header-2 Port 5 & Port 7 Slot 3 & Slot 4
Header-3 Port 9 & Port 11 Date: Tuesday, August 28, 2007 Sheet 29 of 58
5 4 3 2 1
5 4 3 2 1
SATA Port-0,Direct Connect
m
5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57 +V3.3S
Interlock Switch to SATA port 0 R7H9
o
5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,31,32,35,36,38,39,40,41,43,48,49,52,55,56,57 +V3.3S R8Y1 0.002 +V3.3S_SATA_P0 43K
1% SATA Device Status J7H1
16,19,27,31,55,57 +VBATS C8J3 Presence Shunt (Default)
C8J2 0.1uF Removed No Shunt
22uF 10% 23 SATA_DET#0
+V3.3_SATA_EN0_4
2
R8H13 .
5
6
7
8
1M This jumper simulates the drive status. For proper function J7H1
Q9Y1 of the hot plug, this jumper must be "No Shunt" when drive
.
is removed and "Shunt" after the drive is plugged in.
D R8H10 D
1
IRF7835
SATA_3.3_EN0 4
SATA Port 0,
s
1M C9Y1 Direct Connect
1
2
3
. 1000pF
10% J8J1
21 SATA_TXP0 2 TX GND_2M_S_1 1
3 4
it c
21 SATA_TXN0 TX# GND_2M_S_4
5 RX# GND_2M_S_7 7
21 SATA_RXN0
6 RX
21 SATA_RXP0
8 V_3.3_1 GND_1M_P_4 11
9 V_3.3_2 GND_2M_P_5 12
5,11,12,16,17,18,24,28,31,32,39,48,49,52,55,56,57 +V5S R8J2 4.3 V_3.3_3_PC 10 13
V_3.3_3_PC GND_2M_P_6
R8Y2 1 V_5.0_7_PC 14 V_5.0_7_PC
15 V_5.0_8
16 V_5.0_9 GND_2M_P_10 17
a
R8W12 C8W4 TP_SATA_RESEV 18
1000pF TP9H1 P_RESERVE_11
1M 1
. 10% NO_STUFF V_12_13_PC 20 19
R8W11 V_12_13_PC GND_1M_P_12
21 V_12_14
SATA_5V_EN0_1 SATA_5V_EN0_2 2 R9Y1 22
5.1 V_12_15
3
SI4925BDY
1M Q8H4A Serial ATA Recepticle
3
. 4
m
Q7H2
BSS138 SI4925BDY
SATA_PWR_EN#0_5V Q8H4B 7 8
1
Layout Note:
Place this connector
2
on the edge of CRB
e
5 6 +V5_SATA_EN0_3 R8H12 0.002 +V5S_SATA_P0
C 1% C
1
+ C8J4 C8J5
C8J1 C8Y1 0.1uF 0.1uF
3
100uF 22uF 10% 10%
2
h
Q8J1 . .
BSS138
23 SATA_PWR_EN#0 1
2
c
R8J1
10K 25,26,31,32,43,55,57 +V12S
1%
s
R9H20 C9H5
-
1M 1000pF
2
10%
Q9H3
SATA_12V_EN0_1 R8H11 1M SATA_12V_EN0_2 1 SI2307DS
3
3
p
Q9H2
2N7002 +V12_SATA_EN0_3 R8W14 0.002 +V12S_SATA_P0
SATA_PWR_EN#0_5V 1 1% + C9J1 C9J2 C9J3
15uF 0.1uF 0.1uF
20% 20% 20%
2
t o
+V12S is only for desktop type SATA devices
B B
l. a p
SATA Port-5, eSATA
w
J7J1
21 SATA_TXP5 2 TX GND1 1
21 SATA_TXN5 3 TX# GND4 4
5 RX# GND7 7
21 SATA_RXN5
6 RX
w
21 SATA_RXP5
eSATA_Signal_Plug
w
A A

Title
SATA (1 of 3)

355659 1.0
5 4 3 2 1
5 4 3 2 1
m
SATA Port-1 and Port-2, Cable Connect
o
SATA Power Connector
. c
D D
5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,32,35,36,38,39,40,41,43,48,49,52,55,56,57 +V3.3S
s
+V3.3_SATA_EN1_3 R6J3 0.002
1%
C5J4
it c
C6J3 0.1uF
16,19,27,30,55,57 +VBATS 22uF 10%
.
R6J2
1M
+V3.3S
5
6
7
8
Q6Y1
a
SATA_PWR_EN#1_5V R6J1 SATA_3.3V_EN1_1 4 IRF7822
R9H15 1M .
1
2
3
43K C6J2
1000pF J5J1
10% +V3.3S_SATA_P1 1 6
V_3.3_1 GND_1
2 V_3.3_2 GND_2 7
23 SATA_DET#1
2
3 V_5_1 GND_3 8
J9H2 5,11,12,16,17,18,24,28,30,32,39,48,49,52,55,56,57 +V5S 4 9
m
V_5_2 GND_4
Interlock Switch to SATA port 1 5 10
1
V_12_1 GND_5
SATA Device Status J9H2 R4J5 C4Y4 SATA_POWER_CONNECTOR

1M
e
Presence Shunt (Default) 1000pF
5%
1
2
3
Removed No Shunt 10%
C . C
Q4Y1
SATA_5V_EN1_1 R4J6 5% SATA_5V_EN1_2 4
3
This jumper simulates the drive status. For proper function 1M SI4835BDY
of the hot plug, this jumper must be "No Shunt" when drive Q4J5
h
is removed and "Shunt" after the drive is plugged in. BSS138
1 .
5
6
7
8
2
3
c
Q4J3
J4J2
BSS138 +V5_SATA_EN1_3 R4Y4 0.002 +V5S_SATA_P1
23 SATA_PWR_EN#1 2 1 SATA_PWR_EN#1_J 1 1%
1
+ C5J6 C5J5
C5J8 C5J1 0.1uF 0.1uF
2
s
100uF 22uF 10% 10%
2
. .
R4J2
10K
-
1%
SATA Port-2 SATA Port-1 Jumper (J4J2)

Device not Hot 25,26,30,32,43,55,57 +V12S
p
connected plug/removal Shunt (Default)
thru cable supported
Device Hot R4J4

connected plug/removal No Shunt 1M C4Y3
1
2
3
thru cable not supported 1000pF
o
10% Q4J4
SATA_12V_EN1_1 R4J3 SATA_12V_EN1_2 4
SI4835BDY
t
1M
3
Q4J2 R4Y3 0.002 +V12S_SATA_P1

2N7002 1%
B SATA_PWR_EN#1_5V 1 + C5J7 C5J3 C5J2 B
5
6
7
8
15uF 0.1uF 0.1uF
p
20% 20% 20%
2
+V12_SATA_EN1_3
l. a
SATA Signal Connectors
w
SATA Port-1 SATA Port-4
J6J3 J6J2
21 SATA_TXP1 2 TX GND1 1 21 SATA_TXP4 2 TX GND1 1
21 SATA_TXN1 3 TX# GND4 4 21 SATA_TXN4 3 TX# GND4 4
w
5 RX# GND7 7 5 RX# GND7 7
21 SATA_RXN1 21 SATA_RXN4
6 RX 6 RX
21 SATA_RXP1 21 SATA_RXP4
SATA_Signal_Plug SATA_Signal_Plug
w
A A
Notes:
-- Both SATA Port-1 and SATA Port-2 share the same power connector, J5J1
-- Use Y-Cable available with Kit to feed the power from J5J1 to SATA Title
device on port-1 and SATA device on Port-2.
-- Connect Power cable first before connecting SATA signal cable. SATA (2 and 3 of 3)

355659 1.0
5 4 3 2 1
5 4 3 2 1
o m
. c
D D
Place close to PCI Edge
Connector
+V3.3S
s
NO_STUFF
TP8D2
it c
57 -V12S
Default is to use pin A11 as a +V5S power pin (R9N2
TP9D2 +V5_PCI +V12S_PCI stuffed)
+V3.3A Stuff R9N3 and unstuff R9N2 if using ATX power

+V5S_PCI supply directly on extension board.
+V5S_PCI
S9B1 DO NOT STUFF BOTH R9N3 AND R9N2 AT THE SAME TIME
TP9D1 +V3.3S_PCI B1 A1 +V3.3S_PCI
-12V GND(TRST#)
B2 GND(TCK) +12V A2
a
B3 GND1 INT#(TMS) A3 INT_PIRQH# 22
TP8D1 B4 A4
22 PCI_REQ#0 REQ#0(TDO) GNT#0(TDI) PCI_GNT#0 22
B5 +5V_1 +5V_5 A5
B6 +5V_2 INTA# A6 INT_PIRQC# 22
22 INT_PIRQE# B7 INTB# INTC# A7 INT_PIRQG# 22
B8 A8 5,11,12,16,17,18,24,28,30,31,39,48,49,52,55,56,57 +V5S
22 INT_PIRQF# INTD# +5V_6
B9 REQ#1(PRSNT1#) RSV3 A9 PM_CLKRUN# 23,38,40,43
22 PCI_REQ#1
B10 RSV1 +5V(+V_I/O3) A10
B11 A11 PM_SLP_S4#_R R9B1
m
22 PCI_GNT#1 GNT#1(PRSNT2#) +5V(RSV4)
B12 A12 0
GND2 GND13 R9B3
B13 GND3 GND14 A13 PM_S4_STATE# 23,40,43,44,55,57
B14 A14 NO_STUFF 0
.
+3.3V(RSV2) 3.3VAUX PCI_RST#_R R9P1
B15 GND4 RST# A15 PCI_RST# 22,41
B16 A16 0
36 CLK_PCI_PCIGOLDF CLK +5V(+V_I/O4)
e
B17 A17 PCI_GNT3 R9P2
GND5 GNT#5(GNT#) 0 PCI_GATED_RST# 41
B18 A18 . NO_STUFF
C 22 PCI_REQ#3
B19
REQ#5(REQ#) GND15
A19 C
+5V(+V_I/O1) PME# PCI_PME# 22,43
22 PCI_AD31 B20 AD31 AD30 A20 PCI_AD30 22
22 PCI_AD29 B21 AD29 +3.3V_11 A21
B22 A22 PCI_AD28 22
h
GND6 AD28
22 PCI_AD25 B24 AD25 GND16 A24
B25 A25 +V3.3S_PCI
+3.3V_2 AD24 PCI_AD24 22
B26 A26 +V3.3S
22 PCI_CBE#3 C/BE3# +3.3V(IDSEL)
22 PCI_AD23 B27 A27
c
AD23 +3.3V_12
B28 GND7 AD22 A28 PCI_AD22 22
B29 A29 R8P2
22 PCI_AD21 AD21 AD20 PCI_AD20 22
B30 A30 1K R8P3
22 PCI_AD19 AD19 GND17
B31 +3.3V_3 AD18 A31 PCI_AD18 22 10K
22 PCI_AD17 B32 AD17 AD16 A32 PCI_AD16 22 .
s
B33 A33
LVL_PCIRST#
22 PCI_CBE#2 C/BE2# +3.3V_13
B34 GND8 FRAME# A34 PCI_FRAME# 22
22 PCI_IRDY# B35 IRDY# GND18 A35
-
B36 +3.3V_4 TRDY# A36 PCI_TRDY# 22
22 PCI_DEVSEL# B37 DEVSEL# GND19 A37 3
B38 GND9 STOP# A38 PCI_STOP# 22
B39 A39 1 Q8P1
22 PCI_LOCK# LOCK# +3.3V_14
B40 A40 2N3904
22 PCI_PERR# PERR# SMBCLK SMB_CLK_A1 23,25,26,44
B41 A41 SMB_DATA_A1 23,25,26,44
p
+3.3V_5 SMBDAT 2
22 PCI_SERR# B42 SERR# GND20 A42
B43 +3.3V_6 PAR A43 PCI_PAR 22 PCI_GNT#3 22
22 PCI_CBE#1 B44 C/BE1# AD15 A44 PCI_AD15 22
22 PCI_AD14 B45 AD14 +3.3V_15 A45
+V5_PCI B46 A46
GND10 AD13 PCI_AD13 22
+V5 27,42,43,48,52,55,56,57
to
B49 GND11 AD09 A49 PCI_AD9 22
R8B3 0.002 +V5 +V5S
1% 5V KEY
NO_STUFF B52 A52
22 PCI_AD8 AD08 C/BE0# PCI_CBE#0 22 Place close to PCI Edge
B53 A53
NO_STUFF
B 22 PCI_AD7 AD07 +3.3V_16 Connector B
25,26,30,31,43,55,57 +V12S B54 A54 R9N1 R9B2
+3.3V_7 AD06 PCI_AD6 22
B55 A55 0.002 0.002
22 PCI_AD5 PCI_AD4 22
p
+V12S_PCI AD05 AD04 1% 1%
B57 A57 +V5S_PCI
GND12 AD02 PCI_AD2 22
R8B1 0.002 B58 A58
22 PCI_AD1 AD01 AD00 PCI_AD0 22
1% B59 A59
+5V(+V_I/O2) +5V(+V_I/O5)
B60 +5V(ACK64#) +5V(REQ64#) A60
C9E2 C9C3 C9C2 C9E3
la
B61 +5V_3 +5V (7) A61
C9B1 C9B2 B62 A62 22uF 0.1uF 0.1uF 0.1uF
C8B2 0.1uF 0.1uF +5V_4 +5V (8) 20% 20% 20%
10uF 20% 20% PCI_EXTENSION_GOLDFINGERS_5V
NO_STUFF
.
+V3.3 19,27,39,41,42,43,55,57
PCI - EDGE CONNECTOR
+V3.3S
(GOLDFINGER)
NO_STUFF
R9D5
0.002
1% R9D2
w
0.002
1% +V3.3S_PCI
C9D5 C9C4 C9D2 C9C1

22uF 0.1uF 0.1uF 0.1uF
w
20% 20% 20%
Place close to PCI Edge

Connector
w
A A

Title
PCI Edge Connector (Goldfinger)

355659 1.0
5 4 3 2 1
5 4 3 2 1
22,24,34,44,48,55,57 +V3.3M_WOL +V3.3M_LAN +V1.8_LAN 34 +V1.8_LAN_M
m
C8B1 Place crystal less than
27pF 0.75 (~1.9 cm) inches from
LAN Controller R7A2 R8A11
5% 1 2 1 2
. 0.002 0.002
4
Place GLAN_CLK series
o
Y8A1 resistor close to LAN +V3.3M_LAN
25MHZ Controller
EU8A1
1
C8A8 LAN_XTAL1 C8M11 C8A2
c
10 3
27pF LAN_XTAL2 XTAL1 VCC3P3[1] 0.1uF 4.7uF
9 46
XTAL2 VCC3P3[2] 10% 10%
5% 28
VCC3P3[3]
.
R8M6 33 GLAN_CLK_R 45
.
21 GLAN_CLK JKCLK
D D
50 5 +V1.0_LAN_M
21 LAN_RSTSYNC JRSTSYNC VCC1P0[1]
8
VCC1P0[2]
44 33
s
21 LAN_TXD2 JTXD2 VCC1P0[3] R8A3
LCI
43 38 +V1.0_LAN_M_IN 1 2
21 LAN_TXD1 JTXD1 VCC1P0[4]
42 0.002
21 LAN_TXD0 JTXD0
11
VCC1P8[1]
49 14
21 LAN_RXD2 JRXD2 VCC1P8[2]
it c
48 18
21 LAN_RXD1 JRXD1 VCC1P8[3] 34 +V1.8_LAN_M +V3.3M_LAN
47 19
21 LAN_RXD0 JRXD0 VCC1P8[4]
VCC1P8[5] 24
R8A12 4.99K RES_COMP 15 25
1% RSET VCC1P8[6]
VCC1P8[7] 30
22 GLAN_TXP 55 GLAN_RXP VCC1P8[8] 32
GLCI
56 54 R8M1
. 22 GLAN_TXN GLAN_RXN VCC1P8[9]
41 1K
C8M16 0.1uF C8M15 GLAN_RXP_C VCC1P8[10]
52 GLAN_TXP
22 GLAN_RXP 10% 0.1uF GLAN_RXN_C 53
a
22 GLAN_RXN . 10% GLAN_TXN DIS_REG1P0
DIS_REG1P0 34
Place C8M15 & C8M16 close . +V3.3M_LAN
to LAN Controller
31 CTRL_10_R R8M3 CTRL_10
CTRL10 0 R8M2
34 LAN_MDI0P 27 MDI_PLUS[0] 5%
26 29 CTRL_18 . R8A6 1K
34 LAN_MDI0N MDI_MINUS[0] CTRL18 10K NO_STUFF
5%
23
m
34 LAN_MDI1P MDI_PLUS[1] .
34 LAN_MDI1N 22 MDI_MINUS[1]
MDI
37 LAN_DIS R8A2
LAN_DIS# PM_LAN_ENABLE 23,40,43
21 0 +V3.3M_LAN
34 LAN_MDI2P MDI_PLUS[2]
34 LAN_MDI2N 20 MDI_MINUS[2] NO_STUFF
e
17 4 C9M3 C9M4 Place C9M3 & C9M4
34 LAN_MDI3P MDI_PLUS[3] LED0 LAN_LED_LNK#_ACT 34
C 34 LAN_MDI3N 16 MDI_MINUS[3] LED1 2 R9A7 5.1K 0.1uF 10uF close to pin3 C
LAN_LED_1000# 34 5% 10% 20%
LED2 1
LAN_LED_100# 34 . .
3
h
51 CTRL_18 1 Q9A2
NC BCP69
LAN_TEST_EN 36
TEST_EN
1V Source Stuff No_Stuff 2 4
c
13
R8A4 LAN_ATEST_N IEEE_TEST_N +V1.8_LAN
12
10K R8M10 LAN_ATEST_P IEEE_TEST_P IVRi R8M2 R8M3, R8M1, Q9A1
5% 0
.
R8M3, R8M1, Q9A1
s
NO_STUFF 40 IVRd (Default) R8M2 +V1.8_LAN
JTAG_TCK
JTAG
7 +V1.8_LAN_M
JTAG_TDI
6
JTAG_TDO
-
Layout Note: 39 C8M14 C8A5 C8M2 C8M12 C8M3 C8M9 C8M8 C8M7
Keep this resistor JTAG_TMS Place C8M14 close to PNP 10uF 10uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
35
on top side and JTAG_TRST Collector (pin4) 20% 80% 10% 10% 10% 10% 10% 10%
route differentially
57
VSS
p
+V3.3M_LAN +V3.3M_LAN +V3.3M_LAN IC,BOAZ,56QFN,11-28-06,LAN,R0p7 Place C8A5, C8M2, C8M12, C8M3, C8M9,
LAN_JTAG_TRST
LAN_JTAG_TDO
LAN_JTAG_TMS
LAN_JTAG_TCK
C8M8 & C8M7 close to LAN Controller

LAN_JTAG_TDI
(EU8A1)
o
R8A5 R9A2 R9A1
200 200 200
t
5% 5% 5%
NO_STUFF NO_STUFF NO_STUFF
B 34 +V1.8_LAN_M B
p
R9A8 5.1K C9M2 C9M1
5% 0.1uF 10uF Place C9M1 & C9M2
TP9A5 TP9A1 . 10% 20% close to pin3
R8A1 3 .
l. a
TP9A6 TP9A3 TP9A4 1K
NO_STUFF CTRL_10 1 Q9A1
NO_STUFF
NO_STUFF
NO_STUFF
NO_STUFF
NO_STUFF
BCP69
2 4
+V1.0_LAN_M
w
+V1.0_LAN_M
+V1.0_LAN_M_IN
Place C8M6 close to PNP C8M6 C8A1 C8M5 C8M13 C8M4

Collector (pin4) 10uF 10uF 0.1uF 0.1uF 0.1uF
20% 80% 10% 10% 10%
w
Place C8A1, C8M5, C8M13 & C8M4
close to LAN Controller
(EU8A1)
w
A A
Title
LAN Boazman

A 355659 1.0
5 4 3 2 1
5 4 3 2 1
33 +V1.8_LAN_M
44 +V1.8_VCT_LAN_DOCK
m
22,24,33,44,48,55,57 +V3.3M_WOL
R9C4
0
C9C5 C9C6 Place C9C5 & C9C6 close
0.01uF 0.01uF to docking connector
56
50
38
27
18
10
.
o
4
5
EU7A1 10% 10%
LAN_DOCK_EN#_R 17 48 .402 .402
VDD6
VDD5
VDD4
VDD3
VDD2
VDD1
VDD0
NC
SEL 0B1 LAN_MDI0P_Q_DOCK 44
1B1 47 LAN_MDI0N_Q_DOCK 44
2B1 43 LAN_MDI1P_Q_DOCK 44
33 +V1.8_LAN_M
c
42 LAN_MDI1N_Q_DOCK 44
3B1
37 LAN_MDI2P_Q_DOCK 44
4B1
33 LAN_MDI0P 2 36 LAN_MDI2N_Q_DOCK 44
A0 5B1
.
33 LAN_MDI0N 3 32 LAN_MDI3P_Q_DOCK 44
A1 6B1
D 33 LAN_MDI1P 7
A2 7B1
31 LAN_MDI3N_Q_DOCK 44
C5N1 C5A1 Place C5A1 & C5N1 close D
8 R5B1 0.01uF 0.01uF to RJ45
33 LAN_MDI1N A3
11 22 0 10% 10%
33 LAN_MDI2P A4 0LED1 LAN_LED_LINK#_DOCK 44 .402 .402
12 23
s
33 LAN_MDI2N A5 1LED1 LAN_LED_1000#_DOCK 44
33 LAN_MDI3P 14 52 LAN_LED_100#_DOCK 44 .
A6 2LED1 J5A1A
33 LAN_MDI3N 15
A7 LAN_RJ45_VCT
PI3L500 LAN Switch 9
VCC0
it c
19 46 LAN_MDI0P_Q 10
33 LAN_LED_LNK#_ACT LED0 0B2 0+
20 45 LAN_MDI0N_Q 11
33 LAN_LED_1000# LED1 1B2 0-
54 41 LAN_MDI1P_Q 12
33 LAN_LED_100# LED2 2B2 1+
40 LAN_MDI1N_Q 13
3B2 LAN_MDI2P_Q 1-
4B2 35 14 2+
34 LAN_MDI2N_Q 15
5B2 LAN_MDI3P_Q 2- ACTIVITY LED
6B2 30 16 3+
57 29 LAN_MDI3N_Q 17 Green = LINK UP
Layout Note: THRM 7B2 3- BLINKING = TX/RX ACTIVITY
This is thermal PAD of 25 LAN_LED_LNK#_ACT_Q 22,24,33,44,48,55,57 +V3.3M_WOL
a
IC (at bottom) and to 0LED2 LAN_LED_1000#_Q LAN_LED_LNK#_ACT_Q
26 19
GND10
GND11
GND12
GND13
be shorted to GND GND0 1LED2 LED_LINK#
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
51 LAN_LED_100#_Q 20 SPEED LED
2LED2 LAN_LED_100#_Q LED_ACT Off = Link 10 Mbps
21 LED_100#
LAN_LED_1000#_Q 22 Green = Link 100 Mbps
LED_1000# Orange = Link 1000 Mbps
1
6
9
13
16
21
24
28
33
39
44
49
53
55
8
U5M1
22,24,33,44,48,55,57 +V3.3M_WOL 18
VP
GND0
m
RJ45 1000 WITH DUAL USB
NO_STUFF
22,24,33,44,48,55,57 +V3.3M_WOL
R7A3
10K LAN_MDI0P_Q 1 10 LAN_MDI2P_Q
5% LAN_MDI0N_Q I/O1 I/O8 LAN_MDI2N_Q
2 9
e
LAN_MDI1P_Q I/O2 I/O7 LAN_MDI3P_Q
3 I/O3 I/O6 7
C C7M1 C7M4 LAN_MDI1N_Q 4 I/O4 I/O5 6 LAN_MDI3N_Q C
LAN_DOCK_EN#_R 0.1uF 0.1uF
R7A4 10% 10%
41 DOCK_LAN_EN#
0 . .
h
NO_STUFF
R7M8
VN
.
1K
5% ESD DIODE ARRAY
5
c
NO_STUFF
SPI Interface VCC

CS
MISO
GND
CLK
MOSI +V3.3M_SPI_CON
p
Mode
-s J9D1 J8C1 J9C1 +V3.3M_SPI_CON

.
o
LAYOUT NOTE: Normal 1-X All 1-X +V3.3M_SPI_CON +V3.3M_SPI_CON
At any time either U8B2/U8C3 or U8C1/U8C3 can be SPI ISP Conn pinout J8D2 Operation Open U8C4 U8C1
stuffed. 1 2 8 5 SPI1_SI_R 8 5 SPI0_SI_R
t
SPI_CS# SPI_CLK_SW Programing 1-2 1-2 1-2 C8P1 C8N3 VDD SI SPI1_SO_R VDD SI SPI0_SO_R
3 4 2 2
SPI_SO_SW 5 SPI_SI_SW R7F11 SPI0 3-X SO SPI_CS#1_CON SO SPI_CS#0_CON
U8B2/U8C3 R7T21 6 0.1uF 0.1uF
CE#
1
CE#
1
B 1 23 ICH_GPIO60
ICH_GPIO60_SPI
7 8 ICH_GPIO24_SPI
ICH_GPIO24 23Programing
10% 10% R8P5 SPI1_WP# 3
WP# SCK
6 SPI1_CLK_R R8N7 SPI0_WP# 3
WP# SCK
6 SPI0_CLK_R
B
HOLD# 16 CLK 5% 0 5% 0 1-2 1-X 1-2 . . 3.3K 3.3K
NO_STUFF 8Pin HDR NO_STUFF SPI1 2-3
p
VCC 2 15 DI R8P4 SPI1_HOLD#
7 4 R8N4 SPI0_HOLD#
7 4
22,24,33,44,48,55,57 +V3.3M_WOL 3.3K HOLD# VSS 3.3K HOLD# VSS
NC 3 14 NC SST SPI FLASH SST SPI FLASH
+V3.3M_SPI
NC 4 8 7 6 5 13 NC
R8R1
l. a
U8C1/U8C4 1 2 +V3.3M_SPI_CON OE#1
NC 5 12 NC 0.002
1 2 3 4
NC 6 11 NC J9D1 J8C1
R8P1 SPI_CS0#_PULLUP 1 2 SPI_CS#0_CON 1 R8R2
CS# 7 10 VSS 3.3K 2 SPI_CS# 100
+V3.3M_SPI_CON R8P7 SPI_CS1#_PULLUP 1 . 2 SPI_CS#1_CON 3
DO 8 9 WP# 3.3K .
J9C1. CON3_HDR SPI1_SI_R R8N6 47 SPI_SI_SW
SPI0_SI_R R8N2 47
w
C8N2 C9P1 24,29,38,44,46,47,50,51,56,57 +V5A 24,29,38,44,46,47,50,51,56,57 +V5A
0.1uF 0.1uF U8R1 SPI0_SO_R R8N8 15 1%
10% 10% C8R1 OE#1 1 1OE# VCC 8
. . 0.1uF 2 1A OE#1 SPI1_SO_R R8P8 15 1% SPI_SO_R R8P6 SPI_SO_SW
10%22 SPI_CS#0 SPI_CS#0_CON 2OE# 7 SPI_CS#1_CON 0
3 1B
. 2B 6 SPI0_CLK_R R8N3 47 5%
4 GND
2A 5 SPI_CS#1 22 .
w
SN74CBTD3306 SPI1_CLK_R R8N5 47 SPI_CLK_SW
U8B2 U8C3
SPI_CS#0_CON 7 16 SPI0_CLK_R SPI_CS#1_CON 7 16 SPI1_CLK_R
CS# CLK CS# CLK 24,29,38,44,46,47,50,51,56,57 +V5A
SPI0_SI_R 15 8 SPI0_SO_R SPI1_SI_R 15 8 SPI1_SO_R
DI DO DI DO U8D1
SPI0_WP# SPI1_WP# +V3.3M_SPI_CON OE#1
Pillar Rock
w
A 9 WP#
11
9 WP#
11 +V3.3M_SPI
1
2
1OE# VCC 14
13 OE#1 Intel Confidential A
74CBT3125
NC5 NC5 22 SPI_SO 1A 4OE#

SPI0_HOLD# 1 12 SPI1_HOLD# 1 12 SPI_SO_SW 3 12
HOLD# NC6 HOLD# NC6 1B 4A SPI_SI 22
NC7 13 NC7 13 OE#1 4 2OE# 4B 11 SPI_SI_SW
OE#1
Title
2 14 2 14 5 10
+V3.3M_SPI_CON VCC NC8 +V3.3M_SPI_CON VCC NC8
6
2A
2B
3OE#
3A 9 SPI_CLK 22
LAN Docking and SPI
3 3 7 8 SPI_CLK_SW
NC1 NC1 GND 3B
4 NC2 4 NC2 24,29,38,44,46,47,50,51,56,57 +V5A
5
6
NC3 GND 10 5
6
NC3 GND 10
NC4 NC4
32Mb SPI FLASH 32Mb SPI FLASH
C8R2
0.1uF
A 355659 1.0
10%
NO_STUFF NO_STUFF .
5 4 3 2 1
5 4 3 2 1
m
9,10,15,47,55 +V1.05M
CPU,MCH and XDP BCLK FREQUENCY
+V3.3M 13,14,15,23,55,57 SELECTION TABLE
o
+VDDIO_CLK FSC FSB FSA Host Clock
R5V12 0.002 VDD_CK505 R5V8 0.002
1% 1% frequency MHz
C6V8 C6W3 C6W4 C6W5 C6W1 C6V10 C5V7 C6V9 C6V7 BSEL2 BSEL1 BSEL0
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF C6V12 C6W2 C5V5 C5V6
1 1 100
c
C5W1 10% 10% 10% 10% 10% 10% 10% 10% 10% 10uF 10uF 10uF 10uF 0
4.7uF . . . . . . . . . 20% 20% 20% 20%
0 0 1 133
10% . . . .
.
D
.
0 1 1 166 D
0 1 0 200
C6W6
0.1uF 266
s
10% 0 0 0
.
1 0 0 333
Place each 0.1uF cap as close as
+VDDIO_CLK possible to each VDD_IO pin. Place 400
the 10uF cap on the VDD_IO plane. 1 1 0
it c
C6V13
1 1 1 Reserved
0.1uF
10%
.
CK505D
C5H1
QFN-64
0.1uF EU6H1
10% 56 45
VDD_CPU_I/O PCI_STOP# PM_STPPCI# 23,43
a
. 33 44
VDD_SRC0_I/O CPU_STOP# PM_STPCPU# 23,43
43 VDD_SRC1_I/O
52 58 CLK_CPU1 R6H11 0
VDD_SRC2_I/O CPU1_MCH CLK_MCH_BCLK 6
19 57 CLK_CPU#1 R6H10 0
VDD_I/O CPU1_MCH# CLK_MCH_BCLK# 6
C6V11 C6V6 27 .
4.7uF 0.1uF VDD_PLL3_I/O CLK_CPU0 R6H13
CPU0 61 . 0 CLK_CPU_BCLK 3
10% 10% 23 60 CLK_CPU#0 R6H12 0
VDD_PLL3 CPU0# CLK_CPU_BCLK# 3
. . 62 .
Y5H1 VDD_CPU CLK_SRC8_ITP R6H9
9 54 . 0
m
VDD_PCI SRC8/CPU_ITP CLK_XDP 20
2 1 4 53 CLK_SRC#8_ITP# R6H8 0
VDD_REF SRC8#/CPU_ITP# CLK_XDP# 20
46 VDD_SRC .
16 29 CLK_SRC2# R6G9 . 0
14.318MHZ VDD_48 SRC2# CLK_PCIE_3GPLL# 7
XTAL_OUT 28 CLK_SRC2 R6G10 0
SRC2 CLK_PCIE_3GPLL 7
XTAL_IN
.
e
R5G9 33 2 51 .
23 CLK_USB48 XTAL_OUT SRC7/CLKREQ_F# PCI0_OE#_R R6H14 475
3 50
C CLK_BSEL0 R5G8 2.2K FSA 17
XTAL_IN SRC7#/CLKREQ_E# CLK_SATA_OE# 23 C
C5W3 C5W4 USB/FS_A CLK_SRC7 R6H2 0
SRC11/CLKREQ_H# 40 CLK_SRC_DB800 36
33pF 33pF CLK_BSEL1 64 39 CLK_SRC#7 R6G19 0
FSB/TEST_MODE SRC11#/CLKREQ_G# CLK_SRC_DB800# 36
5% 5% .
h
. . CLK_BSEL2 R5H2 FSC CLK_SRC#4 R6G16
5 REF/FSC/TEST_SEL SRC4# 35 . 0 CLK_PCIE_PEG# 19
10K 34 CLK_SRC4 R6G15 0
SRC4 CLK_PCIE_PEG 19
R5W9 33 .
23 CLK_REF_ICH CLK_SRC#3 R6G7
. SRC3#/CLKREQ_D# 32 . 0 CLK_PCIE_XDP_3GPLL# 20
R5H3 33 8 31 CLK_SRC3 R6G8 0
CLK_PCIE_XDP_3GPLL 20
c
38 CLK_REF_SIO PCI0/CLKREQ_A# SRC3/CLKREQ_C#
+V3.3S .
R5H4 33 10 38 CLK_SRC#9 R6G18 . 0
43 CLK_REF_LPC PCI1/CLKREQ_B# SRC9# CLK_PCIE_DMI_LAI#
37 CLK_SRC9 R6G17 0
SRC9 CLK_PCIE_DMI_LAI
11 PCI2 .
R5G14 CLK_MCH_R_OE# 42 CLK_SRC#10 R6H5 . 0
7 CLK_MCH_OE# SRC10# CLK_PCIE_ICH# 22
-s
R5V9 475 R5G15 PCI1_R 12 41 CLK_SRC10 R6H3 0
10K PCI1 PCI3 SRC10 CLK_PCIE_ICH 22
475 1% . .
5% R5G13 22 PCI4_SRC5_EN CLK_SRC#6 R6H6
36 CLK_PCI
13 PCI4/SEL_LCDCLK# SRC6# 47 . 0 CLK_PCIE_SATA# 21
48 CLK_SRC6 R6H7 0
SRC6 CLK_PCIE_SATA 21
R5G11 22 PCIF5_ITP_EN 14 .
36 CLK_PCIF PCIF5/ITP_EN CLK_SS_CLK R6G12
23,36 SMB_CLK_M3
7 SCL LCDCLK/27M 24 . 0 DREFSSCLK 7
6 25 CLK_SS_CLK# R6G11 0
23,36 SMB_DATA_M3 SDA LCDCLK#/27M_SS DREFSSCLK# 7
.
R5G12 15 21 CLK_DOT96# R6G13 . 0 DREFCLK# 7
p
10K VSS_PCI SRC0#/DOT_96# CLK_DOT96 R6G14 0
5%
18 VSS_48 SRC0/DOT_96 20 DREFCLK 7
22 VSS_I/O .
26 VSS_PLL3 .
30 63 R6W1 0
VSS_SRC0 CKPWRGD/PD# CLK_PWRGD 23,36
36 VSS_SRC1
o
59 VSS_CPU CLK_PWRGD_R
49 VSS_SRC2 NC 55 .
1 VSS_REF
t
65 THERM
SLG8SP533
J5H1
B NO_STUFF 1 XTAL_IN_D R5W2 XTAL_IN B
0
p
5 3
2 4 R5W8 R5W6
NO_STUFF XTAL_OUT
5Pin_JACK 49.9 0
1% 3,4,20,39,43,52,54 +V1.05S_CPU
NO_STUFF NO_STUFF
l. a
R1G4
56
FSB Frequency Select: 3,4,20,39,43,52,54 +V1.05S_CPU

(Default
Setting)
CPU J1G5 -> 1-2 SPARE

Driven J1G3 -> 1-2
BSEL0_PULLUP
J1G1 -> 1-2 RP1F1D 5 4

NO_STUFF 0
J1G5 -> Open R1F2 R1G1 RP1U1D 5 4

1067 J1G3 -> 2-3 1K 1K 0
w
J1G1 -> 2-3
CLK_BSEL0
J1G5
3 CPU_BSEL0 1
J1G5 -> Open 2 R1G5 1K
FSB Speed J1G3 -> Open 3
(MT/s) J1G1 -> 2-3 MCH_BSEL0 7
800 RP1F1A 8 1
CON3_HDR R1G6 NO_STUFF 0
w
1K
J1G5 -> 2-3 RP1U1A 8 1
667 J1G3 -> Open 20 XDP_OBS0 XDP_BPM#3 3
0
J1G1 -> 2-3 J1G3
3 CPU_BSEL1 1
2 R1G3 1K
3 MCH_BSEL1 7
w
RP1F1B 7 2
A CON3_HDR NO_STUFF 0 A
CLK_BSEL1
20 XDP_OBS1
RP1U1B 7
0
2 XDP_BPM#2 3 Pillar Rock Intel Confidential
J1G1
1
Title
3 CPU_BSEL2
3
2 R1F1 1K CK505
MCH_BSEL2 7
RP1F1C 6 3
CON3_HDR NO_STUFF 0
CLK_BSEL2
RP1U1C 6 3
Custom 355659
20 XDP_OBS2 XDP_BPM#1 3
0
1.0
5 4 3 2 1
5 4 3 2 1
+V3.3S +V3.3S_DB800 CLK_PCIE_SLOT1 R7D4 49.9
m
CLK_PCIE_SLOT1# R7D5 49.9
R7C9 CLK_PCIE_SLOT2 R7D6 49.9
0.002 CLK_PCIE_SLOT2# R7D7 49.9
1% C7P3 C7P5 C7P2 C7P7 C7P6 CLK_PCIE_SLOT3 R7C6 49.9
. C7C2 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF CLK_PCIE_SLOT3# R7C7 49.9
o
22uF 10% 10% 10% 10% 10% U7C2 CLK_PCIE_SLOT4 R7D8 49.9
. . . . . R7P11 2 8 DIF0 R7C21 33 CLK_PCIE_SLOT4# R7D9 49.9
VDD1 DIF0 CLK_PCIE_SLOT1 25
10K 11 9 DIF#0 R7C22 33 CLK_PCIE_SLOT5 R7C10 49.9
VDD2 DIF#0 CLK_PCIE_SLOT1# 25
5% 19 6 CLK_PCIE_SLOT5# R7C8 49.9
VDD3 OE0# CLK_SLOT1_OE# 25
C7P4 CLK_PCIE_DOCK R7C4 49.9
c
. 31
0.1uF VDD4 DIF1 R7C23 33 CLK_PCIE_DOCK# R7C5 49.9
39 12 CLK_PCIE_SLOT2 25
10% R7C11 +V3.3S_DB800_VDDA VDD5 DIF1 DIF#1 R7C24 33
48 13 CLK_PCIE_SLOT2# 25
VDDA DIF#1
.
. 1 DB800_OEINV 40 14
OE_INV OE1# CLK_SLOT2_OE# 25
D C7P1 D
0.1uF 4 16 DIF2 R7C16 33
35 CLK_SRC_DB800 SRC_IN DIF2 CLK_PCIE_SLOT3 26
10% 5 17 DIF#2 R7C17 33
35 CLK_SRC_DB800# SRC_IN# DIF#2 CLK_PCIE_SLOT3# 26
. 15
s
OE2# CLK_SLOT3_OE# 26
5 23,35 SMB_CLK_M3 23
U7C1 AGND_DB800 SCLK DIF3 R7C25 33
23,35 SMB_DATA_M3 24 20 CLK_PCIE_SLOT4 26
SDATA DIF3 DIF#3 R7C26 33
21 CLK_PCIE_SLOT4# 26
DB800_PD DIF#3
2 4 26
PWRDWN OE3#
7 CLK_SLOT4_OE# 26
23,35 CLK_PWRGD
it c
DB800_SRC_STOP 27
+V3.3S_DB800 SRC_STOP DIF4 R7P2 33
30 CLK_PCIE_SLOT5 26
DIF4 DIF#4 R7P1 33
INVERTER 45 29 CLK_PCIE_SLOT5# 26
3 DB800_HIGH_BW# LOCK DIF#4
28 HIGH_BW# OE4# 43 CLK_SLOT5_OE# 26
DB800_SRC_DIV# 1 +V3.3S_DB800
SRC_DIV#
DIF5 34
R7P9 R7D2 R7P10 DB800_BYPASS#_PLL 22 33
10K 10K 10K BYPASS#/PLL DIF#5 DB800_OE5# R7C14 10K
OE5# 35
5% 5% 5% DB800_IREF 46 IREF
NO_STUFF . NO_STUFF 38
a
DIF6
3 GND1 DIF#6 37
R7C12 10 36 DB800_OE6# R7C13 10K
475 GND2 OE6#
18 GND3
25 42 DIF7 R7C18 33
GND4 DIF7 CLK_PCIE_DOCK 44
32 41 DIF7# R7C19 33
GND5 DIF#7 CLK_PCIE_DOCK# 44
47 GNDA OE7# 44 CLK_REQ#_DOCK 44
R7P8 R7C15 R7P14 R7P12 DB800
m
10K 10K 10K 10K R7P7
5% 5% 5% 5% 0
. . NO_STUFF .
.
AGND_DB800
e
C C
c h
5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,38,39,40,41,43,48,49,52,55,56,57 +V3.3S
5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,38,39,40,41,43,48,49,52,55,56,57 +V3.3S
U7E4
TP_OE 14
-s
OE PCIF_QA7 R7T6 33
13 CLK_PCIF_ICH 22
QA7
15 12 . CLK_PCIF_2Y2
VDD QA6
5 11
VDDA1 QA5 C7T16 C7T13 C7T12
6
VDDA2 QA4
8 . 0.01UF . 0.01UF . 0.01UF
p
23 7
VDDB1 QA3
24 4
VDDB2 QA2
3
QA1
o
Layout Note:
9 2 Series termination resistors should be placed
GND1 QA0
t
10
as close to the device as possible.
GND2 Place the 0.01uF decoupling capacitors closest.
19
B GND3
16 PCI_QB7 R7T9 15 B
QB7 CLK_PCI_SIODOCK 38
20
p
GND4 PCI_QB6 R7T10 33
17 . CLK_PCI_PCIGOLDF 32
QB6
18 PCI_QB5 R7T11 33
.
QB5 CLK_PCI_XDP
1 21 PCI_QB4 R7T15 33
.
INA QB4 CLK_PCI_SIO 38
l. a
35 CLK_PCIF
22 PCI_QB3 R7T7 33
QB3 . CLK_PCI_TPM 43
28
35 CLK_PCI INB PCI_QB2 R7T19 33
25
QB2 CLK_PCI_LPC 43
26 PCI_QB1 .
R7T18 33
QB1 CLK_PCI_KBC 40
27 .
QB0
MK74CB218B .
w w Pillar Rock
w
A Intel Confidential A
Title
DB800 & Buffers

A 355659 1.0
5 4 3 2 1
5 4 3 2 1
BOARD REVISION FAB ID Strapping Table
m
FAB_REV BOARD FAB
19,21,23,24,25,26,27,28,29,32,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57 +V3.3A 3 2 1 0
0 0 0 0 1
0 0 0 1 2
19,21,23,24,25,26,27,28,29,32,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57 +V3.3A 0 0 1 0 3
o
0 0 1 1 4
19,21,23,24,25,26,27,28,29,32,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57 +V3.3A
0 1 0 0 5
R9V5 R9V4 R9G22 R9G21 R9G4 0 1 0 1 6
10K 10K 10K 10K C9G2 1K 0 1 1 0 7
c
0.1uF 5% 0 1 1 1 8
.
NO_STUFF NO_STUFF NO_STUFF 20%
.
NO_STUFF U9G1 1 0 0 0 9
D 16
VDD RESET#
15 PCA9557_RST# 1 0 0 1 10 D
8 1 0 1 0 11
BOARD_ID0 VSS BOARD_ID0 1 0 1 1 12
6
BOARD_ID1 I/O0 BOARD_ID1
1 7
s
40,43,51,52 SMB_BS_CLK SCLK I/O1 1 1 0 0 13
BOARD_ID2 2 9 BOARD_ID2
40,43,51,52 SMB_BS_DATA SDATA I/O2 1 1 0 1 14
BOARD_ID3 10 BOARD_ID3
R9V8 A0_R I/O3 REV_FAB_ID0 1 1 1 0 15
3 11
R9V7 R9V10 0 A1_R A0 I/O4 REV_FAB_ID1 1 1 1 1 16
4 12
A1 I/O5
it c
10K R9V6 R9G19 R9G18 R9V9 0 A2_R 5 13 REV_FAB_ID2
10K 10K 10K 0 A2 I/O6 REV_FAB_ID3
. 14
I/O7
. .
. . . . PCA9557PW
BOARD REVISION Strapping Table
BOARD REVISION BOARD ID
8-bit I/O Port Expander 3 2 1 0
0 0 0 0 Pillar Rock
a
0 0 0 1 Silver Cascade
0 0 1 0 Fern Hill
0 0 1 1 STHI CPV-MCH DDR2
FAB REVISION 0 1 0 0 STHI CPV-MCH DDR3
0 1 0 1 STHI CPV-ICH DDR2
19,21,23,24,25,26,27,28,29,32,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57 +V3.3A 0 1 1 0 STHI PPV-PGA DDR2
0 1 1 1 Sundial
slave address
m
1 0 0 0 TBD
1 0 0 1 TBD
0 0 1 1 A2 A1 A0 R/W 1 0 1 0 TBD
1 0 1 1 TBD
e
R9G7 R9G12 R9G8 R9G9 fixed programmable
C 10K 10K 10K 10K 1 1 0 0 TBD C
5% 5% 5% 5% 1 1 0 1 TBD
PCA9557 Address 1 1 1 0 TBD
NO_STUFF NO_STUFF . NO_STUFF
1 1 1 1 TBD
h
REV_FAB_ID0
REV_FAB_ID1
REV_FAB_ID2
c
REV_FAB_ID3
R9G13 R9G20 R9G14 R9G15
s
10K 10K 10K 10K
5% 5% 5% 5%
. . .
-
NO_STUFF
o p
t
B B
l. a p
w w
w
A A
Title
I/O Port Expander

A 355659 1.0
5 4 3 2 1
5 4 3 2 1
5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,39,40,41,43,48,49,52,55,56,57 +V3.3S
+V3.3S
m
+V3.3S
+V3.3S_SIO SMSC PORT-SWITCH
o
R8T8 R8E6 C7T11 C7T17
10K 10K R8T7 0.1uF R7T17 0.1uF
U7E3 5% 5% 10K 20% 10K 20%
5% 5%
c
5 64 LPC_AD0 21,40,43
VCC1 LAD0
5
+V3.3A 17 2 U8E5
VCC2 LAD1 LPC_AD1 21,40,43
5
31 4 U8E4 1
VCC3 LAD2 LPC_AD2 21,40,43 43 LPC_DRQ#0
.
POWER & GROUND
42 7 LPC_AD3 21,40,43 43 TPM_DRQ#0 1 4 ICH_DRQ#0 21
VCC4 LAD3
D 60
VCC5 LFRAME
14
LPC_FRAME# 21,40,43
4 AND_DRQ#0 2 D
24 SIO_DRQ#0 2
LDRQ0 SIO_DRQ#1 74AHC1G08
48 12
3
VTR LDRQ1 SIO_RST# 74AHC1G08 +V3.3S
22
3
C7T6 PCI_RESET
8 25
VSS1 LPCPD PM_SUS_STAT# 23,40,43
LPC INTERFACE
0.1uF 20 16
VSS2 CLKRUN PM_CLKRUN# 23,32,40,43
R7T14 20% 29 19
VSS3 SER_IRQ INT_SERIRQ 23,40,43
8.2K 37 47 PM_RI_SIO R7T8 C7T7
VSS4 IO_PME PM_RI# 23,43
it c
45 21 0 R8E5 0.1uF
VSS5 PCI_CLK CLK_PCI_SIO 36 10K
62 10 20%
VSS6 LPC_CLK_33 CLK_PCI_SIODOCK 36 5%
SIO_14M 23 . CLK_REF_SIO 35
5
U8E3
39 RS232_EN 27 GPIO10 43 LPC_DRQ#1 1
39 IRDA_CIR_SLT 28 GPIO11 4 ICH_DRQ#1 21
30 63 D_LAD_0 2
23,40,43,44 SMC_EXTSMI# GPIO12/IO_SMI# DLAD(0)
TP_SIO_GPIO13 32 1 D_LAD_1
DOCKING LPC INTERFACE

LPCD_OPNREQ_OUT# GPIO13/IRQIN1 DLAD(1) D_LAD_2 74AHC1G08
33 3
3
GPIO14/IRQIN2 DLAD(2)
GENERAL PURPOSE I/O

34 6 D_LAD_3
39 RS232_RI#
a
GPIO15 DLAD(3) D_LFRAME#
43 LPCS_PME# 35 GPIO16 DLFRAME 13
LPCD_RI# 36 11 D_LDRQ1
LPCD_PWRGD GPIO17 DLDRQ1 D_CLKRUN
38 GPIO30 DCLKRUN 15
39 18 D_SER_IRQ
17 L_BKLTSEL1# TP_GPIO32 GPIO31 DSER_IRQ D_CLK_33
40 GPIO32 DLPC_CLK_33 9
R7T13 TP_GPIO33 41 26 D_CLK_14
100K LPCD_LPCPD# GPIO33 DSIO_14M
43
5% LPCD_LPCRST# 44
GPIO34 LPC HOT DOCKING
m
LPCD_PWREN# GPIO35 19,21,23,24,25,26,27,28,29,32,37,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57 +V3.3A
46 GPIO36
61 52 J9E3
17 L_BKLTSEL0# GPIO37 RXD1 SER_SINA 39
53 D_LAD_0 1 2 D_LAD_2
TXD1 SER_SOUTA 39
D_LAD_1 D_LAD_3
UART1
DSR1 54 SER_DSRA# 39 3 4
56 LPCD_PWRGD 5 6 LPCD_PWREN#
e
CTS1 SER_CTSA# 39
58 R9F11 7 8 LPCD_PCI_PME#
RI1 SER_RIA# 39
C 100K C
IR
UART2
49 59 D_LFRAME# 9 10 D_LDRQ1
39 IR_TXD IRTX2 DCD1 SER_DCDA# 39 5%
50 55 LPCD_SMC_EXTSMI# 11 12 LPCD_PD#
39 IR_RXD IRRX2 RTS1#/SYSOPT0 SER_RTSA# 39
51 57 D_CLKRUN 13 14 D_SER_IRQ
39 IR_MODE IRMODE/IRRX3 DTR1#/SYSOPT1 SER_DTRA# 39
15 16 LPCD_RST#
h
40 KSC_LPC_DOCK#
SIO1007-JV SER_DTRA# 17 18
SER_RTSA# 19 20 LPCD_OPNREQ#
21 22
D_CLK_33 23 24 D_CLK_14
c
2X12-HDR_SHRD
+V3.3S_SIO
5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,39,40,41,43,48,49,52,55,56,57 +V3.3S
-s
R7E4 SER_RTSA# R7E2 C9F1 0.1uF
10K 10K Base Address:
00 = 0x002E
R7E3
. SER_DTRA# R7E1
NO_STUFF 01 = 0x004E R9F8
10K 10K 10 = 0x162E 100K U9F1
11 = 0x164E 5% 5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,39,40,41,43,48,49,52,55,56,57 +V3.3S
1 4
GND VCC
. NO_STUFF
p
+V3.3S_SIO
Default: LPCD_OPNREQ# 2 3 LPCD_OPNREQ_OUT#
11= 0x164E IN OUT
MAX6816 R7T2 0.002
1%
o
C7T15 C7T14 C7T8 C7T10 C7T5
C7T1 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
22UF 20% 20% 20% 20% 20%
t
B B
LPC DOCKING
p
24,29,34,44,46,47,50,51,56,57 +V5A
+V3.3S C7T18
l. a
C7T2 19,21,23,24,25,26,27,28,29,32,37,39,40,41,43,44,45,46,47,48,50,51,52,55,56,57 +V3.3A 0.1uF Default:
0.1uF 20% 1 - 2
20%
R8E9
5
U7E1 10K J7E1

LPCD_LPCPD# 1 5% 1
7,19,22,25,26,41,57 PLT_RST#
4 LPCD_PD# . U7E5 2 SIO_RST#
PM_SUS_STAT# 2 LPCD_QSEN# 1 8 RST_PD 3
LPCD_PCI_PME# OE1# VCC
2 7
74AHC1G08 LPCD_RI# 1A OE2# SMC_EXTSMI# CON3_HDR
3 6
3
1B 2B
3
w
4 5 LPCD_SMC_EXTSMI# R7E5
Q8E5 GND 2A 10K
BSS138 74CBT3306 5%
LPCD_PWRGD 1
2
+V3.3S
w
C7T3
0.1uF
20%
5
U7E2
LPCD_LPCRST# 1
LPCD_RST#
w
4
A PLT_RST# 2
A
74AHC1G08
3
Title
R7T3 SIO
0
NO_STUFF
A 355659 1.0
5 4 3 2 1
5 4 3 2 1
+V3.3 19,27,32,41,42,43,55,57 +V3.3A +V3.3A In Ckt H8 Programming J7A1 and J8B2
m
Disable 1-2 (Default)
Enable 2-3 (In Ckt Programming)
RS-232 TRANSCEIVER
C7M6 C7M7
0.1uF C6A2 0.1uF C7N2
o
20% 22UF R7M11 +V3.3A 20% 22UF J8B2
10K U7B1 SERBUF_SOUTA# 1
5% C7B2 0.1uF C1+1 1 2 TX_OUT
26
. C1+ VCC 16
U6A1 R7M10 10%. SER_TX_OUT 3
10K C1-3 V_C_2 C7N1 0.1uF
c
3 2
VCC
SERBUF_C1+ SERBUF_V+ 5% R7M9 C1- V+ 10% CON3_HDR
28 27 . .
C6M8 C1+ V+ C7M5 R7A5 10K C7B3 0.1uF C2+4 V_C_6 C7B1 0.1uF
4 6
C2+ V-
.
0.1uF 0.1uF 10K 5% 10%
. 10%. J7A2 J7A1
D .10% SERBUF_C1- 24
C1- .10% 5% . C2-5 5
C2- 1 SERBUF_SINA# 1 D
. 2 2 RX_IN
12 13 SER_KBCPROG_RX_IN 3 SER_KBCPROG_RX_IN 3
38 RS232_RI# 40 KBC_PROG_RX# R1OUT R1IN
SERBUF_C2+ 1 3 SERBUF_V- 9 8 SER_EC_SCIF_RXD
s
C6M4 C2+ V- 40 EC_SCIF_RXD_TRANSC R2OUT R2IN SER_TX_OUT CON3_HDR CON3_HDR
40 KBC_PROG_TX# 11 14
T1IN T1OUT
3
0.1uF C6M3 10 7 SER_EC_SCIF_TXD
40 EC_SCIF_TXD_TRANSC T2IN T2OUT
10%
. SERBUF_C2- 2 0.1uF 15
Q7M1 C2- GND
.10%
it c
BSS138 1 SER_RIA 20 MAX3232_RS232_TRNCVR
19
R2OUTB
4 SERBUF_CTSA SERIAL PORT CONNECTOR
38 SER_CTSA# R1OUT R1IN
18 5 SERBUF_RIA
38 SER_RIA#
2
19,27,32,41,42,43,55,57 +V3.3 R2OUT R2IN SERBUF_SINA# J2A2A

38 SER_SINA 17 R3OUT R3IN 6
16 7 SERBUF_DSRA GND 5
38 SER_DSRA# R4OUT R4IN RI
15 8 SERBUF_DCDA SERBUF_RIA FB2A3A 1 8 60OHM-100MHZ SERPRT_RIA 9
38 SER_DCDA# R5OUT R5IN DTR
SERBUF_DTRA FB2A3B 2 7 60OHM-100MHZ SERPRT_DTRA 4
R7M6 14 9 SERBUF_DTRA SERBUF_CTSA FB2A3C 3 6 60OHM-100MHZ SERPRT_CTSA CTS 8
38 SER_DTRA# T1IN T1OUT TXD
1K 13 10 SERBUF_SOUTA# TX_OUT FB2A3D 4 5 60OHM-100MHZ SERPRT_TX_OUT 3
38 SER_SOUTA T2IN T2OUT RTS
12 11 SERBUF_RTSA SERBUF_RTSA FB2A5A 1 8 60OHM-100MHZ SERPRT_RTSA 7
38 SER_RTSA#
a
T3IN T3OUT RX_IN FB2A5B 60OHM-100MHZ SERPRT_RX_IN RXD
5% 2 7 2
SER_ON 23 SERBUF_DSRA FB2A5C 3 6 60OHM-100MHZ SERPRT_DSRA DSR 6
FORCEON SERBUF_DCDA FB2A5D 60OHM-100MHZ SERPRT_DCDA DCD
38 RS232_EN 22 FORCEOFF# 4 5 1
21 INVALID# GND 25
5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,40,41,43,48,49,52,55,56,57 +V3.3S 2IN1
R7M12
1K MAX3243
m
5% R4M3
0.002
1% IR
+V3.3S_IR
U4A1
e
R4M4 3.9 LED_A 1
C 5,11,12,16,17,18,24,28,30,31,32,48,49,52,55,56,57 +V5S LED_A C
2 IO_VCC
Spare C4M1 + C4A4 C4A1 IRDA_TXD 3
0.1uF 6.8uF 0.1uF TXD_IR
3 10% 38 IR_RXD 4 RXD
U1B3D .10% .10% 5
h
38 IR_MODE SD
6 VCC
R1P1 U1C1D_SPARE 11 + CIR_TXD 7
10K TXD_RC
13 8 9
R4A1 4.7 VCC_HSDL GND SHLD
10 -
c
R4M2 R4M1 HSDL-3021_021
SIO VID VOLTAGE TRANSLATION .
C4A2 + C4A5 10K 10K
LM339 C4A2,C4A5 Should be 0.1uF 6.8uF
12 near U4A1. 10%
.10%
-s
U4M1
5,11,12,16,17,18,24,28,30,31,32,48,49,52,55,56,57 +V5S 5,11,12,16,17,18,24,28,30,31,32,48,49,52,55,56,57 +V5S 1 6
38 IRDA_CIR_SLT S Y0
2 5
GND VCC
3 3 38 IR_TXD 3 4
U1B1A U1B1D A Y1
NON-INV DMUX C4M2
p
VID_COMP 5 + VID_COMP 11 + 0.1uF
2 SIO_VID0 13 SIO_VID3 10%
R1N17 1K VID_0_D 4 R1N18 1K VID_3_D 10 .
52 VR_VID0 - 52 VR_VID3 -
IRDA_CIR_SLT =0, then Y0=A, IRDA_CIR_SLT=1,then Y1=A.
o
LM339 LM339
12 12
5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,40,41,43,48,49,52,55,56,57 +V3.3S
t
B R1N12 R1N15 R1N22 R1N28 R1N32 R1N36 R1N43 B
5,11,12,16,17,18,24,28,30,31,32,48,49,52,55,56,57 +V5S 5,11,12,16,17,18,24,28,30,31,32,48,49,52,55,56,57 +V5S 330 330 330 330 330 330 330
p
3 3
LED_VID0
LED_VID1
LED_VID2
LED_VID3
LED_VID4
LED_VID5
LED_VID6
10K
10K
10K
10K
10K
10K
10K
U1B1B U1B3A
VID_COMP 7 + VID_COMP 5 +
l. a
1 SIO_VID1 2 SIO_VID4
R1N21 1K VID_1_D 6 - R1N38 1K VID_4_D 4 -
52 VR_VID1 52 VR_VID4
R1N13
R1N16
R1N23
R1N29
R1N33
R1N37
R1N44
2
CR1B1 CR1B2 CR1B3 CR1B4 CR1B5 CR1B6 CR1B7
LM339 LM339 GREEN GREEN GREEN GREEN GREEN GREEN GREEN
12 12
1
SIO_VID0
5,11,12,16,17,18,24,28,30,31,32,48,49,52,55,56,57 +V5S 5,11,12,16,17,18,24,28,30,31,32,48,49,52,55,56,57 +V5S
w
SIO_VID1
3 3
U1B1C U1B3B SIO_VID2
VID_COMP 9 + VID_COMP 7 + SIO_VID3

14 SIO_VID2 1 SIO_VID5
R1N26 1K VID_2_D 8 - R1P4 1K VID_5_D 6 - SIO_VID4
w
52 VR_VID2 52 VR_VID5
SIO_VID5
LM339 LM339
+V5S 5,11,12,16,17,18,24,28,30,31,32,48,49,52,55,56,57 12 12 SIO_VID6
3,4,20,35,43,52,54 +V1.05S_CPU
w
A A
5,11,12,16,17,18,24,28,30,31,32,48,49,52,55,56,57 +V5S Pillar Rock Intel Confidential
C1N2
0.1uF
C1N5
0.1uF VID_COMP
3
U1B3C
Title
20% 20% Legacy Support
VID_COMP 9 +
14 SIO_VID6
R1N41 R1P2 R1P3 1K VID_6_D 8
1K
1%
1K
1%
52 VR_VID6 - Size Document Number Rev
CAD NOTE: C1N8
Place near
.
0.1uF
.
LM339
A 355659 1.0
U1B1 & 20% 12
U1B3
5 4 3 2 1
5 4 3 2 1
41,42 +V3.3A_KBC
Boot Mode Programming Straps
m
P90-P92 needs to be at VCC for boot mode programming. They are
Y9G1 already pulled up in the design. MD0, MD1 needs to be at Vss.
1 2 System needs to supply +V3.3A to flash connector.
R9G6 R9G5 R9G3
10MHZ 240 240 240
o
C9G4 C9G3
J8G5 J8G3
LEDD1
LEDD2
LEDD3
18PF 18PF Mode Type MD1 MD2 NMI
Run Mode 0 1 0 X STUFFED

U9G2A Program Boot Block 0 1 1 STUFFED OPEN
2
MD1 E2 N1 CR9G2 CR9G3 CR9G1 Program Flash 0 1 1 STUFFED X
MD1 PA7/KIN15#/PS2CD KBC_GP_DATA 42
MD2 K1 M4 GREEN GREEN GREEN
MD2 PA6/KIN14#/PS2CC KBC_GP_CLK 42
LED_SCROLL
3 LED_CAPS
23,43,44,47,55,57 PM_SLP_M# E1
PH0/ExIRQ6#/TDPCYI2
D 7 PM_EXTTS#0_EC C4
PH3 PA3/KIN11#/PS2AD
N3 KBC_MOUSE_DATA 42 D
13,15 PM_EXTTS#0_DIMM0_1 D4 R2 KBC_MOUSE_CLK 42
1
J9F1 SMC_XTAL PH4 PA2/KIN10#/PS2AC
A2
SMC_EXTAL XTAL
1 B2 N2
LED_NUM
s
42 SMC_RST# EXTAL PA5/KIN13#/PS2BD KBC_KB_DATA 42
2 R1 KBC_KB_CLK 42
SMC_RES# PA4/KIN12#/PS2BC KBC_CAPSLOCK Q9G3
3 E3
RES# P95/IRQ14#
H2
F3 J4 KBC_SCROLLOCK BSS138
17 ALS_INTR# PH1/ExIRQ7#/TDPCKI2/TDPMCI2 P94/IRQ13#
3
CON3_HDR R9G16 100NMI_R F4 J3 KBC_NUMLOCK 1
42 SMC_INITCLK NMI P93/IRQ12#
it c
Q9G2
SMC/KSC J9F1 L13 KBC_SCANIN0 BSS138
2
P60/KIN0#
3
Enable 1-2 (Default) L14 KBC_SCANIN1 1
Disable 2-3 P61/KIN1# KBC_SCANIN2 Q9G1
39 EC_SCIF_RXD_TRANSC G4 P51/FRxD P62/KIN2# L15
G1 K12 KBC_SCANIN3 BSS138
39 EC_SCIF_TXD_TRANSC
2
P50/FTxD P63/KIN3# KBC_SCANIN4
37,43,51,52 SMB_BS_CLK F2 P52/SCL0 P64/KIN4# K13 1
K14 KBC_SCANIN5
P65/KIN5# KBC_SCANIN6
37,43,51,52 SMB_BS_DATA G2 J12
2
P97/SDA0/IRQ15# P66/IRQ6#/KIN6# KBC_SCANIN7
43,50 BC_ACOK H1 P96/PHI/EXCL P67/IRQ7#/KIN7# J13
43,51 SMB_BS_ALRT# J1 KBC_SCANIN[7:0] 42
a
H8_P91_IRQ1# P92/IRQ0# KBC_SCANOUT15
J2 P91/IRQ1# P27 F14
K4 E13 KBC_SCANOUT14
43,56 SMC_ONOFF# P90/IRQ2# P26
TP9G1 E15 KBC_SCANOUT13
NO_STUFF P25 KBC_SCANOUT12
41 GFX_PWRMN_EC N12 P70/AN0 P24 E14
R13 E12 KBC_SCANOUT11
41 CPU_VCC_R_EC P71/AN1 P23
P13 D15 KBC_SCANOUT10
23,32,43,44,55,57 PM_S4_STATE# P72/AN2 P22
R14 D14 KBC_SCANOUT9
41 VBRK_MON P73/AN3 P21
R9H13 NO_STUFF P14 D13 KBC_SCANOUT8
m
50 PSYS 43,56 ATX_DETECT# P74/AN4 P20 PM_LAN_ENABLE J8B1
0 R15 C15 KBC_SCANOUT7
41 CPU_ICC_R_EC P75/AN5 P17 Enable 1-2 (Default)
R9H11 EC_BRK_CURRENT_R N13 D12 KBC_SCANOUT6
51 EC_BRK_CURRENT P76/AN6 P16 Disable 2-3
0 PBATT_R P15 C14 KBC_SCANOUT5 J8B1
R9H7 NO_STUFF EC_THERM_STRAP P77/AN7 P15 KBC_SCANOUT4 PM_LAN_ENABLE_H8 1
50 PBATT P3 PA1/KIN9#/PA2DD P14 B15
.0 PM_LAN_ENABLE_H8 R3 B14 KBC_SCANOUT3 2
e
PA0/KIN8#/PA2DC P13 PM_LAN_ENABLE 23,33,43
A5 A15 KBC_SCANOUT2 3
5,43 CPU_TACHO_FAN P40/TMI0/TxD2/TCMCYI0 P12
C 43 IMVP_VR_ON
R9V11 IMVP_VR_ON_R B5 P41/TMO0/RxD2/TCMCKI0/TCMMCI0 P11 C13 KBC_SCANOUT1 C
0 C3 B12 KBC_SCANOUT0 CON3_HDR
R9G11 PM_THERM#_R P43/TMI1/SCK2/TCMCKI1/TCMMCI1 P10
5,12,23,43 PM_THRM# 12,43 MCH_TACHO_FAN B1 P44/TMO1/PWMU2B/TCMCYI2 KBC_SCANOUT[15:0] 42
0 . C2 D9
h
23,43,56 PM_RSMRST# P45/PWMU3B/TCMCKI2/TCMMCI2 P30/LAD0 LPC_AD0 21,38,43
5,43 CPU_PWM_FAN
D3 P46/PWX0/PWMU4B/TCMCYI3 P31/LAD1 C9 LPC_AD1 21,38,43
. 12,43 MCH_PWM_FAN C1 P47/PWX1/PWMU5B/TCMCKI3/TCMMCI3 P32/LAD2 A9 LPC_AD2 21,38,43
+V3.3S C11 B9
21,43 H_RCIN# PB5/DTR# P33/LAD3 LPC_AD3 21,38,43
41,43 SMC_RSTGATE# B11 D8 LPC_FRAME# 21,38,43
PB4/DSR# P34/LFRAME# PLT_RST_R
c
C8 R9H3 100
P35/LRESET# BUF_PLT_RST# 22,43
5,12,43 SMB_THRM_CLK A11 A8 CLK_PCI_KBC 36
R9H2 PB3/DCD#/PWMU1B P36/LCLK
5,12,43 SMB_THRM_DATA D10 D7 INT_SERIRQ 23,38,43
8.2K PB2/RI#/PWMU0B P37/SERIRQ
23,43 SMC_RUNTIME_SCI# A10 B7 PM_CLKRUN# 23,32,38,43
PB1/LSCI P82/CLKRUN#
23,38,43,44 SMC_EXTSMI# B10 D6 PM_SUS_STAT# 23,38,43
-s
PB0/LSMI# P83/LPCPD#
23,43 SMC_WAKE_SCI# C7
R9H1 H_A20GATE_R P80/PME#
21,43 H_A20GATE A7
0 P81/GA20
A6 KBC_PROG_RX# 39
P85/IRQ4#/RxD1
43,51 BS_DISA# D11 B6 SMB_CLK_ME 23,43
PB7/RTS# P86/IRQ5#/SCK1/SCL1
. 23,43 PM_BATLOW# A12 D5 SMB_DATA_ME 23,43
PB6/CTS# P42/SDA1/TCMCYI1
C6 H12 41,42 +V3.3A_KBC
39 KBC_PROG_TX# P84/IRQ3#/TxD1 PC7/TIOCB2/TCLKD/WUE15# BS_CHGB# 43,51
H13 BS_CHGA# 43,51
PC6/TIOCA2/WUE14#
p
41,43 RSMRST#_PWRGD 43,51 LIBP_BAT_SEL B3 H15 BS_CLR_LTCH# 43,51
PH5 PC5/TIOCB1/TCLKC/WUE13# R9H5
H14 SMC_LID 41,43
PC4/TIOCA1/WUE12#
26 EC_PCIE_SLOT4_VAUX_ON R7 G12 VIRTUAL_BATTERY 41
PG7/ExIRQ15#/ExSCLB PC3/TIOCD0/TCLKB/WUE11# 10K
P7 G13 ME_G3_TO_M1# 56
PG6/ExIRQ14#/ExSDAB PC2/TIOCC0/TCLKA/WUE10# 41,42 +V3.3A_KBC
17 ALS_CLK M8 G15 SMC_SHUTDOWN 43,56
PG5/ExIRQ13#/ExSCLA PC1/TIOCB0/WUE9#
o
17 ALS_DATA R8 G14 . DOCK_EXP_CPPE# 44
PG4/ExIRQ12#/ExSDAA PC0/TIOCA0/WUE8#
41 H8S_I2C_CLK P8
PG3/ExIRQ11#/SCL2
N9
PD7/AN15 M10
t
41 H8S_I2C_DATA PG2/ExIRQ10#/SDA2 BC_SHDN 50
R9 R8H1
+V3.3A
43,51 LIBP_CHG_EN_A PG1/ExIRQ9#/TMIY/TDPCKI1/TDPMCI1 PD6/AN14 N10 BS_DISB# 43,51
10K
P9
43,56 NETDETECT# PG0/ExIRQ8#/TMIX/TDPCYI1 PD5/AN13 R10 ALL_SYS_PWRGD_R R9G1
KSC_LPC_DOCK# 38
P10 ALL_SYS_PWRGD 23,43,47
B N5
PD4/AN12
R11 KBC_DISABLE# 0 . B
23,43,56 AC_PRESENT PF7/PWMU5A PD2/AN10
P5
PD3/AN11 N11
p
PF6/PWMU4A LAN_WOL_EN 23,43,55,57
2
R9G27 50 ICHRM
44 DOCK_PE_DET# R5 P11 .
PM_PWRBTN# 23,43
10K PF5/PWMU3A PD1/AN9
19,21,23,24,25,26,27,28,29,32,37,38,39,41,43,44,45,46,47,48,50,51,52,55,56,57 +V3.3A J8G6 KBC J8G6
M6
5% 50 VCHRM PF4/PWMU2A PD0/AN8 M11 NMI_GATE 42
41,42 +V3.3A_KBC Enable 1-X (Default)
. N6
44 PE_OPNREQ# PF3/IRQ11#/TMOX/TDPCKI0/TDPMCI0 Disable 1-2
R6
1
44 DOCK_SYS_PWRGD# PF2/IRQ10#/TMOY/TDPCYI0 KBC_FWE R9F10 4.7K
P6 K2
PF1/IRQ9#/PWMU1A PH2
l. a
23,43 SUS_PWR_ACK KBC_PE5 R9F4 4.7K
M7 L1
11,23,43,44,46,47,49,55,57 PM_SLP_S3# PF0/IRQ8#/PWMU0A ETRST# KBC_PE4 R9F2 4.7K
L2
PE4*/ETMS KBC_PE3 R9F3 4.7K
L4
PE3*/ETDO KBC_PE2 R9F5 4.7K R9F9
M1
PE2*/ETDI KBC_PE1 R9F6 4.7K 0
M2
PE1*/ETCK KBC_PE0 R9F7 4.7K
M3 NOTE: Stuff R9F9 for
PE0/ExEXCL
NO_STUFF write protect
+V3.3S
H8S2117 BGA176
R9W6 10K SMC_EXTSMI#
w
R9W3 10K SMC_RUNTIME_SCI#
R9G29 4.7K 5% ALS_DATA
R9G28 4.7K 5% ALS_CLK
57 +V3.3A
CPU Thermal Monitor Strap
w
R9V12 8.2K H8_P91_IRQ1#
+V3.3A 19,21,23,24,25,26,27,28,29,32,37,38,39,41,43,44,45,46,47,48,50,51,52,55,56,57
R9V15 8.2K ALS_INTR#
R9G24 10K DOCK_SYS_PWRGD# R9G26

100K +V3.3A_KBC 41,42
R9H12 10K PBATT_R NO_STUFF
w
A A
R8M8
.
10K PM_LAN_ENABLE EC_THERM_STRAP
R9F12 Shunt J8G5 as default and
. R9G2
R9W1 10K SMC_WAKE_SCI# 10K 4.7K as external programming
Title
.
R9V14 4.7K SMB_BS_DATA R9G23 Embedded Controller 1 of 2
100K MD1 MD2
R9V13 4.7K SMB_BS_CLK MD2 J8G3
2
Normal Operation 1-X

J8G5
R9V16 10K NMI_GATE Pullup = Disable J8G3 Advanced Single Chip Mode 1-2
Pull down = Enable A 355659 1.0
1
10K R9G25 AC_PRESENT

5 4 3 2 1
5 4 3 2 1
+V3.3A
m
19,27,32,39,42,43,55,57 +V3.3
40,42 +V3.3A_KBC
R8H8 0.002
1%
o
C8H2 C9W2 C9W1 C9V3 C9V2 C8H3 C9V4 R8W2 R8W1
22uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 10K 10K
10% 10% 10% 10% 10% 10%
. . . . . . Q8H2
BSS138
c
32 PCI_GATED_RST# 3 2 PCI_RST# 22,32
.
D Q8H3 D
BSS138
1
19 PLT_GATED_RST# 3 2
PLT_RST# 7,19,22,25,26,38,57
1
SMC_RSTGATE# 40,43
it c
+V3.3A_KBC 40,42
+V3.3A
U9G2B
10K R9H8 VIRTUAL_DOCK_DET# K15 A1
VIRTUAL_DOCK_DET# PJ7 VCC1
26 EC_PCIE_SLOT3_VAUX_ON J14 PJ6 VCC2 P1
10K R9C2 DOCK_PE_PWRGD# F15 P2
44 DOCK_PWR_EN# PJ5 VCC3
A14 J15 R9W2
44 DOCK_PE_PWRGD# PJ4 VCC4 45 +V5A3A_MBL_PWRGD RSMRST#_PWRGD 40,43
10K R7J1 HYBRID_GFX_SW C12 F1 VCL 0
44 DOCK_PE_RST# PJ3 VCL
C10 C9V1 CR4W1
44 DOCK_PE_QSEN# PJ2
B8 0.1uF 3 1 .
16 DOCK_CRT_EN# PJ1 56 ATX_PWROK
a
C5 D2 10%
34 DOCK_LAN_EN# PJ0 VSS1
D1 . BAT54
VIRTUAL_DOCK_DET# MCH_TSATN_EC VSS2
G3 PI7 VSS3 P4
HYBRID_GFX_SW H4 R4
SW9H1 PI6 VSS4
18 DOCK_TV_EN# H3 PI5 VSS5 F12
1 K3 PI4 VSS6 F13
2 51 LIBP_CHG_EN_B L3 PI3 VSS7 B13
3 M5 A13 49,52 GFX_VR_PWRIN R9W5 GFX_PWRMN_R_EC R9W4 100
m
PI2 VSS8 GFX_PWRMN_EC 40
N7 A4 0 1%
51 CHGA_EN# PI1 VSS9 5%
SPDT_SLIDE N8 B4 +V3.3A_KBC 40,42 . C9H1
51 CHGB_EN# PI0 VSS10 0.1uF
51 +VREF_ADC . 10%
A3 N14 LAYOUT NOTE: .
e
NC7 AVCC1 PLACE R, C close to
L12 NC6 AVCC2 N15
C M13 M14 For External H8 ADC monitor H8 input pins C
NC5 AVref1 NO_STUFF : R9W5 (Default STUFF)
M12 NC4 AVref2 M15
HYBRID_GFX_SW M9 STUFF : R1N27 AGND_VCORE
NC3
N4 P12
h
SW7J1 NC2 AVSS2
E4 NC1 AVSS1 R12
1
GND_SYS_CURRENT
2
3 H8S2117 BGA176
c
SPDT_SLIDE R9W7 CPU_VCC_EC R9H4 100
52 CPU_VCC CPU_VCC_R_EC 40
0 1%
5% C9H2
.
0.1uF
-s
. 10%
LAYOUT NOTE: .
PLACE R, C close to
+V3.3A 19,21,23,24,25,26,27,28,29,32,37,38,39,40,43,44,45,46,47,48,50,51,52,55,56,57 H8 input pins
For External H8 ADC monitor
NO_STUFF : R9W7 (Default STUFF) AGND_VCORE
STUFF : R2N19
R9H16 SW9H2
p
10K 1
40,43 SMC_LID 2
2
. 3
J9H3 J8F1
SPDT_SLIDE 16 15 R9W8 CPU_ICC_EC R9H6 100
56 ND_SW# RTC_RST# 21 52 CPU_ICC 0 CPU_ICC_R_EC 40
o
14 13 1%
1
HYBRID_GFX_SW 5% C9H3
12 11 VIRTUAL_BATTERY 40 NO_STUFF
10 9 0.1uF
t
8 7 HDA_DOCK_EN#_R R2F20 100K . 10%
23 BIOS_REC HDA_DOCK_EN# 21,27
6 .
4 3 LAYOUT NOTE:
B VIRTUAL_DOCK_DET# SMC_LID 40,43 For Internal H8 ADC monitor PLACE R, C close to B
2 1
STUFF : R9W8 (Default NO_STUFF) H8 input pins AGND_VCORE
p
2X8_HDR_KEY12 NO_STUFF : R1B4
52,55,56,57 +V3.3A
l. a
5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,43,48,49,52,55,56,57 +V3.3S
R9H18
10K
SW9H3
40 VIRTUAL_BATTERY
. 1
2
2
J9H4 3
R8H4
SPDT_SLIDE 24 +V1.05S_ICH R8H5 1K
1
1K 5%
5% .
MCH_TSATN_Q
.
w
R8H7 3 MCH_TSATN_EC
54.9
1% 5 CR8H1A
3904
4
R2P4 6
w
MCH_TSATN_R R8H6 330 MCH_TSATN_LVL 2 CR8H1B
7 MCH_TSATN#
50 +VAC_IN_L 3904
+V3.3A
19,21,23,24,25,26,27,28,29,32,37,38,39,40,43,44,45,46,47,48,50,51,52,55,56,57 +V3.3A +V3.3A 0 5% 1
.
1%
. C2Y1
0.1uF
w
A 15K C8G3 A
R2Y4
8 16V 10% 0.1uF
10% R8V8
R8V7
4.7K
R8V9
10K
.
4.7K 5% 1%
VBRK_MON_IN 3 +
U2J4A
VBRK_MON
.
U8V1
5% .
H8S_EEPROM_WP
NO_STUFF Title
1 VBRK_MON 40 .
R2Y5
2 - 1 A0 VCC 8 Embedded Controller 2 of 2
C2Y3 2 7
4.02K 1uF AD8552 A1 WP R8V6
1% 3 A2 SCL 6
20% 4 4 5 H8S_I2C_CLK 40 100
.
. GND SDA H8S_I2C_DATA 40 . Size Document Number Rev
AT24C02N
A 355659 1.0
GND_SYS_CURRENT

5 4 3 2 1
5 4 3 2 1
40,41 +V3.3A_KBC
m
40,41 +V3.3A_KBC
R9G10 100K
14 14 14 14
o
40,41 +V3.3A_KBC U9F2A U9F2B U9F2C U9F2E
J9G2
C9U1 R9H17 1M SMC_INIT_CLK1 1 2 SMC_INIT_CLK2 3 4 SMC_INIT_CLK3 5 6 11 10 SMC_INITCLK_J1 2 SMC_INITCLK 40
0.1uF
20% 74HC04 74HC04 C9G1 74HC04 74HC04
3 c
3
U9V1 14 . 4.7uF
U9F2D Q9H4 7 7 10% 7 7
VCC
.
BSS138 . Boot Block Programming
D RST#
2 SMC_RST#_D R9V3 100 9 8 SMC_RST 1 SMC_INIT_CLK4 R9V2 SMC_INITCLK# J9G2 D
100K Normal Shunt (Default)
GND
74HC04 . Program No Shunt
3
.
2
MAX809 R9V1 7 Q9H1 1Hz Clock J9H1
1
100K BSS138 J9H1 Disable Shunt
1 Enable No Shunt (Default)
SMC_RST# 40 40 NMI_GATE
1
it c
. NMI Jumper
2
NOTE: Shunt J9H1 for SMC Programming
40,41 +V3.3A_KBC
Circuitry provides an interrupt to the SMC every 1s 14

while in suspend (this allows the SMC to complete U9F2F
housekeeping functions while suspended)
R9F1 100 INVD2 13 12 TP_INVD2
a
. 74HC04
7
Spare gate
m
Scan Matrix Key Board
e
C KBC_SCANOUT[15:0] 40
C
J9E1
h
KBC_SCANOUT1 2 1 KBC_SCANOUT0
KBC_SCANOUT9 KBC_SCANOUT8
c
10 9
19,27,32,39,41,43,55,57 +V3.3 KBC_SCANOUT15 16 15 KBC_SCANOUT14
19,27,32,39,41,43,55,57 +V3.3
18 17
s
20 19
22 21
KBC_SCANIN1 24 23 KBC_SCANIN0
-
+V5_PS2 KBC_SCANIN7 30 29 KBC_SCANIN6
2x15-SHD-HDR
p
+V5_PS2
+V5_PS2
2
KBC_SCANIN[7:0] 40
F1A1
1
1.1A
3
to
RP1B1A +V5_PS2
4.7K RP1B1C
PS2_PWR_L + 1
4.7K
CBTD has integrated
8
FB1A2 diode for 5V to 3.3V

6
KBD_CLK FB1A4 voltage translation C9N1

B 1 KBD_DATA 0.1uF B
60ohm@100MHz
. 20%
p
CP1B1A 60ohm@100MHz
. .
47PF C1M1 U8B1
8 FB1A6 47pF 3 24
40 KBC_GP_DATA 1A1 VCC
31Ohm@100MHz +V5_PS2 4
40 KBC_GP_CLK 1A2
. 7 2 GP_DATA
40 KBC_MOUSE_DATA 1A3 1B1
la
L_KBD_DATA
+V5_PS2 8 5 GP_CLK
40 KBC_MOUSE_CLK 1A4 1B2
2
L_PS2_PWR 11 6 MOUSE_DATA
40 KBC_KB_DATA 1A5 1B3
RP1B1B 9 MOUSE_CLK
L_KBD_CLK
4.7K 1B4 KBD_DATA

4 40 KBC_KB_CLK 14 10
J1A1 2A1 1B5
17
.
2A2
4
6 2 18 15 KBD_CLK
7
RP1B1D 6 4 2 FB1A5 2A3 2B1

21 16
4.7K GP_DATA 2A4 2B2
5 1 22 19
5 1 2A5 2B3
20
FB1A7 60ohm@100MHz C1A6 2B4
13 3 . 23
5
GP_CLK 13 3 47pF OE#_PS2 2B5

14 1
14 1OE#
w
15 16 13 12
60ohm@100MHz 15 16 +V5_PS2 2OE# GND
. 17
17 R8N1 SN74CBTD3384
2 10
10 100 .
2
CP1B1B L_GP_CLK 12 8 L_GP_DATA

47PF 12 8 RP1B2B +V5_PS2 +V5 27,32,43,48,52,55,56,57 .
7 L_MOUSE_CLK 11 7 L_MOUSE_DATA 4.7K
w
11 7
9 R1A1 0.002
7
DUAL_PS2 FB1A3 MOUSE_DATA 1%

9
4
+V5_PS2 60ohm@100MHz
. .
CP1B1D
47PF
w
A A
1
5
RP1B2A Pillar Rock Intel Confidential
4.7K +V5_PS2
FB1A8
Title
8
PS2
3
5 RP1B2D 4
MOUSE_CLK
RP1B2C
C1A5 C1B1
4.7K
4.7K
3 60ohm@100MHz
. Spare 22uF 0.1uF
20%
CP1B1C . Size Document Number Rev
6
47PF
6 A 355659 1.0
5 4 3 2 1
5 4 3 2 1
+V3.3_LPCSLOT
m
+V3.3A LPC SLOT TPM HEADER
5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,48,49,52,55,56,57 +V3.3S
25,26,30,31,32,55,57 +V12S
+V12S 25,26,30,31,32,55,57 R9M2 0.002 +V3.3S_R1_TPM
o
+V3.3_LPCSLOT 19,21,23,24,25,26,27,28,29,32,37,38,39,40,41,44,45,46,47,48,50,51,52,55,56,57 +V3.3A 1% +V5 27,32,42,48,52,55,56,57
+V5_LPCSLOT R9A3 0.002 +V3.3A_R1_TPM +V5_R1_TPM R9M1 0.002

J8E1 1% 1%
C9A5 C9A4 C9A2
c
B1 A1
+V12S_1 +V12S_2 0.1uF 0.1uF 0.1uF
23 SUS_CLK B2 A2
SUSCLK_32KHZ NC1(-12V) 20% 20% 20%
B3 A3
GND1 GND2
.
12,40 MCH_TACHO_FAN B4 A4 PM_DPRSLPVR 7,23,52
TACHO_FAN PM_DPRSLPVR
D B5
+V3_3 +V3_1
A5 D
B6 A6 J9A1
NC7 NC2
B7 A7 36 CLK_PCI_TPM 1 2
GND3 GND5 LPC_FRAME#
B8 A8 3
s
NC8 NC3 BUF_PLT_RST#
B9 A9 5 6
40,56 NETDETECT# NC9(NETDETECT#) NC4 LPC_AD3 LPC_AD2
B10 A10 7 8
GND4 GND7 NO_STUFF TP9A2 LPC_AD1
B11 A11 9 10
40,51 LIBP_BAT_SEL LIBP_BAT_SEL LIBP_CHG_EN LIBP_CHG_EN_A 40,51 LPC_AD0
B12 A12 11 12
LPCSLOT_B12 NC10(CPU_PECI) NC5
it c
B13 A13 +V1.05S_CPU 3,4,20,35,39,52,54 13 14
GND6 +V5_1 19,23 SMB_CLK_S4 SMB_DATA_S4 19,23
B14 A14 +V1.05S_CPU_RSVD NO_STUFF R8F2 15 16 INT_SERIRQ
STPCLK#
R6V11 +V3ALWAYS NC6(VTTCPU) 0 PM_CLKRUN#
B15 NC11(STPCLK#) GND10 A15 17 18
3,21 H_STPCLK# 0 B16 A16 PM_SUS_STAT# 19 20
21,40 H_RCIN# CPU_RESET# SERIRQ INT_SERIRQ 23,38,40 TPM_DRQ#0 38
21,40 H_A20GATE B17 KBC_A20_GATE CLKRUN# A17 PM_CLKRUN# 23,32,38,40
NO_STUFF B18 A18 2x10-HDR_P4KEY
GND8 GND12
23,38,40,44 SMC_EXTSMI# B19 LSMI# PWM_FAN A19 MCH_PWM_FAN 12,40
+V5_LPCSLOT KEY
a
B20 +V5_3 +V5_2 A20
38 LPC_DRQ#1 B21 LDRQ1# LDRQ0# A21 LPC_DRQ#0 38
21,38,40 LPC_FRAME# B22 LFRAME# GND14 A22
B23 GND9 LAD3 A23 LPC_AD3 21,38,40
21,38,40 LPC_AD2 B24 LAD2 LAD1 A24 LPC_AD1 21,38,40
21,38,40 LPC_AD0 B25 LAD0 GND15 A25
B26 GND11 LCLK A26 CLK_PCI_LPC 36
B27 A27
m
22,40 BUF_PLT_RST# LRST# LPCPD# PM_SUS_STAT# 23,38,40
B28 GND13 GND16 A28
35 CLK_REF_LPC B29 OSC_14MHZ PME# A29 LPCS_PME# 38
B30 +V3_4 +V3_2 A30
60Pin_CardCon
e
C C
Note: LPC_SLOT_B12 , H_STPCLK# and +V1.05S_CPU have been
routed to LPC slot pins testing purpose.
19,27,32,39,41,42,55,57 +V3.3
Decaps for LPC Slots
c h
s
+V3.3_LPCSLOT
-
R8F1 0.002
1%
C8F1 C8G1 C8G2 C8E4
22uF 0.1uF 0.1uF 0.1uF
20% 20% 20%
p
+V5 27,32,42,48,52,55,56,57 CAD NOTE:
o
Place close to LPC Slot J8E1
+V5_LPCSLOT
t
R8E3 0.002
1%
C8E3 C8F2
B 22uF 0.1uF B
20%
LPC SIDE BAND HEADER
l. a p
w
J9G1
PM_RI# 23,38
1 2 NO_STUFF TP7E1
23,40 PM_PWRBTN# A1 A2 ALL_SYS_PWRGD 23,40,47 PM_STPCPU# 23,35
3 4 J1G2 NO_STUFF TP6G2
23,40,56 PM_RSMRST# A3 A4 IMVP_VR_ON 40 PM_STPPCI# 23,35
5 6 PM_DPRSLPVR 1 2 NO_STUFF TP6H1 PM_CLKRUN#
5,12,23,40 PM_THRM# A5 A6 CPU_PWM_FAN 5,40 H_DPRSTP# 3,7,21
7 8 3 4 NO_STUFF TP9B1
23,40 PM_BATLOW# A7 A8 CPU_TACHO_FAN 5,40 3,21 H_NMI H_DPSLP# 3,21 PCI_PME# 22,32
9 10 5 6 NO_STUFF TP9C1
11,23,40,44,46,47,49,55,57 PM_SLP_S3# A9 A10 ATX_DETECT# 40,56 3,21 H_SMI# H_CPUSLP# 3,6 PM_SLP_M# 23,40,44,47,55,57
11 12 7 8 NO_STUFF TP7B1
w
23,32,40,44,55,57 PM_S4_STATE# A11 A12 SMB_DATA_ME 23,40 3,21 H_PWRGD
23,33,40 PM_LAN_ENABLE 13 14 SMB_CLK_ME 23,40
A13 A14 8Pin HDR
15 16
A15 A16
23,40 SMC_RUNTIME_SCI# 17 18 SUS_PWR_ACK 23,40
A17 A18
23,40 SMC_WAKE_SCI# 19 20 AC_PRESENT 23,40,56
A19 A20
40,41 SMC_RSTGATE# 21 22 BC_ACOK 40,50
A21 A22
40,56 SMC_ONOFF# 23 24 PM_SLP_M# 23,40,44,47,55,57
A23 A24
w
25 26
A 40,41 SMC_LID
27
A25 A26
28
A
40,56 SMC_SHUTDOWN
29
A27
A29
A28
A30 30
BS_CLR_LTCH# 40,51
RSMRST#_PWRGD 40,41
5,12,40 SMB_THRM_CLK 31 A31 A32 32 BS_CHGA# 40,51
5,12,40 SMB_THRM_DATA 33 A33 A34 34 BS_CHGB# 40,51 Title
37,40,51,52 SMB_BS_CLK 35 A35 A36 36 BS_DISA# 40,51
37,40,51,52 SMB_BS_DATA 37 A37 A38 38 BS_DISB# 40,51 LPC Slot and TPM Header
40,51 SMB_BS_ALRT# 39 A39 A40 40 LAN_WOL_EN 23,40,55,57
LPC Sideband Header
A 355659 1.0
5 4 3 2 1
5 4 3 2 1
19,21,23,24,25,26,27,28,29,32,37,38,39,40,41,43,45,46,47,48,50,51,52,55,56,57 +V3.3A
PCI-Express Docking Interface
o m
R9C1 10K PE_OPNREQ#
5%
J9C2
c
S1 S99 PCIE_WAKE#_DOCK .
S1 S99
S2 S100 DOCK_PWR_EN# 41
S2 S100
.
22 USB_PN9_R S3 S101 CLK_REQ#_DOCK 36
S3 S101
D S4
S4 S103
S103 D
22 USB_PP9_R S5 S104 PCIE_TXP1_DOCK 22
S5 S104
S7 S105
S7 S105
S8 S107
s
S8 S107 PCIE_TXN2_DOCK 22
S9 S108 PCIE_TXP2_DOCK 22
SMB_DATA_DOCK S9 S108
S10 S109 PCIE_RXN2_DOCK 22
S10 S109
S12 S110 PCIE_RXP2_DOCK 22
S12 S110
S13 S111
S13 S111
it c
S14 S112 TV_DCONSEL1_DOCK 18
S14 S112
S15 S113
S15 S113
S16 S16 S114 S114 HDA_DOCK_RST# 21,27
Reserved S17 S115 HDA_SPKR_DOCK R9E5 22,24,33,34,48,55,57 +V3.3M_WOL
S17 S115 HDA_SPKR 23,27
S18 S116 0 NO_STUFF
S18 S116
S19 S19 S119 S119
S20 S20 S120 S120
S21 S21 S121 S121 LAN_MDI1P_Q_DOCK 34
S23 S122 34 +V1.8_VCT_LAN_DOCK
16 CRT_BLUE_DOCK S23 S122
S24 S127
a
S24 S127
16 CRT_GRN_DOCK S25 S25 S128 S128
S26 S26 S129 S129 SATA_RXP4_DOCK 21
16 CRT_RED_DOCK S27 S27 S130 S130 SATA_RXN4_DOCK 21
S28 S28 S131 S131 SATA_TXP4_DOCK 21
16 CRT_HSYNC_DOCK S29 S29 S132 S132 SATA_TXN4_DOCK 21
S30 S30 S133 S133
27 HDA_SDATAIN_DOCK S31 S31 S135 S135
+V3.3A S32 S136
m
34 LAN_LED_1000#_DOCK S32 S136
S33 S33 S137 S137
34 LAN_MDI2N_Q_DOCK S34 S34 S139 S139 RSTBTNDB 56
S35 S140 PE_OPNREQ#
34 LAN_MDI3P_Q_DOCK S35 S140 PE_OPNREQ# 40
34 LAN_MDI3N_Q_DOCK S36 S36 S141 S141 DOCK_PE_RST# 41
S37 S143
e
34 LAN_LED_LINK#_DOCK S37 S143 DOCK_PE_PWRGD# 41
S38 S144 SMI#_DOCK
C S38 S144 C
S43 S43 S145 S145
R9C3 Note: PE_DET# - GND in CRB, S44 S147
100K Shorted to PE_DET# in S44 S147 PCIE_TXN1_DOCK 22
5%
S45 S45 S148 S148
Docking Board S46 S149
h
S46 S149 PCIE_RXN1_DOCK 22
S47 S47 S150 S150 PCIE_RXP1_DOCK 22
S48 S48 S151 S151
40 DOCK_EXP_CPPE# S49 S152 TV_DACA_OUT_DOCK 18
SMB_CLK_DOCK S49 S152
S51 S153
S51 S153
c
40 DOCK_PE_DET# S52 S154 TV_DACB_OUT_DOCK 18
S52 S154
S53 S155
S53 S155
23,32,40,43,55,57 PM_S4_STATE# S54 S156 TV_DACC_OUT_DOCK 18
S54 S156
S56 S157
S56 S157
S57 S158 HDA_BCLK_DOCK 27
s
S57 S158
S58 S161 LAN_LED_100#_DOCK 34
S58 S161
S60 S162
Reserved S60 S162
S61 S163 LAN_MDI0N_Q_DOCK 34
S61 S163
-
S62 S164 LAN_MDI0P_Q_DOCK 34
S62 S164
S64
24,27,28 +V3.3A_1.5A_HDA_IO S64
S65 M84 CLK_PCIE_DOCK 36
S65 M84
S66 M126 CLK_PCIE_DOCK# 36
S66 M126
16 CRT_VSYNC_DOCK S67
S67
p
S68
S68 41,50 +VAC_IN_L
S69
S69
18 TV_DCONSEL0_DOCK S70 P1
S70 P1
16 CRT_DDC_CLK_DOCK S71 P2
S71 P2
16 CRT_DDC_DATA_DOCK S72 P3
S72 P3
to
27 HDA_SYNC_DOCK S73 P4
S73 P4
27 HDA_SDO_DOCK S74
S74
S75
S75 NOTE: Power pins rated
S79
S79 at 7A per pin.
34 LAN_MDI2P_Q_DOCK S77
S77
34 LAN_MDI1N_Q_DOCK S80 G1
B S85
S80 G1
G2 B
S85 G2 +V5A 24,29,34,38,46,47,50,51,56,57
S86 G3
p
S86 G3
S87 G4
S87 G4
S88 G5
S88 G5
S89 G6
S89 G6 C9P2
S90 G7
S90 G7 0.1uF
50 AMPS_CONTROL S91 G8
S91 G8
la
S92 G9 20%
S92 G9
11,23,40,43,46,47,49,55,57 PM_SLP_S3# S93 G10
S93 G10
23,40,43,47,55,57 PM_SLP_M# S95 G11
S95 G11
56 PS_ON_SW# S96 G12
S96 G12 U9C1
S97
.
40 DOCK_SYS_PWRGD# S97
23,25,26,32 SMB_CLK_A1 3 24
PCI-E DOCKING CONN 1A1 VCC
23,25,26,32 SMB_DATA_A1 4
1A2 SMB_CLK_DOCK
19,23,25,26 PCIE_WAKE# 7 2
1A3 1B1 SMB_DATA_DOCK
23,38,40,43 SMC_EXTSMI# 8 5
TP_1A5 1A4 1B2 PCIE_WAKE#_DOCK
11 6
1A5 1B3 SMI#_DOCK
9
1B4
w
TP_2A1 14 10 TP_1B5
TP_2A2 2A1 1B5
17
TP_2A3 2A2 TP_2B1
18 15
TP_2A4 2A3 2B1 TP_2B2
21 16
TP_2A5 2A4 2B2 TP_2B3
22 19
2A5 2B3 TP_2B4
20
2B4 TP_2B5
23
w
2B5
1
1OE#
41 DOCK_PE_QSEN# 13 12
2OE# GND
SN74CBTD3384
w
A A
Title
Docking

A 355659 1.0

5 4 3 2 1
5 4 3 2 1
VREF2 V5A_MBL_PWRGD R3W11 +V5A3A_MBL_PWRGD
0
m
+V5A_MBL 56 NO_STUFF R3H11
0
C3W4 VREF2 +V3_LDO R3W22 51120_EN1_C R3W20
1000pF 0 Q3W3 0 +V3_LDO
.
5% NO_STUFF . C3W6 AGND_51120
o
2 3 0.1uF .
10%
C3H9 R3H17 NO_STUFF +VBATA 26,46,47,56,57
R3W12 1000pF AGND_51120 10K R3H16
40.2K 5% R3H15 5% 220K BSS138 51120_DRVH1_+VBATA R3H18
1
AGND_51120
1% 0 . 5% 0.002
NO_STUFF . 1%
VR_ALW_ENABLE 28,56
.
C3H13
D 51120_EN1 0.1uF C3H12 D
10% 22uF
5
6
7
8
R3H9 AGND_51120 .
10K R3W18 R3H14 Q3H5
s
1% 0 0 51120_DRVH1_R R3H13 51120_DRVH1_Q IRF7811A +V5A_MBL 56
4
NO_STUFF 0
1
2
3
Icc-max=8A
51120_TONSEL
.
. L3H1 OCP=15A
it c
51120_+V5A_MBL_Q 1 2 51120_+V5A_MBL_QL R3J2 0.002
AGND_51120
1%
+V5_LDO_FILT AGND_51120 3.3uH
1
51120_SKIPSEL CR3H1
5
6
7
8
NO_STUFF
C3H11
1
0.47uF Q3H4 C4Y2 + C3Y1 + C3J1
R3W19 51120_VBST1 51120_DRVL1_Q 4 IRF7822 B320A 0.1uF 220uF 220uF
R3W15 0 NO_STUFF 10% 10% 10%
. .
1
2
3
2
0 NO_STUFF
32
31
30
29
28
27
26
25
EU3H1
a
+V5_LDO_FILT_RC1
. 33
SKIPSEL
TONSEL
PGOOD1
EN1
VBST1
DRVH1
LL1
DRVL1
56 +V5A_MBL TH
26,46,47,56,57 +VBATA
C3H10 AGND_51120 +V3_LDO
R3H10 470pF AGND_51120
9.76k_1% 5% 1 24 +V5_LDO_FILT
NO_STUFF NO_STUFF VO1 PGND1 C3H8
51120_COMP1 2 23 51120_CS1_R 1 R3W14 2 0.1uF
m
COMP1 CS1 10.7K 10%
51120_VFB1 3 22 1% . +V5_LDO
C3W5 VREF2 VFB1 VIN
2200PF
NO_STUFF
4 VREF2 TPS51120 VREG5 21
e
5 20 R3W10
C GND V5FILT 49.9 C
R3H8 C3H7 1% C3H5
6 VFB2 VREG3 19
AGND_51120
0 1.0uF 10uF
NO_STUFF 7 18 51120_CS2_R R3W8 C3H6 20% 20%
h
COMP2 CS2 12.4K 10uF .402 .
1%
R3H6 51120_VFB2 8 17 20%
R3H5 0 VO2 PGND2 . +VBATA 26,46,47,56,57
0 NO_STUFF
PGOOD2
51120DRVH2_RQ
c
AGND_51120
DRVH2
DRVL2
VBST2
. 51120DRVH2_+VBATA_Q R3H3
EN5
EN3
EN2
LL2
51120_COMP2 0.002
C3G8 1%
C3H1 0.1uF
VR_ALW_ENABLE_R 9
10
11
12
13
14
15
16
51120VBST2_LR
s 5
6
7
8
R3W7 100pF NO_STUFF 56 +V3.3A_MBL 22uF 10%
30.1K C3H4 Q3H2 .
1% 5% 51120DRVH2 R3H4 IRF7811A
NO_STUFF 4
-
0 +V3.3A_MBL 56
51120VBST2
+V5_LDO_EN3
1
2
3
+V5_LDO_FILT_RC2 C3H3
C3W2 0.47uF . Icc-max=8A
470pF 51120VBST2_Q 1 2 R3G5 OCP=18A
5% L3G2 0.002
51120_VR_ALW_ENABLE
1
p
NO_STUFF CR3G2 3.3uH 1%
5
6
7
8
NO_STUFF
R3W2
0 Q3H1 C4H1 + C3G6 + C4G4
R3H1 51120_DRVL2_Q 4 IRF7822 B320A 0.1uF 330uF 330uF
+V5_LDO 20% 20%
AGND_51120
. 0 NO_STUFF 10%
1
2
3
2
100K
o
R3H2 41 +V5A3A_MBL_PWRGD
28,56 VR_ALW_ENABLE .
t
R3W6
10K R3W3 V5A_MBL_PWRGD
B AGND_51120 5% 0 B
. C3H2
p
0.1uF R3W4
.
10% 0 +V3_LDO
+V3.3A_MBL 56 +V3.3A NO_STUFF NO_STUFF
l. a
AGND_51120
Note: RC network for manually adjusting soft start delay
C3W3
R3H7 1000pF
23.7K 5%
1%
.
R3H12
3.3V_EV V5 Output Mode Selection V3.3 Output Mode Selection
0
NO_STUFF R3W9 C3H9, R3W12 & R3H9 R3H8 C3W3, R3H10 & R3W9 R3H6
10K Fixed Output Mode NO_STUFF STUFF Fixed Output Mode NO_STUFF STUFF
1%
w
Adjustable Mode (default) STUFF NO_STUFF Adjustable Mode (default) STUFF NO_STUFF
V5 Mode Selection V3.3 Mode Selection

R3W15 R3H10, C3H10 & C3W5 R3H5 R3W7, C3H4 & C3W2
Current Mode NO_STUFF STUFF Current Mode NO_STUFF STUFF
D_CAP Mode (default) STUFF NO_STUFF D_CAP Mode (default) STUFF NO_STUFF
w
PROGRAMMING TABLE
AGND_51120
PIN AGND VREF2 FLOAT +V5_LDO_FILT
SKIPSEL AUTO-SKIP AUTO-SKIP FAULTS OFF PWM FAULTS OFF PWM
COMP N/A N/A N/A D-CAP MODE
TONSEL(CH1/2) 380KHz/590KHz 290KHz/440KHz 220KHz/330KHz (DEFAULT) 180KHz/280KHz
VFB1 N/A SHOULD NOT BE USED N/A 5V FIXED OUTPUT
w
A A
VFB2
EN1,EN2
N/A
SWITCHER OFF
SHOULD NOT BE USED
SHOULD NOT BE USED
N/A
N/A
3.3V FIXED OUTPUT
SWITCHER ON
EN3,EN5 LDO OFF SHOULD NOT BE USED N/A LDO ON
Title
TPS51120 System Power

A 355659 1.0

5 4 3 2 1
5 4 3 2 1
m
SKIP# (Pulse Skipping Enable)
Resistor used: Skip mode:
R4B2(Default) Enabled
R4N1 Disabled 24,29,34,38,44,47,50,51,56,57 +V5A
o
R4B1
DDR_AVDD
DDR2 VREG
10 5%
R4N1 .
c
10K C4B4
1uF
.
Note: C4B7 adjusts the soft-start time for the VTT R4B2 NO_STUFF 10%
D output. The charge rate at the SS pin is 4uA and the DDR_SKIP# . D
threshold voltage is 1.6V. A 4700pF capacitor gives a CR4B1
1.88mS soft-start. This roughly matches the 1.7mS 10K AGND_DDR
1 3 26,45,47,56,57 +VBATA
digital soft-start built in to the switching output. .
s
AGND_DDR
R4A4
C4N2 CMPSH-3 1.8_VIN
DDR_REF 4.7uF
10% C4B3 0.002 1%
it c
. DDR_BST_R R4N10 DDR_BST_RC .
C4B2 0 C4A9 C4A7 C4A8
R4N15 0.22uF 5% 0.22uF 20% 10uF
25V 10uF
25V 10uF
25V
100K .
20%
1% . C4B7 .
1.8_VIN
.
5
6
7
8
R4B3
DDR_SS
4700PF DDR_DH_R R4N13 DDR_DH_RQ 4 Q4B1
TON (Switching Frequency Select) 10K 0 IRF7811A
.
1
2
3
Resistor used: Frequency: R4B4 NO_STUFF R4N17 5% 9,10,13,14,48,55,57 +V1.8
.
a
R4N6 600KHz 23.7K
R4B4 450KHz 1% L4B1 R5B2
28
25
17
26
22
.
8
3
None (Default) 300KHz 10K EU4N1 DDR_LX 1 2 +V1.8_L_R
5
6
7
8
AGND_DDR
R4B3 200KHz NO_STUFF R4N6 1.0uH
TPO
SKIP#
REF
SS
VIN
AVDD
VDD
1
Q4N1 0.002 1%
CR4N1 C5B1 .
10K AGND_DDR
DDR_ILIM 4 20 IRF7834 MBR0530 330uF 20%
NO_STUFF DDR_TON ILIM BST DDR_DL_R R4N5 DDR_DL_RC 2.5V
1 18 4
m
AGND_DDR
DDR_OVP TON DH 0 . NO_STUFF
2 19
2
R4N12 OVP/UVP MAX8632 LX 5%
27 SHDN# DL 21 .
7 23
1
2
3
STBY# PGND1
5 POK1 FB 15
DDR_SHDN_RU
OVP/UVP (Protection/Discharge Enable) 10K 6 16
e
Resistor used: OVP, Discharge UVP R4N9 POK2 OUT NOTE: LX and PGND1 pin connections to the low-side
.
PGND2
REFIN
C FET must be made as Kelvin-sense connections. C
VTTR
R4N12 (Default) Enabled Enabled
VTTS
GND
VTTI
TAB
VTT
DDR_POK_RU2
None (open) Enabled Disabled DDR_FB_RR
R4N9 Disabled Enabled 10K
R4B5 Disabled Disabled NO_STUFF R4B5 9,10,13,14,48,55,57 +V1.8 R4N20 DDR_AVDD
h
10
24
29
11
9
12
14
13
R4N18 10K
R4N19 10K
10K 1% . Note: Keep trace from FB pin short
NO_STUFF R4N3 10 5% NO_STUFF (feedback resistors near pin).
AGND_DDR
0 C4N3
DDR_VTTR
c
.
+V1.8_EVMC_R
C4B8 0.1uF R4B7 R4N21
. 10uF 10% 22 NOTE: R4N19 10K DDR2, DDR3, EVMC (remote adjust) Selection:
20% 16V 5% to be 1% Resistor used Mode selected Vout, VTT
changed to NO_STUFF
R4B6 . NO_STUFF . STUFF : R4N20 DDR2 1.8V, 0.9V
23,55 PM_SLP_S4#
-s
0 11.5K, 1%. NO_STUFF : R4N19, R4N21
Note: U4A3, R4M8, C4M4 to be stuffed only for DDR3 board (for DDR3 STUFF : R4N19, R4N21 DDR3 1.5V, 0.75V
C4B5 board) NO_STUFF : R4N20
. AGND_DDR
DDR_REFIN STUFF : R4N19, R4N21, R4N22 EVMC enabled 1.5V, 0.75V
NO_STUFF : R4N20
+V3.3A Note: EU4N1 needs to be moved to MPAD.OLB NOTE: Place C4N3 and C4B8 near VTTI 0.1uF 10% R4N22
pin and C4B5 near REFIN pin. +V1.8_EVMC_V_CNTL
0
C4M4 . AGND_DDR
NO_STUFF
p
0.1uF
16V 10% R4N7 NOTE: Place VTT bypass caps as close to 15,55
VTT and +V0.9
NO_STUFF 0 PGND2 pins as possible. Connect VTT sense line
5
U4A3 7,48 M_VREF_MCH (VTTS) separately to VTT at the point of regulation.

1 . C4B6
o
4 SM_PWROK_U 1uF +V3.3A 19,21,23,24,25,26,27,28,29,32,37,38,39,40,41,43,44,45,47,48,50,51,52,55,56,57
2 20%
23,55 PM_SLP_S4# R4M8 Note: C4B6 should be placed . R4B10
t
74AHC1G08 12.1K close to the VTTR pin. +V0.9_R Note: Stuff these parts for DDR3 memory only.
1%
3
NO_STUFF NO_STUFF for DDR2 memory.

NO_STUFF
C4N4 C4B13 C4N5 0.002 1% R6V3
B SM_PWROK 7 B
10uF 10uF 10uF . 10K
R4M7 20% 20% 20% 5%
p
+V3.3A 10K . . . NO_STUFF
1% R4B8 SC1563 10 +V1.8_LDO
.
DDR_POK_RU R4M9 C4M6 0 U6V1 NO_STUFF
10K 0.1uF NOTE: TAB must be star-connected to GND pin 5 R5V1
5% 16V (analog gnd) and to PGND2 through R4B8(0-ohm IN LVDS_OUT
.10% . OUT
4
l. a
.
AGND_DDR resistor). PGND2 and the low side of the VTT C6V2 1
SHDN
5
U4A4 bypass caps are connected to the PGND plane. 1.0uF 0.01 1%
LVDS_SHDN
10% GND ADJ R5V2 NO_STUFF
1
PM_SLP_S3_S4_LDO
48 PM_SYS_PWRGD 10K
4 NO_STUFF
PM_PWROK 47 2 3 1%
2 NO_STUFF
74AHC1G08 R5F20 LVDS_AD C6V3
3
. C5V3 0.1uF
11,23,40,43,44,47,49,55,57 PM_SLP_S3#
3
0 5% 22uF 10%
NO_STUFF Q6F1 R6G1 NO_STUFF NO_STUFF
BSS138 0 R5U28
w
1 NO_STUFF 1%
23,55 PM_SLP_S4#
+V3.3A 0 5% NO_STUFF 20K
R5F21 NO_STUFF
2
NO_STUFF
C4N1
0.1uF C4B1
w
16V .10% 0.1uF R5U24
+V1.8_LDO_EVMC_V_CNTL
16V .10% 0
5
U4M2 Note: Place EVMC control resistor near U6V1

5
1 U4A5 NO_STUFF
4 CANTIGA_DDR_PWRGD 1
47 PM_PGOOD_1_05M 2 4 MPWROK 7,23
2
w
A 74AHC1G08 A
3
.
3
Title
48 VRPWRGD_3.3M_WOL DDR2 VR
Adds 3.3M to the MPWROK tree.
Needed to support G3->M1 and Size Document Number Rev
Moff to M1 transitions.
A 355659 1.0

5 4 3 2 1
5 4 3 2 1
m
1.05M_EV
EV_VCC_V1.05S VR Current Capability
NO_STUFF
NO_STUFF
AGND_51124
R4V1 R5U32 R4V2 Rail I continuous Nominal OCP
o
0 0 +V3.3A
R4G1 10K R4G2 +V1.05M 9A 15A
4,9,10,24,55 +V1.05S NO_STUFF 7.5K 7.5K 9,10,15,35,55 +V1.05M +V1.05S 3A 14A
1% 1% R4V5
R4U6 1%EV_VCC_V1.05S_R R5U27 . . R4V31.05M_EV_R R4V4 10K
c
1%
51124_TONSEL
2.8K 0 0 1% 2.8K .
PM_1.5_1.05S_PGOOD
PM_PGOOD_1_05M 46
51124_VB2
51124_VB1
. . Switching Frequency
D 26,45,46,56,57 +VBATA
11,23,40,43,44,46,49,55,57 PM_SLP_S3# PM_SLP_M# 23,40,43,44,55,57
D
4,9,10,24,55 +V1.05S 9,10,15,35,55 +V1.05M R5V3 26,45,46,56,57 +VBATA TONSEL PIN CH1 CH2
R4G3 24,29,34,38,44,46,50,51,56,57 +V5A 0 V1.05M_VIN R4V10
V1.05S_VIN 1 R5U33 +V5A 24,29,34,38,44,46,50,51,56,57 0.002 1% FLOAT 300kHz 360kHz
s
0
51124_PGD1
. 1
0.002 CR5U1 C4V4 C4V5
1
1% C4G2 C4G1 5 6 . EU5G1 CR5V1 0.1uF 22UF .
. 22UF 0.1uF BAT54 BAT54 10%
VO2
VFB2
TONSEL
VFB1
VO1
GND
10% .
it c
. 351124_VBST2_R 51124_VBST1_R
51124_PGD2 7 24 3
PGD2 PGD1
5
6
7
8
Q4F1B C5F3 R5F18 R5G5 C5G3
IRF9910 4 0.1uF 0 8 23 0 0.1uF Q5V1
10% EN2 EN1 10% IRF7811A
4
. . 51124_VBST2 9 22 51124_VBST1 . . .
1
2
3
VBST2 VBST1
+V1.05S 3 51124_DRVH2_R R5F17 51124_DRVH2 10 TPS51124 21 51124_DRVH1 R5V4 51124_DRVH1_R 9,10,15,35,55 +V1.05M
DRVH2 DRVH1 L4G1
R4F7 L4F1 0 0 R4G4 1%
a
51124_LL2_L
1 2 51124_LL2 11 20 51124_LL1 1 2 51124_LL1_L
1.0uH LL2 LL1
7 8 . .
0.002 1% 51124_DRVL2 12 19 51124_DRVL1 1.0uH 0.002
DRVL2 DRVL1
1
. .
PGND2
PGND1
V5FILT
1
TRIP2
TRIP1
CR5G3 C4G3 C5U5 C5U6 C4V2
V5IN
THM
5
6
7
8
C4U1 C3U1 C7U1 C4F3 C4F4 CR4F1 B320A 0.1uF 270uF 270uF 270uF
270uF 270uF 270uF 270uF 0.1uF B320A Q5G1 20% 20% 20%
2 .10%
m
20% 20% 20% . .
20%
. . . .10% 4 IRF7822
25
13
14
51124_V5FILT 15
16
17
18
2
Q4F1A
51124_TRIP2
51124_TRIP1
.
2
1
2
3
IRF9910
1
e
AGND_51124
C R5F19 12.1K R5G4 C

1% 6.49K 1%
AGND_51124
R5U26
h
.
AGND_51124
24,29,34,38,44,46,50,51,56,57
R5G1 3.9 .
+V5A 0
C5G1
1uF 1% .
AGND_51124
NO_STUFF 20% C5G2
51124_TONSEL .. 4.7uF
c
R5G3 10K 10%
AGND_51124
.
19,21,23,24,25,26,27,28,29,32,37,38,39,40,41,43,44,45,46,48,50,51,52,55,56,57 +V3.3A
s
+V3.3A 19,21,23,24,25,26,27,28,29,32,37,38,39,40,41,43,44,45,46,48,50,51,52,55,56,57
Power Good Logic
-
C4G5 C4V6
0.1uF 0.1uF
R5H1 .10% 16V .10%
5
10K U4W1
1%
5
p
. U4H1 1
46 PM_PWROK
PM_PGOOD_1_05M 1 4 ALL_SYS_PWRGD 23,40,43
4 CANTIGA_VR_PWRGD 2
PM_1.5_1.05S_PGOOD 2
74AHC1G08
3
o
74AHC1G08 .
3
t
B B
p
Note: NO_STUFF V1.5S VR for DDR3. DDR3 will generate V1.5S. +V5A 24,29,34,38,44,46,50,51,56,57
l. a
4,10,11,24,28,55,57 +V1.5S 1 26,45,46,56,57 +VBATA VR Current Capability
CR5G1 Rail I continuous Nominal OCP

BAT54
V1.5S_VIN R5V5 +V1.5S 3A 7.5A
PM_SLP_S3#
0.002
3
C5G4 C5V2
51117_VBST_R 6 5 0.1uF 22UF .
C5G5 10% 1%
.
w
R5F16 R5G7 0.1uF
+V5A 200K 0 10% Switching Frequency
.
.
1% . Q5G2B TON PIN
R5F15 U5F1 R5G651117_DRVH_R
4 IRF9910 4,10,11,24,28,55,57 +V1.5S
301 1 14 51117_VBST 0 200K 400kHz
1% 51117_TON 2 EN_PSV VBST 51117_DRVH L5G1
13
w
TON DRVH 51117_LL 51117_LL_L R5G2 1%
3 12 . 1 2
51117_V5FILT VOUT LL 51117_TRIP R5U30 1% 3 0.002
4 11 8 7
51117_VFB 5 V5FILT TRIP 7.87K 1.0uH
10
VFB V5DRV
1
C5F2 6 9
PGOOD DRVL
1
1uF R5U25 7 8
AGND_51117
CR5G2 . + C5V4 C6V4
51117_PGOOD
20% 20K C5F4 GND PGND . +V5A 24,29,34,38,44,46,50,51,56,57 220uF 0.1uF

B320A 10%
. 1% TPS_51117 Q5G2A .10%
w
.
2
A EV_VCC_1.5S_R 18PF 51117_DRVL 2 IRF9910 A

2
AGND_51117 AGND_51117
.
R5U21
R5U20
0
0
1 Title
NO_STUFF . R5U29 Cantiga VR
0 +V5A 24,29,34,38,44,46,50,51,56,57
EV_VCC_V1.5S
R5U23
R5U22
.
PM_1.5_1.05S_PGOOD C5V1 0 Size Document Number Rev
1% 1uF
20K 20% Place C5V1 close .
A 355659 1.0
. . to U5F1.10 AGND_51117
AGND_51117
5 4 3 2 1
5 4 3 2 1
m
19,21,23,24,25,26,27,28,29,32,37,38,39,40,41,43,44,45,46,47,50,51,52,55,56,57 +V3.3A
5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,49,52,55,56,57 +V3.3S
22,24,33,34,44,55,57 +V3.3M_WOL
o
10,11,55 +V3.3S_TVDAC
5,11,12,16,17,18,24,28,30,31,32,39,49,52,55,56,57 +V5S
R4W10 R4W12 27,32,42,43,52,55,56,57 +V5
13K 100K
R4W8
c
R4W13 1% 100K R4W3
24.9K 13K
1%
UNUSED_BUF_U6A1A_P2
UNUSED_BUF_U6A1A_P3
. PM_SYS_PWRGD 46
D U4H2 1%
VDD+
10 D
U4B1A R4N14
1 16 TLV2463 10K
46 VRPWRGD_3.3M_WOL OUTBOUTC NO_STUFF R4W2 5%
2 15 2
s
OUTAOUTD PP_HYST TP4H1 13K -
3 14 NO_STUFF
V+ HYST +V3.3S_TVDAC_PWRGD
4 13 1
Adds 3.3M_WOL to the MPWROK tree. +V5S_PWRGD INA- IND+ OPAMP4_SHTDN#
5 12 1% 5
INA+ IND- +V3.3S_PWRGD
6 11 3
INB- INC+ +
it c
+V3.3M_WOL_PWRGD 7 10
INB+ INC-
8 9
C4W1 REF V- R4W4 GND R4N16
R4W11 R4W9 0.1uF R4W5 10K 4 10K
10K 10K LTC1444 10K 1%
1% 1% .10% 1% . R4N4 R4N8 5%
. . PP_REFIN R4W7 . 0 0 .
10K
5% . .
VREF = 1.221V .
R4W1
a
2.4M
UNUSED_BUF_U6A1A_P1
.
m
27,32,42,43,52,55,56,57 +V5
e
27,32,42,43,52,55,56,57 +V5
C C
C3N2
0.1uF
h
10%
. R3N7
9,10,13,14,46,55,57 +V1.8 10 10K
VDD+ 5%
NO_STUFF
c
R3N1 8 U4B1B
10K -
1% VREF_MCH_MARG R4N2
. 9
6 OPAMP3_SHTDN# 0
7 NO_STUFF
M_VREF_MCH_A +
-s
TLV2463
R4N11
R3N4 GND 10K
10K C3N3 4 5%
1% 220pF
. .
27,32,42,43,52,55,56,57 +V5 10%
.
p
27,32,42,43,52,55,56,57 +V5
R3N2
M_VREF_MCH 7,46
R3B14 0
o
10K
5% .
9,10,13,14,46,55,57 +V1.8 10 NO_STUFF
t
VDD+ U3B1A
TLV2463
R3N13 2
B 10K - B
1% VREF_DIMM1_MARG R3N11
. 1
p
5 OPAMP2_SHTDN# 0
3 NO_STUFF
M_VREF_DIMM_B +
R3N17
R3B5 C3B6 GND 10K
l. a
10K 220pF 4 5%
1% 10%
. .
.
+V5 27,32,42,43,52,55,56,57
27,32,42,43,52,55,56,57 +V5
w
C3N5
0.1uF R3N16 R6P1
M_VREF_DIMM1 14
.10% 10K 0
9,10,13,14,46,55,57 +V1.8 10 5%
VDD+ NO_STUFF .
U3B1B
R3N15 8 TLV2463
w
10K -
1% VREF_DIMM0_MARG R3N9
. 9
6 OPAMP1_SHTDN# 0
7 NO_STUFF
M_VREF_DIMM_A +
C3N7 R3B12
R3B11 220pF GND 10K
w
A 10K 10% 4 5% A
1%
. . . Pillar Rock Intel Confidential
Title
M_VREF_DIMM0 13 DDR2 VREF

A 355659 1.0

5 4 3 2 1
5 4 3 2 1
5,11,12,16,17,18,24,28,30,31,32,39,48,52,55,56,57 +V5S
Attach VCC_AXG_SENSE and VCC_AXG_SENSE 5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,52,55,56,57 +V3.3S 17,53,55,56,57 +VBAT
m
underneath Cantiga. Ground and output
resistors should be tied to +VGFX_CORE NO_STUFF R3G6
bypass caps. R3V2 GVR_VID0 20K
R3F5 .002 1%
R2G15 R2V14 0.002 1% NO_STUFF
o
5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,52,55,56,57 +V3.3S 20K 30.1K 1%
R3V1 1% R2G19
.
0 C3V9 C3V8 C3V3 C3V2 GVR_VID1 20K
1%
GVR_VBAT
R2G12 +V5S_GVR 0.01uF 0.01uF 0.01uF 0.01uF 1%
. 10% 10% 10% 10% NO_STUFF
c
402 402 402 402
GND_GVR R2G18
.
1
.
Connect Power ground to Controller 10K R2G13 C3V1 GVR_VID2 20K
VSS_AXG_SENSE 9 ground under the controller
D 5% 100K R3G3 1.0uF 1% D
GVR_VR_EN
10 20% C3V4 C3G5 C3V5 C3G7 C3V7 C3V6 NO_STUFF
GVR_PGDLY
GVR_VID0
GVR_VID1
GVR_VID2
GVR_VID3
GVR_VID4
GVR_GNDS 5% .402
1R4T1 2 R3F7 30.1 . 47uF 47uF 47uF 47uF 4.7uF 4.7uF
10 1% 20% 20% 20% 20% 20% 20% R2G14
2
. NO_STUFF NO_STUFF GVR_VID4 20K
NO_STUFF
C3G2 1%
2
. R3F6 1000pF Refdes R2F2 GND_GVR C3G3 NO_STUFF

+VGFX_CORE J4G1 1K 5% 1.05V (Default) 11K, 1% 1.0uF
1%
5
1.25V 7.87K, 1% D
it c
20%
GVR_VCC
GND_GVR .402
1
G Q3V3
1R4R12 2 R3F4 1%GVR_FB_R R2F2 11K 4 HAT2168H
10 100 1% GND_GVR
C3F1 . S
1
2
3
1000pF C3G4
. VCC_AXG_SENSE 9 10% 0.22uF
GVR_FB GVR_BST R3G4GVR_BST_R
5% 0
+V3.3S GND_GVR 9 +VCC_GFXCORE
GVR_DRVH_G 5%
a
C2G1 GVR_CCV .
100pF L3G1
R2G5 R2G3 71.5K 1% GVR_TIME GVR_SW_PHASE
10K Graphics VR Controller 1
0.88uH
2
5% GVR_VRHOT#
GND_GVR GVR_DRVL_G
R3F9
m
GVR_POUT 3.57K
1%
5
D D
.
1
Placement of R4T1 and R4R12
Place R4R12 close to GMCH pins on +VGFX_CORE G G CR3G1 R3F8
Place R4T1 close to GMCH GND pins RT3F1
GND_GVR
4 Q3V2 4 Q3V1 1.78k
e
HAT2164H HAT2164H GVR_NTC 1 2
B320A
C 5,11,12,16,17,18,24,28,30,31,32,39,48,52,55,56,57 +V5S S S C
1
2
3
1
2
3
2
NO_STUFF
1K
h
C2G2 GND_GVR
GVR_REF
GVR_CSN
GVR_TON
GVR_CSP
GVR_OFS
GVR_THRM
GVR_VCC
0.22uF
R2G8
c
GND_GVR
0
5% 8 OP_GVR_POUT_R
NO_STUFF
R2V5 200K 5 U2G1B
+
R3G2 1% 7
s
13.7K R2G9 6
1% 0 -
. 5%
. C3G1 AD8552 GVR_8552B_OUT
4
-
GND_GVR C3F3 0.1uF GND_GVR
0.22uF 10%
1
. GND_GVR
RT3V1 R3G1
100K 0
5%
p
.
C3F2
2
0.01uF C2G3 0.1uF

10% 10% .
GND_GVR .402
to
25V
R2G1
GND_GVR
40.2K 1% .
Note: Place R2G2, R2G6, R2G7 & R2G1 close to U2G1 and keep
B +V3.3S input lines (pins 2 and 3) short. Extend GND (both B
inputs) and GVR_POUT_R as a pair and connect locally to
p
+V3.3S graphics VR (EU3G1).
R2G2 4
GND_GVR
10K 1% . GAIN ADJUSTED FOR 4.02

Input Output S2 S1 S0 GVR_POUT_R- 2 - U2G1A
GFX_VR_PWRIN 41,52
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
A C 1 1 0 1
la
B C 1 1 1 GVR_POUT GVR_POUT_R+ 3 +
A D 1 1 1 AD8552
R2V9
R2V7
R2V4
B D 1 1 0 GND_GVR R2G6 +V3.3S

8
R2V13
R2V11
R2V2
R2V1
10K 1% .
R2G11
U2G2 C2G6 R2G7 OP_GVR_POUT_R R2G4 10
.
GVR_STRAP_VID0 2 46 GVR_VID0 0.1uF 40.2K 1%
GVR_STRAP_VID1 A0 C0 GVR_VID1 10% 1% C2G4
5 44
GVR_STRAP_VID2 A1 C1 GVR_VID2 . 0.1uF Note:Place the 0 ohm resistors close to
8 41 .
GVR_STRAP_VID3 A2 C2 GVR_VID3 10% the source and route a thick trace from
11 38
GVR_STRAP_VID4 A3 C3 GVR_VID4 16V source to destination
13 36
GVR_STRAP_VR_EN A4 C4 GVR_VR_EN_R R2V3 GVR_VR_EN . NO_STUFF
16 33
A5 C5
w
GVR_STRAP_EXTRA 18 31 0 GND_GVR
A6 C6 . R2V10 GND_GVR_R R9H14
21 28
A7 C7 0 0
10
12
14
16
23 26
A8 C8
2
4
6
8
R2V6
J2H2 3 45 0 NO_STUFF R1J8
7 GFXVR_VID_0 B0 D0 AGND_VCORE
6 43 NO_STUFF GND_GVR 0
7 GFXVR_VID_1 B1 D1
7 GFXVR_VID_2 9 40 11,23,40,43,44,46,47,55,57
1
3
5
7
9
11
13
15
w
B2 D2
7 GFXVR_VID_3 12 37 .
B3 D3 Note: Extend this ground and the GND_SYS_CURRENT
7 GFXVR_VID_4 14 35 PM_SLP_S3#
B4 D4 output as a pair to the point where
7 GFXVR_EN 17 32
B5 D5 the output is being delivered (A/D).
19 30
GVR_V5_S0 B6 D6 GVR_VR_EN
22 27
B7 D7 +V5S For Teenah STUFF: R2V6
24 25
B8 D8 NO_STUFF: R2V3
w
A +V3.3S A
1
48
S0
S1
VCC
GND0
7
4
For Cantiga STUFF:
NO_STUFF:
R2V3
R2V6 Pillar Rock Intel Confidential
GVR_S2_S1 47 10
S2 GND1
R2G10 10K 34 GND5 GND2 15 C2G5 Title
39 20 .01uF
. 42
GND6
GND7
GND3
GND4 29 20% Graphics Core VR
74CBT16209A
A 355659 1.0
5 4 3 2 1
5 4 3 2 1
51,56 +VBS
m
Route resistor sense
R2W1 lines from the PADs POS_SENSE 51
0 of the resistor(R1H1) C1W2 C1V1
22uF 22uF
. 20% 20%
o
NO_STUFF NO_STUFF
PWR_JACK_GND 51,56 +VBS
AGND_AMPS
CR1W1
2 1
c
4A, 50V, DCresist=12mohm-1 line- CR1W251 +VCHGR_OUT
J1G9 J2Y1
1k@100MHz B320A 1 2
.
4 5 B320A 22 21
CASE4 GND1 +VAC_IN_L 41,44 Q1H2
D 3
CASE3 GND2
6 1 4 Q1H1 20 19 D
2 3 3 R1G12 0.020 FDS6679AZ 18 17
CASE2
1 7+V_JACK_PWR 2 3 +VAC_IN_L 2 5 AMPS_AD+_Q1 5 2 R1H1 3 8 16 15
CASE1 PWR1 .007
8 1 1 2 7 14 13
s
PWR2 R1H2 C1W3 C1W4 1%
L1G1 1 6 12 11
9 4.7K 22uF 0.1uF SI7483ADP SI7483ADP . 5 10 9
CNTRL_ADFC 5% 20% 10% R1G13
. 8 7
4
2.2 PBATT 40
25V
. . 5%
NO_STUFF R1G11 Q1H3 6 5BC_SHDN
4
PWR_JACK NO_STUFF NO_STUFF 100 40 PSYS
it c
. 5% 40 VCHRM 4 3 ICHRM 40
NO_STUFF CR1W3 1 3+V_JACK_PWR 10% . 2 1AMPS_ACPRES
C1W1 2.2uF C2H4 2.2uF AMPS_CP_C
1 3
AMPS_SAMBP
BAT54
CR1W4 10% AMPS_SBM C2G9 2x11-PLG
AGND_AMPS
R1G10 0.47uF C2V4 NO_STUFF
BAT54 1K EU2G1 4.7uF
5% 10%
. . 20% 51 +VCHGR_OUT
17 AMPS_CP
14 .
44 AMPS_CONTROL SBM CP
C1V3 R1W1
a
1uF 10K 15 13
10% 5% SAMBP VSYS 51 +VCHGR_OUT
.
.. C1V2 16 18 AMPS_CA
R2G23 1uF SAP CA R2V21
0 10% AMPS_PA 20 19 AMPS_BATT 3 100 +V5A 24,29,34,38,44,46,47,51,56,57
PA WUPD 5%
NO_STUFF
. AMPS_DCIN 12 21 C2V1 CR2V1 C2V2
AGND_AMPS DCIN BAT 1uF 0.1uF
BAT54
m
AMPS_CONT 24 6 AMPS_IPROG 10% . .10% R2H5
CONT IPROG 40.2K
..
AMPS_COMP_R
AMPS_AD+_Q AMPS_COMP 1
3 COMP VPROG 2 AMPS_VPROG .
1%
AGND_AMPS
R2G22 R2G20 AMPS_CELLS 7 9 AMPS_REF_EN
e
R2W8 100K 0 CELLS REF_EN
C 100K 5% .
AMPS_IBATT 8 5 C
5% R2V25 IBAT WK_TH R2H1
3 . . .
CR2W2 R2H11 100K C2V6 AMPS_PAD_MAX
1 PAD_MAX 23 AMPS_PAD 49.9K
100K 0.47uF PAD C2G8 1%
5% .
h
AGND_AMPS
. C2G7 NO_STUFF 11 4 AMPS_ACPRES 1000pF
Battery Wakeup Threshold MMBZ5246BN 3.3uF AMPS_LDO LDO ACPRES 10%
AMPS_AD+_R
(Vzener=16V) 1 10% C2H2 10

REF NC
22 AMPS_OVP .
AGND_AMPS
WK_TH Threshold Voltage . 4.7uF
AMPS_AD+_ZNR
AGND_AMPS AGND_AMPS AGND_AMPS AGND_AMPS

10%
c
3
. 25
0 V 2.9 V/Cell THRM R2H18 +VBS 51,56
3
Q2W6 JASPERSI_0X 0 R2V20
AGND_AMPS
3 V 3.2 V/Cell 1 BSS138 Q2G2 10K
-s
2N7002 AMPS_REF NO_STUFF
3
AGND_AMPS
. 1 51,56 +VBS .
2
3
Number of Cells 40 BC_SHDN
C2H1
AGND_AMPS
4.7uF 56 BC_ACOK_BATT
2
AMPS_CELLS Number of Cells 1 1 BC_SHDN NO_STUFF 10% Q2V1
. R2V24 1 BSS138
R2H8 Q2H1 Q2W5 100K
2
AGND_AMPS
AMPS_REF 4 Cells 2N7002 2N7002 R2H10 5% . .
2
100K
p
R2G17 +V3.3A
5% AGND_AMPS
LOW 3 Cells 1K . 0
BC_ACOK#
.
3
Hi Z 2 Cells R2W3
AGND_AMPS AGND_AMPS
10K
AGND_AMPS AGND_AMPS
Q2G1
o
Adapter Over Voltage Protection AMPS_ACPRES_R
1 BSS138 .
3
40,43 BC_ACOK
t
.
2
Q2H2
1 BSS138
B AMPS_REF R2G16 B
16.9K
1% .
2
p
.
R2W2
162K
1%
.
l. a
AMPS_IPROG R2V26
AMPS_CONT R2V17 AMPS_PAD_MAX 0 ICHRM 40
3
0 NO_STUFF
51,56 +VBS
NO_STUFF R2G24 330K R2G26 C2V3 Q2W1
100K
AMPS_LM358A_IN+
5% 0.1uF 1 BC_SHDN
R2V22 AGND_AMPS 1%
. .10% 2N7002
0 .
2
AMPS_REF C2W1 1uF R2H9

. 10% 1M
AGND_AMPS AGND_AMPS 5%
8AMPS_VBS_LM358
w
AMPS_REF_LM358A_IN-
AGND_AMPS .
R2G21 8AMPS_VBS_LM358 AMPS_VPROG : To set maximum charging voltage for each cell
3 +
U2H1A 330K ..
R2V27
Vcell = Vvprog/10 + 4.1
1AMPS_LM358B_OUT 5 +
U2H1B Vvprog = 1 V for 4.2V per cell
AGND_AMPS
2 5% 7 1 2
-
R2H7 6 -
LM358 4.99k_1% R2V15
84.5K
AMPS_REF AMPS_IPROG : To set maximum charging current
w
4 23.7K . LM358 Set to 1.25V for a Charging current of 2A
1% 4 1% R2V16
.
AMPS_LM358B_IN- R2V18 AMPS_PAD_MAX_LM358 39.2K
AGND_AMPS
AMPS_REF_R_LM358 1% R2H4
R2G25 232K
R2H6 R2V19 330K 330K .
10K 49.9K 5% 5%
w
A 1% 1% . . 1% A
. .
AMPS_VPROG R2V23
VCHRM 40
0
AGND_AMPS AGND_AMPS AGND_AMPS AGND_AMPS
R2W4 C2V5
NO_STUFF Title
100K 0.1uF System Charger AMPS
1% . .10%

AGND_AMPS AGND_AMPS
A 355659 1.0

5 4 3 2 1
5 4 3 2 1
m
System Current Sense Amp (6A Dynamic Range) 19,21,23,24,25,26,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,52,55,56,57 +V3.3A
H8 ADC Reference
(Place close to the sense resistor near the brick connector) +V5A 24,29,34,38,44,46,47,50,56,57 (Place very close to the EC)
NO_STUFF
o
+V3.3A R1J9 +V5A 24,29,34,38,44,46,47,50,56,57 +V3.3A
+VAC_IN_L_R
41 +VREF_ADC
10K 41 +VREF_ADC
R1Y7 EC_CS_GAIN_SEL R9H10
c
U2J3 22 475 R9H9
1% EC_CS_GAIN_SEL 5% 1% 3.3V ADC reference 0
1 8 . 8 .
SHDN# GSEL
.
R2Y3 1K POS_SENSE_A 2 7 R2J4
50 POS_SENSE RS- VCC
D +VAC_IN_L_A 3
RS+ OUT
6 MAX4072_OUT MAX4072_OUT_RC5
+
U2J4B 10K NO_STUFF D
MAX4072_REFIN EC_BRK_CURRENT 40
R2Y6
1%
1K 4
GND RFIN
5 R2J3
20K 6
7 . * *CAD Note:
System current groud trace needs to be
-
C2Y4 MAX4072 C2J1 R2Y1 20 mil or larger going from the brick to
s
+VBS . . C2J20.1uF C1J6 C1Y5 1uF AD8552 the EC and MAX4072 current sense
0.1uF10% 0.1uF 0.1uF C2Y2 20% 1% 4 GND_SYS_CURRENT
amp.
10% . .10% 10% 22UF . 100K
. .
16V .
it c
R1Y9 R2J2 1 The precision ADC and and 3.3 ADC reference
80.6 0 optons are mutually exclusive. DO NOT STUFF
1% 3.0V Precision ADC LM4040 C9W3
. BOTH AT THE SAME TIME OR THE PRECISION
GND_SYS_CURRENT GND_SYS_CURRENT
. Reference circuit U9H1 REFERNCE COULD BE DAMAGED. C9H4 0.1uF
+VAC_IN_L_R GND_SYS_CURRENT
22UF 10%
2 .
CURRENT SENSE RANGE
R1Y8
475 0 - 3A: EN_CS_GAIN_SEL = 3.3V 0-6A
1% EN_CS_GAIN_SEL = 0V (DEFAULT)
.
a
POS_SENSE 50
GND_SYS_CURRENT
SMBUS Address for Battery B = 1E 50 +VCHGR_OUT
SMBUS Address for Battery A = 1C +V3.3A 19,21,23,24,25,26,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,52,55,56,57
m
SMBUS Address for LIBP = 16 C1H1 C1W6
10UF 10UF 19,21,23,24,25,26,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,52,55,56,57 +V3.3A
25V 25V
J1H1
e
1 .
C 1 SMB_CLK_BATT_B C1Y4 C1Y2 C1J3 C1W9 C
2 2
3 SMB_DATA_BATT_B 5 R1J4 0.1uF 0.1uF 0.1uF 0.1uF
3 BC_THERMB Q2J2 BSS138 U1Y2 10K
Batt B 4 4 5 .10% .10% .10% .10%
5 U2J2 1 16V 16V 16V 16V
h
5 BS_CHGB# 40,43
6 CHGB 3 2 CHGB_XOR 1 BS_CHGB
4 .
6 19,21,23,24,25,26,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,52,55,56,57 +V3.3A
7 7 4 2
2
CON_1X7_156mil_HDR 74AHC1G02
74AHC1G86 3
c
1
GATE_CHGB 3 C1Y7 C1Y6

+V3.3A DISB# R1Y3 0.1uF 0.1uF R1Y5
BS_DISB# 40,43 10K
1K .10% .10% R1Y2
5%
5
R1W11 BC_THERMB R1W3 1% 6.81K U1Y1 R1J3 100K 16V 16V 10K
41 LIBP_CHG_EN_B 5% .
-s
0 1 5% .
C1W5 0.1uF 4 PRE_L
NO_STUFF NO_STUFF 2 40,43 SMB_BS_ALRT#
3
R1J2 BC_THERMA NO_STUFF
0 C1W7 0.1uF 74AHC1G08 U1J3 Q1J2
3
. 8 1 VBS_TRIP BSS138
VCC CLK
NO_STUFF R1J1 4.7K 7
PRE# D
2 Q1Y1 1 VBS_TRIP#
6 3 BSS138
CLR# Q#
p
Battery Address Key FLIPFLOP_Q 5 4 1 .
2
Address Host Resistor Total (Host + 200) Q GND
14 820 1020 5 R1Y1 1G D-FLIP FLOP .
2
16 1800 2000 5 U1J1 10K FLIPFLOP_Q#
18 2700 2900 U2J1 1
1A 3900 4100 BS_CHGA# 40,43
o
1 BS_CHGA
4 .
1C 4700 4900 BS_CLR_LTCH# 40,43
4 2
1E 6800 7000 2
t
20 9100 9300 74AHC1G02 50,56 +VBS
J1H2 22 11000 11200 74AHC1G86 3
1 . 3
B 1 SMB_CLK_BATT_A B
2
2 SMB_DATA_BATT_A
3 BS_DISA# 40,43
3
p
Batt A 4 BC_THERMA Q2J1 BSS138 C1Y3 C1W8 C2W5 C1J2 25V
4 40,43 LIBP_CHG_EN_A
5
5 U1J2 R1J5 100K MAX809 Trip Point = 2.93V 47uF 0.1uF 47uF 22uF C1Y1
5 CHGA CHGA_XOR VBS Trip Point = 6.0V R1Y4 25V 10UF
6 3 2 1 . . .
6 13K
7 4 .
7 1%
2
l. a
CON_1X7_156mil_HDR
74AHC1G08 +V3.3A +V3.3A
1
GATE_CHGA . VBS_DIV
DISA# +V3.3A +V3.3A 3
C1Y8
R1Y6 0.1uF BZX84C2V4LT1
3
DISB# R1W2 100K R8G8 R8G10 U1J4 12.4K CR1J1
1% .10%
R1W10 100K 10K 10K . 16V
VCC
CHGB R1W4 10K R8V12 R8H3 1
R1W7 10K 10K 10K VBS_TRIP# 2
NO_STUFF 5% RST#
GND
w
NO_STUFF GATE_CHGA
Q8G2 41 LIBP_CHG_EN_B
+V3.3A
3
BSS138
NO_STUFF
GATE_CHGB MAX809
40,43 LIBP_CHG_EN_A
1
Q8H1 .
3
BSS138
NO_STUFF
C8G4 R8G7
+V3.3A . 0.1uF 1M 1 R2Y2 R8G9
C2H5 C8H1 R8H2 20% . 10K 10K
w
U2H2 0.1uF 0.1uF 1M 1
2
R2H14 10K LIBP_CL1 1 20 20% 20% . . .
R2H12 10K LIBP_CL2 2 EXPSCL1 VCC .
CHGA_EN# 41
2
R2H15 10K LIBP_DA118 EXPSCL2 SMB_CLK_BATT_B

5
R2H16 10K LIBP_DA219 EXPSDA1 SCL1 SMB_DATA_BATT_B
6 CHGB_EN# 41
EXPSDA2 SDA1
3 8 SMB_CLK_BATT_A
w
A 37,40,43,52 SMB_BS_CLK SCL0 SCL2 A
4 9 SMB_DATA_BATT_A
37,40,43,52 SMB_BS_DATA SDA0 SDA2 Pillar Rock Intel Confidential
40,43 LIBP_BAT_SEL 7 EN1 SCL3 12
+V3.3A
LIBP_I2C_EN_NOT 11
EN2 SDA3 13 +V3.3A Title
14 EN3
17 EN4 SCL4 15 System Charger Battery
C2W3 5 10 16 LIBP_CHG_EN_B R8V11 100K
0.1uF U1H1 VSS SDA4 LIBP_CHG_EN_A R2J1 100K
20% EXP. 5-CH-I2C HUB LIBP_BAT_SEL R2W11 10K
. 2 4 SMB_CLK_BATT_B R1W6 4.7K Size Document Number Rev
SMB_DATA_BATT_B R1W5 4.7K
SMB_CLK_BATT_A R1W9 4.7K
A 355659 1.0
INVERTER SMB_DATA_BATT_A R1W8 4.7K
3
5 4 3 2 1
5 4 3 2 1
+V3.3A 19,21,23,24,25,26,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,51,55,56,57
+V3.3A
CPU VCC_Core VR and MUX Buffer 53 +VDC_PHASE
3,4,20,35,39,43,54 +V1.05S_CPU
m
Connect from ICH & daisy chain
Place RT2C2 thermistor between the through CPU - Do not 'T' +V5S_IMVP6
R1N42 R1N45 inductor L2C1 and one of the bottom 1% R2B14
10K 10K switches Q2C2, Q2C3, Q2C4, Q2C6 R2N20 10 +V5S_IMVP6 10 Connect Vdd and PVCC to R2B23
5% 5% V5S_IMVP6 separately
o
. . 1% 68 R2N25
U1N1 +V3.3A C3P1 1.0uF 5% 10K
1% 5%
37,40,43,51 1 NC1 AD7417 NC2 16 .
6262_PMONITOR 2 15 CONVST# R2B15 147K 10% . C2P1 C2P2 H_PROCHOT#
SMB_BS_DATA SDA CONVST# AGND_VCORE
3 14 1uF 1uF C2N11 NO_STUFF
c
SMB_BS_CLK SCL VDD
U1N1_TP 4 13 AD7417_A0 NO_STUFF +V3.3S 10% 10% 0.1uF
37,40,43,51 OTI A0 10%
5 12 AD7417_A1 C1N6 C1N7 R2B10 6262_NTC_MID . . PSI#_R
.
D
REF_IN A1 AD7417_A2 0.1uF 10uF R2B7 4.02K .C2B6 C2B11 1.0uF 6262_VDD .
D
6 GND A2 11
. CPU_ICC_R 7 10 10% 20% 100K 5% 1% 10%
AGND_VCORE A_IN1 A_IN4 AGND_VCORE
8 A_IN2 A_IN3 9GFX_VR_PWRIN_R . . . 0.01uF 10% . 6262_VIN
AGND_VCORE
CPU_VCC_R R2N19 6262_PIN 6262_RBIAS
RT2C2
s
AGND_VCORE AGND_VCORE
0 R1N25 5,11,12,16,17,18,24,28,30,31,32,39,48,49,55,56,57 +V5S
NO_STUFF
. .
AGND_VCORE
1% 100 R1N39 1 2 6262_NTC +V5S_IMVP6
41,49 GFX_VR_PWRIN 10K 3 H_PROCHOT# 6262_UGATE1 53
100 1% R1N27 R2N21
VT_TT#_R
. 5% 6262_SOFT 0 6262_BOOT1 R2C56262_BOOT1_R R1B1 1%
470K
it c
6262_PMON R2N18 NO_STUFF C1N4 C2B8 0.015uF 0 C2C4 .002
0 0.1uF R2N11 0.22uF
0 39 VR_VID0 .
NO_STUFF C1B3 10% 10% . 10%
SMBUS address: 100 AGND_VCORE 5% 39 VR_VID1
10%
. . . .
39 VR_VID2 6262_LGATE1 53
0.1uF
AGND_VCORE 39 VR_VID3 6262_PHASE1 53
AGND_VCORE 39 VR_VID4
39 VR_VID5
39 VR_VID6
Connect PGND1 directly to
AGND_VCORE ISEN1 53
3,7,21,43 the sources of the lower
a
1%
R2N26
R2N17 499 PM_DPRSLPVR_IMVP6
H_DPRSTP# CPU Core VR FETs of phase 1, Q2C2 and
7,23,43 PM_DPRSLPVR Q2C4.
3 PSI#
0 5%
PSI#_R
6262_PMON
Controller 6262_UGATE2 53
.
C2N8 6262_BOOT2 R2P36262_BOOT2_R
AGND_VCORE 23 VR_PWRGD_CLKEN#
330pF 0 C2P3
. 40,43 IMVP_VR_ON
0.22uF
7,23 DELAY_VR_PWRGOOD
m
4 VCCSENSE . 10%
Layout Note: Use C2N9 .
27.4 Ohm routing 6262_LGATE2 53
6262_FB_C
330pF
for Vssense and Place R2N22 near
Vccsense 4 VSSSENSE Controller 6262_PHASE2 53
C2N10 6262_VDIFF
C2B10
e
C 0.01uF C
ISEN2 53
10% NO_STUFF R2N22 6262_FB R2B21 6262_FB2 Connect PGND2 directly
.402 475
6262_FB_R
J1E1 226 1% 1% 100 to the sources of the
1% 100pF C3B10 R2B18
2 1 . 560pF lower FETs of phase 2,
+V3.3A C2B3 56pF .
h
Q2C6 and Q2C3
6262_COMP
AGND_VCORE
5% 5%
AGND_VCORE
6262_FB_RC . R2B20
R2N23 R2N24 R3B25 1.87k 0
NO_STUFF
NO_STUFF
6262_COMP_R
27.4 27.4 6262_FB 5%
.
c
R3N25 392K 6262_COMP_RC
R1N34 R1N46 1%
Put the thermistor RT2C1 as physically
6262_DROOP
R1N30
NO_STUFF
10K 10K .
10K R2B19 1% C2B9 C3B11 1% close to the inductor L2C1 as possible
5% 5%
-s
.
6262_VW
5% . 0 6.49K 1000pF R3B24 1K 0
NO_STUFF NO_STUFF NO_STUFF R2B13 10% 100pF .
AD7417_A0 .
AD7417_A1 R3B22 VSUM 53
AD7417_A2 6262_OCSET R3B27
Load Line: -2.1mOhmLL(default) 6262_DFB_EXR2N10 6262_DFB 2.74K
To enable -5.1mOhm LL 90.9K 1% 1%
.
R1N31 R1N35 R1N40 stuff: R2B16 ,Q2B2, Q2B1, R3B13, J3B1 C2N7 R2B16 R2B5
p NO_STUFF
10K 10K 10K unstuff: R2B11 330pF R2B6 R2B9 R2B12 NO_STUFF 6262_VSUM_R
5% 5% 5% R2B11 0 0 154K 1.07k
. . 1%
NO_STUFF 13K NO_STUFF 1.07k
1% NO_STUFF
NO_STUFF C2N6 0.1uF R3B28
1
o
27,32,42,43,48,55,56,57 +V5 6262_DFB_Q 6262_DFB_NS R2N8 11K
1%
2
J3B1 (1-X): -2.1mOhmLL (DEFAULT) 10% C2B4 11K RT2C1 C3B12
AGND_VCORE AGND_VCORE AGND_VCORE 1% .
J3B1 (1-2): -5.1mOhmLL R3B13 Q2B2 0.1uF R3B26 10K 1uF C2B12
NO_STUFF
t
1 .
1K BSS138 C3B13 10% 0 20% 0.1uF C2B13
NO_STUFF NO_STUFF
1% C2B7 0.1uF NO_STUFF NO_STUFF 10% 0.22uF
2
B
5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,55,56,57 +V3.3S NO_STUFF 180pF 10%
. NO_STUFF 10%
B
DLL_FET 5% .
3 3
p
+V3.3S 6262_FET .
2
AGND_VCORE
J3B1
Q2B1
R1N7 BSS138
VCC_PRM 53
R1N19 R1N14 R1N11 R1N9 R1N5 R1N3 R1N1 NO_STUFF 1
l. a
1
R2B2
2
8.2K R2N5 402K

1% CPU_ICC 41
8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K U1B2 7.5K .
IMVP6_STRAP_VID0
2 46 1% 4
A0 C0 VR_VID0 39
IMVP6_STRAP_VID1 5 A1 C1 44 VR_VID1 39 .
AGND_VCORE
8 41 6262_VO_R R2N3 7.5K 6262_VO_RR 2 - U2B1A R1B4
IMVP6_STRAP_VID2 A2 C2 VR_VID2 39
11 38 1% 1 CPU_ICC CPU_ICC_R
13 36 C2N4 R2B3 15K 6262_DROOP_R 3 + 100 1%
16 33 0.1uF . 1%
w
18 31 10% . AD8552 C1B4
IMVP6_STRAP_VID6 A6 C6 VR_VID6 39 8 .
21 28 NO_STUFF R2N7 C2N5 +V5 27,32,42,43,48,55,56,57
0.1uF
A7 C7 402K 0.1uF 10%
Power Monitoring 23 26
15
13
11
A8 C8 1%
9
7
5
3
1
AGND_VCORE
J2B2 6262_DROOP . 10% OP_CPU_ICC_R R2B8 10 .
VCORE Signal 3 B0 16V 1%
4 H_VID0 D0 45 NO_STUFF C2B5
4. H_VID1 6 B1 D1 43
w
9 B2 0.1uF GAIN ADJUSTED FOR 27
4 H_VID2 D2 40
16
14
12
10
8
6
4
2
AGND_VCORE
0.1uF 12 B3 .10%
C2B16
4 H_VID3 D3 37 16V
4 H_VID4 14 B4 D4 35
AGND_VCORE AGND_VCORE
1% 17 B5
75K
4 H_VID5 D5 32 AGND_VCORE
NO_STUFF
4 H_VID6 19 B6 D6 30
6262_PMON R2B22 R2N9 V3_3_S0 22 B7
V3_3_S0 D7 27
5,11,12,16,17,18,24,28,30,31,32,39,48,49,55,56,57 +V5S
w
. 49.9K 1% 24 B8
A
5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,55,56,57
10% +V3.3S D8 25 A
Input Output S2 S1 S0 Pillar Rock Intel Confidential

8 OP_CPU_ICC_R 1 S0 VCC 7
NO_STUFF R1B2 48 4 A C 1 1 0
VCCSENSER2N12 49.9K
SPR_GT_5 5 + U2B1B R1B3 S2_S1 47
S1
S2
GND0
GND1 10 B C 1 1 1 Title
1% 7CPU_VCC CPU_VCC_R C1N3 A D 1 1 1
VSSSENSE R2N13 49.9K SPR_GT_6 6 100 10K 1%
34
39
GND5 GND2 15
20 .01uF B D 1 1 0 IMVP-6 Controller
- GND6 GND3
NO_STUFF 1% 1% C1B2 42 29 20%
AD8552 NO_STUFF 0.1uF . GND7 GND4 .
R2B17 4 10% 10% 74CBT16209A Size Document Number Rev
49.9K
1% . AGND_VCORE
.
0.1uF
C2B15 SPR_GT_6
A 355659 1.0
AGND_VCORE
R2N16 75K NO_STUFF
AGND_VCORE
1%
CPU_VCC 41
5 4 3 2 1
5 4 3 2 1
52 +VDC_PHASE
m
+VBAT 17,49,55,56,57
R1P5 1%
o
.002
c
C2C10 C2C13 C2C9 C2C5 C2C12 C2P5
0.01uF 0.01uF 0.01uF 0.01uF C2C8 C2C7 47uF 47uF C2C11 C2C2 C2P4
.
5
5
D D
Phase1 D D 10% 10% 10% 10% 10UF 10UF 20% 20% 10UF 10UF 10UF
.402 .402 .402 .402 16V 16V
G Q2C1 G 25V 25V 25V 25V NO_STUFF NO_STUFF
s
4 HAT2168H 4 Q2C5
HAT2168H 4,54,55 +VCC_CORE
S S
6262_UGATE1
1
2
3
1
2
3
NO_STUFF
it c
52 6262_PHASE1
1
CR2P2 R2C7
6262_LGATE1 11K
R2C3
1%
5
D D Connect at the R2P2 R2C6 1.00
11K 1% NO_STUFF
B320A 3.32k
G Q2C2 G
same point. 1% 1% . ISEN2
a
.
2
4 HAT2164H 4 Q2C4 C2C6 0.1uF
HAT2164H 10% Place near Controller LAYOUT NOTES:
S S
1
2
3
1
2
3
C2C3 0.1uF Place R2P2 & R2C6 right next to
VCC_PRM 52
m
each other. Route a single trace
from the input pad of the inductor
10%
and T at the resistors. --> Do not
e
C use plane flood. This applies for C
R2P1 & R2C4

as well.
h
ISEN1
VSUM 52 Place CR2P2 near Q2C2, Q2C4 and

Q2C1 . Route
c
Use a large pad for
this voltage. sharing the ground and switch
nodes with low side FETs. This
The jumper and sense
-s
resistor for this side of applies for CR2P1 and Q2C3, Q2C6
52 +VDC_PHASE J3C3
the inductor must be in the 2 1 and Q3C1as well.
same layout fashion as the
ones for the other side of
the inductor. . Place the 0402 caps near the drain
C3C8 C3C9 C3C12 C3C3 C3P3 C3C1 C3C11 C3P2 C3C6
0.01uF 0.01uF 0.01uF 0.01uF C3C2 C3C10 47uF 47uF of the high side FETs for each
p
10% 10% 10% 10% 10UF 10UF 20% 20% 10UF 10UF 10UF phase.
.402 .402 .402 .402 16V 16V J2C1
25V 25V 25V 25V NO_STUFF NO_STUFF 1 2 R2D1
o
L2C1 NO_STUFF
0.002
. 2 2 *1 1
t
Use a large pad for
B this voltage. R2D2 B
NO_STUFF
0.002
4
4 *3 3
p
52 +VDC_PHASE Coupled_Inductor 310nH
The jumper and sense

resistor for this side of
l. a
the inductor must be in the
same layout fashion as the
5
D D ones for the other side of

Phase2 the inductor.
G G
4 Q3C1 4 Q3C2
HAT2168H HAT2168H
S S NO_STUFF 1%
w
6262_UGATE2
1
2
3
1
2
3
R2C2 11K
ISEN1
52 6262_PHASE2
NO_STUFF
6262_LGATE2
Connect at the R2C1
w
R2P1 R2C4 1.00
11K same point.
5
D Q2C3 D CR2P1 3.32k 1%

1% .
1% .
Q2C6 G G C2C1 0.1uF
B320A 10%
w
A 4 4 A
HAT2164H HAT2164H
2
S S
1
2
3
1
2
3
C2B14 0.1uF
Title
Place near Controller
IMVP-6 Drivers and FET
10%
52 VSUM A 1.0
ISEN2
52 VCC_PRM
5 4 3 2 1
5 4 3 2 1
Vccp Core Decoupling
m
3,4,20,35,39,43,52 +V1.05S_CPU
o
Place these inside socket
C3T7 C2T25 C2T1 C2U1 C2T26 C2T2 cavity on L8 ( North side
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF Secondary)
.10% .10% .10% .10% .10% .10%
. c
D D
s
4,53,55 +VCC_CORE Vcc Core Decoupling
it c
Place these inside socket C2T7 C2T3 C2T23 C2T20 C2T18 C2T15 C2T9 C2T13
22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF
cavity on L8 ( North side 20% 20% 20% 20% 20% 20% 20% 20%
Secondary) . . . . . . . .
a
C2T16 C2T24 C2T21 C2T19 C2T11 C2T8 C2T6 C2T4
22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF
20% 20% 20% 20% 20% 20% 20% 20%
Place these inside socket . . . . . . . .
cavity on L8 ( South side
Secondary)
C2T5 C2T22 C3T6 C3T1
m
330uF 330uF 330uF 330uF
10% 10% 10% 10%
. NO_STUFF
e
C C
Place these outside socket C2T14 C2T12 C3T4 C3T3 C3T2
22uF 22uF 22uF 22uF 22uF
cavity on L8 ( North side
h
20% 20% 20% 20% 20%
Secondary) . . .
s c
C3T5 C2T17 C2T10
Place these outside socket 22uF 22uF 22uF
20% 20% 20%
-
.
Secondary)
p
C2E1 C2E3 C2E7 C2E6 C2E4 C2E2
Place these inside socket 22uF 22uF 22uF 22uF 22uF 22uF
20% 20% 20% 20% 20% 20%
cavity on L8 ( North side
o
. . . . . .
Primary)
t
B B
C2E5 C2E8 C2E9 C2E12 C2E10 C2E11
p
Place these inside socket 22uF 22uF 22uF 22uF 22uF 22uF
20% 20% 20% 20% 20% 20%
. . . . . .
Primary)
l. a
w w
w
A A
Title
CPU Decoupling

A 355659 1.0

5 4 3 2 1
5 4 3 2 1
SLP_S3# DISCHARGE CKT SLP_S4# DISCHARGE CKT
DESIGNED FOR ~100ms DESIGNED FOR ~100ms
m
DISCHARGE ON ALL S3 DISCHARGE ON ALL S4
RAILS. RAILS.
o
19,27,32,39,41,42,43,57 +V3.3
5,7,10,12,13,16,17,18,19,20,21,22,23,24,25,26,28,30,31,32,35,36,38,39,40,41,43,48,49,52,56,57 +V3.3S
25,26,30,31,32,43,57 +V12S
1
c
R7B1 R5V11
180 R4W15 97.6
.
17,49,53,56,57 +VBAT 97.6 .
D . D
3 2
PP_V12SDIS PP_V3SDIS PP_V3DIS
3
Q7B1 Q4H3 Q5G3
s
1
BSS138 BSS138 BSS138
CR3R1 1 1 1
BAT54
. . .
2
it c
3
VBATA_DISCHARGE
5,11,12,16,17,18,24,28,30,31,32,39,48,49,52,56,57 +V5S +V5 27,32,42,43,48,52,56,57

19,57 +VBAT_S4
1
C3P5 R3R6
a
22UF 100K R6N5
R4W14 R5W1 180
97.6 97.6
. .
3 2
PM_SLP_S3 PP_V5SDIS PP_V5DIS PP_BATS4DIS
3
Q4W1 R3R1 Q5V2 Q6N2
3
BSS138 100K BSS138 BSS138
m
Q3R1 1 1 1
BSS138 R3R5
1 1M . . .
11,23,40,43,44,46,47,49,57 PM_SLP_S3#
2
.
e
C 2 PP_S4GT C
16,19,27,30,31,57 +VBATS
15,46 +V0.9
9,10,13,14,46,48,57 +V1.8
h
4,10,11,24,28,47,57 +V1.5S R5V10
1
1M R4B9
R5H5 R4V14
180 100K R5B3
c
68
R4V6 220 5%
3 2
47 PP_12DIS PP_V0.9DIS .
3
4,9,10,24,47 +V1.05S
Q5H1 Q3R2 Q4B2 PP_V1.8DIS
-s
3
PP_V1.5SDIS BSS138 BSS138 BSS138
3
1 1 DDR_DIS 1 Q5N1
+V3.3A R3D3 Q4V1 BSS138
470 BSS138
5% . . . 1
2
3
. 1
Q4G6 .
2
R4D3 PM_SLP_S3_BUF_R . BSS138
2
100K 1
3
p
Q4D1 .
2
BSS138
23,32,40,43,44,57 PM_S4_STATE#
PM_SLP_S3_BUF 1
3
o
. 10,11,48 +V3.3S_TVDAC
23,46 PM_SLP_S4#
2
Q3R5
BSS138
t
11,23,40,43,44,46,47,49,57 PM_SLP_S3# 1
R3R12 22,24,33,34,44,48,57 +V3.3M_WOL
. 4.87K
2
B 4,53,54 +VCC_CORE 1%
.
B
p
PP_V3STVDIS R4V12
97.6
3
R4R8 9,10,15,35,47 +V1.05M . 13,14,15,23,35,57 +V3.3M
47 Q3R3 PP_V3MDIS
l. a
3
BSS138
1 Q4G4
PP_VIMVPDIS R4V13 BSS138 R4H1
3
470 470
. 5% 1 5%
2
Q3R4 . .
BSS138 R4V11 .
2
1 10K PP_V105M_DIS PP_V33MCKDIS
3
. . Q4G5 Q4H1
2
BSS138 PP_V33M_DIS BSS138

PM_SLP_M1 1
3
w
. R4G5 Q4G2 .
2
100K BSS138
3 5%
1 .
Q4G3 R4V9
BSS138 1M
2
1
w
23,40,43,44,47,57 PM_SLP_M#
. LAN_WOL_EN 23,40,43,57
2
ATX Mounting Holes
w
A MT1B1 MT1J1 MT1F1 MT5A1 MT9A1 MT9F1 MT9J1 MT5J1 A
2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 Pillar Rock Intel Confidential
3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7
4 8 4 8 4 8 4 8 4 8 4 8 4 8 4 8 Title
5 9 5 9 5 9 5 9 5 9 5 9 5 9 5 9
DISCHARGE CIRCUITS
MT156 MT156
NO_STUFF NO_STUFF MT156
NO_STUFF MT156
NO_STUFF MT156
NO_STUFF MT156
NO_STUFF MT156
NO_STUFF MT156
NO_STUFF

A 355659 1.0
5 4 3 2 1
5 4 3 2 1
45 +V5A_MBL
+VBATA_PS_LATCH
SI4965DY
Q3H6A 50,51 +VBS Q1J1 26,45,46,47,57 +VBATA 17,49,53,55,57 +VBAT
m
24,29,34,38,44,46,47,50,51,57 +V5A SI7483ADP 26,45,46,47,57 +VBATA
8 3 FDS6679AZ
1 +V5_ATX 5 2 3 8 3
+V5SB_ATXA 7 R4J1 1 2 7
1 2 C1J5 + C1J1 1 6 + C5B2 + C2W2 + C2W4 1 2 +VBATA_LATCH_SHUTDOWN
o
R1J7 0.1uF 15uF R2H17 5 15uF 15uF 15uF
0 100K 10% 20% 1M C1J4 R1J6 20% 20% 20%
J3J2
4
2 NO_STUFF . . 390K Q2W8 . . . CR1
6 0.33uF
4
1
1
+ C5H2 + C4H5 BAT54A
3
220uF 220uF . 80% 2 1
Q3H6B VBSGT PWRONLATCHG
c
5 10% 10% 20K
SI4965DY . . Power 20K
2
R3V4 R3W1
PS_ON_SW# 44
.
R3V3 Button Latch
4
D 10K R2H13 D
26,45,46,47,57 +VBATA 5% 100K SHUTDWN#
. CR2W3
3
R3W21 100K C4V3 V12ATXSW 3 1 PS_LATCH#
3
Q4G1 0.1uF
3
BSS138 10% BAT54 Q2W3 Q3W1
R4V7 ATXPWR 1 . Q3G1 POWER ON CR3V1 BSS138 BSS138
0 BSS138 and S5 3 1 1 1
ENTER/EXIT
it c
. 1 ATX_PWR_CNTRL +V3.3A
R2G27
2
R4V8 Button BAT54
. . .
2
1K . Battery Mode: ATX_PWR_CNTRL = VBATA SMC_SHUTDOWN_R
2
5% Brick Mode: ATX_PWR_CNTRL = VBATA 3.3K 5%
ATX Mode: ATX_PWR_CNTRL=0V
+V3.3A R2W5 R2W6
3
+V3.3_ATX 100K 100K .
ATX_PWR_CNTRL 57
3
4
3
+V3.3A_MBL Force Shutdown J2G1 4700PF R3W13 Q1V4
Q4G7 C3W1
PS_PWRBTN
SW1C1 Q2W7 43K
IRF7822 SMC_ONOFF# 40,43
R4W21 Push_Button BSS138 NO_STUFF 1
2
a
3
. 8 1 2 1 BSS138
40,43 SMC_SHUTDOWN
3 7 Q2W4 .
1
2
2
2 6 + C4H4 + C4H2 0 BSS138 .
2
3
1 5 220uF 220uF NO_STUFF 1
10% 10%
3
VR_ALW_ENABLE CR2W4
. .
Active High: Q2W2 . BAR43S R2W10
2
SHUTDWN#||BC_ACOK_BATT)&ATX_PWR_CNTRL BSS138 100K
23,40,43 PM_RSMRST#
4
1 26,45,46,47,57 +VBATA
m
Enables on board Always VRs (5MBL,
1
R2W7ADAPT_PRES_R 3.3MBL, and 1.5A) when running off .
50 BC_ACOK_BATT
2
0 AC brick or battery. Low in ATX
BC_ACOK_BATT R2W9 mode.
100K . R3W5
e
Active High: When AC brick
present charger starts and NO_STUFF 100K 2
C asserts this signal, which R8E4 R8E2 +V3.3A C
CR2W1 Q3W2 100K 100K
starts the on board always
BAT54C BSS138
Net Detect
rails by forcing the
assertion on VR_ALW_ENABLE Button Latch R8T3
h
assuming ATX_PWR_CNTRL is 3 PS_ACENABLE 3 2 CR8E1 100K Signals EC of a net
VR_ALW_ENABLE 28,45 detect button event.
asserted. Ignored by H8 in 3 1 NETDETECT_12V
ATX mode. NETDETECT_12V#
. BAT54
41 ND_SW# NETDETECT# 40,43
3
1
3
Q8E4 Q8E3
Jumper J4H1 1 BSS138 BSS138 Q8E2 3.3V Net Detect Level Shifter
3
4
Open (Default) No After_G3 support 1 1 1 BSS138
1-2 After G3 support with ATX supply SW8E1 Q8E1 1
-s
MOBILE OPTION 2-3 After G3 Support with AC brick Push_Button . . BSS138
.
2
SHUTDWN# R3W17 Net Detect . SMC_NET_DETECT: Net
2
PS_LATCH# 0 Button C8E2 R8E1 Detect trigger signal
1
2
PS_ON# SHUTDWN# NO_STUFF 1000PF 43K to ICH9M. Also clears
10% NO_STUFF netdetect button
1 latch.
PS_ON# internally pulled up Active High: Goes high .
to 5V standby in all ATX on pwr button press Stuff R3W17 only AC_PRESENT 23,40,43
supply per ATX 12V spec. turing on the on board for G3 Mobile
p
CR4W2 3 PS_ON# always rails in battery power cycling
BAT54A mode. Forces
VR_ALW_ENABLE high when
+V5SB_ATX +V5A ATX ALWAYS ON ATX_PWR_CNTRL is high
DT OPTION (in mobile mode). Also 19,21,23,24,25,26,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,57 +V3.3A
2 allows H8 to shut the
o
+V3.3S
board down via
PS_ON_SW#
SMC_SHUTDOWN when R3W17
1
R5W12
t
is stuffed.
RESET 10K
+V3.3A J4H1 BUTTON SW1C2 U5H2 C5W6 C5W5
RSTBTNDB 44
CON3_HDR . 1 4 . 0.01uF 0.1uF
2
B R4W19 1 3
GND VCC
10% .10% B
5
1K 2 4 U5H1
p
R4H3 NO_STUFF Push_Button 2 3 MASTER_RESET#
1
220K IN OUT
ME_G3_TO_M1
5% 4 PM_SYSRST# 23
5% -V12_ATX 57 -V12A 26,45,46,47,57 +VBATA MAX6816 2
. 5,11,12,16,17,18,24,28,30,31,32,39,48,49,52,55,57 +V5S R5W13 100K
+V12_ATX 1 74AHC1G08
3
l. a
40 ME_G3_TO_M1# R4Y1 0.002 +V5S
.
3
1% Shunt pins 13 & 15 CR6W1

XDP_DBRESET#_R
3
Q4H10 for SV forcing ATX BAT54 R7H17

Q4J1 BSS138 . on and VBAT on for 330 R7H16
BSS138 1 power cycling +V5 27,32,42,43,48,52,55,57 330
1 R4Y2 +V5SB_ATXA 3 J6H5
.
. +V3.3_ATX ATX POWER +V3.3_ATX 0.002 +V5SB_ATX FRONT1 1 2 FRONT2 .
2
. 1% 3 4
21 SATA_LED#
2
J4J1 +V5_ATX . 5 6 PWR_CONN_D C7H6

11 1 ATX_DETECT# RST_PUSH#_D 7 8 470pF
R4H5 11 1 +V3.3A 5%
12 2 Acitve Low: Indicates system is 9 10
12 2
w
390K 13 3 powered by ATX supply to H8: 11 12 .
13 3 R5H8 0.002
14 4 Note H8 looks at this signal 13
14 4 1% R9H19 PS_LATCH#
15 5 before BC_ACOK#. 15 16
15 5 10K CR7H2
16 6 3.3V=Mobile Mode (BATT or Brick)
+V5_ATX 16 6 R9H22 5% HDR_2x8 PS_ON_SW#
17 7 . 0V=ATX mode powerd by ATX supply 3 1
17 7 10K
18 8 ATX_PWROK 41 .
+V5SB_ATX 18 8 5% C7H4 C7H8 C6H4 BAT54
19 9
w
19 9 ATX_DETECT# 40,43
5V_DL R5J1 3.0 20 10 . 470pF 470pF 470pF C7H7
20 10
3
5% 5% 5% 5% 470pF
5V_DL_R
5SB_ATXA_R
CON20_PWR Q9H5 . . . 5%
. BSS138 Front Panel Header .
1
2
5
6
R5H9 R4W20 1
10K Q5Y1 3.0
5% R5H7 5%
w
.
A A
2
.
+V5_DL_Q 3
SI3442BDV
R5W20
3.0
5% +V5SB_ATXA +V3.3_DL_QR R4H4 3.0 3.3V_DL_R
. Pillar Rock Intel Confidential
3.0 . 5% R9H21
Title
1
2
5
6
5% 10K
PS_ATXSENS
R5H6 Q4H9 5%
. .
Start Up Sequence
4
10K .
5% SI3442BDV 3V MIN CURRENT
+V3.3_DL_Q
. 3 DUMMY LOAD:
Gives 0.5A min
5V MIN CURRENT current load Size Document Number Rev
DUMMY LOAD: Gives
0.5A min current A 355659 1.0
4
load

5 4 3 2 1
5 4 3 2 1
+V3.3S
m
+V3.3A 4,10,11,24,28,47,55 +V1.5S
9,10,13,14,46,48,55 +V1.8 Q4U1 19,21,23,24,25,26,27,28,29,32,37,38,39,40,41,43,44,45,46,47,48,50,51,52,55,56 +V3.3A
5,11,12,16,17,18,24,28,30,31,32,39,48,49,52,55,56 +V5S IRF7822
26,45,46,47,56 +VBATA 8 Q4W2 8
2
SI4965DY 7 3 IRF7822 7 3 +V3.3A
o
Q3H3A 6 2 . 6 2 Q5W4
24,29,34,38,44,46,47,50,51,56 +V5A 5 1 5 1 1 SI2307DS
23,32,40,43,44,55 PM_S4_STATE#
2
8 R4W18
1 100K NO_STUFF Q5W3 .
3
C4V1 SI2307DS PP_S4LEDSW1
c
7 23 PM_SLP_S5# 1
4
VBATA_SLEEP 0.33uF
+V3.3A C327 80% .PP_S5LED
3
3
.
R4W16 0.1uF C4W2 Note: only stuff Q4U1 NO_STUFF R5W10
2
D 100K .10% Q4H4 . 0.01UF and C4V1 for DDR3 Board 75 D
BSS138 +V3.3A 10%
R4H2 1 R5W7
10K PS_S3CNTRL R4W23 PS_S3CNTRL_R 75
s
5% 100K +V5 27,32,42,43,48,52,55,56
. 19,27,32,39,41,42,43,55 +V3.3 PP_S4LED
2
3
2
NO_STUFF 5% CR5H7
Q4H5 26,45,46,47,56 +VBATA PP_S5LEDSW GREEN
BSS138 . Q3H3B Q4H2 19,27,32,39,41,42,43,55 +V3.3
S4
8
2
SI4965DY
it c
1 7 3 IRF7822 13,14,15,23,35,55 +V3.3M CR5H5
11,23,40,43,44,46,47,49,55 PM_SLP_S3#
6 6 2 . S5 GREEN
1
2
. 3 R4W17 5 1 PP_S4_LEDSW2 .
2
24,29,34,38,44,46,47,50,51,56 +V5A 5 100K Q5W5
3
1 SI2307DS
11,23,40,43,44,46,47,49,55 PM_SLP_S3#
1
. Q5H2
4
C3W8 SLPS4#_CONTROL . R4W6 BSS138
3
3
R3W16 0.1uF 4 C4H3 PP_S3CLED 75 1
100K 23 PM_SLP_S5#
R4W24 .10% Q4W4 0.1uF
BSS138 10% .
2
a
PS_S4CNTRL PS_S4CNTRL_R 1 . R5W11
75 PP_M0_LED
3
2
100K +V3.3S
2
Q4H6 CR5H3
BSS138 . PP_S3CLEDSW GREEN
5%
M0/M1 +V3.3S
23,32,40,43,44,55 PM_S4_STATE# 1
2
R8W9 CR5H6
25,26,30,31,32,43,55 +V12S 75 S3 GREEN
m
.
2
1
26,45,46,47,56 +VBATA Q5H3 .
+V3.3A SI4425DY COLD
3 8 SYS_STATUS_PU
1
2
2 7 PP_S3CLEDSW_D
. R5W14
1 6 C4Y1 System Power Good CR7H3 75
3
5 0.33uF GREEN
C R5W16 80% Q4W3 C
10K C5W8 . BSS138 PP_S0LED
3 1
5% 0.1uF SYS_STATUS_CR
. PS_S3CNTRL 1
2
ATX_PWR_CTRL_1
. 10% R5W17 75 ohms chosen for ~16mA of CR5H4
h
. 100K Q7H1 . LED current SO GREEN
2
1%
3
. BSS138
Q4H8 1
7,19,22,25,26,38,41 PLT_RST#
BSS138 PS_12SSW
1
PP_S0_LEDSW
c
56 ATX_PWR_CNTRL 1 . .
2
C5W7 R4W22
3
. 0.1uF 100K
2
10% +V3.3A Q5W6

5
U5H3 . BSS138
-s
1 22,24,33,34,44,48,55 1
PS_12SG 11,23,40,43,44,46,47,49,55 PM_SLP_S3#
4 Q6B4 +V3.3M_WOL
2 8 IRF7822 .
11,23,40,43,44,46,47,49,55 PM_SLP_S3#
2
3
7 3
74AHC1G08 Q4H7 6 2 .
3
. BSS138 5 1
PM_S3#_AND 1
26,45,46,47,56 +VBATA
p
.
2
4
17,49,53,55,56 +VBAT Q6B2 +VBATS 16,19,27,30,31,55 19,55
Q6N1 +VBAT_S4 R6N4 V3M_G_SWITCH 13,14,15,23,35,55 +V3.3M
SI4425DY SI4425DY 100K
3 8 17,49,53,55,56 +VBAT 3 8 J8G2
3
o
2 7 2 7 R7N1 C6N2 1 2 PP_S3CLEDSW_D
1 6 1 6 100K Q6B1 . 0.01UF PP_S5LED 3 4 PP_S0_LEDSW
5 C6B2 5 C6N7 BSS138 10% 5 6 PP_S4_LEDSW2
t
0.33uF 0.33uF V3M_G_SWITCH_OR 1 PP_S3CLED 7 8 PP_S4LEDSW1
C6N3 R6N3 80% C6N1 R6N2 80%
4
0.33uF 100K . 0.1uF 100K . 8Pin HDR

PS_VBATSG
PS_VBAT_S4_G
2
B B
3
80% 10%
. . Q7B2 Q6B5
p
BSS138 BSS138
23,40,43,44,47,55 PM_SLP_M# 1 1 LAN_WOL_EN 23,40,43,55
R6M13 R6N1 . . Added for WOL in
2
100K 100K S3/Moff. Enabled by
l. a
CLGPIO3=LAN_WOL_EN.
WOL_GPIO56
PS_VBATSW PS_VBAT_S4_D
3
3
Q6N3 Q6M1 +V3.3A BSS138
BSS138 BSS138 13,14,15,23,35,55
Q5W1 +V3.3M Q7C1
11,23,40,43,44,46,47,49,55
1 1 8 IRF7822 1
PM_SLP_S3# 23,32,40,43,44,55 PM_S4_STATE# ICH_GPIO12 23
7 3
. . 6 2 . .
2
2
26,45,46,47,56 +VBATA 5 1
w
ICH_GPIO12 SLP_M# LAN_WOL_EN 3.3M_WOL 3.3M SYSTEM STATE
4 1 0 0 0V 0V Moff / No WOL
1 0 1 3.3V 0V Legacy WOL / Moff
R5V7 100K C5V8 1 1 0 3.3V 3.3V M1
56 -V12A V3.3M_SWITCH 1 1 1 3.3V 3.3V M1
. 0.01UF 0 0 1 0V 0V Moff / No WOL
10%
w
R5V6
3
C9A7 100K
0.1uF Q5W2
10% BSS138
R9A6 . V3.3M_INV 1
10K
3
5%
Pillar Rock
w
A .
Intel Confidential A
2
. Q4W5
1
2
3
BSS138
Q9A3 1 Title
4
U9B1 SI4420DY . Sleep control
PS_-12SSW
1 4 C9A6
0.1uF
+V5S 10%
. 32 -V12S Size Document Number Rev
5
6
7
8
R9M3PS_-12OPTSW
330
2 3
Added to isolate CK505 from 3.3M
A 355659 1.0
TLP280 when WOL/Moff is enabled.
.
5 4 3 2 1
5 4 3 2 1
Steps 1 leads to either 1BAT for battery only

Pillar Rock Mobile Power On Sequence
m
mode or 1AC for AC mode. 5AC leads to 5a
to 5b to 5c to 6. Battery mode requires +VBAT +VBATA
o
Battery OR AC
SHT 51
button press to begin power up. AC mode insertion cause 1
+VBS 1 Battery
c
requires button press to boot. Sequence waits here for 1BAT i®AMPS Pack
.
button press before
D D
doing step 1BAT = 5AC.
Startup 1AC Circuit AC
5AC
s
PM_SLP_S3# BC_ACOK_BATT SHT 50
PS_ON_SW# Circuit
Only AC insertion
causes 1AC
Adapter
+VBATS +VBAT PG 56 SHT 50
7
it c
7 +VBATA SHT 56
+V3.3S_TVDAC
7 +V5S 6 +V5A +V3.3A
SMC_ONOFF#
SLP_S3 SYSTEM
LDO
SHT 11 SWITCHES 3 +V5A 5a
7 +V3.3S +V3.3A VR VR_ALW_ENABLE MAX-809
a
SHT 57
+V3.3A
3 SHT 45 2 SHT 42 ICH9M
SHT
PWRGD 4 21,22,23,24
+V5A3A_MBL_PWRGD
H8 SMC
m
7 +VBAT_S4 PM_S4_STATE#+VBAT SMC_RST#
+V1.5A_HDA_IO +V3.3A SHT 40 & 41 MPWROK CLPWROK
LDO
7 6 +V5A 3 14
e
+V5
C SLP_S4 SHT 28 C
SWITCHES PM_PWRBTN# 5b CLK_PWRGD
7 +V3.3 +V3.3A
CLGPIO3/GPIO9
SHT 57
VRMPWRGD
5c
c
PM_SLP_S4# +VBAT
RSMRST#_PWRGD PM_RSMRST# 17 H_PWRGD
(300ms MAX)
7 +V1.8
3a IMVP_VR_ON
PM_ICH_PWROK
s
99ms DELAY
6 PWROK
DDR VR 11 10 16
-
7 +V0.9 SHT 46
6 SHT 23 18
to line
PLT_RST#
+V3.3M_WOL switches
to
PWRGD VRPWRGD_3.3M_R PM_SLP_S4#
+V3.3A 6 PM_S4_STATE# 6 to DDR VR
+V5S
DDR_PGGOD_RU
SYSTEM 6 PM_SLP_S3#
B VR POWER
+V3.3S
8 6 PM_SLP_M# +VCC_GMCH_CORE, +VCC_CORE, B
GOOD MPWROK 9 7
p
SHT 46 LAN_WOL_EN +VCCP +VCCP
MONITOR to ICH & MCH +V3.3M_WOL +V3.3A
+V3.3S_TVDAC
7 SWITCH
SHT 48 +V3.3A
la
PM_PGOOD_1_05M +V3.3M SHT 57 OR PWRGD
CANTIGA
PM_SLP_M#
+VBAT SWITCH
CPU
PM_SLP_S3#
9 SHT 57 GMCH 19 H_CPURST#
.
PM_SLP_S3#
SHT 46 PM_PWROK
8 PM_SYS_PWRGD +V1.05M
SHT
+VBAT 6,7,8,9,10,11
7 PWROK
11 SHT 47
ALL_SYS_PWRGD
w
CLK_PWRGD 14 +VCC_CORE IMVP_VR_ON +V1.05S +V1.5S MPWROK
CLPWROK SHT 3,4
+V3.3M VCCP 7 ICH LOGIC
12 MCH,ICH CORE SHT 47 GVR_VR_EN
ENABLE ENABLE +VBAT +VCC_GFXCORE
w
VR_PWRGD_CLKEN# GFX VR
CK505 PM_1.5_1.05S_PGOOD
System IMVP6+ CPU 8 +V3.3A
Clock 13 CORE VR
w
A +V3.3S Pillar Rock Intel Confidential A
SHT 35 CANTIGA_VR_PWRGOOD
SHT 47 Title
+V3.3S SHT 52 POWER SEQUENCING TIMING BLOCK DIAGRAM
DB800M 10
SHT 47
CLOCK EN PM_PWROK
BUFFERS 15 DELAY_VR_PWRGOOD A 355659 1.0
VR_PWRGD_CLKEN
SHT 36
5 4 3 2 1

Laptop Schematic Diagram (Intel Montevina Mobile Platform)

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Laptop Schematic Diagram (Intel Montevina Mobile Platform)

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Copyright:

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5 4 3 2 1

PILLAR ROCK Montevina Mobile Platform Fab 3

Size Document Number Rev

3 As seen from top 2

Wake Events State Supported

A5 C7 H_D#6 E25 U25 H_D#38

TP_CPU_RSVD05 B2 H25 U22

Date: Tuesday, August 28, 2007 Sheet 3 of 58

53,54,55 +VCC_CORE 53,54,55 +VCC_CORE

Date: Tuesday, August 28, 2007 Sheet 4 of 58

GND0 GND2 NO_STUFF

Size Document Number Rev

H_VREF & H_DVREF

Size Document Number Rev

DDR CLK/ CONTROL/COMPENSATION

MCH_CFG_9 AD35 DMI_RXP0 Layout Note: PEG_TX0

C23 16 CRT_BLUE E28 J42

MCH_CFG_18 CFG_18 16 CRT_DDC_DATA_MCH CRT_DDC_DATA PEG_TX_9

TP_MCH_NC3 BD48 AH34 MCH_CLVREF_R 0

TP_MCH_NC10 BG45 E36

TP_MCH_NC24 NC_23 HDA_SYNC IMPORTANT NOTE:

AV5 BG26 AV2 BB16

Size Document Number Rev

BC29 AG19 0.002 AF28

T14 BA37 +VCCSM_LF2

Size Document Number Rev

L5F1 10uH SMC0402

NO_STUFF 1000pF V1 1.0uF 10uF

C FB4E1 + . 22uF 22uF 4.7uF 1.0uF AR17 VCCA_SM_4

C5R5 C5R6 C5R9 AP25 B21 R5E4 C5E6 C5E15 20%

R5T10 U48 7 +VCC_PEG

10% L37 A8 +VTTLF_CAP1 NO_STUFF L5D1

AB2 +VTTLF_CAP3 91nH 0.002

+V1.5S_LDO_QDAC_R 180ohm@100MHz C5U3 C5U2 46 +V1.8_LDO 0.002 SMC0402 SMC0402 NO_STUFF

VSS_67 VSS_166 VSS_266 VSS_NCTF_7

VSS_79 VSS_178 VSS_278 VSS_SCB_2 PM_SLP_S3# NO_STUFF

VSS_93 VSS_192 VSS_292 NC_34

Size Document Number Rev

FSB Dynamic ODT

3 7481_D1P_Q R3B16 U3B2

MCH_CFG_10 (PCIE Loopback enable) Size Document Number Rev

C5C1 C4C13 C5C3 C4C12 C5C4 C4C11

Date: Tuesday, August 28, 2007 Sheet 13 of 58

SO-DIMM1 is placed farther from

Size Document Number Rev

Size Document Number Rev

19,27,30,31,55,57 +VBATS +V5S_F_DAC

5,11,12,16,18,24,28,30,31,32,39,48,49,52,55,56,57 +V5S +V3.3S

R6V2 0.002 TP_+V2.5 VDL_CLKAP

+V3.3S STUFF R6V2 50

TP_+V2.5 STUFF R6V4

Size Document Number Rev

Port Value Voltage

TV_DCONSEL1_LVL VDD IO_0 R2A4 10K DLINE2

5 TV-OUT DAC Channel Definition

Date: Tuesday, August 28, 2007 Sheet 19 of 58

Size Document Number Rev

CR7H1 . 24.9 AG25

NMI AF23 H_NMI 3,43

THRMTRIP# 1% PM_THRMTRIP# 3,7

B SATA_RXN5_C C7H12 0.01uF B

H_RCIN# R8U6 10K

Size Document Number Rev

Date: Tuesday, August 28, 2007 Sheet 21 of 58