Date: Exercise.

No:9
COUNTERS

Objective
1. To design 1-DIGIT COUNTER, 2-DIGIT COUNTER and To Write a
VHDL Code for it.
2. To generate the Test Bench Waveform and verify it with the design.

THEORY

In digital logic and computing, a counter is a device which stores (and sometimes
displays) the number of times a particular event or process has occurred, often in
relationship to a clock signal.In electronics, counters can be implemented quite easily
using register-type circuits such as the flip-flop, and a wide variety of classifications
exist:
1.Asynchronous (ripple) counter – changing state bits are used as clocks to
subsequent State flipflops
2.Synchronous counter – all state bits change under control of a single clock
3.Decade counter – counts through ten states per stage
4.Up/down counter – counts both up and down, under command of a control input
5.Ring counter – formed by a shift register with feedback connection in a ring
6.Johnson counter – a twisted ring counter
7.Cascaded counter
Occasionally there are advantages to using a counting sequence other than the natural
binary sequence—such as the binary coded decimal counter, a linear feedback shift
register counter, or a Gray-code counter.
1 DIGIT COUNTER

BLOCK DIAGRAM
 FUNCTION TABLE

VHDL CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity cntr_1 is
Port ( CLK : in STD_LOGIC;
Q : out INTEGER RANGE 0 to 9);
end cntr_1;
architecture Behavioral of cntr_1 is
begin
PROCESS(CLK)
VARIABLE Y:INTEGER RANGE 0 TO 10:=0;
BEGIN
IF RISING_EDGE(CLK) THEN
Y:=Y+1;
IF (Y=10) THEN Y:=0;
END IF;
END IF;
Q<=Y;
END PROCESS;
end Behavioral;
 TEST BENCH WAVE FORM

2 DIGIT COUNTER

BLOCK DIAGRAM

FUNCTION TABLE

VHDL CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CNTR_2 is
Port ( CLK : in STD_LOGIC;
Q1,Q2 : out INTEGER RANGE 0 to 9);
end CNTR_2;
architecture Behavioral of CNTR_2 is
SIGNAL Y1,Y2:INTEGER RANGE 0 TO 10:=0;
begin
PROCESS(CLK)
BEGIN
IF RISING_EDGE(CLK) THEN
Y1<=Y1+1;
IF(Y1=9) THEN Y1<=0;Y2<=Y2+1;
END IF;
IF(Y2=9) THEN Y2<=0;Y1<=0;
END IF;
END IF;
END PROCESS;
Q1<=Y1;Q2<=Y2;
end Behavioral;

TEST BENCH WAVE FORM

Conclusion

The 1, 2-DIGIT COUNTERS are designed using VHDL and verified the
same by generating TEST BENCH WAVEFORM.