Professional Documents
Culture Documents
h>
// Configuration Bit settings
// SYSCLK = 72 MHz (8MHz Crystal/ FPLLIDIV * FPLLMUL / FPLLODIV)
// PBCLK = 36 MHz
// Primary Osc w/PLL (XT+,HS+,EC+PLL)
// WDT OFF
// Other options are don't care
//
#pragma config FPLLMUL = MUL_20, FPLLIDIV = DIV_2, FPLLODIV = DIV_1, FWDTEN = OF
F
#pragma config POSCMOD = HS,FNOSC = PRIPLL,FPBDIV = DIV_2
//Let compile time pre-processor calculate the PR1 (period)
#define FOSC 80E6
#define SYS_FREQ (80000000L)
#define PB_DIV 8
#define PRESCALE 8
#define T1_TICK 0x30D4 // for 10ms
#define FALSE 0
#define TRUE 1
#define FALLING 0
#undef TIMERMODULE
int Dftmain(void);
void WaitTicks(unsigned int Ticks){
while(--Ticks);
}
extern void dft(int *inSignal, int size, unsigned char order, float *mag, float
*phase);
extern float Magnitude, Phase;
extern int Signal[2000];
main(void)
{
unsigned int temp,pbClk;
char HarmonicsOrder;
// SYSTEMConfigPerformance(FOSC);
pbClk = SYSTEMConfig(SYS_FREQ, SYS_CFG_WAIT_STATES | SYS_CFG_PCACHE);
// pbClk = SYSTEMConfig(SYS_FREQ,SYS_CFG_PCACHE);