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1. INTRODUCTION
2. SYLLABUS
INTRODUCTION
Here are some guidelines to help you perform the experiments and to submit the
reports:
5. If you have any doubt about the safety of any procedure, contact the
demonstrator before hand.
THE BREADBOARD
The breadboard consists of two terminal strips and two bus strips (often broken in
the centre). Each bus strip has two rows of contacts. Each of the two rows of
contacts are a node. That is, each contact along a row on a bus strip is connected
together (inside the breadboard). Bus strips are used primarily for power supply
connections, but are also used for any node requiring a large number of
connections. Each terminal strip has 60 rows and 5 columns of contacts on each
side of the centre gap. Each row of 5 contacts is a node.
You will build your circuits on the terminal strips by inserting the leads of circuit
components into the contact receptacles and making connections with 22-26 gauge
wire. There are wire cutter/strippers and a spool of wire in the lab. It is a good
practice to wire +5V and 0V power supply connections to separate bus strips.
The 5V supply MUST NOT BE EXCELLED since this will damage the IC’s
(Integrated Circuits) used during the experiments. Incorrect connection of power to
the ICs could result in them exploding or becoming very hot – with the possible
serious injury occuring to the people working on the experiment! Ensure that
the power supply polarity and all components and connections are correct
before switching on power.
1. Turn the power (Trainer Kit) off before you build anything!
3. Connect the +5V and ground (GND) leads of the power supply to the power
and ground bus strips on your breadboard.
4. Plug the chips you will be using into the breadboard. Point all the chips in
the same direction with 1 at the upper-left corner. (Pin 1 is often identified
by a dot or a notch next to it on the chip package).
5. Connect +5V and GND pins of each chip to the power and ground bus strips
on the breadboard.
7. Get one of your roup members to check the connections, before you turn
the power on.
8. If an error is made and is not spotted before you turn the power on, Turn the
power off immediately before you begin the rewire the circuit.
9. At the end of the laboratory session, collect your hook-up wires, chips and
all equipment and return them to the demonstrator.
10. Tidy the area that you were working in and leave it in the same condition as
it was before you started.
2. Not turning on the power supply before checking the operation of the circuit.
OBJECTIVE:
APPARATUS REQUIRED:
THEORY:
IC Family Summary :- Various families of logic ICs exist on the market however
the families. Mainly used in digital electronics lab are the TTL and the high speed
CMOS families.
MM74XXXNNRP
MM - Manufacturer
R - Revision
RP - Package Type
Manufacturer --- MM
DM - National Semiconductor
Temperature Range – 74 or 54
Fv -- Fast TTL
Vcc :- It is supply voltage which operate any instrument without damaged. Vcc
terminal is always Red.
PROCEDURE:
1. OR Gate
• Make the connection for gate 1 connect among pin 1,2 and 3.
2. AND Gate
3. NOT Gate
4. NAND Gate
5. NOR Gate
6. X-OR Gate
1 1 0
RESULT:
PRECAUTIONS:
EXPERIMENTAL QUIZ:
EXPERIMENT NO.2
OBJECTIVE:
Implementation of the given Boolean function using logic gates in both SOP and
POS forms.
APPARATUS REQUIRED:
THEORY:
The logic sum of two or more logical product terms is called a Sum of Products
Expression. It is basically an OR operation of AND operated variable such as:
In this approach we simplified the given Boolean expression using basic Boolean
laws and theorem. In this approach we assign ‘1’ value to the normal variable and
‘0’ to its complements. Also considered the values to find the expression from any
arithmetic or logic calculation.
Product of Sums (POS)
Product of Sums(POS):
In POS form we simplified the given Boolean expression using basic Boolean laws
and theorem. In this approach we assign ‘0’ values to normal variable and ‘1’ to its
complements. Also considered the values to find any arithmetic or logic
calculation.
PROCEDURE:-
5. For different combination of inputs observe the output and match them with respective
truth table and verify the equations SOP & POS.
INPUT OUTPUT
A B
0 0 0
0 1 1
1 0 1
1 1 0
INPUT OUTPUT
A B
0 0 1
0 1 0
1 0 0
1 1 1
RESULT:
Study of Boolean function and both equations SOP & POS are verified.
PRECAUTIONS:
6. After completed the experiments switch off the supply of the apparatus.
EXPERIMENTAL QUIZ:
EXPERIMENT NO. 3
STUDY OF DIGITAL COMPARATOR
MOTIVATION: In digital circuits, the logic comparison of two quantities is frequently required.
The basic function of the combinational circuit-comparator is to compare and determine the
relationship of two binary quantities. Magnitude comparators are often used as a part of address
decoding circuitry used in computer to select a specific input or output device.
THEORY: A comparator compares the magnitude of two numbers and indicates which one is
bigger of the two, or if the two numbers are equal. IC 7485 is a 4-bit comparator which indicates
whether A=B, A>B or A<B. In addition, it has three cascading inputs; A<B, A=B, A>B. These
A0 comparators to be cascaded for comparison of any number of bits greater
inputs allow several
than four. The logic symbol and pin diagram of a 4-bit comparator is shown below:-
A1
A <B
A2 Vc
c
A>B
1
15
16
A3 B3 A3
2
A=B 14
A<Bin B2
3
B0 IC 13
A=Bin A2
4
12
A>Bin A1
B1 7485 5 11
A>Bout B1
B2 6 10
A=Bout A0
B3 7 9
A<Bout
8
B0
G
N
D
B1
LOGIC SYMBOL
B2 7485 - PIN DIAGRAM
B3
The general procedure used in a comparator is to check for an inequality in a bit position, starting
with MSB. When such an inequality is found, the relationship of the two numbers is established
and any other inequalities in lower-order bit positions must be ignored. Thus to determine the
inequality of binary numbers A and B, first examine the highest order bit in number. The
following conditions are possible:-
PROCEDURE:
0 0 0 0 0 1 0
0 0 0 1 1 0 0
0 0 1 0 1 0 0
0 0 1 1 1 0 0
0 1 0 0 0 0 1
0 1 0 1 0 1 0
0 1 1 0 1 0 0
0 1 1 1 1 0 0
1 0 0 0 0 0 1
1 0 0 1 0 0 1
1 0 1 0 0 1 0
1 0 1 1 1 0 0
1 1 0 0 0 0 1
1 1 0 1 0 0 1
1 1 1 0 0 0 1
1 1 1 1 0 1 0
EXPERIMENT NO.4
OBJECTIVE:
APPARATUS REQUIRED:
THEORY:
Adder: An adder is a logic circuit which adds two or three bits at a time and give sum and carry
as the result.
Parallel Adder :
A n-bit parallel adder can be constructed using number of full adders circuit connected in parallel
the carry output of each is connected to the carry input of the next higher-order adder.
Since all the bits of the augends and addend are fed into the adder circuits simultaneously and the
additions in each position are known as parallel adder.
A3 A2 A1 A0 → Augends bits
B3 B2 B1 B0 → Addend bits
S3 S2 S1 S0 → Sum bits
Where A0, A1, A2, A3 & B0, B1, B2, B3 are BCD inputs
PROCEDURE:
1. Connect ground and Vcc to 7483 IC from trainer kit through patch cords.
2. Connect inputs A0,A1,A2,A3 and B0,B1,B2,B3 to logic input switches.
3. Connect carry in from pin no.13 to ground so that carry input(CY1) will be logic ‘0’
state.
4. Connect S0,S1,S2,S3 and carry out(CY0) from pin nos. 9,6,2,15 and 14 to the output
display.
5. Verify truth tables for different combinations of inputs.
TRUTH TABLE:
The Truth table operation of the 4-bit Parallel Adder is shown below:
INPUTS OUTPUT
A0 A1 A2 A3 B0 B1 B2 B3 CY1 S0 S1 S2 S3 CY0
0 0 0 1 0 1 0 1 1 1 1 0 0 1
1 0 0 0 1 1 1 0 0 0 0 0 0 1
RESULT: For various combinations of selected input lines, observed the LED output and
verified the truth table.
PRECAUTIONS:
POST-EXPERIMENTAL QUIZ:
1. Draw the block diagram of a full adder as a combination of two half adders.
2. Derive the Boolean expressions for the outputs S and Co of a full adder from the truth
table.
3. Make the truth table and logic diagram of a half adder.
4. Implement a half adder using only NAND gates.
5. Implement a full adder using only NOR logic.
THEORY:
Multiplexer: A multiplexer (MUX) is a device that accepts data from one of many input
sources for transmission over a common shared line. To achieve this MUX has several
data lines and a single output along with data-select inputs, which permit digital data on
any of the inputs to be switched to the output line. The logic symbol for a 1 to 4 data
selector/multiplexer is shown in Figure:
0
Data S0
MUX
Select S1 1
0
D0 Y
D1 1
2
Data D2
3
Inputs D3
The selection lines decide the number of inputs lines of particular multiplexer. If the
number of n inputs lines is equal to 2m, then m select lines are required to select one of
the n input line.
Note that if a binary zero appears on the data-select lines then data on input line D0 will
appear on the output. Thus, data output Y is equal to D0 if and only if S1=0 and S0=0.
Similarly, the data output is equal to D1, D2 and D3 for , and
respectively. Thus the total multiplexer logic expression, formed from
ORing terms is
TRUTH TABLE :
PROCEDURE:
1. What is a multiplexer?
2. What are the advantages of using multiplexers over gates in order to realize
any function?
3. Draw the circuit of full adder using multiplexer.
EQUIPMENT REQUIRED: Digital trainer kit, NAND-7410, NOT-7404 Gate IC, Connecting wires.
THEORY: A Demultiplexer performs the reverse operation; it takes a single input and
distributes it over several outputs. So ,a Demultiplexer can be thought of as a “distributor” ,since
it transmits the same data to different destinations. Thus Demultiplexer is a 1-to-N(or 2n) device.
Fig. below shows the logic circuitry for a 1-line to 4-line Demultiplexer circuit . The input data
line goes to all of the NAND gates.The two select lines S0 and S1 enable only one gate at a time,
and the data appearing on the input will pass through the selected gate the associated output line.
POST-EXPERIMENTAL QUIZ:
EXPERIMENT NO.6
MULTIPLEXER TREE
MOTIVATION: In order to meet the requirement of larger number of inputs, there should be a
provision for expansion of the multiplexers. Hence it is essential to get familiar with the design
of multiplexer trees or stacks.
EQUIPMENT REQUIRED: IC 74151A (2), IC 7432, IC 7404, digital trainer kit, multimeter, wires.
THEORY: A single 8:1 multiplexer IC can handle a maximum of 8 inputs. When the number of
inputs is more than 8, a multiplexer tree can be used, also called a multiplexer stack. Fig. 1
shows an arrangement for 16:1 multiplexer using two 8:1 MUX and one 2:1 MUX.
2
Data Inputs
3
8 : 1 M U X Y 1
4
7
L o g i c 0 S 2 S 1 S 0
B
C 2 : 1 M U X Y
D
S
8 S 2 S 1 S 0
9 L o g i c 0
A ( M S B )
1 0
Data Inputs
1 1
8 : 1 M U X Y 2
1 2
1 3
1 4
1 5
L o g i c 0
Fig.1
If one out of N inputs is to be selected, the number of select inputs required is m where 2 m = N. In
MUX1, one out of 8 inputs is to be selected and the number of select lines is 3. So is the case in
MUX2. In MUX3, one out of two inputs is to be selected and the number of select lines is 1.
MUX1 selects one out of its 8 inputs (I0 to I7) depending on the address BCD. If BCD is 000, the
output of MUX1 will be I0. Similarly MUX2 selects one out of its 8 inputs (I8 to I15) depending
on the address BCD. For example, if BCD = 000, output of M2 will be I8. MUX3 selects one out
of its two inputs depending on the address A. If A = 0, output of MUX1 will be the final output.
If A = 1, output of MUX2 will be the final output. So if ABCD = 0100, the final output will be
I4. Another method is shown in fig.2 using two 8:1 MUX and one OR gate.
2
Data Inputs
3
8 : 1 M U X Y 1
4
7
S 2 S 1 S 0
B
1
C 3 Y
2
D
8 S 2 S 1 S 0
1 0
Data Inputs
1 1
8 : 1 M U X Y 2
1 2
1 3
1 4
1 5
A ( M S B ) 1 2
7 4 0 4
Fig.2
INPUTS OUTPUT
A B C D Y
0 0 0 0 I0
0 0 0 1 I1
0 0 1 0 I2
0 0 1 1 I3
0 1 0 0 I4
0 1 0 1 I5
0 1 1 0 I6
0 1 1 1 I7
1 0 0 0 I8
1 0 0 1 I9
1 0 1 0 I10
1 0 1 1 I11
1 1 0 0 I12
1 1 0 1 I13
1 1 1 0 I14
1 1 1 1 I15
RESULT: : Study of 16:1 multiplexer using 8:1 multiplexers and verified its truth table.
POST-EXPERIMENTAL QUIZ:
1. What is a multiplexer tree?
2. The Boolean expression for a 4 variable logic function is:
Y= Σ m (0, 2, 6, 8, 9, 11, 13, 15)
Implement using a 16:1 MUX.
3. Design an XOR gate using one 2:1 MUX.
EXPERIMENT 7
IMPLEMENTATION OF DECODER & ENCODER USING LOGIC GATES
MOTIVATION: Decoder is an important part of Digital Circuit and is used not only in computer
systems but also in communication systems. Decoder is used at the receiver to convert the received
encoded data back to the original message.
OBJECTIVE : Implementation and verification of decoder and encoder using logic gates.
EQUIPMENT REQUIRED: Digital trainer kit, 7432 IC, 7404 IC, 7411 IC and Connecting
wires.
Encoder is used at the starting stage to encode the message into a unique code. Encoder
encodes different types of messages into various forms. In Digital Circuits it encodes a decimal
value into a binary word. The encoded binary word has number of bits associated with it. The
number of bits depends upon the decimal value which is being encoded. For example in case of
decimal values ranging from 0 to 7 the number of bits required to encode these values is 3.
TRUTH TABLE OF 4:2 ENCODER
INPUT OUTPUT
I3 I2 I1 I0 Y1 Y0
0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 0 1 1
PROCEDURE:
1. Connect the supply from the trainer kit through patch chords, also connect circuit as per
circuit diagram.
2. Give the input connections to I0,I1,I2 and I3.
3. Observe the output Y0, Y1 on the trainer kit through LED’s.
4. For the different combinations of inputs observe the output and match the truth table.
POST-EXPERIMENTAL QUIZ:
1) R-S flip-flop
2) J-K flip-flop
3) T flip-flop
4) D flip-flop
Using NAND and NOR gates.
EQUIPMENT REQUIRED: IC 7400 (NAND Gate), IC 7402 (NOR Gate), IC 7408 (AND Gate)
THEORY: : In case of sequential circuits the effect of all previous inputs on the outputs is
represented by a state of the circuit. Thus, the output of the circuit at any time depends upon its
current state and the input. These also determine the next state of the circuit. The relationship
that exists among the inputs, outputs, present states and next states can be specified by either the
state table or the state diagram.
State Table
The state table representation of a sequential circuit consists of three sections labeled present
state, next state and output. The present state designates the state of flip-flops before the
occurrence of a clock pulse. The next state shows the states of flip-flops after the clock pulse,
and the output section lists the value of the output variables during the present state.
FLIP-FLOP: The basic one bit digital memory circuit is known as flip-flop.It can store either 0
or 1. Flip-flops are classifieds according to the number of inputs.
R-S FLIP-FLOP : The circuit is similar to SR latch except enable signal is replaced by clock
pulse.
LOGIC DIAGRAM :
↑ 0 0 1 1 (No Change)
↑ 0 1 0 0 Reset
↑ 0 0 1 0
↑ 1 0 0 1 Set
↑ 1 0 1 1
↑ 1 1 0 X Prohibited
State
↑ 1 1 1 X
D FLIP-FLOP: The modified clocked SR flip-flop is known as D-flip-flop.From the truth table
of SR flip-flop we see that the output of the SR flip-flop is in unpredictable state when the inputs
are same. In many practical applications, these input conditions are not required. These input
conditions can be avoided by making then complement of each other.
J-K FLIP-FLOP: In a RS flip-flop the input R=S=1 leads to an indeterminate output. The RS
flip-flop circuit may be rejoined if both inputs are 1 than also the output are complement of each
other.
CLOCK J K Qn Qn+1 State
↑ 0 0 0 0 Qn
↑ 0 0 1 1 (No Change)
↑ 0 1 0 0 Reset
↑ 0 1 1 0
↑ 1 0 0 1 Set
↑ 1 0 1 1
↑ 1 1 0 X Qn (toggle)
↑ 1 1 1 X
↑ 0 1 1
↑ 1 0 1 Toggle
↑ 1 1 0
PROCEDURE:
PRECAUTIONS:
POST-EXPERIMENTAL QUIZ:
1. What is the advantage of JK flip flop over SR flip flop?
2. What is the race around condition in flip-flops?
3. Convert a JK flip flop into SR flip flop.
EXPERIMENT NO.-9
MOTIVATION: To verify Two bit asynchronous counter using J-K flip flops
THEORY: Counters are the sequential circuits used to count the clock pulses. Counters are
broadly classified as Synchronous and Asynchronous counters. Asynchronous counters are also
known as Ripple counters In case of synchronous counters a single clock is used for all the flip
flops whereas the clock used for asynchronous counter depends on the previous output of flip
flop. Due to this reason the asynchronous counters are slower than synchronous counterpart. The
stages of flip flops depend on the number of states. Ripple counters are deigned by using J-K and
T flip flops. The n bit asynchronous counter uses n flip flops and counts 2n clock pulses.
1 Q 01 Q 1
2
4 1 5 4 1 5
PRE
PRE
J Q J Q
1 1
C L K C L K C L K
1 6 1 4 1 6 1 4
K Q K Q
C LR
C LR
3
3
TIMING DIAGRAM OF 2 BIT ASYNCRONOUS COUNTER
PROCEDURE:
POST-EXPERIMENTAL QUIZ
Q1). Design a Negative edge triggered MOD-12 Asynchronous Down counter using J-K Flip
flops?