ARM (Advance RISC Machine)

RISC FEATURES:
 Reduced instructions
 Pipelining
 Load store architecture
 Registers

Reduced instructions :
 Utilizes a small, highly-optimized set of instructions.
 Pipeline organization
• 3-stage pipeline: Fetch – Decode - Execute
• Three-cycle latency, one instruction per cycle
throughput
i
n
s
t i Fetch Decode Execute
r
u
i+1 Fetch Decode Execute
c
t
i i+2 Fetch Decode Execute
o
n
t t+1 t+2 t+3 t+4 cycle
Load store architecture :
 Does not support memory to memory data processing
 Must move to registers before using them.
 Process becomes much faster due to register access to process data.

Registers :
 Large general purpose register set.
 Contains either data or address.
 ARM (Advance RISC Machine)
ARM FEATURES:

 Low power consumption

 High code density
 Hardware debugging technology
 Reduced area of die.
 Low cost memory device.
 ARM 7TDMI-S
Nomenclature:

ARM –Acron Risc Machine (Now Advanced Risc Machine)

 T – The Thumb 16 bit instruction set.
 D – On chip Debug support.
 M – Enhanced Multiplier
 I – Embedded ICE hardware to give break point and watch
point support.
 S- Synthesizable
 ARM REGISTERS
Sys/user FIQ SVC ABT IRQ UNDEF
ARM7 CPSR Format
 ARM7 Operational Modes
MODE [4:0]

User USR Normal application execution environment* 10000

Fast
FIQ Response-time critical interrupt 10001
Interrupt
Interrupt IRQ General purpose interrupt 10010

Supervisor SVC Protected mode for operating system 10011

Abort ABT Virtual memory protection & management 10111

Undefined UND Undefined Instruction (reserved for coprocessor) 11011

System SYS Privileged user mode for operating system 11111