ADL Chie Design @ practical guide for designing, synthesizing and simulating ASICs and FPGAs using VADL or Verilog Douglas J Smith Foreword by Alex Zamfirescu Doone Publications eu%eqadHDL Chip Design TL © 1996 by Doone Publications, Madison, AL, USA. First printing June 1996, ‘Second printing January 1997, minor revisions Third printing June 1997, minor revisions All rights reserved. No part of this book may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying, recording or by any information storage and retrieval system, without written permission from the publisher. ISBN 0-9651934-3-8 Library of Congress Catalog Card Number: 96-84641 ‘Cover graphic: designed using ModelView from Intergraph Software Solutions. Interior design: Doone Publications. Package STANDARD & package TEXTIO reprinted from IEEE Std 1076-1993 IEEE Standard VHDL. Language Reference Manus, Copyright © 1994 by the Institute of Electrical and Electronics Engineers, Ine. ‘Standard logic Package STD_LOGIC_1164 (IEEE 1164) reprinted from 1164-1993 IEEE Standard Mutivalue Logic System for VHDL Model Interoperabilty, Copyright © 1995 by the Institute of Fleccal and Electronics Engineers, In. ‘Standerd synthesis package NUMERIC_STD (IEEE 1076.3) reprinted from IEEE Draft Standard P1076. dated 1999, Draft Standard VHDL Synthesis Package, Copyright © 1995 by the Institute of Electrica ar Electronics Engineer, Inc. This isan unepproved draft ofa proposed IEEE Standard, subject to change. Use of information contained inthe unapproved drafts at your own risk. ‘The IEEE disclaims any responsibilty or labilty resulting from the placement and use in this product, Information ls reprinted with the permission of the IEEE. 7950 Awy 72W #6106, Madison AL, 35758. USA Doone Tek 1-800-311-3753 Publications — ¢ax: 205-837-0580 ° {nt TeVFax: +1 205-837-0580 048 0 444 eait: asmitnedoone.com web: htte/www.doone.comHDL Chip Design FOREWORD The EDA industry is an increasingly challenging area in which to be working. | work at VeriBest Incorporated and have been in the EDA industry for many years, and | am fully aware of the books that are available. This one, however, is unique as it deals extensively with both VHDL and Verilog in a comparative manner and includes many graphic examples of synthesized circuits. Doug Smith, also of VeriBest Inc., has been mastering the valuable art of Hardware Description Language (HDL) chip design for many years in both European and American ‘companies. He has cleverly captured years of design experience within the pages of this book. The abundant examples throughout show complete functional designs and not just snippets of code. Doug has spent endless months researching HDL and design topics to ensure that people in the EDA industry were in agreement with his methods. I am certainly an advocate of Doug's HDL guide for EDA veterans and first semester EE freshmen alike. His tips on planning and executing HDL designs (including the modeling caveats) are invaluable. Designers can surely benefit by applying his precepts and principles using the techniques emerged from his design experience. You will probably keep this book close to your desk for many projects to come. Often, worth is measured by magnitude, however this book not only contains ‘more examples than any other previously published work dealing with HDL driven design, but is more comprehensive than any other book of synthesis recipes whatsoever. A technical work must stand or fall by its accuracy and authority; “HDL Chip Design” stands head-and-shoulders over all other books covering this subject. The authority of this work rests on almost a lifetime of practical experience, through his career. Its accuracy has been verified through machine-processing of all the examples, and by leading industry experts. As a result “HDL Chip Design” is the very best hands-on book you can own today. It will enable you to survive in the competitive world of HDL chip design, and will be a beacon in your quest for perfect HDL design. Alex Zamfiréscu IEEE Project 1076.3 (Synthesis Packages) Chariman IEC TC93 Working Group (HDLs) Convenor