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M.SURESH,B.E.,M.E.,
Assistant Professor (gr-II)
ECE Department
Roever Engineering College
Elambalur, Perambalur.
sureshvlsi@ibibo.com
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WELCOME
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UNIT I
NMOS and PMOS transistors – Threshold voltage – Body effect – Design equations–
Second order effects – MOS models – Small signal AC characteristics – Basic CMOS technology
PART -A
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(e) Diffusion
(f) Ion Implantation
(g) Isolation technique
(h) Metallization
(i) Assembly processing & Packaging
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body effect.
The layers are Substrate, diffused Drain & Source, Insulator (SiO2) & Gate.
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PART B
1. Explain MOS Transistors in detail with neat Diagram
Basic MOSFET Structure In the introduction to a system, we got an overview of various levels of
design, viz. Architectural level design, Program level design, Functional level design and Logic
level design. However we can't understand the levels of design unless we are exposed to the basics
of operation of the devices currently used to realize the logic circuits, viz., MOSFET (Metal Oxide
Semiconductor Field Effect Transistor). So in this section, we'll study the basic structure of
MOSFET. The cross-sectional and top/bottom view of MOSFET are as in figures
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An n-type MOSFET consists of a source and a drain, two highly conducting n-type semiconductor
regions which are separated from the p-type substrate by reverse-biased p-n diodes. A metal or poly
crystalline gate covers the region between the source and drain, but is isolated from the
semiconductor by the gate oxide.
Types of MOSFET MOSFETs are divided into two types viz. p-MOSFET and n-MOSFET
depending upon its type of source and drain.
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2. Explain in detail the MOS Transistor Definitions
• n-type MOS: Majority carriers are electrons.
• p-type MOS: Majority carriers are holes.
•V tdefines the voltage at which a MOS transistor begins to conduct. For voltages
less than V t (threshold voltage), the channel is cut off.
• For n-MOS, with V gs > V tn , electric field attracts electrons creating channel.
• Channel is p-type silicon which is inverted to n-type by the electrons attracted by
the electric field.
• What are the parameters that effect the magnitude of I ds ? (Assume V gs and V ds are
fixed, e.g. 5V).
• The distance between source and drain (channel length).
• The channel width.
• The threshold voltage.
• The thickness of the gate oxide layer.
• The dielectric constant of the gate insulator.
• The carrier (electron or hole) mobility.
Most are related to the material properties. In other words, V t is largely determined
at the time of fabrication, rather than by circuit conditions, like I ds .
Threshold Voltage
• The expression for threshold voltage is given as:
Threshold Voltage
• Threshold voltage (cont.):
Basic DC Equations
Beta calculation
(e) Transistor beta calculation example: Typical values for an n-transistor in 1
micron technology:
Beta Ratios
• Region C is the most important region. A small change in the input voltage, V in ,
results in a LARGE change in the output voltage, V out .
• Boththe n and p-channel transistors have a beta. Varying their ratio will change the
characteristics of the output curve.
Beta Ratios
• Therefore, the
• Sincebeta is dependent W and L, we can adjust the ratio by changing the sizes of
the transistor channel widths, by making p-channel transistors wider than n-
channel transistors.
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UNIT II
NMOS and CMOS Inverters – Stick diagram – Inverter ratio – DC and transient characteristics
– Switching times – Super buffers – Driving large Capacitance loads – CMOS logic
structures – Transmission gates – Static CMOS design – Dynamic CMOS design
PART A
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13. What are the basic processing steps involved in BiCMOS process?
Additional masks defining P base region
N Collector area
Buried Sub collector (SCCD)
Processing steps in CMOS process
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PART B
1.Explain tristate transmission buffer
Input Output
g = 0, gb = 1 g = 1, gb = 0
g
a b 0 strong 0
a b g = 1, gb = 0 g = 1, gb = 0
a b 1 strong 1
gb
g g g
a b a b a b
gb gb gb
Pass transistors produce
degraded outputs Transmission gates pass both 0 and 1 well
EN
EN A Y
A Y
0 0 Z
0 1 Z
EN
1 0 0
1 1 1 A Y
EN
Transmission gate acts as tristate buffer Only two transistors But nonrestoring
Noise on A is passed on to Y
CMOS inverters (Complementary NOSFET Inverters) are some of the most widely used and
adaptable MOSFET inverters used in chip design. They operate with very little power loss and at
relatively high speed. Furthermore, the CMOS inverter has good logic buffer characteristics, in that,
its noise margins in both low and high states are large.
This short description of CMOS inverters gives a basic understanding of the how a CMOS inverter
works. It will cover input/output characteristics, MOSFET states at different input voltages, and
power losses due to electrical current.
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A CMOS inverter contains a PMOS and a NMOS transistor connected at the drain and gate
terminals, a supply voltage VDD at the PMOS source terminal, and a ground connected at the
NMOS source terminal, were VIN is connected to the gate terminals and VOUT is connected to the
drain terminals.(See diagram). It is important to notice that the CMOS does not contain any
resistors, which makes it more power efficient that a regular resistor-MOSFET inverter.As the
voltage at the input of the CMOS device varies between 0 and 5 volts, the state of the NMOS and
PMOS varies accordingly. If we model each transistor as a simple switch activated by VIN, the
inverter’s operations can be seen very easily:
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When VIN is low, the NMOS is "off", while the PMOS stays "on": instantly charging VOUT to
logic high. When Vin is high, the NMOS is "on and the PMOS is "on: draining the voltage at VOUT
to logic low.
This model of the CMOS inverter helps to describe the inverter conceptually, but does not
accurately describe the voltage transfer characteristics to any extent. A more full description
employs more calculations and more device states.
The multiple state transistor model is a very accurate way to model the CMOS inverter. It reduces
the states of the MOSFET into three modes of operation: Cut-Off, Linear, and Saturated: each of
which have a different dependence on Vgs and Vds. The formulas which govern the state and the
current in that given state is given by the following tabel:
NMOS Characteristics
Condition on Condition on Mode of
VGS VDS Operation
ID = kN [2(VGS - VTN ) VDS - VGS > VTN VDS < VGS -VTN Linear
VDS2 ]
ID = kN (VGS - VTN )2 VGS > VTN VDS > VGS -VTN Saturated
PMOS Characteristics
Condition on Condition on Mode of
VSG VSD Operation
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ID = kP [2(VSG + VTP ) VSD - VSG > -VTP VSD < VSG +VTP Linear
VSD2 ]
ID = kP (VSG + VTP )2 VSG > -VTP VSD > VSG +VTP Saturated
In order to simplify calculations, I have made use of an internet circuit simulation device called
"MoHAT." This tool allows the user to simulate circuits containing a few transistors in a simple and
visually appealing way. The circuits shown below show the state of each transistor (black for cut-
off, red for linear, and green for saturation) accompanied by the voltage transfer characteristic curve
(VOUT vs. VIN). The vertical line plotted on the VTC corresponds to the value of VIN on the
circuit diagram. The following series of diagrams depict the CMOS inverter in varying input
voltages ranging from low to high in ascending order.
Table of figures
figure mode of operation Logic output level
1 VIN < VIL High
2 VIN < VIL High
3 VIL < VIN <VIH <undetermined>
4 VIN > VIH Low
5 VIN > VIH Low
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As I mentioned before, the CMOS inverter shows very low power dissipation when in
proper operation. In fact, the power dissipation is virtually zero when operating close to VOH and
VOL. The following graph shows the drain to source current (effectively the overall current of the
inverter) of the NMOS as a function of input voltage. dissipation).
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The CMOS inverter is an important circuit device that provides quick transition time, high buffer
margins, and low power dissipation: all three of these are desired qualities in inverters for most
circuit design. It is quite clear why this inverter has become as popular as it is.
• Therefore, the shape of the transfer characteristic and the V OL of the inverter is
Pseudo-nMOS was popular for high-speed circuits, static ROMs and PLAs.
5. Explain Pseudo-nMOS
• Example: Calculation of noise margins:
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• The
transfer curve for the pseudo-nMOS inverter can be used to calculate the noise
margins of identical pseudo-nMOS inverters
10. Two parameters, Low noise margin (NM L ) and High noise margin (NM H
).
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Noise Margins
• Ideal characteristic: V IH = V IL = (V OH +V OL )/2.
• This implies that the transfer characteristic should switch abruptly (high gain in the
transition region).
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(ii)FALL TIME
The time needed for Vout to fall from 0.9 VDD to 0.1 VDD is known as Fall time.
The time needed for Vout to rise from 0.1 VDD to 0.9 VDD is known as Rise time.
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UNIT III
3. What are the dependent factors that the switching speed of MOS system depends on?
Parasitic capacitance
Interconnect capacitance of wires
Resistance of transistors and wires
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tr = 2CL/βpVDD(1-n)[(n-0.1)/(1-n)+1/2ln(19-20n)]
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PART B
1.Explain in detail about scaling
Gate area Ag = L W
' '
Ag scaled = L ×W
L W
×
α α
A
2g
α
C g =C o × Ag
C g scaled =C o scaled ×A g scaled
Gate capacitance
A β
βC o× 2g =C g 2
α α
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L 1 L 1
. = .
W σt W Q on μ
L /α 1
R on scaled = .
W / α Q on μ
R on
Transistor delay
T d =R on×C g
β
T d scaled =Ron C g
α2
β
Td
α2
Transistor current
C o μW 2
I ds =
2L V gs −V t
2
βC o μ W /α V gs V t
I ds scaled =
2 L/α β
−
β
I ds
β
Switching energy
1
E= C g V 2DD
2
1 β V 2DD
E scaled = C
2 α2 g β2
1
2 E
α β
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2
V
P s = DD
R
static
V 2DD 1 P s
P s scaled = 2 . = 2
β R β
1
P sw =f × C g V 2DD
2
α2 1 β V 2DD
dynamic P sw scaled = f × 2 Cg 2
β 2α β
1
2 P sw
β
Gate Area
Gate Capacitance per unit area
Gate Capacitance
Charge in Channel
Channel Resistance
Transistor Delay
Maximum Operating Frequency
Transistor Current
Switching Energy
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=> R = ρL/t*W
Let L = W (square slab)
=> RAB = ρ/t = Rs ohm / square
Layer Rs (Ohm / Sq
Aluminium 0.03
N Diffusion 10 – 50
Silicide 2–4
Polysilicon 15 - 100
N-transistor Channel 104
P-transistor Channel 2.5 x 104
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•
• The reduction of the threshold voltage with a reduction in the channel length can be
explained by the charge sharing model.
Fig The depletion charge profiles for (a) a long channel device, and (b) a short channel device.
• For a long channel device, the depletion layer thickness at the source end of the channel and
at the drain end of the channel are much less than the channel length L, and, thus, the
depletion charge enclosed by these sections are much smaller than the total depletion charge
under the gate.
• However, for a short channel device, the widths of these depletion regions are a non-
negligible fraction of the total depletion charge under the gate.
• Note: essentially, the depletion regions near the source and the drain are contributed by the
source-substrate and the drain-substrate bias, and gate has no role to play.
• Under an applied drain-source bias, the depletion region thickness near the drain will
obviously be larger than that at the source side.
• The net effect is that the gate now has to compensate for a lower depletion charge density
than that for a long channel device, which qualitatively explains the reduction of the
threshold voltage with a reduction in the channel length.
• The exact analysis of the charge sharing effects requires a two-dimensional analysis,
however, to the first order, it is assumed that the effect of the depletion width at the drain
side of the channel is to reduce the effective channel length in the saturation region from L
to where
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UNIT IV
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Fault grading consists of two steps. First, the node to be faulted is selected. A simulation is
run with no faults inserted, and the results of this simulation are saved. Each node or line to be
faulted is set to 0 and then 1 and the test vector set is applied. If and when a discrepancy is detected
between the faulted circuit response and the good circuit response, the fault is said to be detected
and the Simulation is stopped.
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TMS signals. It provides signals that control the test data registers, and the instruction register.
These include serial-shift clocks and update clocks.
24.Define Decoder?
A decoder is a multiple - input multiple output logic circuit that converts coded inputs into
coded outputs where the input and output codes are different.
27.Define multiplexer?
Multiplexer is a digital switch. If allows digital information from several sources to be
routed onto a single output line.
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PART -B
1.Explain the algorithms of automatic test pattern generation.
The objective is to automatically generate a test for faults in the circuit-under-test
Major classes of methods:
Pseudorandom
Ad-Hoc
Algorithmic
D-algorithm
PODEM
FAN and related algorithms
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Adding additional functional tests to exercise areas of design with undetected faults
Re-fault simulating and repeating until desired fault coverage is achieved.
No special test generation system is required, only fault simulator.Utilizes existing vectors
and designer expertise.Achieving high fault coverage may be difficult and time consuming -
especially for synthesized designs
D Algorithm
First algorithm proved “complete” - developed by Roth at IBM in 1966
Complete - can be proven that the algorithm will generate a test for a fault if it
exists.Introduced D notation D - “1” in the good circuit “0” in the faulty, D’ - “0” in
the good circuit “1” in the faulty (Dbar)
PDCF - Primitive D cube of failure - a set of inputs to a module that will sensitize a specific
fault within the module. PDC - Propagation D cube - a set of inputs to a module that will
propagate a D from the inputs to the outputs.
PODEM
Path Oriented DEcision Making - developed in 1981 by Goel to address the problem D
algorithm had with XOR gates. D algorithm is exponentially complex to the number of
internal circuit nodes - XOR gates make the complexity of the D algorithm approach this
limit PODEM expresses the search space in terms of assignments to the primary inputs only.
PODEM is also a branch-and-bound algorithm which is exponentially complex to the
number for circuit inputs - usually a much smaller number than circuit nodes.
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This figure show the basic structure of a boundary-scan cell. One of these cells is
added to each I/O port on the chip. One reason that boundary scan may be popular is that the
relative cost of adding the scan cells to the I/O pads is low compared to the cost of adding
full scan. For example, only a mux is added to the normal I/O path, which does add some
delay, but it’s in the context of the already large I/O pad delay. Second, there is some
additional logic that has to be added to the Pad buffer, but most of the pad area is dominated
by the size of the physical pad, and the additional logic doesn’t increase it by much.
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This figure shows the architecture of a boundary-scan-complaint chip. Note that the application
logic of the chip itself may include DFT or BIST techniques (scan, BILBO, etc.) and this test logic
is controlled by the boundary-scan TAP controller.
Boundary-Scan Advantages/Disadvantages
Boundary-scan has a lower overhead than scan design because, in terms of speed, the increase in
normal on/off chip time is much less a percentage increase than is true for scan design. Also, in
terms of area, the additional logic is small compared to an I/O pad.
Another major advantage to using boundary scan is that it can also be used to scan in/out functional
vectors and responses. This can be useful in a number of design verification tasks.
Boundary-scan does have non-zero area, speed, and testing overheads, and that needs to be
considered when adding it.
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A form of on-line BIST in which testing occurs simultaneously with normal function
Nonconcurrent On-Line BIST
A form of on-line BIST where testing is carried out while the system is in an idle state
Off-Line BIST
BIST in which testing occurs when the system is not in its normal operation
Functional Off-Line BIST
Off-line BIST that uses tests based on the functional description of the circuit-under-test
Structural Off-Line BIST
Off-line BIST that uses tests based on the structure of the circuit-under-test
Pseudo Random Pattern Generator (PRPG)
a multi-output device that generates pseudorandom output patterns - usually implemented with a
Linear Feedback Shift Register (LFSR)
Multiple-Input Signature Register (MISR)
a multi-input device that compresses a series of input patterns into a (pseudo) unique signature
Test-Pattern Generation for BIST
There are several ways that test patterns for BIST can be generated. Remember that the device itself
is generating the test patterns, so they have to be generated or stored (rarely used) in hardware on
chip.
Exhaustive Testing –
apply all 2n input patterns to a combinational circuit with n inputs,Binary counter can be
used as a TPG
Pseudorandom testing –
It generate patterns that appear to be random but are in fact deterministic (repeatable)
LFSR used as a TPG
Weighted Pseudorandom Test Generation
LFSR used as TPG with combinational circuit to modify the probability of a "1" or "0" so they
are nonuniform
Adaptive Pseudorandom Test Generation –
weighted random testing with the weights being modified using output of fault simulation -
more than one weight used
Pseudoexhaustive Testing - segment device and test each portion exhaustively
Pseudorandom Test Generation LFSRs
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Pseudorandom (likelihood of "1" or "0" is 50%, but patterns are deterministic/repeatable) patterns
may be generated by a linear feedback shift register (LFSR).
LFSRs are constructed from:
- unit delays or D flip-flops
- modulo-2 adders
- modulo-2 scalar multipliers
The devices are linear because they preserve the principle of superposition; i.e., its response to a
linear combination of inputs is the linear combination of the responses of the circuit to the
individual stimuli.
Signature Analysis
Once the test patterns are automatically applied, the responses must be gathered. The only way to
do this practically for true BIST is to compress the responses into a single (we hope) unique value.
Signature analysis attempts to perform this function.
Signature analysis uses an LFSR to compress the input stream to a single value. The basic
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principal is that the input polynomial (stream) gets divided by the characteristic polynomial of the
LFSR, resulting in a quotient (output stream) and a remainder. Because this is basically a “lossy”
compression scheme, there is more than one input stream that can generate a specific signature. The
occurrence of an erroneous input stream that generates a correct signature is called aliasing. The
probability of aliasing as show here is very small, but it is also circuit dependent; i.e., the types of
errors generated by faults in the circuit may make aliasing more probable.
4. Explain the design of CMOS Adder Circuit.
For 1-Bit Full Adder logic function sum and carry equations are given by
Sum = A XOR B XOR C = ABC + AB’C’ + A’BC’ + A’B’C
Carry_out = AB + AC + BC
Sum function can be written as Sum = ABC + (A + B + C) · Carry_out’.
The alternate representation of the sum function allows the 1-bit full adder to
beimplemented in complex CMOS with 28 transistors, is shown in figure.
Layout
Carry-Ripple Adder
Simplest design: cascade full adders
o Critical path goes from Cin to Cout
o Design full adder to have fast carry delay
A4 B4 A3 B3 A2 B2 A1 B1
Cout Cin
C3 C2 C1
S4 S3 S2 S1
Generate / Propagate
Equations often factored into G and P
Generate and propagate for groups spanning i:j
Gi:j =
Gi:k+Pi:k Gk 1g
:j −
Pi:j =
Pi:k Pkg1:j −
Base case
Gii: G
=
i Ai Bi g
Pii: P
i A
i =
Bi
Sum: Si = Pi G
− 1:0i
PG Logic
A4 B4 A3 B3 A2 B2 A1 B1 Cin
1: Bitwise PG logic
G4 P4 G3 P3 G2 P2 G1 P1 G0 P0
2: Group PG logic
C3 C2 C1 C0
3: Sum logic
C4
Cout S4 S3 S2 S1
G4 P4 G3 P3 G2 P2 G1 P1 G0 P0
Gi:0G=+
iPi Gi 1
:0 g −
C3 C2 C1 C0
S4 S3 S2 S1
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Carry-Skip Adder
Carry-ripple is slow through all N stages
Carry-skip allows carry to skip over groups of n bits
o Decision based on n-bit propagate signal
Carry-Lookahead Adder
Carry-lookahead adder computes Gi:0 for many bits in parallel.
Uses higher-valency cells with more than two inputs.
+ + + + Cin
Carry-Select Adder
Trick for critical paths dependent on late input X
4. Precompute two possible outputs for X = 0, 1
5. Select proper output when X arrives
Carry-select adder precomputes n-bit sums
6. For both possible carries into n-bit group
0 0 0
+ + +
Cout C12 C8 C4
1 1 1 Cin
+ + + +
1
1
0
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D0 0
Y
D1 1
• Gate-Level
Y = SD1 + Mux Design
SD0 (too many transistors)
20 transistors are needed 20
D1
S Y
D0
D1 4 2
S 4 2 Y
D0 4 2
2
D0 S D0 D1 S
S D1 S S
Y Y D0 0
S S S S Y
D1 1
4:1 Multiplexer
4:1 mux chooses one of 4 inputs using two selects
(1) Two levels of 2:1 muxes
S1S0 S1S0 S1S0 S1S0
D0 0
D1
D1 1
0
Y Y
1
D2 0 D2
D3 1
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ocations .
Design Style Specific Issues
• Full Custom
– All the steps required for general cells.
• Standard Cell
– Dimensions of all cells are fixed.
– Floorplanning problem is simply the placement problem.
– For large netlists, two steps:
• First do global partitioning.
• Placement for individual regions next.
• Gate Arra
– Floorplanning problem same as placement problem
Estimating Cost of a Floorplan
• The number of feasible solutions of a floorplanning problem is very large.
– Finding the best solution is NP-hard.
• Several criteria used to measure the quality of
floorplans:
a) Minimize area
b) Minimize total length of wire
c) Maximize routability
d) Minimize delays
e) Any combination of above
How to determine wire length?
– A coarse measure is used.
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– Based on a model where all I/O pins of the blocks are merged and assumed to reside at its
center.
– Overall wiring length L = Σi,j (cij * dij)
where cij : connectivity between blocks i and j
dij : Manhattan distances between the centres of rectangles of blocks i and j
Typical cost function used:
Cost = w1 * A + w2 * L
where w1 and w2 are user-specified parameters
Slicing Structure
– A rectangular dissection that can be obtained by repeatedly splitting rectangles by
horizontal and vertical lines into smaller rectangles.
• Slicing Tree
– A binary tree that models a slicing structure.
– Each node represents a vertical cut line (V), or a horizontal cut line (H).
• A third kind of node called Wheel (W) appears for nonsliceable floorplans
– Each leaf is a basic block (rectangle).
Floorplanning Algorithms
– Integer programming based
– Rectangular dual graph based
– Hierarchical tree based
– Simulated annealing based
Integer Linear Programming Formulation
• The problem is modeled as a set of linear equationsusing 0/1 integer variables.
• Given:
– Set of n blocks S = {B1, B2, …,Bn} which are rigid and have fixed orientation.
– 4-tuple associated with each block (xi, yi, wi, hi)
Rectangular Dual-Graph Approach
• Basic Concept:
– Output of partitioning algorithms represented by a graph.
– Floorplans can be obtained by converting the graph into its rectangular dual.
• The rectangular dual of a graph satisfies the following properties:
– Each vertex corresponds to a distinct rectangle.
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M x N-bit multiplication
o Produce N M-bit partial products
o Sum these to produce M+N-bit product
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Product: �M −1
� N− 1
j � i�
−N 1−M 1
P =�� y j 2� �
� x i 2=�� � x iy j 2i j +
�j =0 ��=
i 0 �=i 0= j 0
y5 y4 y3 y2 y1 y0 multiplicand
x5 x4 x3 x2 x1 x0 multiplier
x0y5 x0y4 x0y3 x0y2 x0y1 x0y0
x1y5 x1y4 x1y3 x1y2 x1y1 x1y0
x2y5 x2y4 x2y3 x2y2 x2y1 x2y0 partial
x3y5 x3y4 x3y3 x3y2 x3y1 x3y0 products
x4y5 x4y4 x4y3 x4y2 x4y1 x4y0
x5y5 x5y4 x5y3 x5y2 x5y1 x5y0
p11 p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 p0 product
Dot Diagram
x0
partial products
multiplier x
x15
Array Multiplier
y3 y2 y1 y0
x0
x1
CSA
Array
x2
x3
CPA
p7 p6 p5 p4 p3 p2 p1 p0
A B
Sin A Cin critical path A B
A B
B Sin
= Cout Cin = Cout Cin
Cout Cin
Sout
Cout Sout Sout
Sout
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Booth Encoding
Instead of 3Y, try –Y, then increment next partial product to add 4Y
Similarly, for 2Y, try –2Y + 4Y in next partial product
Booth Hardware
Booth encoder generates control lines for each PP
o Booth selectors choose PP bits
yj yj1
Xi x2i1
x2i
2X i
x2i+1
Mi
Booth
Encoder
Booth
Selector
PP ij
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Dynamic:
Charge/discharge capacitors when switching between 0 and 1
Short-circuit currents on transitions
Static (Leakage)
o From sub-threshold currents
Static (2~5%)
P static =N⋅V⋅k design⋅I leak
1
P dync = C⋅V 2⋅A⋅ f
2
V ' =0 . 7V
'
C ' =0 .7×2C ⇒ P dync=1 . 4P dync
f ' =2f
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UNIT V
Introduction to FPGA – Xilinx FPGA – Xilinx 2000 – Xilinx 3000 – Overview of Digital
Design with Verilog HDL – Hierarchical modeling concepts – Modules and Port definitions –
Gate level modeling – Data flow modeling – Behavioral modeling
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reference in the design. Identifiers consists of upper and lower case letters, digits
0 through 9, the underscore character(_) and the dollar sign($). It must be a single
group of characters. Examples: A014, a ,b, in_o, s_out
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PART B
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Gate-Level Modelling
Primitive logic gates are part of the Verilog language. Two properties can be specified,
drive_strength and delay. Drive_strength specifies the strength at the gate outputs. The strongest
output is a direct connection to a source, next comes a connection through a conducting transistor,
then a resistive pull-up/down. The drive strength is usually not specified, in which case the
strengths defaults to strong1 and strong0. Refer to Cadence Verilog-XL Reference Man-ual for
more details on strengths.
Delays: If no delay is specified, then the gate has no propagation delay; if two delays are specified,
the first represent the rise delay, the second the fall delay; if only one delay is specified, then rise
and fall are equal. Delays are ignored in synthesis. This method of specifying delay is a special case
of “Parameterized Modules” on page 11. The parame-ters for the primitive gates have been
predefined as delays.
Basic Gates
These implement the basic logic gates. They have one output and one or more inputs. In the gate
instantiation syntax shown below, GATE stands for one of the keywords and, nand, or, nor, xor,
xnor.
Syntax Example
GATE (drive_strength) # (delays) and c1 (o, a, b, c, d); // 4-
instance_name1(output, input_1, input AND called c1
input_2,..., input_N), and c2 (p, f g); // a 2-
instance_name2(outp,in1, in2,..., inN); input AND called c2.
Delays is or #(4, 3) ig (o, a, b); /* or gate
#(rise, fall) or called ig
# rise_and_fall or (instance name);
#(rise_and_fall) rise time = 4, fall
time = 3 */
xor #(5) xor1 (a, b, c); // a = b
XOR c after 5 time units
xor (pull1, strong0) #5
(a,b,c); /* Identical gate
with pull-up strength pull1
and pull-down strength
strong0. */
Syntax
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Example
Verilog supports structural data types called nets which model hardware connections between
circuit components. The two most common structural data types are wire and reg. The wire nets act
like real wires in circuits. The reg type hold their values until another value is put on them, just like
a register hardware component. The declarations for wire and reg signals are inside a module but
outside any initial or always block. The initial state of a reg is x unknown, and the initial state of a
wire is z.
Ports:Modules communicate with each other through ports, the signals listed in the parameter list at
the top of the module. Ports can be of type in, out, and inout.
Here are 3 simplistic rules for matching the structural data type to the type of port:
13. Use reg as the outputs of Behavioral blocks. If you us a wire then the value will never be
seen by other blocks.
14. Use wire for all inputs, inouts, and most outputs of Structural elements.
15. If you need a special strength type operation use special net keyword wand, wor, tir, triand,
trior, trireg.
The types in integer and real are convenient data types to use for counting in behavioral code
blocks. These data types act like their counter parts in other programming languages. If you
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eventually plan to synthesize your behavioral code then you would probably want to avoid using
these data types because they often synthesize large circuits.
The data type time can hold a special simulator value called simulation time which is extracted
from the system function $time. The time information can be used to help you debug your
simulations.
integer i, y;
real a;
real b = 3.5;
real c = 4;
time simulationTime;
initial
begin
y = 4;
i = 5 + y;
c = c + 3.5;
a = 5.3e4;
simulationTime = $time;
$display("integer y = %d, i = %f \n", y, i);
$display("reals c = %f, a = %e, b= %g \n", c, a, b);
$display("time simulationTime = %t \n", simulationTime);
end
Number Syntax
'
The size is always specified as a decimal number. If no is specified then the default size is at least
32bits and may be larger depending on the machine. Valid base formats are 'b , 'B , 'h , 'H 'd , 'D ,
'o , 'O for binary, hexadecimal, decimal, and octal. Numbers consist of strings of digits (0-9, A-F, a-
f, x, X, z, Z). The X's mean unknown, and the Z's mean high impedance If no base format is
specified the number is assumed to be a decimal number. Some examples of valid numbers are:
There are 2 kinds of assignment statements: blocking using the = operator, and non-blocking using
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the <= operator. Blocking assignments act like sequential code statements and execute when they
are called. Non-blocking schedule events to happen at some time in the future. This can be
confusing because lines that appear after a non-blocking statement execute at the same time as the
non-blocking statement. Here are some examples:
#5 x = 1'b0; // blocks for 5 time units, applies value to x, then next line
goes
y = 1'b1; // blocks, sets y to 1 now, then next statement goes
y <= #3 1'b0; // evaluates now, schedules apply y=0 in 3 time units, and next
line goes
#5 x <= y; // waits for 5 time units, evaluates,
// schedules apply at end of current time, and next line goes
Verilog supports three similar data structures called Arrays, Vectors, and Memories. Arrays are used
to hold several objects of the same type. Vectors are used to represent multi-bit busses. And
Memories are arrays of vectors which are accessed similar to hardware memories. Read the
following examples to determine how to reference and use the different data structures.
//*** Arrays for integer, time, reg, and vectors of reg ***************
integer i[3:0]; //integer array with a length of 4
time x[20:1]; //time array with length of 19
reg r[7:0]; //scalar reg array with length of 8
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Here is a small selection of the Verilog Operators which look similar but have different effects.
Logical Operators evaluate to TRUE or FALSE. Bitwise operators act on each bit of the operands to
produce a multi-bit result. Unary Reduction operators perform the operation on all bits of the
operand to produce a single bit result.
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THANK YOU
HERE BY
SURESH
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