1
Limits of CMOS Technology Scaling and
Technologies Beyond-CMOS
Daniel Rairigh, Student Member, IEEE
Μ
Abstract—The scaling of CMOS transistors has driven
the tremendous growth of the semiconductor industry for
the last four decades. However, most experts are saying
CMOS is reaching its limits. This paper discusses the
technologies that may postponing the scaling limit and the
technologies that may replace CMOS when the limit is
reached.
Index Terms—CMOS scaling, Double Gate, Quantum
Computing, Carbon Nanotube, Quantum Cellular Automata.
I.INTRODUCTION
I n 1965, Gordon Moore wrote a paper entitled
“Cramming more Components onto Integrated
Circuits” where he first proposed that transistor density
on chips would grow exponentially [1]. This became
known as Moore's law. Remarkably the industry has
kept pace with this exponential growth for that last four
decades. There is however a problem with exponential
growth: it rapidly approaches infinity, while physical
systems generally cannot run to infinity. As Moore
himself pointed out in 2003, “No exponential change of
a physical quantity can, however, continue forever.” [2].
This raises the question, what needs to be done to
maintain this growth in the near term and what will take
its place in the long term?
This paper examines briefly what issues are
preventing CMOS scaling from approaching infinity.
Then we examine some material and structural design
changes that are being proposed to enable the transistors
to continue to scale a little more. Finally we take a brief
look at what technologies may one day supersede the
MOSFET transistor and what obstacles they currently
face.
II.LIMITING FACTORS IN CMOS
Since the 1970's people have been predicting the end
of CMOS [3]. Despite these predictions, the monetary
benefit of growth has driven massive research, which
has overcome all previous barriers [2]. However, many
experts are now claiming that the industry is reaching
limits that no amount of research can push past.
There are three key factors limiting continued scaling
Μ
Manuscript received November 21, 2005.
Daniel Rairigh is with Michigan State University, Lansing, MI 48824
USA (phone: 517-490-9266; e-mail: rairighd@egr.msu.edu).
in CMOS:
1. Minimum dimensions that can be fabricated
2. Diminishing returns in switching performance
3. Off-state leakage
So far the primary limitations to chip scaling have
been lithographic issues. Simply, how small can a
transistor can be fabricated? Continuing advances have
pushed current lithographic technologies down to using
ultraviolet wavelengths (193 nm). And research is being
done to reduce the minimum wavelength into the
extreme ultraviolet spectrum (13 nm wavelengths) [4].
However, transistor dimensions are approaching a hard
limit that cannot be overcome. That limit is the size of
the atom and molecule. Clearly devices cannot be
fabricated smaller than the dimension of a single
molecule and some dimensions will need to be more
than a molecule wide. It should also be pointed out here
that lithographic equipment costs have also grown
exponentially [2], and this is beginning to limit the
profitability of increased scaling. Thus there is a rapidly
approaching limit to how small transistors can actually
be fabricated.
MOS transistors may, however, never reach single
molecule gate length. As mentioned earlier, physical
systems can not run to infinity, generally this means that
as a model approaches infinity some non-ideal effect
will begin to dominate and break the model. This is
certainly the case for MOS transistors. These effects,
such as electron and hole mobility, mean that the
performance gains from each successive generations is
less than the gain from the last generation. So that
scaling all the way down to the molecular level in
traditional silicon may not produce devices that are
significantly better than their larger ancestors.
The final, and most significant factor limiting MOS
scaling is really a subset of the diminishing returns
discussed above. The dominant non-ideal effect that
must be addressed for current scaling to continue, is off-
state power consumption. Within digital logic, the
sources that contribute to off-state power consumption
are: junction leakage, gate induced drain leakage, sub-
threshold channel current, and gate tunnel currents.
These become more and more significant as the
dimensions decrease. In fact, leakage currents grow

exponentially as gate length decreases [4].
Extrapolating current power trends, the off-state power
consumption would be about equal active power around
the 10nm node. However, in practical terms, off-state
power needs to be less than 10% to 20% of total power
consumed, and current 90nm technology is already
approaching this limit [3].
Most predictions are, if trends continue, CMOS
scaling can continue for only a decade or two [4],[2],[5].
Many experts are claiming that the practical limit will be
near the 22 nm to 30 nm node [6], [7], [3]. Even before
that limit is reached though, there are some serious
obstacles to be overcome. So, let us move on to the
solutions researchers are proposing.
III.IMPROVEMENTS TO CMOS
A. New Materials
The materials used in CMOS devices have been slow
to change, but increasingly it has become obvious that
problems encountered in the chips can be directly
addressed by adjusting the materials that influence these
properties. These new materials and material
modifications include, low-resistivity conductors,
strained Si and low-K dielectrics. The use of tungsten
and copper to reduce resistance has been in long use
now and will not be addressed here. However, the other
two are more recent and prove to be of more interest.
Strained Si is the process of introducing physical
strain on the silicon lattice to help improve electron and
hole mobility. This strain can be introduced in a number
of different manners, but in general, some layer is added
to the silicon. This layer may expand or in some other
way stretch the silicon. For instance, a layer may be
added on top of the silicon which has a larger lattice
structure than silicon (See Fig. 1) and force the silicon to
stretch to make the bonds. This allows the holes and
electrons to flow more freely thus reducing device
resistance and other properties effected by electron/hole
mobility. While this technique is implemented, it has
the disadvantage that from a fabrication stand point, it is
not compatible with many of the other new technologies.
2
Figure 1: Straining Silicon using a larger lattice.
High-K dielectrics are designed to address one
particular aspect of off-state power consumptions: gate
tunneling currents. It is likely that the gate dielectric
thickness will be the first dimension to reach atomic
dimensions. This is because the dielectric thickness
indirectly controls the gate length. In general, the
effective gate length needs to be 40 times the dielectric
thickness to properly control short channel effects (SCE)
[3]. Thus, the scaling that reduces gate length must also
reduce the dielectric thickness. However, as the
dielectric thickness decreases, electron tunneling
through the dielectric becomes a significant issue. The
proposed solution to this problem is to find a material
that has a higher K value than the silica (SiO2) currently
used as the gate dielectric. This would allow the actual
thickness of the gate dielectric to be increased while still
maintaining the same electric field in the channel.
While this sounds good in theory, implementation has
proved to be challenging. To do this, a material must be
found that meets many criteria. The material must be
compatible with the surrounding silicon and the
fabrication processes used. Also, it must have a
breakdown time at least as long as silica. While there
are many other requirements, suffice it to say that many
materials have been proposed, but no good substitute has
yet been found.
B. New Structures
There have also been proposals to try and change the
structure of the transistor itself. Here we will discuss the
two most prominent structural changes: Silicon on
Insulator (SOI) and Double Gate CMOS (DGCMOS)
The basic concept of Silicon on Insulator is fairly
simple. Rather than fabricating a transistor whose body
is connected to the substrate (Fig. 2.a), which is the
normal method, an insulating oxide is first deposited on

the substrate and then the transistor is fabricated on top
of that (Fig. 2.b). By doing this the body is then
electrically isolated from its surroundings. This means
that the bulk to source voltage Vbs is now floating.
This design provides a number of performance
benefits. First of all Vbs is now always greater than or
equal to zero. This lowers the threshold voltage, Vt,
providing a performance increase. Also, there is now no
junction area capacitance. Finally, stacked circuits do
not suffer form the reverse body effect. The new
structure also lends itself to some new uses, such as
using the insulating layer for a high resistance element.
[3]
Figure 2: Bulk and SOI transistor structures.
There are of course some disadvantages to the new
structural as well. While the floating Vbs provides many
benefits, its variability can also be problematic. The
value of Vbs is a function of the present current level in
the gate as well as the history of previous states which
the gate has been in. This means that the threshold of a
gate may vary significantly throughout its operation.
Also, if Vbs climbs too high it can cause pass-gate
leakage. There have been techniques developed to
address some of these issues.
To test this technology, IBM redesigned some of their
PowerPC line chips using SOI. They were able to
demonstrate a 22-33% performance increase over the
bulk CMOS version of these chips [3]. They also found
that, while implementing SOI requires an understanding
of the unique problems that this technology has, it was
possible to redesign existing technologies in a
3
reasonable amount of time. [3]
The second structure is more experimental, but
promises great benefits in the future. That structure is
the Double-Gate CMOS (DGCMOS). The basic idea of
this structure is to add an extra gate (or more) to increase
coupling between the gate and the channel. Some have
called this the “ideal structure for scalability” [4]. Most
agree that it is the design of the future, but there are
some difficulties to overcome before then.
The difficulties arise in how to implement the
DGCMOS structure. Using traditional fabrication
processes a second gate could be added below the body.
However, the alignment issues of such a gate are
troublesome. The proposed solution is known as the
FinFET. This structure builds the drain, source, and gate
up vertically. (See Fig. 3). This may solve the
alignment issue, but there is one other challenge to
overcome. In order to control SCE, the body thickness
must be ¼ of the gate length [4]. This is a daunting
challenge because the gate length is usually the smallest
dimension that can be fabricated. There are some
technologies that may address this, but more work needs
to be done in this area.
Figure 3: FinFET structure
IV.ALTERNATIVES TO CMOS
So far scaling has had such tremendous benefits that
alternative technologies have not been able to compete
with the power of mainstream CMOS devices. Also, so
much research and knowledge has been placed into
CMOS technology, that it is hard to introduce drastically
different technologies. However, no matter how much
research is being done, scaling CMOS is unquestionably
approaching its limits. Even if off-state power
consumption and the other issues can be over come,
scaling still can't progress past the size of the molecule.
This leads to the question of what technology might
surpass CMOS. There are a handful of technologies that
show promise for the future, we will address the three
most prominent ones.

The first technology to consider is Quantum
Computing. The concept was first proposed by Peter
Shor in 1994. Shor proposed a method of factoring
numbers (a computationally difficult task) using
quantum mechanical principles. This concept is built
around the theory that quantum particles can exist in
many 'universes' at once and only collapse down to one
'universe' when observed. Shor theorized that we could
leverage the 'multiple universe' theory to achieve
massive parallelism in computation [8],[9]. Shor's
quantum computer could be incredibly fast in certain
applications.
To illustrate, the possible performance gains, assume
we wanted to factor a 2048 bit number. It is estimated
that a traditional computer system would take longer
then the age of the universe so complete this task. The
same estimate stated that a quantum computer running at
100MHz could complete the task in one hour! [8] The
speed increase here is incredible, but there are many
challenges that must be overcome before this can
become possible.
As is the case with most of the new technologies
implementation is the challenge. The 100Mhz quantum
computer mentioned in the above example, would have
to be made of 4x106 qubits1. This represents a very
complex system, especially since current experimental
systems have only been made with, at most, a couple
qubits. Adding to the challenge, these systems need to
be isolated from any outside interference (thermal,
electrical, etc.). Finally, there is a question of how best
to build theses systems. Proposals have ranged from
using ions, and photons to solid state systems and supper
conductors. Currently no one knows which
implementation, if any, will work [10].
Figure 4: Basic carbon nanotube transistor
1
A qubit is the basic unit of a quantum computer.
4
The second, and possibly most popular, new idea is
using carbon nanotubes as transistors (An example
configuration is shown in Fig. 4). This concept it very
appealing because it is still a transistor and could make
use of all the architectural knowledge developed for
CMOS. As mentioned earlier, incremental changes
always seem to be the easiest to introduce. It has also
been suggested that some sort of chemical self assembly
process could use to manufacture carbon nanotube
systems [5].
Carbon nanotubes, do however, have a long way to go
before they can start replacing the MOS transistor. First
of all, current nanotube transistors have very poor
performance characteristics. Many of the problems they
are exhibiting are similar the the challenges CMOS is
currently facing, such as high off-state leakage and
source-to-drain tunneling [3]. Also, despite the hopes
for chemical self assembly some day, it is currently still
difficult to produce nanotube transistors.
The final new technology we would like to consider is
Quantum Cellular Automata (QCA). This technology is
built up in cells. Each cell has 2 electrons trapped on it
and 4 or 5 islands. The electrons can be on any island
and can tunnel between the islands. However, due to
Coulomb repulsion, they will always settle to one of two
stable states (See Fig 5.a). This is an inherently binary
system and these states can be labeled “1” and “0”.
When cells are placed next to each other, electrons can
not travel between them, but the Coulomb interaction
between cells will force the neighbor to settle to the
same state as the first cell. In this way a “binary wire”
can be assembled (Fig. 5.b) where all cells in the chain
have the same value. The fundamental logic gate is the
Majority Gate (Fig. 5.c). A majority gate takes three
inputs, it's output is equal to whichever two inputs agree.
Figure 5: Basic QCA structures
 5

This technology has many advantages. It is “edge
driven,” meaning an input is brought to an edge of a
QCA block, it is evaluated and output at another edge.
This also means that no power lines need be routed
internally. The second advantages is that QCA systems
should be very low power, because there is no current
flowing. Only enough energy needs to added to lift the
electrons from their ground states. Finally, QCA cells
are very small. [11]
The problem with QCA is that it has to be very small.
In order for a QCA system to operate at room
temperature it must be fabricated on the nanometer
scale. Systems which have been fabricated with current
technology have to be operated at liquid helium
temperatures. There is also an issue of tolerance. Each
cell needs exactly 2 electrons trapped in it. With 3
electrons cell performance rapidly degrades. Also
within a single cell each island has to be exactly the
same size. If they are not, they will bias a cell towards
a “1” or “0” value. It has been suggested that these
issues could be addressed by fabricating QCA cells from
molecules with multiple redox sites [12].
There have been some other suggested technologies.
One new theory is known as DNA computing but it is in
the very early stages of development [5]. Also, organic
transistors, which use semiconducting polymers are
being developed. These transistors have very low
performance, but offer the promise of low cost
fabrication [13].
[5] T.N. Theis, “Beyond the silicon transistor: personal observations,”
Computing in Science & Engineering, Jan.-Feb. 2003, pgs. 25 – 29
[6] T. H. Ning, “Why BiCMOS and SOI BiCMOS?”, Journal of Research
and Development, March/May 2002, pgs. 181 – 186
[7] Victor V. Zhirnov, Ralph K. Cavin, III, James A. Hutchby, and George
I. Bourianoff, “Limits to Binary Logic Switch Scaling-A Gedanken
Model,” Proceedings of the IEEE, Vol. 91, no. 11, November 2003, pgs.
1934 – 1939
[8] K.K. Berggren, “Quantum computing with superconductors,”
Proceedings of the IEEE, Oct. 2004, pgs. 1630 – 1638
[9] A. Narayanan, “Quantum computing for beginners,” Evolutionary
Computation, 1999. CEC 99. Proceedings of the 1999 Congress on, 6-9
July 1999, pgs. 2238 Vol. 3
[10] David P. DiVincenzo, “The Physical Implementation of Quantum
Computation,” Fortschritte der Physik special issue, Experimental
Proposals for Quantum Computation, August 13 2000, pgs. 1 – 8
[11] C. S. Lent, P. D. Tougaw, W. Porod, G. H. Bernstein, “Quantum
Cellular Automata,” Nanotechnology 4, 1993, 49-57
[12] C. S. Lent, B. Isaksen, “Clocked molecular quantum-dot cellular
automata,” IEEE Transactions on Electron Devices 50, 2003, 1890-1896
[13] B. Ong, “Towards printed organic electronics,” Asian Green
Electronics, 2004. AGEC. Proceedings of 2004 International IEEE
Conference on the, 2004, pgs. 42

V.CONCLUSION
So what does the future hold for computing? Clearly
CMOS is going to be around for a long time yet. Even
when scaling reaches it's limits, higher level design
changes can be implemented to reduce power and
improve performance. Most likely one or two of the
alternate technologies discussed above will produce
practical applications as well. These technologies will
probably develop in parallel with CMOS allowing
developers to choose the technology that best fits their
needs.

REFERENCES
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Delayed!”, Solid-State Circuits Conference, 2003. Digest of Technical
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[3] Scott E. Thompson, Robert S. Chau, Tahir Ghani, Kaizad Mistry, Sunit
Tyagi, and Mark T. Bohr, “In Search of 'Forever,' Continued Transistor
Scaling One New Material at a Time,” IEEE Transactions on
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[4] E. J. Nowak, “Maintaining the benefits of CMOS scaling when scaling
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