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Aim:
To study the tools available in xilinx software manuals
Beginning
Verilog was invented by Phil Moorby and Prabhu Goel during the winter of
1983/1984 at Automated Integrated Design Systems (later renamed to Gateway
Design Automation) in 1985 as a hardware modeling language. Gateway Design
Automation was later purchased by Cadence Design Systems in 1990. Cadence now
has full proprietary rights to Gateway's Verilog and the Verilog-XL simulator logic
simulators.
Verilog-95
With the increasing success of VHDL at the time, Cadence decided to make the
language available for open standardization. Cadence transferred Verilog into the
public domain under the Open Verilog International (OVI) (now known as Accellera)
organization. Verilog was later submitted to IEEE and became IEEE Standard 1364-
1995, commonly referred to as Verilog-95.
Verilog 2001
Extensions to Verilog-95 were submitted back to IEEE to cover the deficiencies that
users had found in the original Verilog standard. These extensions became IEEE
Standard 1364-2001 known as Verilog-2001.
Verilog 2005
SystemVerilog
The advent of High Level Verification languages such as OpenVera, and Verisity's E
language encouraged the development of Superlog by Co-Design Automation Inc.
Co-Design Automation Inc was later purchased by Synopsys. The foundations of
Superlog and Vera were donated to Accellera, which later became the IEEE standard
P1800-2005: SystemVerilog.
Result:
Thus, the tools which is used for synthesis and simulation was studied.
HALF ADDER
Exp.No.2
Aim:
To write a HDL code for the half adder using Verilog
Algorithm:
PROGRAM:
Module ha (a,b,s,c);
Input a;
Input b;
Output s;
Output c;
XOR x1(s,a,b);
And x2(c,a,b);
End module;
Result:
Thus the HDLcode for half adder was implemented and verified.
FULL ADDER
Exp.No.3
Aim:
To write a HDL code for full adder using verilog
Algorithm:
PROGRAM:
Module fa(a,b,d,s2,carry);
Input a,b,d;
Output s2,carry;
Wire s1,c1,c2;
Ha ha1(a,b,s1,c1);
Ha ha2(s1,d,s2,c2);
Or g1(carry,c1,c2);
End module;
Result:
Thus the HDL code for full adder was implemented and verified.
4-BIT FULL ADDER
Expt.No.4
AIM:
To write a HDL code for 4-bit full adder using verilog
Algorithm:
PROGRAM:
Result:
Thus the HDL code for 4bit full adder was implemented and verified.
EQUALITY DETECTOR
Expt.No:5
Aim:
To write a HDL code for equality detector using verilog
Algorithm:
PROGRAM:
Module eqd(a,b,y);
Input [3:0] a;
Output [3:0] b;
Output y;
Wire p,q,r,s;
XNOR x1(p,a[0],b[0]);
XNOR x2(r,a[1],b[1]);
XNOR x3(r,a[2],b[2]);
XNOR x4(s,a[3],b[3]);
AND x5(y,p,q,r,s);
End module;
Result:
Thus HDL code for equality detector was implemented and verified.
PRIORITY ENCODER
Expt.No.6
AIM:
To write a HDL code for priority encoder using verilog
Algorithm:
Program:
Module penc(d,x,y,v);
Input (3:0)d;
output x;
output y;
output v;
wire s,r;
not g1(s,d[2]);
or g2(x,d[3],d[2]);
and g3(r,s,d[1]);
or g4(y,v,d[3]);
or g5(v,x,d[1],d[0]);
end module
Result:
Thus HDL code for priority encoder was implemented and verified.
MAGNITUDE COMPARATOR
Ex.No.7
Aim:
To write a HDL code for magnitude comparator using verilog
Algorithm:
Program:
Module mgc(x,y,a,b,c);
Input x,y;
Output a,b,c;
Wire p,q;
Not g1(p,x);
Not g2(q,y);
And g3(a,y,p);
And g4(b,x,q);
Xnor g5(c,x,y);
End module
Result:
Thus HDL code for magnitude comparator was implemented and verified.
3X8 DECODER
Expt.No.8
AIM:
To write a HDL code for 3X8 decoder using verilog
Algorithm:
Program:
Module dec(x,y,z,d);
Input x,y,z;
Output [7:0] d;
Wire p,q,r;
Not g1(p,x);
Not g2(q,y);
And g3(d[0],p,q,r);
And g4(d[1],p,q,z);
And g5(d[2],p,q,r);
And g6(d[3],p,y,z);
And g7(d[4],x,q,z);
And g8(d[5],x,q,z);
And g9(d[6],x,y,r);
And g10(d[7],x,y,z);
End module
Result:
Thus HDL code for 3X8 decoder was implemented and verified.
4X1 MULTIPLXER
Expt.No.9
AIM:
To write a HDL code for 4X1 MUX using verilog
Algorithm:
Program:
Result:
Thus the HDL code for multiplexer was implemented and verified.
D-FLIP FLOP
Expt.No.10
AIM:
Algorithm:
Program:
Result:
Thus HDL code for d-Flip flop was implemented and verified.
T-FLIP FLOP
Expt.No.11
AIM:
To write a HDL code for T-flip flop using verilog.
Algorithm:
Program:
Module tff(q,clk,rst);
Output q;
Input clk,rest;
Wire d;
Dff dff0(q,d,clk,rst);
Not n1(d,q);
End module
Result
Thus the HDL code for T-flip flop was implemented and verified.
4-BIT SHIFT REGISTER
Expt.No.12
AIM:
Algorithm:
Program:
module flop (clk, d, ce, pre, q);
input clk, ce, pre;
input [3:0] d;
output [3:0] q;
reg [3:0] q;
always @(posedge clk or posedge pre)
begin
if (pre)
q <= 4’b1111;
else if (ce)
q <= d;
end
end module
Result:
Thus HDL code for shift register was implemented and verified.
JK-FLIP FLOP
Expt.No.13
AIM:
To write a HDL code for JK flip flop using verilog.
Algorithm:
Program:
Result:
Thus the HDL code for JK flip flop using D-flip flop was implemented and verified.
SEQUENCE DETECTOR
Expt.No.14
AIM:
To write a HDL code for sequence detector using verilog
Algorithm:
Program:
Result:
Thus HDL code for sequence detector was implemented and verified.
COUNTER
Expt.No.15
AIM:
To write a program for counter using verilog
Algorithm:
1. Start the program
2. create verilog module for counter
3. when reset is high, count is zero,when its goes high,count is incremented
4. stop the program
Program:
Module counter(clk,ce,rst,count);
Input rst,clk,ce;
Reg [3:0]count;
Output[3:0] cont;
Always @(posedge clk)
If (rst)
Count= 4`b0000;
Else
If (ce)
Count<=count+1;
Else
Count=count;
End module
Result:
Expt.No.16
AIM:
To write a HDL code for clock divider using verilog.
Algorithm:
Program:
reg [5:0]cnt;
Result:
Thus HDL code for clock divider was implemented and verified.