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Pascal BLANC
STEricsson
OUTLINE
• Case study
• Current low-power adjacent fill
• Shift power effort feature
• Experimental work
– simulation
– silicon
• Conclusions
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CASE STUDY
• Application: Baseband
• Technology: 65 nm
• Complexity: 280,000 FFs
• Scan configuration:
– DFTMax compression
– 17 test clock domains
– 65 external channels
– 3276 internal scan chains
– 89 Flip-Flops per scan chain in compression mode
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CURRENT LOW-POWER ADJACENT FILL (1/2)
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CURRENT LOW-POWER ADJACENT FILL (2/2)
• Advantages
– Reduce the average switching
activity in shift mode
– Easy to setup
• Improvements required
– More effective in a compression
mode
– First patterns less “power-
hungry”
– Reduce peak switching activity in
shift mode
– Control the adjacent fill efficiency
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SHIFT POWER EFFORT FEATURE
• Command :
set_atpg –fill adjacent \
–shift_power_effort {low|medium|high}
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EXPERIMENTAL WORK – SIMULATION (1/2)
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EXPERIMENTAL WORK – SIMULATION (2/2)
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EXPERIMENTAL WORK – SILICON
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CONCLUSIONS
• Good benefits :
– Significant shift switching activity reduction (average and peak)
– Increase the scan shift frequency on silicon
– Possibility to control the switching activity
– No excessive peak power consumption in the first test vectors
– No DFT feature nor basic design modifications needed
• Improvements needed :
– Huge difference between the high case and the low and medium ones
– Switching activity not constant during the overall set of patterns
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End
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