Introduction to VLSI

Static CMOS Logic Gates

CMOS Gates Their Ups and Downs

We want complementary pullup

and pulldown logic:
the pulldown should be “on” when
the pullup is “off”, and vice versa. Pullup
Structure

Complementary F

Pulldown
Structure
CMOS Gates: Ups and Downs

pullup: make this connection

... when we want F (A1,…,An) = 1
1A
... F ,A
1,
… n)
(A
A
n
pulldown: make this connection
... when we want F (A1,…,An) = 0

Since we want VOH = Vdd better use on P-fets in the pullup

path
Similarly, since we want VOL= 0, better use N-fets in pulldown
path.
Pullup and pulldown paths are never both on at the same time.
CMOS gates are naturally inverting.
 CMOS Gates: True Output

pullup: make this connection

... when we want F (A1,…,An) = 1

1A
... F (A1,…,An)
An
... pulldown: make this connection
when we want F (A1,…,An) = 0
 CMOS Gates: False Output

pullup: make this connection

when we want F (A1,…,An) = 0
...

1A
_
... F (A1,…,An)
A
n

... pulldown: make this connection

when we want F (A1,…,An) = 1
 Complementary Structures
Pull Down Pull Up

Conducts when Vgs is high Conducts when Vgs is low

A B

Conducts when
_  _ A is low
Conducts when A is high or B is low A+B
and B is high AB

Conducts when A is high

or B is high A+B
Conducts when__A is low
and B is low AB
 Determining Complementary
Stucture: K Map
B
A 0 1

0 1 0

1 0 0

A
B
Determining the Complementary
Structure: Graphic Method
A

A C
B D
Invert-Or Gate
Nand Gate

A
3-input Nand Gate

C
B
A
 Nor Gate

B
 3-input Nor

C
Bubble Matching
 Complex Gates
A
B A

C B
C
A
A
B
B
C
C

AOI OAI

B C
A C A B
Odd # of bubbles between any 1 input and output means it can be designed
with only one CMOS gate (no inverters)
 XOR Gate

B 0 1
A
0 0 1

1 1 0

B
Limits on the Number of Inputs
Gate Trees
 Gate Trees
A = 48 A = 144