Cmos_process.

ppt

CMOS Fabrication Process

N-Well Implant and Drive-in Diffusion

Dotted outline
is the final
circuit (for
reference).

Heavy line is
the current
process step

EE534 GYRobinson Ref: W. Maly, Atlas of IC 1

CSU Technologies, 1987.
 P+ Implant and Mask for Field Oxide Growth

EE534 GYRobinson Ref: W. Maly, Atlas of IC 2

CSU Technologies, 1987.
 Thick Field Oxide Growth

EE534 GYRobinson Ref: W. Maly, Atlas of IC 3

CSU Technologies, 1987.
 Gate Oxide Growth

Before the next

process step, by masking the wafer,
the channel regions can be separately
implanted. This extra step will allow
adjustment of Vtn and Vtp by altering
NB locally under each gate.

EE534 GYRobinson Ref: W. Maly, Atlas of IC 4

CSU Technologies, 1987.
 Deposit Gate Poly Si Layer and Etch

Avoid undercut of
poly so that L is
accurately transferred
from the mask.

EE534 GYRobinson Ref: W. Maly, Atlas of IC 5

CSU Technologies, 1987.
 Implant n-Channel n+ Regions

Gate poly acts as mask

and thus alignment of
gate and source/drain is
automatic (self-aligned
process).

EE534 GYRobinson Ref: W. Maly, Atlas of IC 6

CSU Technologies, 1987.
 Implant n-Channel p+ Regions

EE534 GYRobinson Ref: W. Maly, Atlas of IC 7

CSU Technologies, 1987.
 Implant n-Well n + Region

n+ contact for
n-well

EE534 GYRobinson Ref: W. Maly, Atlas of IC 8

CSU Technologies, 1987.
 Deposition of CVD SiO2 Layer

Abrupt steps are

smoothed over with
deposited insulating
layer.

EE534 GYRobinson Ref: W. Maly, Atlas of IC 9

CSU Technologies, 1987.
 Open Contact Cuts

EE534 GYRobinson Ref: W. Maly, Atlas of IC 10

CSU Technologies, 1987.
 Metallization

Deposit
aluminum (Al)
layer.

EE534 GYRobinson Ref: W. Maly, Atlas of IC 11

CSU Technologies, 1987.
 Final Circuit - CMOS Inverter

p+ contact

n+ contact

Entire wafer is
covered with a
protective
layer of glass
(passivated),
not shown
here.

P-
n+ contact for
n-well

Requires a p+ contact
for connection to
substrate.

EE534 GYRobinson Ref: W. Maly, Atlas of IC 12

CSU Technologies, 1987.