Microcontroller Based UPS

Project Supervisors:

Prof. Azhar Hussain Shah

Project Team:

Jamshaid Minhas L2F06BSEE0444

Ammar Ilyas Butt L2F06BSEE0449

M. Farooq Adil L2F06BSEE0451

SESSION 2006

FACULTY OF ENGINEERING
UNIVERSITY OF CENTRAL PUNJAB
LAHORE, PAKISTAN

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 Microcontroller Based UPS

This project report is submitted to the Faculty of Engineering, University of Central Punjab,
Lahore, Pakistan for the partial fulfillment of requirements for the degree

Of

Bachelor of Science

In

Electrical Engineering

---------------------
Internal Examiner: Sign: _____________________________

Name: ____________________________

External Examiner: Sign: ______________________________

Name: _____________________________

SESSION 2006

FACULTY OF ENGINEERING
UNIVERSITY OF CENTRAL PUNJAB
LAHORE, PAKISTAN

2
 Acknowledgement

We would like to thank Allah, the Almighty at the first place for giving us much
courage and strength during the completion of this project and thesis, without the
help of Whom all His creatures are worthless .

Several people should also be mentioned for their contributions to accomplish our
task. We are greatful to our project supervisor Prof Azhar Hussain Shah for his
kind supervision, help and support. We are also thankful to the lab staff in the
Project Lab for their cooperation during this work

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 Contents
Page No.
Introduction 4-19

Chapter 1

Components of UPS

1.1 DC/DC Converter 20

1.1.1 Forward Converter 21
1.1.2 Push-Pull Converter 21
1.1.3 Half-Bridge Converter 23
1.1.4 Full-Bridge Converter 24
1.1.5 Flyback Converter 25
1.2 VOLTAGE SOURCE INVERTER (VSI) 26
1.2.1 Half-Bridge VSI 26
1.2.2 Full-Bridge VSI 27
1.3 BATTERY CHARGER 28
1.3.1 Linear Chargers 28
1.3.2 Switch Mode Chargers 29
1.3.3 Ferroresonant Chargers 29
1.3.4 SCR Chargers 30

Chapter 2
Hardware Overview

2.1 Principles and configurations 31

2.2 Design criteria and selection 31
2.3 Selecting an UPS 32
2.4 INVERTER 33
2.5 Modified sine wave 34

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2.6 Pulse Width Modulation 35
2.7 Block Diagram: 36

Chapter 3
Software

3.1 Introduction 37
3.2 Software Listing 37-57
3.3 Software Flowchart 58

Chapter 4

System operation
4.1 Introduction 59
4.2 LED status 60
4.3 Transformer 60
4.4 Feedback 60
4.5 Other components 61
4.6 Ups conversion 62
4.7 Output wave form 63
4.8 Problem encounter 63
4.9 PCB and assembly 64

Recommendations and Refrences 69

Appendix A 70-71

Appendix B 72-73

Appendix C 74-75

Appendix D 76-77

Appendix E 78-79

Appendix F 80-82

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 Introduction
An Uninterruptible power supply (UPS), also known as a battery back-up, provides emergency
power and, depending on the topology, line regulation as well to connected equipment by
supplying power from a separate source when utility power is not available. It differs from an
auxiliary or emergency power system or standby generator, which does not provide instant
protection from a momentary power interruption. A UPS, however, can be used to provide
uninterrupted power to equipment, typically for 5–15 minutes until an auxiliary power supply
can be turned on, utility power restored, or equipment safely shut down. While not limited to
safeguarding any particular type of equipment, a UPS is typically used to protect computers, data
centers, telecommunication equipment or other electrical equipment where an unexpected power
disruption could cause injuries, fatalities, serious business disruption or data loss. UPS units
come in sizes ranging from units which will back up a single computer without monitor (around
200 VA) to units which will power entire data centers, buildings, or even an entire city. (several
megawatts).

An UPS contains an internal rechargeable battery that gets charged from the power
line then gets used to generate line power to the load when the power line fails. To accomplish
that they also contain an inverter, an electronic device capable of generating 110/220v AC from
battery-level DC voltage. There are different types of UPS depending on how and when the
power generation occurs, and how precisely sine waveshaped AC voltage they produce. Power
line AC voltage is supposed to be a sine-wave, and it mostly is. UPS-generated AC is usually a
lot less sine-shaped and some devices care more about than that others.

For large power units, Dynamic Uninterruptible Power Supply are sometimes
used. A synchronous motor/alternator is connected on the mains via a choke. Energy is stored in
a flywheel. When the mains power fails, an Eddy-current regulation maintains the power on the
load. DUPS are sometimes combined or integrated with a dieselgenerator, forming a diesel
rotary uninterruptible power supply, or DRUPS.

Generally, an ideal UPS should be able to deliver uninterrupted power while

simultaneously providing the necessary power conditioning for the particular power application.
Therefore, an ideal UPS should have the following features

● Regulated sinusoidal output voltage with low total harmonic distortion (THD) independent of
the changes in the input voltage or in the load, linear or nonlinear, balanced or unbalanced.

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● On-line operation, which means zero switching time from normal to backup mode and vice
versa.

● Low THD sinusoidal input current and unity power factor.

● High reliability.

● Bypass as a redundant source of power in the case of internal

failure.

● High efficiency.

● Low electromagnetic interference (EMI) and acoustic noise.

● Electric isolation of the battery, output, and input.

● Low maintenance.

● Low cost, weight, and size.

The Need for Standby Generation:

The need for standby generation arises if the consequences of a failure or disruption of the
normal supply are not acceptable. The types of installation in which the need arises seem to be
limitless. There are basically four reasons for installing standby generation: safety, security,
financial loss and data loss.

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Safety Where there is a risk to life or health such as in air traffic control, aviation ground
lighting, medical equipment in hospitals, nuclear installations, oil refineries.

Security against vandalism, espionage, or attack Area lighting, communication systems,

military installations, etc.

Data loss Situations in which the loss of data may be catastrophic and irretrievable such as data
processing and long-term laboratory type of testing or experiment

Financial loss Critical industrial processes, large financial institutions, etc.

The advances in power electronics during the past three decades have resulted in a
great variety of new topologies and control strategies for UPS systems. The research has been
focused mainly on improving performance and expanding application areas of UPS systems. The
issue of reducing the cost of converters has recently attracted the attention of researcher.
Reducing the number of switches provides the most significant cost reduction. Another form of
cost reduction is to replace active switches such as IGBTs, MOSFETs, and thyristors with
diodes. Not only are diodes more reasonable than the controlled switches, but there is also a cost
reduction from eliminating gate drivers for active switches and power supplies for gate drivers.
Another way of reducing cost is to develop topologies that employ switches with lower reverse
voltage stresses and lower current ratings, which means less silicon and smaller switching losses
resulting in lower cost and higher efficiency.

Classification:
UPS systems are classified into three general types: static, rotary, and hybrid static/rotary. In this
section, we explain these three categories of the UPS systems.

On-Line UPS:
On-line UPS systems appeared during the 1970s. They consist of a rectifier/ charger, a battery
set, an inverter, and a static switch (bypass). Other names for this configuration are inverter-
preferred UPS and double-conversion UPS Figure 1 shows the block diagram of a typical on-line
UPS. The rectifier/charger continuously supplies the DC bus with power. Its power rating is
required to meet 100% of the power demanded by the load as well as the power demanded for

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charging the battery bank. The batteries are usually sealed lead–acid type. They are rated in order
to supply power during the backup time, when the AC line is not available. The duration of this
time varies in different applications. The inverter is rated at 100% of the load power since it must
supply the load during the normal mode of operation as well as during the backup time. It is
always on; hence, there is no transfer time associated with the transition from normal mode to
stored energy mode.This is the main advantage of the on-line UPS systems. The static switch
provides redundancy of the power source in the case of UPS malfunction or overloading. The
AC line and load voltage must be in phase in order to use the static switch. This can be achieved
easily by locked-phase control loop.

Figure 1: On-Line UPS

There are three operating modes related to this topology: normal mode, stored energy mode, and
bypass mode.

Normal Mode of Operation:

During this mode of operation, the power to the load is continuously supplied via the
rectifier/charger and inverter. In fact, a double conversion, that is, AC/DC and DC/AC, takes
place. It allows very good line conditioning. The AC/DC converter charges the battery set and
supplies power to the load via the inverter. Therefore, it has the highest power rating in this
topology, increasing the cost.

Stored-Energy Mode of Operation:

When the AC input voltage is outside the preset tolerance, the inverter and battery maintain
continuity of power to the load. The duration of this mode is the duration of the preset UPS

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backup time or until the AC line returns within the preset tolerance. When the AC line returns, a
phase-locked loop (PLL) makes the load voltage in phase with the input voltage and after that the
UPS system returns to the normal operating mode.

Bypass Mode of Operation:

The UPS operates in this mode in case of an internal malfunction such as over current. This
mode is also used for fault clearing. It should be mentioned that the output frequency should be
the same as the AC line frequency in order to ensure the transfer of power. In some cases, there
can be a maintenance bypass as well. A manual switch usually operates it.

The main advantages of on-line UPS are very wide tolerance to the input
voltage variation and very precise regulation of output voltage. In addition, there is no transfer
time during the transition from normal to stored energy mode. It is also possible to regulate or
change the output frequency.

The main disadvantages of this topology are low-power factor, high THD at the
input, and low efficiency. The input current is distorted by the rectifier unless an extra power
factor correction (PFC) circuit is added; but, this adds to the cost of the UPS system. Because of
this inherently low input power factor, the on-line UPS cannot efficiently utilize the utility
network and local installation. The low efficiency is inherent to this topology because of the
double-conversion nature of this UPS. Power flow through the rectifier and inverter during the
normal operation means higher power losses and lower efficiency compared to off-line and line-
interactive UPS systems.

Despite the disadvantages, double-conversion UPS is the most preferred

topology in performance, power conditioning, and load protection. This is the reason why they
have a very broad range of applications from a few kVA to several MVA. This broad range of
applications brings a large diversity of topologies in on-line UPS systems. Each topology tries to
solve different specific problems and the particular choice depends upon the particular
application. However, generally, there are two major types of double-conversion topologies: with
a low-frequency transformer isolation and with a highfrequency transformer isolation.Figure 2
shows the block diagram of an online UPS with a low-frequency transformer isolation at the
output.

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Figure 2: Block diagram of an on-line UPS with a low-frequency transformer isolation at the output.

In this configuration, there is an isolating transformer at the output, which

operates at low frequency. This, of course, means a larger transformer. Therefore, this topology
is used only in high-power ratings (_20 kVA), where the switching frequency is limited to less
than 2 kHz. Apart from the large size of the isolating transformer, the drawback of this topology
is high acoustic noise from the transformer as well as the reactor of the output filter. This
topology also has a poor transient response to the changes in the load and input voltage.

By increasing the switching frequency of the inverter above 20 kHz, these

problems are solved, except for the size of the isolating transformer, since it is independent of the
switching frequency. A topology employing a high frequency transformer link can significantly
reduce the weight and the size of the transformer. The use of high-frequency pulse width
modulation (PWM) techniques can additionally reduce the size of the output filter. Figure 3
shows the block diagram of an on-line UPS with a high-frequency transformer isolation between
the input and the output.

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Figure 3: Block diagram of an on-line UPS with high-frequency transformer isolation.

Off-Line UPS:
This configuration is also known as the standby UPS or line-preferred UPS. As shown in Figure
4, it consists of an AC/DC converter, a battery bank, a DC/AC inverter, and a static switch.
Afilter may be used at the output of the UPS or inverter to improve the quality of the output
voltage. The static switch is on during the normal mode of operation when the AC line is alive.

Therefore, the load is supplied with power from the AC line directly without any
power conditioning. The AC/DC converter charges the battery set. It is rated at a much lower
power rating than the rectifier/charger in an on-line UPS since it is not required to meet the
power demand of the load. This, in turn, makes the off-line UPS systems more reasonable than
the on-line UPS systems. The inverter is rated at 100% of the load’s demand. It is connected in
parallel to the load and stays standby during the normal mode of operation. It is turned on only
when the primary power is out of a given preset tolerance or is not available at all. During this
mode of operation, the power to the load is supplied by the battery set via the inverter for the
duration of the preset backup time or until the AC line is back again. The duration of the
switching time depends on the starting time of the inverter. The transfer time is usually about ¼
line cycle, which is enough for most of the applications such as personal computers.

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Figure 4: OFF-Line UPS

The DC/AC inverter is conventionally off in this mode. Therefore, an offline UPS
is not usually correcting the power factor. However, in the normal mode of operation, the
DC/AC inverter may be used as an active filter to reduce the harmonic content of the line current
or improve the power factor of the load. Further modification can also be made to reduce the
harmonic content of the sinking current by the AC/DC converter when charging the battery. Yet,
these increase the complexity of the system.

There are two operating modes for an off-line UPS system: normal mode and
stored-energy mode.

Normal Mode of Operation:

In this mode, the AC line supplies the load via filter/conditioner, which, in fact, is not always
required, but often exists. The filter/conditioner depends on the requirements of the particular
load and the quality of the AC line power supply. The AC/DC converter charges the battery in
this mode in order to provide backup power for the stored-energy mode of operation.

Stored-Energy Mode of Operation:

When the AC line is beyond the preset tolerance or is not available, the load is supplied by the
battery set through the inverter for the backup time or until the AC line is available again. The
rating of the AC/DC converter has to meet only the charging requirements of the battery, which
contributes to the lower cost of this UPS.

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 The main advantages of this topology are a simple design, low cost, and small
size. The line conditioning, when there is such a feature, is passive and the technique is very
robust. On the other hand, lack of real isolation of the load from the AC line, no output voltage
regulation, long switching time, and poor performance with nonlinear loads are the main
disadvantages.

The use of a three-winding transformer, as shown in Figure 5, can provide electric

isolation for the off-line UPS. This technique has a high reliability at a moderate cost. The
transformer allows limited power conditioning for the output voltage as well. The use of a Ferro-
resonant transformer leads to a heavier UPS with a lower efficiency. The disadvantages of off-
line UPS systems limit their application to less than 2 kVA.

Figure 5: Block diagram of a typical off-line UPS using a three-winding transformer for electric isolation.

Line-Interactive UPS:
In the 1990s, line-interactive UPS systems were presented. As shown in Figure 6, a line-
interactive UPS system consists of a static switch, a series inductor, a bidirectional converter,
and a battery set.

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Figure 6: Block diagram of a typical line-interactive UPS system.

A line-interactive UPS system can operate either as an on-line UPS or as an off-

line UPS. For an off-line line-interactive UPS, the series inductor is not required. However, most
of the line-interactive UPS systems operate on-line in order to either improve the power factor of
the load or regulate the output voltage for the load.

Figure 7: Line-Interactive UPS, Typical protection time: 5 - 30 minutes, Capacity expansion: Several hours

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 When the AC line is within the preset tolerance, it feeds the load directly. The
inverter is connected in parallel with the load and charges the battery. It may also supply the
reactive power required to keep the power factor close to unity or to regulate the output voltage.

Rotary UPS:

Atypical rotary UPS is shown in Figure 8. It consists of an AC motor, a DC machine, an AC

generator, and a battery bank. Electric machines are mechanically coupled. There are two
operating modes: normal and stored energy. During the normal mode of operation, the AC line
supplies the AC motor, which drives the DC machine. The DC machine drives the AC generator,
which supplies the load. During the stored energy mode of operation, the battery bank supplies
the DC machine, which in turn drives the AC generator. The AC generator supplies the load.

Figure 8: Block diagram of a typical rotary UPS system.

The rotary UPS systems are more reliable than the static UPS systems. However,
they require more maintenance and have a much larger size and weight. But, they have many
advantages making them desirable in high power applications. One of the advantages of the
rotary UPS systems is that the transient overload capability is 300 to 600% of the full load for

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rapid fault clearing. The transient overload capability for the static UPS systems is typically
150% for a short term. The performance of the rotary UPS systems with nonlinear loads is good
because of the low output impedance. The input current THD is very low, typically 3% or less.
The electromagnetic interference (EMI) is also low. The efficiency is usually 85% or higher.

Hybrid Static/Rotary UPS:

Hybrid static/rotary UPS systems combine the main features of both static and rotary UPS
systems. They have low output impedance, high reliability, excellent frequency stability, and low
maintenance cost. These are because of the missing mechanical commutator . In Figure 9, a
typical hybrid static/rotary UPS is depicted. It consists of a bidirectional AC/DC converter, an
AC motor, an AC generator, a battery bank, and a static switch.

Figure 9: Block diagram of a typical hybrid static/rotary UPS.

During the normal mode of operation, the AC motor is fed from the AC line and
drives the generator. The AC generator supplies the load. The bidirectional converter, which
behaves as a rectifier, charges the battery.

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 During the stored-energy mode of operation, the inverter supplies the AC
generator from the battery set through the AC motor. In fact, the bidirectional converter, which
behaves as an inverter, drives the AC motor. The AC motor drives the generator supplying the
load. When an internal malfunction in the UPS system occurs, the static switch (bypass) is turned
on and the load is supplied directly from the AC line. However, since the AC line and output
voltage are not synchronized, the transition is not transient-free.

The AC generator is started on utility power to avoid starting current overloads

allowing the inverter to be rated for the normal operation. After the AC generator is on, the AC
line is disconnected and the supply to the AC generator is given by the inverter. It is relatively
easy because of the large inertia of the AC generator. This configuration has the advantage that
the transfer from the AC line to the inverter takes place under controlled conditions instead of
under fault conditions when different undesired conditions can influence the transfer. Another
good point is that the inverter is always on, allowing no transfer time for switching to the stored-
energy mode of operation.
The main advantages of this UPS over the static UPS include low output
impedance, low THD with nonlinear loads, higher reliability, and better isolation. Hybrid UPS
systems are usually used in very high-power applications, that is, several hundreds kVA.

DESIGN BACKGROUND:

When designing a UPS system, there are three items that must be considered: cost vs.
performance, output waveform and topology.

Cost vs. Performance:

A UPS system has to be reliable. Money saved on features or performance can be overshadowed
by the cost associated with data loss or component failure. So it is important to develop a cost
effective solution which satisfies both end user price sensitivity and design robustness.

Output Waveform:
Some UPS designs use a square wave output instead of a sine wave. This makes the system
cheaper to produce. But is this type of waveform really acceptable?

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 Electrical equipment uses power delivered in the form of a sine wave from local
utility companies. When considering alternative waveforms, how differing loads rely on different
parts of the standard power company waveform must be examined.

For instance, most appliances are always on, thus the power used by the appliance
is the RMS value of the sine wave, which is approximately 120 volts. However, equipment such
as computers use peak voltage values, which are approximately 170 volts. When a square wave
output is used to supply power to computer equipment, the RMS and peak values are equivalent,
thus stressing some loads and under-supplying others. So the best output to provide electrical
equipment is the output that they are designed to operate with - a sine wave.

Application Markets for UPS Systems:

UPS systems provide for a large number of applications in a variety of industries. Their common
applications range from small power rating for personal computer systems to medium power
rating for medical facilities, life-support systems, data storage, and emergency equipment, and
high power rating for telecommunications, industrial processing, and online management
systems. Different considerations should be taken into account for these applications. As an
example, a UPS for emergency systems and lighting may support the system for 90-120 minutes.
For other applications like computer backup power, a UPS may typically support the system for
15-20 minutes. If power is not restored during that time, the system will be gracefully shut down.

If a longer backup period is considered, a larger battery is required. For process

equipment and high power applications, some UPS systems are designed to provide enough time
for the secondary power sources, such as diesel generators, to start up.

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Chapter 1

COMPONENTS OF UPS
Mainly UPS consists of

DC/DC CONVERTER
VOLTAGE SOURCE INVERTER (VSI)
BATTERY CHARGER

1.1 DC/DC Converters:

Most UPS designs contain a transformer-type DC/DC converter. The transformer provides
electrical isolation between the input and output of the converter. The transformer also provides
the option to produce multiple voltage levels by changing the turns ratio, or provide multiple
voltages by using multiple secondary windings.

Transformer-type DC/DC converters are divided into five basic topologies:

• Forward Converter
• Push-Pull Converter
• Half-Bridge Converter
• Full-Bridge Converter
• Flyback Converter

The Flyback topology operation differs slightly from other topologies in that energy is
stored in magnetic material and then released. Other topologies always transfer energy directly
from input to output. Another case in which topologies are distinguished from each other is
transformer core utilization:

Selection of a topology depends on careful analysis of the design specifications, cost and
size requirements of the converter. Operation of each of the above topologies is described in the
following sections of this application note. Details of the topology selection and hardware design
are provided in subsequent sections.

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1.1.1 Forward Converter:

A forward converter, which can be a step-up or stepdown converter, is shown in Figure 1.1.
When the transistor Q is ON, VIN appears across the primary, and then generates output voltage
determined by Equation 1.

The diode D1 on the secondary ensures that only positive voltages are applied to the output
circuit while D2 provides a circulating path for inductor current if the transformer voltage is zero
or negative. A third winding is added to the transformer of a forward converter, also known as a
―reset winding‖. This winding ensures that the magnetization of the transformer core is reset to
zero at the start of the switch conduction. This winding prevents saturation of the transformer.

Figure 1.1: FORWARD CONVERTER

1.1.2 Push-Pull Converter:

A push-pull converter is shown in Figure 1.2. When Q1 switches ON, current flows through the
upper half of the T1 transformer primary and the magnetic field in T1 expands. The expanding
magnetic field in T1 induces a voltage across the T1 secondary; the polarity is such that D2 is
forward-biased and D1 is reverse-biased. D2 conducts and charges the output capacitor C2 via
L1. L1 and C2 form an LC filter network. When Q1 turns OFF, the magnetic field in T1

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collapses and after a period of dead time (dependent on the duty cycle of the PWM drive signal),
Q2 conducts, current flows through the lower half of T1's primary, and the magnetic field in T1
expands. At this point, the direction of the magnetic flux is opposite to that produced when Q1
conducted. The expanding magnetic field induces a voltage across the T1 secondary; the polarity
is such that D1 is forward- biased and D2 is reverse-biased. D1 conducts and charges the output
capacitor C2 via L1. After a period of dead time, Q1 conducts and the cycle repeats.

Figure 1.2: PUSH-PULL CONVERTER

There are two important considerations with the push-pull converter:

Both transistors must not conduct together, as this would effectively short circuit the supply.
This means that the conduction time of each transistor must not exceed half of the total
period (d < 0.5) for one complete cycle, otherwise conduction will overlap.
The magnetic behavior of the circuit must be uniform; otherwise, the transformer may
saturate, and this would cause destruction of Q1 and Q2. This behavior requires that the
individual conduction times of Q1 and Q2 must be exactly equal and the two halves of the
center-tapped transformer primary must be magnetically identical.

These criteria must be satisfied by the control and drive circuit and the transformer. The
output voltage equals that of Equation 2.

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1.1.3 Half-Bridge Converter:

The half-bridge converter (see Figure 1.3) is similar to the push-pull converter, but a center-
tapped primary is not required. The reversal of the magnetic field is achieved by reversing the
direction of the primary winding current flow. In this case, two capacitors. C1 and C2, are
required to form the DC input mid-point. Transistors Q1 and Q2 are turned ON alternately to
avoid a supply short circuit, in which case the duty cycle, d, must be less than 0.5.

For the half-bridge converter, the output voltage VOUT equals that of Equation 3.

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 Figure 1.3: HALF-BRIDGE CONVERTER

1.1.4 Full-Bridge Converter:

The full-bridge converter topology shown in Figure 1.4, is basically the same as the half-bridge
converter, where four transistors are used. Diagonal pairs of transistors (Q1-Q4 or Q2-Q3)
conduct alternately, thus achieving current reversal in the transformer primary. Output voltage
equals that of Equation 4.

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 Figure 1.4: FULL-BRIDGE CONVERTER

1.1.5 Flyback Converter:

Figure 1.5 shows a flyback converter circuit. When transistor Q1 is ON, due to the winding
polarities, the diode D1 becomes reverse-biased. Therefore, transformer core flux increases
linearly. When transistor Q1 is turned OFF, energy stored in the core causes the current to flow
in the secondary winding through the diode D1 and flux decreases linearly. Output voltage is
given by Equation 5.

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 Figure 1.5: FLYBACK CONVERTER

1.2 VOLTAGE SOURCE INVERTER (VSI):

A single-phase Voltage Source Inverter (VSI) can be defined as a half-bridge and a full-bridge
topology. Both topologies are widely used in power supplies and single-phase UPS systems.

1.2.1 Half-Bridge VSI:

Figure 1.6 shows the topology of a Half-Bridge VSI, where two large capacitors are required to
provide a neutral point N, such that each capacitor maintains a constant voltage vi  2. Because
the current harmonics injected by the operation of the inverter are low-order harmonics, a set of
large capacitors (C+ and C-) is required. The duty cycle of the switches is used to modulate the
output voltage. The signals driving the switches must ensure some dead time to prevent shorting
of the DC bus.

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 Figure 1.6: SINGLE-PHASE HALF-BRIDGE VSI

1.2.2 Full-Bridge VSI:

Figure 1.7 shows the topology of a Full-Bridge VSI. This inverter is similar to the half-bridge
inverter; however, a second leg provides the neutral point to the load. Both switches S1+ and S1-
(or S2+ and S2-) cannot be on simultaneously because a short circuit across the DC link voltage
source vi would be produced. To avoid the short circuit across the DC bus and the undefined AC
output voltage condition, the modulating technique should ensure that either the top or the
bottom switch of each leg is ON at any instant. The AC output voltage can take values up to the
DC link value vi, which is twice the value obtained with half-bridge VSI topologies. Several
modulating techniques have been developed that are applicable to full-bridge VSIs. Among
them, the best known are bipolar and unipolar PWM techniques.

Figure 1.7: SINGLE-PHASE FULL-BRIDGE VSI

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 1.3 BATTERY CHARGER:

When the AC mains voltage is present, the Offline UPS charges the batteries, and therefore, a
battery charger circuit is implemented.

Most battery chargers can be divided into four basic design types, or topologies:
• Linear Chargers
• Switch Mode Chargers
• Ferroresonant Chargers
• SCR Chargers

1.3.1 Linear Chargers:

Linear chargers consist of a power supply, which converts AC power to lower voltage DC
power, and a linear regulating element, which limits the current that flows into the battery. The
power supply typically consists of a transformer that steps down AC power from 220/110 VAC
to a lower AC voltage closer to that of the battery, and a rectifier that smooths out the existing
sinusoidal AC signal into a constant-voltage DC signal. The linear regulating element may be a
passive component such as a resistor or an active component such as a transistor that is
controlled by a reference signal. Figure 1.8 shows a simplified schematic of a linear charger with
a linear power supply with a resistor as the current regulating element.

Figure 1.8: LINEAR CHARGER

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1.3.2 Switch Mode Chargers:

In a switch mode charger, AC voltage is rectified, and then converted to a lower DC voltage
through a DC/DC converter. This type of charger contains additional charge control circuitry to
regulate current flow into the battery. The charge control regulates the way in which the power
switch turns ON and OFF, and may be accomplished through a circuit, a specialized integrated
chip, or some type of software control. A simplified schematic for a single piece switch mode
charger is shown in Figure 1.9.

Figure 1.9: SWITCH MODE CHARGER

1.3.3 Ferroresonant Chargers:

Ferroresonant chargers (sometimes called ferro chargers), operate by way of a special component
called a ferroresonant transformer. The ferroresonant transformer reduces the AC voltage to a
lower regulated voltage level while simultaneously controlling the charge current. A rectifier
then converts the AC power to DC power suitable for the battery. Figure 1.10 shows a block
diagram of a ferroresonant charger.

29
 Figure 1.10: FERRORESONANT CHARGER

1.3.4 SCR Chargers:

SCR chargers use a special component known as a Silicon-Controlled Rectifier (SCR) to control
the current to the battery. The SCR is a controllable switch that can be turned ON and OFF
multiple times per second. After a transformer reduces utility voltage to a value near that of the
battery, the diodes rectify the current while the SCR enables the flow of charge current according
to a control signal. A block diagram of an SCR charger is shown in Figure 1.11.

Figure 1.11: SCR CHARGER

30
Chapter 2

Hardware Overview
2.1 Principles and configurations
An UPS system is an alternate or backup source of power with the electric utility company being
the primary source. The UPS provides protection of load against line frequency variations,
elimination of power line noise and voltage transients, voltage regulation, and uninterruptible
power for critical loads during failures of normal utility source. An UPS can be considered a
source of standby power or emergency power depending on the nature of the critical loads. The
amount of power that the UPS must supply also depends on these specific needs. These needs
can include emergency lighting for evacuation, emergency perimeter lighting for security,
orderly shut down of manufacturing or computer operations, continued operation of life support
or critical medical equipment, safe operation of equipment during sags and brownouts, and a
combination of the preceding needs.

2.2 Design criteria and selection

The UPS selection process involves several steps as discussed briefly here. These steps are
discussed in further detail in chapter 3.

a. Determine need. Prior to selecting the UPS it is necessary to determine the need. The
types of loads may determine whether local, state, or federal laws mandate the
incorporation of an UPS. An UPS may be needed for a variety of purposes such as
lighting, startup power, transportation, mechanical utility systems, heating, refrigeration,
production, fire protection, space conditioning, data processing, communication, life
support, or signal circuits. Some facilities need an UPS for more than one purpose. It is
important to determine the acceptable delay between loss of primary power and
availability of UPS power, the length of time that emergency or backup power is
required, and the criticality of the load that the UPS must bear. All of these factors play
into the sizing of the UPS and the selection of the type of the UPS.

b. Determine safety. It must be determined if the safety of the selected UPS is

acceptable. The UPS may have safety issues such as hydrogen accumulation from
batteries, or noise pollution from solid-state equipment or rotating equipment. These
issues may be addressed through proper precautions or may require a selection of a
different UPS.

31
 c. Determine availability. The availability of the selected UPS must be acceptable. The
criticality of the loads will determine the necessary availability of the UPS. The
availability of an UPS may be improved by using different configurations to provide
redundancy. It should be noted that the C4ISR facilities require a reliability level of
99.9999 percent.

d. Determine maintainability. The selected UPS must be maintainable. Maintenance of

the unit is important in assuring the unit’s availability. If the unit is not properly cared
for, the unit will be more likely to fail. Therefore, it is necessary that the maintenance be
performed as required. If the skills and resources required for the maintenance of the unit
are not available, it may be necessary to select a unit requiring less maintenance.

e. Determine if affordable. The selected UPS must be affordable. While this is the most
limiting factor in the selection process, cost cannot be identified without knowing the
other parameters. The pricing of the unit consists of the equipment cost as well as the
operating and maintenance costs. Disposal costs of the unit should also be considered for
when the unit reaches the end of its life.

f. Re-evaluate steps. If these criteria are not met, another UPS system must be selected
and these steps re-evaluated.

2.3 Selecting an UPS

The process for selecting an UPS consists of eight steps. These steps are: determining the need
for an UPS, determining the purpose(s) of the UPS, determining the power requirements,
selecting the type of UPS, determining if the safety of the selected UPS is acceptable,
determining if the availability of the selected UPS is acceptable, determining if the selected UPS
is maintainable, and determining if the selected UPS is affordable. The last four steps may
require repeating if the UPS does not meet all of the requirements. This process does not and
cannot provide a ―cookbook solution.‖ Each facility has unique requirements for emergency and
standby power. These requirements include the reliability of the prime power source, the nature
of the work done, local and state regulations governing emergency power, etc.
The process does not give a single solution that is applicable to all cases. It is hoped,
however, that it provides the framework for selecting an UPS for any facility. Figure 3-1
illustrates this process. To help illustrate how the selection procedure can be used, an example is
provided in appendix B. This example is completely fictitious and should not be considered as
―the‖ model for how the selection process would be used in every case. It does, however,
illustrate the many factors that go into the decision process and the need for a good staff to assist
the facility manager in making the UPS selection.

32
2.4 INVERTER

The method in which the low voltage DC power is inverted, is completed in two steps. The first
being the conversion of the low voltage DC power to a high voltage DC source, and the second
step being the conversion of the high DC source to an AC waveform using pulse width
modulation. Another method to complete the desired outcome would be to first convert the low
voltage DC power to AC, and then use a transformer to boost the voltage to 120 volts. This
project focused on the first method described and specifically the transformation of a high
voltage DC source into an AC output.Of the different DCAC inverters on the market today there
are essentially two different forms of AC output generated: modified sine wave, and pure sine
wave1.
A modified sine wave can be seen as more of a square wave than a sine wave; it passes
the high DC voltage for specified amounts of time so that the average power and rms voltage are
the same as if it were a sine wave. These types of inverters are much cheaper than pure sine wave
inverters and therefore are attractive alternatives. Pure sine wave inverters, on the other hand,
produce a sine wave output identical to the power coming out of an electrical outlet. These
devices are able to run more sensitive devices that a modified sine wave may cause damage to
such as: laser printers, laptop computers, power tools, digital clocks and medical equipment. This
form of AC power also reduces audible noise in devices such as fluorescent lights and runs
inductive loads, like motors, faster and quieter due to the low harmonic distortion.

33
2.5 Modified sine wave

Figure 2.2: Modified sine wave

A modified sine wave is similar to a square wave but instead has a ―stepping‖ look to it that
relates more in shape to a sine wave. This can be seen in Figure 2, which displays how a
modified sine wave tries to emulate the sine wave itself. The waveform is easy to produce
because it is just the product of switching between 3 values at set frequencies, thereby leaving
out the more complicated circuitry needed for a pure sine wave. The modified sine wave inverter
provides a cheap and easy solution to powering devices that need AC power. It does have some
drawbacks as not all devices work properly on a modified sine wave, products such as computers
and medical equipment are not resistant to the distortion of the signal and must be run off of a
pure sine wave power source.

34
2.6 Pulse Width Modulation

In electronic power converters and motors, PWM is used extensively as a means of powering
alternating current (AC) devices with an available direct current (DC) source or for advanced
DC/AC conversion. Variation of duty cycle in the PWM signal to provide a DC voltage across
the load in a specific pattern will appear to the load as an AC signal, or can control the speed of
motors that would otherwise run only at full speed or off. This is further explained in this
section. The pattern at which the duty cycle of a PWM signal varies can be created through
simple analog components, a digital microcontroller, or specific PWM integrated circuits.
Analog PWM control requires the generation of both reference and carrier signals that feed into a
comparator which creates output signals based on the difference between the signals10. The
reference signal is sinusoidal and at the frequency of the desired output signal, while the carrier
signal is often either a sawtooth or triangular wave at a frequency significantly greater than the
reference. When the carrier signal exceeds the reference, the comparator output signal is at one
state, and when the reference is at a higher voltage, the output is at its second state. This process
is shown in Figure 3 with the triangular carrier wave in red, sinusoidal reference wave in blue,
and modulated and unmodulated sine pulses.

Figure 2.3: Pulse width Modulation

35
 In order to source an output with a PWM signal, transistor or other switching technologies are
used to connect the source to the load when the signal is high or low. Full or half bridge
configurations are common switching schemes used in power electronics. Full bridge
configurations require the use of four switching devices and are often referred to as Hbridges due
to their orientation with respect to a load.

2.7 Block Diagram:

Block Diagram of Harare is shown below.

PWM Comparator

Pre-Driver Circuit
Enable
PIC16F876A
A/B

Current Voltage
Sense Sense

44 7’ 7’ 9 12’

LC Filter H-Bridge
Driver Circuit
Output

36
Chapter 3
Software
3.1 Introduction

Why use C?
The C language was developed at Bell Labs in the early 1970’s by Dennis Ritchie and Brian
Kernighan. One of the first platforms for implementation was the PDP-11 running under a UNIX
environment. Since its introduction, it has evolved and been standardized throughout the
computing industry as an established development language. The PC has become a cost effective
development platform using C++ or other favored versions of the ANSI standard.

C is a portable language intended to have minimal modification when transferring

programs from one computer to another. This is fine when working with PC’s and mainframes,
but Microcontrollers and Microprocessors are different breed. The main program flow will
basically remain unchanged, while the various setup and port/peripheral control will be micro
specific. An example of this is the port direction registers on a PICmicro®MCU are set 1=Input
0=Output, whereas the H8 is 0=Input and 1=Output.

The use of C in Microcontroller applications has been brought about by manufacturers

providing larger program and RAM memory areas in addition to faster operating speeds.

3.2 Software Listing:

The main purpose of the microcontroller software is to provide an inverter fast feedback loop
response, such that the transient response and output distortion are that of a high performance
design.

In addition, the inverter software may be used to provide the necessary communication to
any ―housekeeping‖
code as well as synchronization of the output voltage to the input voltage waveform. The
housekeeping software was not developed for this reference design; however, the inverter
software has ―hooks‖ in place for such interfacing.

37
#include <16F876A.h>
#device *=16
#device ADC=8
#fuses HS,WDT,PUT,BROWNOUT,NOPROTECT,NOLVP,NOCPD
#use delay(clock=20000000, RESTART_WDT)
#use fast_io(B)
#use fast_io(C)

#define ab_chan 0
#define stdby_chan 1
#define i_chan 2
#define acc_chan 3
#define v_chan 4

const long sine_wave[32] = {81,162,241,318,392,462,527,588,642,691,733,768,795, // sine

wave constants;
815,827,831,827,815,795,768,733,691,642,588,527,462,
392,318,241,162,81,0};
const int volt_sine_ref[32] = {0,5,9,14,18,23,27,31,34,37,40,42,44,46,47,48,48,
48,47,46,44,42,40,37,34,31,27,23,18,14,9,5};
//const int delta_v_h[16] = {7,7,6,6,6,5,5,5,4,4,4,3,3,3,2,2};
//const int delta_v_l[16] = {3,3,3,3,3,3,3,2,2,2,2,1,1,1,0,0};
const int delta_corr[32] = {3,6,9,12,15,18,20,23,25,27,28,30,31,31,32,32,32,31,
31,30,28,27,25,23,20,18,15,12,9,6,3,0};

int index, sine_pol, inv_mode, stdby_mode, stdby, i, inv_on, inv_off;

int low_curr_h, low_curr_l, over_curr, short_curr, high_ab, stdby_go_blink;
int low_acc, high_acc, high_t_stop, high_t_blink, low_curr;
int low_acc_delay, acc_avg_counter, volt_ref_counter, volt_l_avg_counter, volt_h_avg_counter;
int volt_h, volt_l, volt_h_avg, volt_l_avg, delta;
int acc_v, acc_v_avg, volt_a, volt_b, stdby_i, stdby_i_h, stdby_i_l, stdby_i_avg_counter;
int volt_ref, volt_ref_avg, curr_h, curr_l, curr_h_avg, curr_l_avg;
signed int delta_h_v, delta_l_v, delta_h_ref, delta_l_ref, volt_ref_delta;
signed long int level_corr[32];
signed int shape_corr[32];
long int pwm_pos, pwm_neg;
long int volt_h_temp, volt_l_temp, volt_ref_temp, acc_v_temp, over_curr_delay;
long int stdby_delay, stdby_go_delay, high_t_delay, curr_h_temp, curr_l_temp, stdby_i_temp;
const long pwm_max=1023;
const int curr_l_max=32, short_curr_l=16, ab_max=96, volt_ref_const_h=180,
volt_ref_const_l=75;
const int stdby_i_h_max=239, stdby_i_h_min=143, stdby_max=253, stdby_min=2;
const int curr_h_max=223, curr_h_min=143, curr_l_min=111, short_curr_h=239;
const int acc_max_l=92, acc_max_h=98, acc_min_l=60, acc_min_h=66;

38
#separate
void sine_pwm_start(void) // Start mode;
{
set_pwm1_duty((sine_wave[index]+level_corr[index])>>1); // positive start sine
half wave;
output_high(PIN_C1); // A=1;
output_low(PIN_C0); // Z=0;
output_high(PIN_B1);
set_adc_channel(ab_chan);
delay_us(10);
read_adc(ADC_START_ONLY);
delay_us(20);
volt_a=read_adc(ADC_READ_ONLY);
if(volt_a>=ab_max) {
// high_ab++;
if(high_ab>8) break;
}
else high_ab=0;
output_low(PIN_C3);
set_adc_channel(i_chan);
delay_us(10);
read_adc(ADC_START_ONLY);
delay_us(20);
curr_h=read_adc(ADC_READ_ONLY);
if(curr_h>=short_curr_h) {
short_curr++;
if(short_curr>8) break;
}
else {
short_curr=0;
if(curr_h>curr_h_max) over_curr_delay++;
else over_curr_delay=0;
}
}

#separate
void sine_pwm_norm(void) // Normal mode;
{
switch (sine_pol) {
case 0: // negative sine half wave;
set_adc_channel(v_chan);
delay_us(10);
read_adc(ADC_START_ONLY);

39
delay_us(20);
volt_l=read_adc(ADC_READ_ONLY);
volt_l_temp+=volt_l;
pwm_neg=sine_wave[index] + shape_corr[index] + level_corr[index];
if(pwm_neg>pwm_max) pwm_neg=pwm_max;
//if(pwm_neg<0) pwm_neg=0;
set_pwm1_duty(pwm_neg);
output_low(PIN_C1); // A=0;
output_low(PIN_C0); // Z=0;
output_low(PIN_B1);
//set_pwm2_duty(volt_l);
set_adc_channel(ab_chan);
delay_us(10);
read_adc(ADC_START_ONLY);
delay_us(20);
volt_b=read_adc(ADC_READ_ONLY);
if(volt_b>=ab_max) {
high_ab++;
if(high_ab>4) break;
}
else high_ab=0;
output_high(PIN_C3);
set_adc_channel(i_chan);
delay_us(10);
read_adc(ADC_START_ONLY);
delay_us(20);
curr_l=read_adc(ADC_READ_ONLY);
if(curr_l<=short_curr_l) {
short_curr++;
if(short_curr>4) break;
}
else {
short_curr=0;
if(curr_l<curr_l_max){
over_curr_delay++;
//level_corr[index+1]-=delta_corr[index+1];
}
else over_curr_delay=0;
}
output_low(PIN_C3);
set_adc_channel(i_chan);
delay_us(10);
read_adc(ADC_START_ONLY);
delay_us(20);
curr_h=read_adc(ADC_READ_ONLY);
curr_h_temp+=curr_h;

40
 /*if(index) {
delta_l_v=(127-volt_sine_ref[index])-volt_l;
delta=delta_corr[index-1]>>2;
if(delta_l_v>delta) shape_corr[index-1]--;
else if(delta_l_v<-delta) shape_corr[index-1]++;
}*/
if(index==31) {
curr_h_avg=curr_h_temp>>5;
if((curr_h_avg<stdby_i_h)&&(!inv_on)) low_curr_l=1;
else low_curr_l=0;
volt_l_avg=volt_l_temp>>5;
delta_l_ref=volt_l_avg-(volt_ref_const_l-volt_ref_delta);
if(delta_l_ref>2) for(i=0; i<32; i++) level_corr[i]+=delta_corr[i]>>1;
else if(delta_l_ref<-2) for(i=0; i<32; i++) level_corr[i]-=delta_corr[i]>>1;
curr_h_temp=0;
volt_l_temp=0;
high_ab=0;
short_curr=0;
sine_pol=1;
}
break;
case 1: // positive sine half wave;
set_adc_channel(v_chan);
delay_us(10);
read_adc(ADC_START_ONLY);
delay_us(20);
volt_h=read_adc(ADC_READ_ONLY);
volt_h_temp+=volt_h;
pwm_pos=sine_wave[index] + shape_corr[index] + level_corr[index];
if(pwm_pos>pwm_max) pwm_pos=pwm_max;
//if(pwm_pos<0) pwm_pos=0;
set_pwm1_duty(pwm_pos);
output_high(PIN_C1); // A=1;
output_low(PIN_C0); // Z=0;
output_high(PIN_B1);
//set_pwm2_duty(volt_h);
set_adc_channel(ab_chan);
delay_us(10);
read_adc(ADC_START_ONLY);
delay_us(20);
volt_a=read_adc(ADC_READ_ONLY);
if(volt_a>=ab_max) {
high_ab++;
if(high_ab>4) break;
}
else high_ab=0;

41
output_low(PIN_C3);
set_adc_channel(i_chan);
delay_us(10);
read_adc(ADC_START_ONLY);
delay_us(20);
curr_h=read_adc(ADC_READ_ONLY);
if(curr_h>=short_curr_h) {
short_curr++;
if(short_curr>4) break;
}
else {
short_curr=0;
if(curr_h>curr_h_max) {
over_curr_delay++;
//level_corr[index+1]-=delta_corr[index+1];
}
else over_curr_delay=0;
}
output_high(PIN_C3);
set_adc_channel(i_chan);
delay_us(10);
read_adc(ADC_START_ONLY);
delay_us(20);
curr_l=read_adc(ADC_READ_ONLY);
curr_l_temp+=curr_l;
/*if(index) {
delta_h_v=(127+volt_sine_ref[index])-volt_h;
delta=delta_corr[index-1]>>2;
if(delta_h_v>delta) shape_corr[index-1]++;
else if(delta_h_v<-delta) shape_corr[index-1]--;
}*/
if(index==31) {
curr_l_avg=curr_l_temp>>5;
if((curr_l_avg>stdby_i_l)&&(!inv_on)) low_curr_h=1;
else low_curr_h=0;
volt_h_avg=volt_h_temp>>5;
delta_h_ref=(volt_ref_const_h+volt_ref_delta)-volt_h_avg;
if(delta_h_ref>2) for(i=0; i<32; i++) level_corr[i]+=delta_corr[i]>>1;
else if(delta_h_ref<-2) for(i=0; i<32; i++) level_corr[i]-=delta_corr[i]>>1;
curr_l_temp=0;
volt_h_temp=0;
high_ab=0;
short_curr=0;
sine_pol=0;
}
break;

42
 }
}

#separate
void sine_pwm_stop(void) // Stop mode;
{
set_pwm1_duty((sine_wave[index]+level_corr[index])>>1); // negative stop sine
half wave;
output_low(PIN_C1); // A=0;
output_low(PIN_C0); // Z=0;
output_low(PIN_B1);
set_adc_channel(ab_chan);
delay_us(10);
read_adc(ADC_START_ONLY);
delay_us(20);
volt_b=read_adc(ADC_READ_ONLY);
if(volt_b>=ab_max) {
high_ab++;
if(high_ab>4) break;
}
else high_ab=0;
output_high(PIN_C3);
set_adc_channel(i_chan);
delay_us(10);
read_adc(ADC_START_ONLY);
delay_us(20);
curr_l=read_adc(ADC_READ_ONLY);
if(curr_l<=short_curr_l) {
short_curr++;
if(short_curr>4) break;
}
else {
short_curr=0;
if (curr_l<curr_l_max){
over_curr_delay++;
//shape_corr[index+1]-=delta_i[index+1];
}
else over_curr_delay=0;
}
}

#separate
void sine_pwm_stdby(void) // Standby mode;
{

43
switch (stdby_mode) {
case 0:
sine_pwm_start();
if(index==31) {
high_ab=0;
short_curr=0;
stdby_mode++;
}
break;
case 1: // negative sine half wave;
pwm_neg=sine_wave[index] + level_corr[index];
if(pwm_neg>pwm_max) pwm_neg=pwm_max;
//if(pwm_neg<0) pwm_neg=0;
set_pwm1_duty(pwm_neg);
output_low(PIN_C1); // A=0;
output_low(PIN_C0); // Z=0;
output_low(PIN_B1);
set_adc_channel(v_chan);
delay_us(10);
read_adc(ADC_START_ONLY);
delay_us(20);
volt_l=read_adc(ADC_READ_ONLY);
volt_l_temp+=volt_l;
set_adc_channel(ab_chan);
delay_us(10);
read_adc(ADC_START_ONLY);
delay_us(20);
volt_a=read_adc(ADC_READ_ONLY);
if(volt_b>=ab_max) {
high_ab++;
if(high_ab>4) break;
}
else high_ab=0;
set_adc_channel(i_chan);
delay_us(10);
read_adc(ADC_START_ONLY);
delay_us(20);
curr_l=read_adc(ADC_READ_ONLY);
if(curr_l<=short_curr) {
short_curr++;
if(short_curr>4) break;
}
else {
short_curr=0;
if (curr_l<curr_l_max){
over_curr_delay++;

44
 //shape_corr[index+1]-=delta_i[index+1];
}
else over_curr_delay=0;
}
output_low(PIN_C3);
set_adc_channel(i_chan);
delay_us(10);
read_adc(ADC_START_ONLY);
delay_us(20);
curr_h=read_adc(ADC_READ_ONLY);
curr_h_temp+=curr_h;
if(index==31) {
curr_h_avg=curr_h_temp>>5;
if(curr_h_avg>=stdby_i_h) stdby=0;
volt_l_avg=volt_l_temp>>5;
delta_l_ref=volt_l_avg-(volt_ref_const_l-volt_ref_delta);
if(delta_l_ref>2) for(i=0; i<32; i++) level_corr[i]+=delta_corr[i]>>1;
if(delta_l_ref<-2) for(i=0; i<32; i++) level_corr[i]-=delta_corr[i]>>1;
curr_h_temp=0;
volt_l_temp=0;
high_ab=0;
short_curr=0;
stdby_mode++;
}
break;
case 2: // positive sine half wave;
pwm_pos=sine_wave[index] + level_corr[index];
if(pwm_pos>pwm_max) pwm_pos=pwm_max;
//if(pwm_pos<0) pwm_pos=0;
set_pwm1_duty(pwm_pos);
output_high(PIN_C1); // A=1;
output_low(PIN_C0); // Z=0;
output_high(PIN_B1);
set_adc_channel(v_chan);
delay_us(10);
read_adc(ADC_START_ONLY);
delay_us(20);
volt_h=read_adc(ADC_READ_ONLY);
volt_h_temp+=volt_h;
set_adc_channel(ab_chan);
delay_us(10);
read_adc(ADC_START_ONLY);
delay_us(20);
volt_b=read_adc(ADC_READ_ONLY);
if(volt_a>=ab_max) {
high_ab++;

45
 if(high_ab>4) break;
}
else high_ab=0;
output_low(PIN_C3);
set_adc_channel(i_chan);
delay_us(10);
read_adc(ADC_START_ONLY);
delay_us(20);
curr_h=read_adc(ADC_READ_ONLY);
if(curr_h>=short_curr_h) {
short_curr++;
if(short_curr>4) break;
}
else {
short_curr=0;
if(curr_h>curr_h_max) {
over_curr_delay++;
//shape_corr[index+1]-=delta_i[index+1];
}
else over_curr_delay=0;
}
output_high(PIN_C3);
set_adc_channel(i_chan);
delay_us(10);
read_adc(ADC_START_ONLY);
delay_us(20);
curr_l=read_adc(ADC_READ_ONLY);
curr_l_temp+=curr_l;
if(index==31) {
curr_l_avg=curr_l_temp>>5;
if((curr_l_avg<=stdby_i_l)) stdby=0;
volt_h_avg=volt_h_temp>>5;
delta_h_ref=(volt_ref_const_h+volt_ref_delta)-volt_h_avg;
if(delta_h_ref>2) for(i=0; i<32; i++) level_corr[i]+=delta_corr[i]>>1;
else if(delta_h_ref<-2) for(i=0; i<32; i++) level_corr[i]-=delta_corr[i]>>1;
curr_l_temp=0;
volt_h_temp=0;
high_ab=0;
short_curr=0;
stdby_mode++;
}
break;
case 3:
sine_pwm_stop();
if(index==31) {
high_ab=0;

46
 short_curr=0;
stdby_mode=0;
inv_mode++;
}
break;
}
}

#int_timer0
void sine_pwm(void)
{
restart_wdt();
clear_interrupt(int_timer0);
set_timer0(60);
if((!low_acc)&&(!high_acc)&&(!inv_off)) { // check acc value and
inverter state;
switch (inv_mode) { // check inverter mode;
case 0: // start mode;
sine_pwm_start();
if(index==31) {
high_ab=0;
short_curr=0;
sine_pol=0;
inv_mode++;
}
break;
case 1: // normal mode;
if((!high_t_stop)&&(!low_curr)&&(!low_acc_delay)) {
output_high(PIN_B4); // Green LED-ON;
output_low(PIN_B5); // Red LED-OFF;
}
sine_pwm_norm();
if(index==31) {
if((low_curr_l)&&(low_curr_h)) { // check for low current;
low_curr=1;
stdby_go_delay++;
if((!low_acc_delay)&&(!high_t_stop)) {
if(stdby_go_blink>30) {
output_high(PIN_B4); // Blink Green&Red LEDs;
output_high(PIN_B5);
}
else {
output_low(PIN_B4);
output_low(PIN_B5);
}

47
 if(!stdby_go_blink) stdby_go_blink=60;
else stdby_go_blink--;
}
if((stdby_go_delay>600)&&(!sine_pol)) {
stdby=1;
stdby_go_delay=0;
stdby_go_blink=60;
low_curr_l=0;
low_curr_h=0;
low_curr=0;
inv_mode++;
output_low(PIN_B4);
output_low(PIN_B5);
}
}
else {
low_curr=0;
stdby_go_delay=0;
stdby_go_blink=60;
}
}
break;
case 2: // stop mode;
sine_pwm_stop();
if(index==31) {
high_ab=0;
short_curr=0;
inv_mode=4;
}
break;
case 3: // standby mode;
sine_pwm_stdby();
stdby_delay--;
break;
case 4: // idle mode;
set_pwm1_duty(0); // M=0;
if((!high_t_stop)&&(!low_curr)&&(!low_acc_delay)) {
if(stdby_delay>1023) output_high(PIN_B4); // Blink Green LED;
else output_low(PIN_B4);
}
if(!stdby_delay) {
stdby_delay=2047;
if(stdby) inv_mode=3;
else inv_mode=0;
}
else stdby_delay--;

48
 break;
}
if(index==15) {
set_adc_channel(acc_chan);
delay_us(10);
read_adc(ADC_START_ONLY);
delay_us(20);
acc_v=read_adc(ADC_READ_ONLY);
acc_v_temp+=acc_v;
acc_avg_counter++;
if(acc_avg_counter==32) {
acc_avg_counter=0;
acc_v_avg=acc_v_temp>>5;
if(acc_v_avg<=acc_min_l) {
low_acc_delay++;
if(!high_t_stop) {
output_low(PIN_B4);
output_high(PIN_B5);
}
if(low_acc_delay==16) {
low_acc=1;
low_acc_delay=0;
}
}
else {
if(acc_v_avg>=acc_max_h) high_acc=1;
low_acc_delay=0;
}
acc_v_temp=0;
acc_v_avg=0;
}
output_low(PIN_C3); // check vref value;
set_adc_channel(stdby_chan);
delay_us(10);
read_adc(ADC_START_ONLY);
delay_us(20);
volt_ref=read_adc(ADC_READ_ONLY);
volt_ref_temp+=volt_ref;
volt_ref_counter++;
if(volt_ref_counter==32) {
volt_ref_avg=volt_ref_temp>>5;
volt_ref_delta=volt_ref_avg-30;
volt_ref_counter=0;
volt_ref_temp=0;
}
}

49
 if(index==31) {
if(over_curr_delay>1600) over_curr=1;
if(!input(PIN_C4)) {
high_t_delay++;
output_high(PIN_C5);
if((high_t_delay>255)&&(high_t_delay<1024)) {
high_t_stop=1;
output_low(PIN_B4);
if(high_t_blink>45) output_high(PIN_B5); // Blink Red LED;
else output_low(PIN_B5);
if(!high_t_blink) high_t_blink=90;
else high_t_blink--;
}
else if(high_t_delay>1023) high_t_stop++;
}
else {
high_t_delay=0;
high_t_stop=0;
high_t_blink=90;
output_low(PIN_C5);
}
output_high(PIN_C3); // check stdby current value;
set_adc_channel(stdby_chan);
delay_us(10);
read_adc(ADC_START_ONLY);
delay_us(20);
stdby_i=read_adc(ADC_READ_ONLY);
stdby_i_temp+=stdby_i;
stdby_i_avg_counter++;
if(stdby_i_avg_counter==32) {
stdby_i=stdby_i_temp>>5;
if(stdby_i>=stdby_max) inv_on=1;
else inv_on=0;
if(stdby_i<=stdby_min) inv_off=1;
stdby_i_h=(stdby_i>>1)+128;
//if(stdby_i_h>stdby_i_h_max) stdby_i_h=stdby_i_h_max;
//else if(stdby_i_h<stdby_i_h_min) stdby_i_h=stdby_i_h_min;
stdby_i_l=255-stdby_i_h;
stdby_i_avg_counter=0;
stdby_i_temp=0;
}
}
index++;
if(index>31) index=0;
}
else { // acc low mode;

50
set_pwm1_duty(0); // M=0;
output_high(PIN_C0); // Z=1;
output_low(PIN_B4); // Green LED-OFF;
if(!inv_off) output_high(PIN_B5); // Red LED-ON;
inv_mode=0;
index=0;
short_curr=0;
over_curr=0;
over_curr_delay=0;
high_ab=0;
high_t_delay=0;
high_t_stop=0;
stdby=0;
pwm_pos=0;
pwm_neg=0;
delta_h_v=0;
delta_l_v=0;
//delta_h_ref_v=0;
//delta_l_ref_v=0;
//diff_h_v=0;
//diff_l_v=0;
delta_h_ref=0;
delta_l_ref=0;
//delta_h_ref_adj=0;
//delta_l_ref_adj=0;
low_curr_h=0;
low_curr_l=0;
curr_h_temp=0;
curr_h_avg=0;
curr_l_temp=0;
curr_l_avg=0;
low_curr=0;
volt_h_temp=0;
volt_h_avg=0;
volt_l_temp=0;
volt_l_avg=0;
volt_ref_temp=0;
volt_ref_avg=0;
volt_ref_delta=0;
volt_ref_counter=0;
volt_h_avg_counter=0;
volt_l_avg_counter=0;
//volt_l_avg_counter=0;
stdby_i_temp=0;
//stdby_i_avg_counter=0;
stdby_go_delay=0;

51
stdby_delay=2047;
high_t_blink=90;
low_acc_delay=0;
stdby_go_blink=60;
//level=0;
//level_corr=0;
//level_l_corr=0;
for(i=0; i<32; i++) {
shape_corr[i]=0;
//shape_l_corr[i]=0;
level_corr[i]=0;
//level_adj[i]=0;
//shape_h_corr_temp[i]=0;
//shape_l_corr_temp[i]=0;
}
output_high(PIN_C3); // check stdby current value;
set_adc_channel(stdby_chan);
delay_us(10);
read_adc(ADC_START_ONLY);
delay_us(20);
stdby_i=read_adc(ADC_READ_ONLY);
stdby_i_temp+=stdby_i;
stdby_i_avg_counter++;
if(stdby_i_avg_counter==32) {
stdby_i=stdby_i_temp>>5;
if(stdby_i>stdby_min) inv_off=0;
//else inv_off=0;
stdby_i_h=(stdby_i>>1)+128;
//if(stdby_i_h>stdby_i_h_max) stdby_i_h=stdby_i_h_max;
//else if(stdby_i_h<stdby_i_h_min) stdby_i_h=stdby_i_h_min;
stdby_i_l=255-stdby_i_h;
stdby_i_avg_counter=0;
stdby_i_temp=0;
}
set_adc_channel(acc_chan);
delay_us(10);
read_adc(ADC_START_ONLY);
delay_us(20);
acc_v=read_adc(ADC_READ_ONLY);
acc_v_temp+=acc_v;
acc_avg_counter++;
if(acc_avg_counter==32) {
acc_avg_counter=0;
acc_v_avg=acc_v_temp>>5;
if(acc_v_avg<=acc_max_l) high_acc=0;
if(acc_v_avg>=acc_min_h) low_acc=0;

52
 acc_v_temp=0;
acc_v_avg=0;
}
if(input(PIN_C4)) output_low(PIN_C5);
}
}

void main()
{
set_tris_b(0xCD);
set_tris_c(0x90);
output_high(PIN_C0); // Z=1;
//output_high(PIN_B4); // test LED's;
//output_low(PIN_B5);
//delay_ms(1000);
output_low(PIN_B4);
//output_high(PIN_B5);
//delay_ms(1000);
output_low(PIN_B5);
index=0;
inv_mode=0; // init to normal start mode;
inv_on=0;
inv_off=0;
stdby_mode=0;
short_curr=0;
over_curr=0;
over_curr_delay=0;
high_ab=0;
high_t_delay=0;
high_t_stop=0;
low_acc=0;
high_acc=0;
acc_v_temp=0;
acc_avg_counter=0;
acc_v_avg=0;
stdby=0;
pwm_pos=0;
pwm_neg=0;
delta_h_v=0;
delta_l_v=0;
//delta_h_ref_v=0;
//delta_l_ref_v=0;
//diff_h_v=0;
//diff_l_v=0;
delta_h_ref=0;

53
delta_l_ref=0;
//delta_h_ref_corr=0;
//delta_l_ref_corr=0;
low_curr_h=0;
low_curr_l=0;
low_curr=0;
curr_h_temp=0;
curr_h_avg=0;
curr_l_temp=0;
curr_l_avg=0;
low_curr=0;
volt_h_temp=0;
volt_h_avg=0;
volt_l_temp=0;
volt_l_avg=0;
volt_ref_temp=0;
volt_ref_avg=0;
volt_ref_delta=0;
volt_ref_counter=0;
volt_h_avg_counter=0;
volt_l_avg_counter=0;
//volt_l_avg_counter=0;
stdby_i_temp=0;
stdby_i_avg_counter=0;
stdby_go_delay=0;
stdby_delay=2047;
high_t_blink=90;
low_acc_delay=0;
stdby_go_blink=60;
//level=0;
//level_corr=0;
//level_l_corr=0;
for(i=0; i<32; i++) {
shape_corr[i]=0;
//shape_l_corr[i]=0;
level_corr[i]=0;
//shape_h_corr_temp[i]=0;
//shape_l_corr_temp[i]=0;
//level_adj[i]=0;
}
setup_adc_ports(ALL_ANALOG); // init the ADC;
setup_adc(ADC_CLOCK_DIV_32); // Tad=1.6us;
set_adc_channel(acc_chan);
delay_us(10);
for(i=0; i<32; i++) {
acc_v=read_adc();

54
 acc_v_temp+=acc_v;
if(i==31) {
acc_v_avg=acc_v_temp>>5;
if(acc_v_avg<=acc_min_l) low_acc=1;
if(acc_v_avg>=acc_max_h) high_acc=1;
acc_v_temp=0;
acc_v_avg=0;
}
}

output_high(PIN_C3); // check stdby current value;

set_adc_channel(stdby_chan);
delay_us(10);
for(i=0; i<32; i++) {
stdby_i=read_adc();
stdby_i_temp+=stdby_i;
if(i==31) {
stdby_i=stdby_i_temp>>5;
if(stdby_i<=stdby_min) inv_off=1;
else if(stdby_i>=stdby_max) inv_on=1;
stdby_i_h=(stdby_i>>1)+128;
stdby_i_l=255-stdby_i_h;
stdby_i_temp=0;
}
}

output_low(PIN_C3);
set_adc_channel(stdby_chan); // check vref value;
delay_us(10);
for(i=0; i<32; i++) {
volt_ref=read_adc();
volt_ref_temp+=volt_ref;
if(i==31) {
volt_ref_avg=volt_ref_temp>>5;
volt_ref_delta=volt_ref_avg-29;
volt_ref_temp=0;
}
}

setup_timer_2(T2_DIV_BY_1, 255, 1); // Init the PWM;

setup_ccp1(CCP_PWM);
set_pwm1_duty(0);
//setup_ccp2(CCP_PWM);

55
//set_pwm2_duty(0);
setup_wdt(WDT_18MS);
set_timer0(60);
setup_timer_0(RTCC_INTERNAL|RTCC_DIV_8); // Init the TIMER0;
enable_interrupts(INT_TIMER0);
enable_interrupts(GLOBAL);
while(TRUE) {
restart_wdt();
if((short_curr)||(high_ab)||(over_curr)||(high_t_stop>1)) { // stop and wait for 60 sec;
set_pwm1_duty(0); // M=0;
output_high(PIN_C0); // Z=1;
disable_interrupts(GLOBAL);
output_low(PIN_B4);
output_low(PIN_B5);
short_curr=0;
over_curr=0;
over_curr_delay=0;
high_ab=0;
high_t_stop=0;
high_t_delay=0;
low_acc=0;
high_acc=0;
acc_avg_counter=0;
acc_v_temp=0;
acc_v_avg=0;
low_curr_h=0;
low_curr_l=0;
index=0;
inv_mode=0;
inv_on=0;
inv_off=0;
stdby_mode=0;
stdby=0;
pwm_pos=0;
pwm_neg=0;
delta_h_v=0;
delta_l_v=0;
//delta_h_ref_v=0;
//delta_l_ref_v=0;
//diff_h_v=0;
//diff_l_v=0;
delta_h_ref=0;
delta_l_ref=0;
//delta_h_ref_corr=0;
//delta_l_ref_corr=0;
//level=0;

56
 //level_corr=0;
//level_l_corr=0;
for(i=0; i<32; i++) {
shape_corr[i]=0;
//shape_l_corr[i]=0;
level_corr[i]=0;
//level_adj[i]=0;
//shape_h_corr_temp[i]=0;
//shape_l_corr_temp[i]=0;
}
curr_h_temp=0;
curr_h_avg=0;
curr_l_temp=0;
curr_l_avg=0;
low_curr=0;
volt_h_temp=0;
volt_h_avg=0;
volt_l_temp=0;
volt_l_avg=0;
volt_ref_temp=0;
volt_ref_avg=0;
volt_ref_delta=0;
volt_ref_counter=0;
volt_h_avg_counter=0;
volt_l_avg_counter=0;
//volt_l_avg_counter=0;
stdby_i_temp=0;
stdby_i_avg_counter=0;
stdby_go_delay=0;
stdby_delay=2047;
high_t_blink=90;
low_acc_delay=0;
stdby_go_blink=60;
delay_ms(30000);
if(input(PIN_C4)) output_low(PIN_C5);
clear_interrupt(int_timer0);
set_timer0(60);
enable_interrupts(GLOBAL);
}
}
}

57
3.3 Software Flowchart:

58
Chapter 4
System Operation
4.1 Introduction
Design is a sine-wave stand-alone PWM voltage-source inverter (Not UPS) with PIC16F876A
MCU, with parameters:

Uin=12V DC
Uo=230V AC
F= 50Hz
P=500W

Inverter have an integrated input under/over voltage protection, output voltage regulation, output
current protection and overtemperature protection.

Output voltage is a pure sine-wave, generated with built-in PWM module of PIC MCU, with
frequency 20Khz.

Carrier frequency is 20kHz (generated with buit-in PWM of the PIC MCU) and each half
period (10ms) we have 32 changes in the PWM signal, this makes 64 changes in whole period
(20ms). But we generated only the half period of the sine-wave and with the help of the direction
signal we can get the whole period of the sine-wave in the output of the inverter.

Sinewave Lookup Table calculation:

Ki = PWMmax*sin(i*180/n),

where:
PWMmax=0-1023, (PWMmax=831)
i = 0,1,2,...,n

e.g const long sine_wave[32] =

{81,162,241,318,392,462,527,588,642,691,733,768,795,
815,827,831,827,815,795,768,733,691,642,588,527,462,
392,318,241,162,81,0};

In this inverter we have a full-bridge power circuits with 4 transistors (paralleled-8

transistors), Q1, Q3, Q5 and Q7. Two of transistors works with low frequency - 50Hz (Q5 and

59
Q7) depending on the state of the A/B (direction) signal (RC1). Other two transistors (Q1 and
Q3) works with high-frequency (20kHz) of the sinewave PWM signal.

Efficiency of this inverter is around 80-85% and depends on the transformer design,
MOSFET Quality (lower Rds, less power losses) and the Output Power (or Input Current).
Higher input current through the MOSFETs leads to more power dissipation on transistors.

4.2 LED status:

1. Green -> Normal operation
2. Green Blinking -> Standby Mode (No load operation)
3. Red -> Low baterry (<10.8V)
4. Red Blinking -> Over Temperature of Power Transistors
5. Orange (Green+Red) Blinking-> Before going in Stanby Mode (for 5 sec).

The green LED (LED1) is connected to pin25 (RB4) and red LED - to pin26 (RB5). When
inverter turned ON without load, after 5 sec inverter stops and going in standby mode. In this
mode inverter starts only for short time for detecting the existence of the load. Time interval
between this short start pulses is 1 sec. Before this mode begin to blink Green LED (for 5 sec).
And after going in standby mode blinking Green and Red LEDs together (Use a single two color
LED - Green and Red) and resulting color is orange.

4.3 Transformer:
For the output power transformer we use a low frequency (50Hz) conventional transformer,
but decision is yours. Ferrite core transformers are more suitable in other type of inverters with
double conversion stages,first stage for boosting the input 12V (or 24V) DC voltage to 350-400V
dc ( with HF PWM and ferrite transformer ) and second for inverting this voltage to 230 Vac
(without transformer ).

4.4 Feedbacks:
There are many feedback input signal needed for proper work of the inverter:

From input DC voltage, temperature sensor (Rt, NTC-47k), output ac current, output ac voltage
(230V), a/b signals (over two low-side power transistor - Q5 and Q7), signals from two POT's
(R22 and RT1) and etc. Better look at schematics of the inverter for signals connected to PIC

60
MCU.
When starting the inverter for the first time (before connectin the voltage and current
feedback signals to PIC MCU) you must fit (adjust) the polarity of the output signals (I and V) to
the polarity of the direction signal A/B (LF, 50Hz signal) from PIC MCU. Signals must be
exactly like this: positive output voltage (and high current - curr-h) must be at the same time
when signal A/B =5V (log.1) and negative when A/B=0V (log.0).

If the voltage (and current) signals are contrariwise you must reverse only input or output
pins of the power transformer. For contrariwise current signal you must reverse the pins (inpu or
output) of the current transformer. And then you can connect this feedback signals to PIC MCU.
b/a signal (pin2 - RA0/AN0) must include only a low levels of the separeted 'a' and 'b' signals
(pin2 and pin1 - U10). If b/a signal include only a high-levels of signals 'a' and 'b', then you must
change a connection places of this two signals to pin1 and pin2 of the U10 (a<->b and b<->a).

Input current is a DC and can be measured only with current sensing resistor (nonisolated) and
Hall sensor (Isolated). This method is a prefarable only for input current measurement (for
MPPT in Photovoltaic converters) and for input current protection.
Output current of the inverters is a AC an can be measured with current sensing resistor, Hall
sensor and Current transformer. This method is a preferable when implementing an output
current control and regulation.

Current transformers secondary side has a two load resistors: R8=100 for high range and
R18=1.5k for low range. They are in the feedbacks of two OPAMPs (U1A and U1C).

These two OP AMPs (U1A and U1C) forms two active current to voltage converters
with two different current to voltage gain ratios.
For more info just look here:

http://en.wikibooks.org/wiki/Circuit_Idea/Op-amp_Inverting_Current-to-Voltage_Converter

4.5 Other components are :

TLP250 are working from 10-35V and if you supplying them directly from input DC voltage
(before LM317) they can work in overall input voltage range (10.8-16Vdc).

"bootstrap"supply, components D6-C17 (for U3) and D7-C18 (for U3) in inverter schematics.
And it is a specially designed only for high-side drivers. For more information see below link

http://www.intersil.com/data/fn/fn9087.pdf

61
D4 is for high voltage battery protection, and D5 is for reverse battery protection of the V_BAT
analog input of PIC MCU (RA3).

4.6 UPS Conversion:

This requires additional circuits as:
1. Zero-cross detection for grid synchronization. (Figure 4.1)
2. Relay(s) for switching the load to grid or to UPS output. (Figure 4.2)
3. Battery charger - embedded in UPS or separated.

Figure 4.1

Figure 4.2

62
4.7 Output Wave Form:
The output of the circuit is shown below

Figure 4.3: Output waveform

4.8 Problem Encounter:

All feedbacks must be connected to circuit for proper function of inverter but unfortunately we
are unable to get Current Transformer from market, so our output is damping out but still pure
sine wave and shown in Figure 4.4

63
 Figure 4.4: Damped Output

4.9 PCB and Assembly:

1) PCB
i) Top Layer
ii) Bottom Layer
iii) Top Overlay
2) Assembly
i) Top Assembly
ii) Bottom Assembly

All figures as following

64
Top Layer:

65
Bottom Layer:

66
Top Overlay:

67
Top Assembly:

Bottom Assembly:

68
 Recommendations and Refrences
Recommendations:
For Proper working of Circuit following parameters must be ensured:

V_OUT = 2.5V +/- max 1.5V (min 1V, max 4V, middle point 2.5V, sine wave)
curr_h = 2.5V +/- max 1V (min 1.5V, max 3.5V, middle point 2.5V, sine wave)
curr_l = 2.5 V +/- max 0.25V (middle point 2.5V, sine wave)
volt = 4.45 - 4.82 Vdc
Stdby = 0 - 5 Vdc
b/a - depending on MOSFET Rds and output current magnitude, approx. 1 - 2V max.
Active level of OE signal is low level (Log. "0").

A/B direction signal is a square wave signal with frequency 50Hz and 50% duty cycle.
For correct work of the inverter all feedback signals must be connected to the PIC MCU,
with normal working levels.

Refrences:
1) UNINTERRUPTIBLE POWER SUPPLIES AND ACTIVE FILTERS
By Ali Emadi, Abdolhosein Nasiri

2) Uninterruptible power supplies

By WilliamKnight

3) Uninterruptible power systems (UPS)

By IEC
4) IEEE 446
Orange Book, Emergency and Standby Power Systems for Industrial and Commercial
1) Applications, (1996) (cited in paragraph 2-3, Table 3-1)
5) IEEE 450
Recommended Practice for Maintenance, Testing, and Replacement of Vented Lead-Acid
Batteries for Stationary Applications, (1995) [cited in paragraphs 3-2b(2), 5-2c, 5-2c(1), 5-
2c(2)(k), 5-2f(4), 5-2f(5)(6)]

6) ANSI/IEEE 519
Recommended Practices and Requirements for Harmonic Control in Electrical Power Systems,
(1992) (cited in table 2-2)

69
 Appendix A
Controller:
 PIC16F87XA:

High-Performance RISC CPU:

o Only 35 single-word instructions to learn
o All single-cycle instructions except for program branches, which are two-cycle
o Operating speed: DC – 20 MHz clock input
- DC – 200 ns instruction cycle
o Up to 8K x 14 words of Flash Program Memory,
o Up to 368 x 8 bytes of Data Memory (RAM),
o Up to 256 x 8 bytes of EEPROM Data Memory
o Pinout compatible to other 28-pin or 40/44-pin
o PIC16CXXX and PIC16FXXX microcontrollers

Analog Features:
o 10-bit, up to 8-channel Analog-to-Digital Converter (A/D)
o Brown-out Reset (BOR)
o Analog Comparator module with:
- Two analog comparators
- Programmable on-chip voltage reference
- (VREF) module
- Programmable input multiplexing from device
- inputs and internal voltage reference
- Comparator outputs are externally accessible

Figurer A: Pin configuration

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Special Microcontroller Features:

o 100,000 erase/write cycle Enhanced Flash program memory typical

o 1,000,000 erase/write cycle Data EEPROM memory typical
o Data EEPROM Retention > 40 years
o Self-reprogrammable under software control
o In-Circuit Serial Programming™ (ICSP™) via two pins
o Single-supply 5V In-Circuit Serial Programming
o Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation
o Programmable code protection
o Power saving Sleep mode
o Selectable oscillator options
o In-Circuit Debug (ICD) via two pins

71
 Appendix B
ANALOG MULTIPLEXER/DEMULTIPLEXER:
 HCF4053B

DESCRIPTION:

The HCF4053B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor

technology available in DIP and SOP packages.The HCF4053B analog multiplexer
demultiplexer is a digitally controlled analog switch having low ON impedance and very low
OFF leakage current. This multiplexer circuit dissipate extremely low quiescent power over the
full VDD - VSS and VDD - VEE supply voltage range, independent of the logic state of the
control signals.

When a logic "1" is present at the inhibit input terminal all channel are off. This device is a triple
2-channel multiplexer having three separate digital control inputs, A, B, and C, and an inhibit
input. Each control input selects one of a pair of channels which are connected in a single pole
double-throw configuration.

Figure B1: Pin Diagram

Electrical Characteristics:

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ALTERNATE:

 MC14053B

Figure B2: Pin Configuration

73
 Appendix C

Quad Operational Amplifiers:

 LM324
Unique Characteristics
o In the linear mode the input common-mode voltage range includes ground and the output
voltage can also swing to ground, even though operated from only a single power supply
voltage
o The unity gain cross frequency is temperature compensated
o The input bias current is also temperature compensated

Advantages
o Eliminates need for dual supplies
o Four internally compensated op amps in a single package
o Allows directly sensing near GND and VOUT also goes to GND
o Compatible with all forms of logic
o Power drain suitable for battery operation

Features
o Internally frequency compensated for unity gain
o Large DC voltage gain 100 dB
o Wide bandwidth (unity gain) 1 MHz (temperature compensated)
o Wide power supply range:
o Single supply 3V to 32V or dual supplies ±1.5V to ±16V
o Very low supply current drain (700 μA)—essentially independent of supply voltage
o Low input biasing current 45 nA (temperature compensated)
o Low input offset voltage 2 mV and offset current: 5 nA Input common-mode voltage
range includes ground
o Differential input voltage range equal to the power supply voltage
o Large output voltage swing 0V to V+ − 1.5V

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 Figure C1: Pin Diagram

ALTERNATE:
i. LM124
ii. LM224
iii. LM2902

75
 Appendix D
Dual Comparator:
 LM393

General Description
The LM193 series consists of two independent precision voltage comparators with an offset
voltage specification aslow as 2.0 mV max for two comparators which were designed
specifically to operate from a single power supply over a wide range of voltages. Operation from
split power supplies is also possible and the low power supply current drain is independent of the
magnitude of the power supply voltage. These comparators also have a unique characteristic in
that the input common-mode voltage range includes ground, even though operated from a single
power supply voltage.

Advantages
High precision comparators
Reduced VOS drift over temperature
Eliminates need for dual supplies
Allows sensing near ground
Compatible with all forms of logic
Power drain suitable for battery operation

Figure D1:Pin Configuration

76
ALTERNATE:

i. LM193
ii. LM293
iii. LM2903

77
 Appendix E
Data Line Selector:
 SN74HC257

These devices are designed to multiplex signals from 4-bit data sources to 4-output data lines in
bus-organized systems. The 3-state outputs do not load the data lines when the output-enable (G)
input is at a high logic level. To ensure the high-impedance state during power up or power
down, G should be tied to VCC through a pullup resistor; the minimum value of the resistor is
determined by the current-sinking capability of the driver.

Figure E1: Pin Configuration

Table E1

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Figure E2: Logic Diagram

79
 Appendix F
Gate Drive:

 TLP250

The TOSHIBA TLP250 consists of a GaAlAs light emitting diode and a integrated
photodetector.
This unit is 8−lead DIP package.
TLP250 is suitable for gate driving circuit of IGBT or power MOS FET.
__ Input threshold current: IF=5mA(max.)
__ Supply current (ICC): 11mA(max.)
__ Supply voltage (VCC): 10−35V
__ Output current (IO): ±1.5A (max.)
__ Switching time (tpLH/tpHL): 1.5μs(max.)
__ Isolation voltage: 2500Vrms(min.)
__ UL recognized: UL1577, file No.E67349
__ Option (D4) type
VDE approved: DIN VDE0884/06.92,certificate No.76823
Maximum operating insulation voltage: 630VPK
Highest permissible over voltage: 4000VPK

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Figure F1:Pin Configuration

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82