Chapter 3.

3 – Computer Architecture and Fetch-Execute Cycle

What is Von Neumann Architecture?

1. Both program instructions and data are stored together in the same memory

2. It uses a single processor

3. It uses linear sequence of fetch-decode-execute cycles

What are the special registers required for implementing the Von Neumann architecture?

1. PC – Program counter
2. CIR – Current instruction register
3. MAR – Memory address register
4. MDR – Memory data register
5. Accumulator

What are the functions of the special registers?

1. Program counter – Holds the memory address of the next instruction to be processed. It is
altered to allow for Jump instructions.

2. Current instruction register – Holds the instruction that is currently being executed. CIR splits
the binary code into operation code and address

3. Memory address register – Contents of PC is copied into MAR. Holds the memory address of
the next program instruction to be processed.
Operand part of the instruction is copied into MAR from CIR. Holds the address of the data
needed to complete the processing of that cycle.

4. Memory data register – Holds a program instruction or a piece of data copied from the
memory. MDR acts as the buffer between the memory and the central processing unit.

5. Accumulator – Temporarily holds the results of calculations.

The processor divides into two areas called central processing unit and the main memory. Main
memory is also known as the memory unit. The central processing unit contains the arithmetic
and logic unit and the control unit.
 2

Arithmetic and logic unit carries out the arithmetic operations (addition, subtraction, division and
multiplication) and logic operations (comparison of two pieces of data to determine whether one
is greater than, smaller than or equal to the other).

Control unit controls the timing and routing of signals inside the processor. It also decodes the
instruction which is held in the current instruction register.

Fetch – Decode – Execute Cycle

This is the set of repetitive tasks always being carried out by the processor when it is switched on.

Fetch phase

Execute phase Decode phase

What is “fetch”?

This is fetching a machine code instruction from the memory

This is “decode”?

This is the process of analyzing a machine code instruction by the control unit to determine its
function.

What is “execute”?

This is carrying out of an instruction

Format of assembly code

Assembly code statements have the following general format

op code operand

Some examples of op codes

ADD, SUB, MUL, DIV, JMP, LDA

 3

What is operand?

The operand is the data that the op code of an assembly language instruction will operate on.
Assembly language instructions have the format where op code is followed by operand.

Example: LDA 100 (100 is the operand on which the operator LDA will operate on)

How the operand will be treated as, depends on the addressing mode.

Following diagram shows the architecture of the processor.

A Segment of a Job in the

Main Memory

100 ADD 200 Area of the

main memory
Central Processing Unit ADD 210
110 containing
assembly
JMP 160 instructions
120

ALU
Accumulator ADD 220
PC 160
Control Unit

CIR
MDR

200 210 Area of the

MAR main memory
220 containing
210
data
IR 220 2500

2500 150

160
2501

180
2502
 4

What is addressing mode?

1. Addressing mode is the method that a machine language instruction uses to tell the processor
the address of the data.

2. Addressing mode forms part of the instruction set architecture of the processor.

3. The addressing mode specifies how to calculate the effective memory address of an operand by
using information held in registers and/or constants contained within a machine instruction.

What is immediate addressing mode?

Under immediate addressing mode, operand is treated as the data itself.

Example: ADD 200

This instruction adds the value 200 to the value that already exists in the accumulator

What is direct addressing mode?

Under direct addressing mode operand is treated as the address of the data.

Example: ADD 200

This instruction adds the value 210 to the value that already exists in the accumulator

What is indirect addressing mode?

Under indirect addressing mode operand is treated as the address of the address of the data.

Example: ADD 200

This instruction adds the value 220 to the value that already exists in the accumulator

What is indexed addressing mode?

Under indexed addressing the operand is added to the value in the indexed register to calculate
the address of the data. Here that operand is called as the base address.

Example: Add 200

Suppose that IR contains the value 20.
Therefore this instruction adds the value 2500 to the value that already exist in the
Accumulator

What is the purpose of using the indirect addressing mode?

This is used to access the areas of memory, which are not otherwise accessible using the space
available for the address in the instruction code.
 5

Example to explain the purpose of using indirect addressing mode

If the operand is only 1 byte in size, the maximum address that the operand can contain is 255.

If the program needs to access the memory address 2500, it can do this by using the instruction
ADD 220 with indirect addressing mode. This is because the address 220 can be accommodated
by the one byte operand.

What is the purpose of using the indexed addressing mode?

Indexed addressing allows a set of contiguous data (array) to be accessed without altering
instruction.

Using this mode of addressing, the address of the operand can be modified by operating on the
contents of the index register.

Example to explain the purpose of using indexed addressing mode

Suppose that the current instruction is the one that is at the memory location 110 which is ADD
210.

Suppose that there is an array containing three pieces of data in the memory locations 2500, 2501
and 2502 and these data have to be added to the accumulator.

Here since the current instruction is the instruction ADD 210, this operation can be performed by
using the indexed addressing mode and setting the index register to 2290 and executing a loop
where IR will be increased by 1 in each round of the loop.

When IR is 2290 the value 150 will be added to the accumulator.

When IR is 2291 the value 160 will be added to the accumulator.

When IR is 2290 the value 180 will be added to the accumulator.

At the end of the loop the execution of the program will fall back to the instruction at the base
address which is the memory location 110.

Steps involved in a linear sequence of fetch-execute cycle for the LDA 200 instruction

1. Value in PC is copied into MAR

2. Value in PC is incremented by 1
3. Contents in the address referred to in MAR is copied into MDR
4. Contents in MDR are copied to CIR
5. Contents in CIR are split into op code (LDA) and operand (200)
6. Operation code (LDA) is decoded as loading in accumulator
7. Load the operand in CIR (200) into MAR assuming that it is the direct addressing mode
8. Load the data containing in the address pointed to by MAR into MDR
9. Load data in MDR to Accumulator replacing its current value
10. Registers are reset and made ready to restart the next cycle
 6

Steps involved in a linear sequence of fetch-execute cycle for the ADD 200 instruction

1. Value in PC is copied into MAR

2. Value in PC is incremented by 1
3. Contents in the address referred to in MAR is copied into MDR
4. Contents in MDR is copied to CIR
5. Contents in CIR are split into op code (ADD) and operand (200)
6. Operation code (ADD) is decoded as an addition
7. Load the operand in CIR (200) into MAR assuming that it is the direct addressing mode
8. Load the data containing in the address pointed to by MAR into MDR
9. Add contents in MDR to the current value in the Accumulator
10. Registers are reset and made ready to restart the next cycle

Steps involved in an unconditional jump instruction (JUMP 300)

1. Value in PC is copied into MAR

2. Value in PC is incremented by 1
3. Contents in the address referred to in MAR is copied into MDR
4. Contents in MDR is copied to CIR
5. Contents in CIR are split into op code (JUMP) and operand (300)
6. Operation code is decoded as an unconditional jump
7. Copy the operand (300) into PC
8. Registers are reset and made ready to restart the next cycle

Increasing the speed of the fetch-execute cycle through pipelining the instructions

Processor is split into three parts. Each part handles one of the three phases of the fetch-execute
cycle. This results in the instructions being pipelined to the processor as shown in the figure given
below:

Fetch Decode Execute

Instruction 1
Instruction 2 Instruction 1
Instruction 3 Instruction 2 Instruction 1
Instruction 4 Instruction 3 Instruction 2
Instruction 5 Instruction 4 Instruction 3

The effect of pipelining is that there are three instructions being dealt with at the same time. This
reduces the execution times considerably to approximately 1/3 of the regular time.

The limitation of pipelining

Pipelining can increase the speed of the fetch-execute cycle only with the execution of a linear
program i.e. as long as there is no Jump instruction exists in the program.
 7

Suppose the instruction 2 is a jump to instruction 10. Then the instructions 3, 4 and 5 are needed
to be removed from the pipe and instruction 10 needs to be loaded into the fetch part of the pipe.
Therefore the pipe has to be cleared and restarted. The result is shown in the figure given below.

Fetch Decode Execute

Instruction 1
Instruction 2 Instruction 1
Instruction 3 Instruction 2 Instruction 1
Instruction 4 Instruction 3 Instruction 2
Instruction 10
Instruction 11 Instruction 10
Instruction 12 Instruction 11 Instruction 10

Parallel Processing

Parallel processor architecture

In this architecture many processors are used simultaneously where each processor carries out an
individual instruction through a separate fetch-execute cycle.

Examples of applications using parallel processor architecture

1. Weather forecasting where large amount of data have to be produced and the results are time
sensitive (results need to be produced within a specified time period).

Why some applications need parallel processing rather than serial processing?

1. Those applications are required to perform number of calculations

2. The results of those calculations are required immediately (means that they are time sensitive)

Things required by a computer to perform parallel processing

1. An array of processors

1. Special operating system which can support parallel processing

3. Application software which has been developed to carry out parallel processing