EEM336 Week02 Addr Modes 4pp

Machine Instructions
An individual machine code is called a

Machine Instruction
Machine Code
e.g. the machine instruction to add 1 to the

value in accumulator A is 01001100
The commands the CPU understands
Week 2: Addressing Modes
The set of all codes recognized by a

particular CPU is known as its Instruction
Set
Machine Code
Machine Instructions
A set of binary codes that are

recognised and executed directly
by a particular CPU
A typical machine instruction consists of an

operation code (op-code), which specifies
what operation the CPU is to do, plus a
number of arguments, which specify what
data the CPU is to operate on
e.g. the machine instruction to add 2 to the

value in accumulator A is 10001011 00000010
What Do/Can Machine Instructions Do?
Instructions: Computations
The arithmetic and logical operations,
normally carried out by the ALU
(Arithmetic Logic Unit)
What might this include?
We can group the instructions according to

function. The groups given here are
generally applicable to most instruction sets
(i.e. they apply to the machine code for
most types of processor)
Instructions: Data Transfer
Instructions: Flow Control
From where, to where?

load (e.g. from memory to a register)
store (e.g. from a register to memory)
move (e.g. from register to register)
add
subtract
increment
invert bits
and more
A computer program is not a lot of use

without loops, functions, etc.
We need to have machine codes to control
the flow of execution through a machine
code program
Branching, jumping to subroutines,
returning from subroutines
6
Instructions: Others
68HC11 Register Set
Youll come across other types of

instruction as the course proceeds
The bulk, however, fall into the three
categories already mentioned:
Every CPU contains a set of registers which

are available to the machine-code programmer
Youve seen two of these already:
the Program Counter (PC)
the Accumulator
Data transfer
Computations
Flow control
You need to know about these registers before

you can start writing machine-code programs
Example machine codes

(68HC11 CPU)
This is the way a programmer needs to view

the CPU
As a programmer, you dont necessarily
need to know about what weve learnt
before regarding the internals, but you need
to know whats sometimes termed the
Programmers Model of the CPU
What does this mean?

If you dont know, its
time to revise!
11
The Programmers Model
The 68HC11 CPU is the one well be

looking at in this course
The codes that follow apply to the whole
68HC11 family of microcontrollers
The CPU has the following characteristics:
an 8-bit word length
a 16-bit address space
memory-mapped I/O
10
12
68HC11 Architecture: Programmers Model

7 Accumulator A 0
15
7 Accumulator
Double accumulator D
15
Index register IX
IX
15
Index register IY
IY
15
Stack pointer
SP
15
Program counter
PC
S X H I N Z V C
Instruction: LDAA direct
A:B
mnemonic:
op-code:
operation:
increasing
addresses
CCR Condition Code Register

Carry
Overflow
Zero
Negative
I interrupt mask
Half-carry (from bit 3)
X interrupt mask
Stop disable
13
increasing
addresses
86
dd
LDAA
86 (hex)
Load accumulator A with the
8-bit value immediately
following the op-code
15
They perform the same operation, but the source is

different
We say they use different addressing modes
Customarily, the same mnemonic is used for all
operations that perform essentially the same
operation, and differ only in their addressing modes
Its the syntax (in assembly code) which
differentiates them
op code for LDAA

data to be loaded
op code for LDAA

address of data to be loaded
Why two instructions with the

same mnemonic?
Instruction: LDAA immediate

mnemonic:
op-code:
operation:
96
dd
LDAA
96 (hex)
Load accumulator A with the
contents of memory location
given by 8-bit number
following the op-code
14
16
Addressing Modes Example
Endian-ness
LDAA immediate to load the value (decimal) 30 into

accumulator A would be written:
LDAA
#30
68HC11 is a big endian microprocessor.

When we write a 16 bit in a memory
location, the first byte of memory contains
the high portion of the 16 bit number.
Big Endian Big End in First
Small Endian Small end in First
Intel 80x86, Pentium processors are the
examples of Small Endian machines.
LDAA direct to load the contents of address 30 into

accumulator A would be written:
LDAA
30
The # sign distinguishes between them
17
19
Memory Addressing
Memory consists of addressable locations. A memory
location has 2 components:
address
contents
Data transfer between CPU and memory involves

address bus and data bus
address bus lines
CPU
Machine Language Execution

How Machine Language Programs
Are Executed on the CPU?
memory
data bus lines
20
Assembly Machine Code
Machine Language Execution
Assembly language facilitates to write programs for humans.

Assembler converts assembly programs to machine code.
Each machine language instruction consists of an operation code

(opcode) and zero or more operands.
Operands are the data or the location of the data to be used in
performing the specified operation.
Often some operands are implicit in the opcode.
Each instruction occupies some number of consecutive bytes of
memory and the machine program consists of a sequence of
instructions stored consecutively in memory.
A special register called the program counter (PC) in the control
unit of the CPU contains the address of the next byte of instruction
code to be fetched.
Unless the program directs otherwise, instructions are executed in
the sequence they are stored in memory.
Machine code equivalent

starting at $C000
Assembly language
program
LDAA
$D000
ADDA
$D001
STAA
$D000
21
The Instruction Execution Cycle

68HC11 Example
Assembler
..
B6
D0
00
BB
D0
01
B7
D0
00
..
LDAA
ADDA $D001
STAA
$D000
23
Instruction Code and Operands
LOAD: copy the content of a memory location into a

register in CPU
LDAA
$D000 load the content of memory at
address $D000 into register A
instruction code
operand
instruction code
..
B6
D0
00
BB
D0
01
B7
D0
00
..
LDAA
$D000
ADDA $D001
ADD: add the content of a memory location to a register in CPU

and store the result in register.
ADDA
$D001 add the content of memory at
address $D001 to register A and
store the result in register A.
instruction code
STORE: store the content of a register into a location in memory

STAA
$D000 store the content of accumulator/
register A into memory at address
$D000.
Different instructions may need different number of

operands or sometimes none at all. In the above
program, all operands are two-byte numbers.
$D000
operand
operand
22
STAA
$D000
24
LDAA $D000
LDAA $D000 ($B6 $D0 $00)
Step 1: Assume PC=$C000. $C000 is

placed on A-bus and READ issued.
Step 2: 8-bit content at location $C000
($B6) is returned on data bus and place in
the Instruction Decode Register (IDR) in the
control unit.
Step 3: Control unit (decoder) recognizes LOAD

instruction. This instruction needs 2-byte value for
operand address.
Issues two READ cycles:
address bus-READ-$C001 data bus returns $D0
address bus-READ-$C002 data bus returns $00
At the end PC becomes $C003
Step 4: Execution of the instruction ($B6) needs

the content of location $D000. A READ is issued
with address = $D000 data bus returns $19 and
that is put into register A.
PC is incremented by 1 to become $C001

The machine instruction loaded into IDR will be
analyzed to understand what to do next in the
control unit.
CPU
IDR
Step 2: $B6 is returned

on D-bus. PC $C001
..
$B6
$D0
$00
$BB
$D0
$01
$B7
$D0
$00
..
$19
$37
..
27
LDAA $D000 ($B6 $D0 $00)
LDAA $D000 ($B6 $D0 $00)

Step 1: A-bus ($C000-READ)
25
..
Step 3: A-bus ($C001 & $C002 READ) $B6
[$C000]
[$C001]
[$C002]
[$C003]
[$C004]
[$C005]
[$C006]
[$C007]
[$C008]
CPU
IDR
[$D000]
[$D001]
MAR
$D0 & $00 is returned on D-bus

saperately and put into Memory
Address Register (MAR)
26
$D0
$00
$BB
$D0
$01
$B7
$D0
$00
..
$19
$37
..
[$C000]
[$C001]
[$C002]
[$C003]
[$C004]
[$C005]
[$C006]
[$C007]
[$C008]
[$D000]
[$D001]
28
LDAA $D000 ($B6 $D0 $00)

Step 4: A-bus ($D000 - READ)
CPU
IDR
MAR ACCA
$19 is returned on D-bus and put
into register A (Accumulator A)
..
$B6
$D0
$00
$BB
$D0
$01
$B7
$D0
$00
..
$19
$37
..
ADDA $D001 ($BB $D0 $01)
[$C000]
[$C001]
[$C002]
[$C003]
[$C004]
[$C005]
[$C006]
[$C007]
[$C008]
Step 4: Execution of the instruction needs the

content of location $D001
A READ is issued with address bus = $D001 and
data bus returns $37 (put into MDR - Memory
Data Register in the control unit).
Step 5: ALU adds the content of MDR ($37) to
ACCA ($19) so that ACCA becomes $50.
[$D000]
[$D001]
29
ADDA $D001 ($BB $D0 $01)
STAA $D001 ($B7 $D0 $01)
Step 1: PC=$C003, $C003 is placed on A-bus and

READ is issued.
Step 2: 8-bit content at location $C003=$BB is
returned on data bus and place in IDR. PC is
incremented by 1 to become $C004.
Step 3: Control unit (instruction decoder)
recognizes ADD instruction. Needs a 2-byte value
for operand address and it issues 2 READ cycles:
Step 1: PC = $C006, $C006 is placed on address bus and READ

is issued.
Step 2: 8-bit content at location $C006 = $B7 is returned on data
bus and placed in IDR. PC is incremented by 1 to become
$C007.
Step 3: Control unit (instruction decoder) recognizes STORE
instruction. It needs a 2-byte value for operand address. It issues
two separate READ cycles
address bus = $C007 data bus = $D0
address bus = $C008 data bus = $01
At the end PC becomes $C009
Step 4: Execution of the instruction needs to issue a WRITE to
memory with address bus = $D001 and data bus = $50
address bus = $C004 data bus = $D0

address bus = $C005 data bus = $01
At the end, PC becomes $C006
MAR
30
31
32
Common Addressing Modes

Machine-code programmers need to know
what addressing modes are provided by a
given CPU
Not all processors implement all addressing
modes
Here we list some of the most common
addressing modes
Addressing Modes
One instruction, multiple meanings
33
35
Immediate
Addressing Modes
The argument itself appears immediately

after the op-code.
In other words, the address of the argument
is the address of the next memory location
after the op-code
This addressing mode is used only for input
arguments (its meaningless for output
arguments think about it!)
Addressing Modes is the technical term for

the various different ways that arguments for
machine instructions can be specified
It is common practice for CPUs to provide
several machine codes for each basic
operation: one code for each addressing mode
that makes sense with this operation.
34
36
68HC11 Immediate
68HC11 Direct
An 8-bit or 16-bit argument immediately

follows the op-code
LDAA #23
An 8-bit address in the range 0255

follows the op-code
The argument (specified in

decimal, by default)
LDAA 23
LDAA $FF
# signifies immediate mode
$ means its hex
37
Direct (or Absolute)
<256, so it must be direct

FF hex = 255 decimal,
so its still direct
39
Extended
The address of the argument (16 bit)
follows the op-code
That is, the number which follows the opcode is treated as an address at memory
locations [$0000 - $FFFF], and the CPU
will look there for the actual argument.
Using this addressing mode, memory space
of HC11 can be fully accessed.
The address of the argument (8 bit) follows

the op-code
That is, the number which follows the opcode is treated as an address at memory
locations [$00 - $FF], and the CPU will
look there for the actual argument.
No # sign, so we know its

not in immediate mode
38
40
68HC11 Relative
68HC11 Extended
This is slightly different. Its only used in

branch instructions see later in the course
To recognise a branch instruction, look for
the B. (BRA, BNE, BLS, BGS etc)
A full 16-bit address follows the op-code

LDAA 257
LDAA $255
$ means its hex
No #, so we know
its not immediate
>255, so it cant be direct,
and must therefore be
extended
BRA $F8
BNE $21
255 hex = 597 decimal, so

its extended
41
Relative
Jump $21 bytes ahead [PC+$21]
43
Indexed
The relative address of the argument

follows the op-code
Relative addresses specify where the
argument is relative to the current value of
the PC
The CPU calculates the actual address by
adding together the relative address and the
current value of the PC
Jump location at [PC 8]
The address of the argument is the value

currently stored in a specified index register
(or general-purpose register) plus an offset
that immediately follows that op-code
68HC11 has two index registers IX and IY
Useful for implementing arrays!
42
44
Inherent
68HC11 Indexed
The instruction is self contained. i.e. no

operands are used.
They are generally one byte instructions
with no operands.
These instructions are generally used to
operate directly on registers. For example,
clear accumulator A, B, X, etc.
The address of the argument is worked out

by adding the value of the IX or IY (index)
registers to the number before the comma
LDAA 1, X
You cant really make
mistake with this one
LDAA 2, Y
its the only one with a
comma
If you were to put the address of the start of an array in IX,

you could address the elements of it using the number
45
68HC11 Inherent
68HC11 Indexed
It loads the byte at address [X+offset]to Accu A
LDAA
47
In these instructions, there is no argument.

They generally operate on registers.
3,X
A0
Offset
(unsigned 8 bit)
0 .. 255
CLRA
INX
Index Register
to be used
X or Y
46
XX+1
48
Patterns in Machine Code
Others (not 68HC11)
Machine codes are not chosen at random!

LDAA imm
LDAA dir
LDAA ext
LDAA ind, X
LDAB imm
LDAB dir
LDAB ext
LDAB ind, X
register
The argument is the current contents of a specific register
register-indirect
The address of the argument is the current value of a
specified register
register-autoincrement/decrement
As register-indirect, but adjust register to point to
next/previous location before or after using its value
Indirect
The number following the op-code is the address of a
memory location that contains the address of the
argument
49
imm
86 dd
Assemblycode syntax
LDAA #dd
dir
96 dd
LDAA dd
ext
A6 dd dd
Machine codes
ind, X B6 dd
ind, Y 18 B6 dd
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
51
How is Addressing Mode Specified?

In most cases, set by bits from opcode
ADDA: $8B $9B $BB $AB
ADDB: $CB $DB $FB $EB
Opcode (8bit) format
How can we
LDAA dddd
Differentiate
Addressing Modes?
A/B AM1 AM0 1
LDAA dd, X
LDAA
dd, Y
Are These
Numbers
Selects Register
A for 0 or B for 1
Chosen Randomly?
1
1
1
1
1
1
1
1
defines the addressing mode
All of LDAA Instructions

Mode
86
96
A6
B6
C6
D6
E6
F6
50
00
01
10
11
immediate
Direct
Extended
Indexed
code for ADD
52
Some Arithmetic Instructions

ADDA
ADDB
ADDD
ABA
add 8-bit word to accumulator A

add 8-bit word to accumulator B
add 16-bit word to double accumulator D
add B to A
Conditionals
Bits in Condition Code Register
Equivalent subtraction operations are:

SUBA, SUBB, SUBD, SBA
Other Instructions
55
Condition Code Register (CCR)
There are also instructions to: Increment, decrement or negate a register or

memory location
Perform bitwise logical operations such as
AND, OR, XOR and NOT
Perform shifts, rotates, and many more
logical and arithmetic operations
53
5 status bits.
Certain bits in CCR indicate the situation after
the operation. For instance, if previous
operation yields a zero output, Z flag becomes
one.
2 interrupt masking bits (later)

1 stop disable bit (later)
54
56
Condition Code Register

CCR bit #
7
6
5
4
3
2
1
0
Bit Name
S
X
H
I
N
Z
V
C
Carry Flag (C)
Function
Stop disable flag
XIRQ interrupt mask
Half carry from lower 4 bit
Interrupt mask
Negative
Zero
Overflow
Carry
Indicates a carry from an addition or a

borrow from a subtraction
For addition,
C = 1 if carry out exists
C = 0 if no carry out
Carry/Borrow (C)
Overflow (V)
Zero (Z)
Negative (N)
Half Carry (H)
59
Example 1
Status Bits
57
Add 53 and 67, and determine if carry bit is set or not.

LDAA
LDAB
ABA
Used by CPUs
branch instructions
to make decisions
#53
#67
MSB
LSB
53
67
120
C
The result fits into
8 bits, therefore no
carry.
58
60
Example 2
Handling of Signed Numbers
LDAA
LDAB
ABA
#130
#163
MSB
130
163
293
6811 handles signed numbers using the 2s

complement numbering system
Recall the most significant bit is the sign
You negate a number by taking its 2s
complement (e.g. complement all bits and
add 1)
Review Digital Logic I and II courses
LSB
C
The result is 9 bits,
we use C flag as the
9th bit.
61
Example 3 (16 bit addition)

LDD
ADDD
All arithmetic (addition/subtraction) performed

on full binary number, including sign.
Hardware treats signed number as unsigned
from perspective of requested operation
Benefit is that we do not need to do anything
special to manage sign of operands or result
Disadvantage, seems counterintuitive.
LSB
50274
1 1 0 0 0 1 0 0 0 1 1 0 0 0 1 0
28712
0 1 1 1 0 0 0 0 0 0 1 0 1 0 0 0
78986
63
Arithmetic with Signed Numbers
#50274
#28712
MSB
1 0 0 1 1 0 1 0 0 1 0 0 0 1 0 1 0
C
The result is 17 bits
(exceeds 65535), we use
C flag as the 17th bit.
62
64
Methods to Determine C Flag Value
2s Complement Ranges
+3 = 00000011
+26 = 00011010
+40 = 00101000
+102= 01100110
Complement
and add 1
Method 1: more like how we do it hand

Explicitly monitor for carry or borrow,
-3 = 11111101
-26 = 11100110
-40 = 11011000
-102= 10011010
Method 2: possible implementation

Express result expressed as 9/17 bit quantity
For addition, extra bit is the carry flag
For subtractioncarry determined from extra bit
borrow from fictitious 9th bit in first subtrahend that is always 1
carry is the complement of the extra 9th/17th bit from result
Range of 2s complement numbers:

8-bit Reg.
-128 to +127 decimal
16-bit reg.
-32,768 to 32,767 decimal

Method 3: possible implementationminimum

hardware?
Examine operands and result, develop Boolean equations for C
Method 3 is how the carry is documented in the 68HC11
manual
67
Signed Addition Example
C Flag (for 2s Complement

Numbers)
Add 56 and 53 ($CB), and determine if carry bit is set or not.

LDAA
LDAB
ABA
C flag set to 1 if
Carry out from MSB for addition
Borrow from MSB for subtraction
#56
#-53
MSB
C flag set to 0 if neither of the above apply

Several hardware implementations possible
to determine value of C
65
LSB
56
-53
C
The result is 8 bits, we don't
use C flag as the 9th bit since
the numbers are taken as
signed
66
68
Signed Subtraction Example
Overflow Flag (V Flag)
Add 56 and 53 ($CB), and determine if carry bit is set or not.

LDAA
SUBA
For subtraction, a
fictitous 9th bit is
assumed.
#56
#-53
MSB
56
-53
3
CPU sets V flag to a logic 1 when the

result of an operation is beyond of the range
that can be represented
Known as 2s complement overflow
CPU clears flag when the number is within
range
LSB
1
C
complement
For subtraction 9th
bit is the
complement of carry
The resultant C is 0
Add 105 and 45, and determine if overflow bit is set or not.
LDAA
ADDA
#33
#-40
MSB
-40
Desired
Value
LSB
33
-7
#105
#45
MSB
+45
-106
how it is
interpreted!
9th bit is the

carry
70
LSB
105
150
71
2s Complement Overflow Example
Signed Addition Example

LDAA
ADDA
69
Result is
Negative!!
Two positive numbers

are added and a
negative number is
computed !!!
OVERFLOW!!!
72
2s Complement Overflow Example 2
In More Simple Terms
Add -120 and -10, and determine if overflow bit is set or not.
LDAA
ADDA
#-120
#-10
MSB
LSB
-120
-10
-130
Range Limit
V Flag
Outside
Inside
1
0
The result exceeds the range

of 8 bit 2s complement
numbers (i.e. less than -128)
OVERFLOW!!!
73
2s Complement Overflow Example 3
Negative Flag
Add 80 and 45, and determine if overflow bit is set or not.

LDAA
ADDA
#80
#45
MSB
80
45
125
N-bit indicates state of msb of a result

If msb = 1 => N-flag = 1
If msb = 0 => N-flag = 0
N-bit is used in 2s complement arithmetic
to indicate the sign of a number
So if V-flag = 0 => correct answer
=> N-flag valid sign
LSB
The result does NOT

exceeds the range of 8 bit
2s complement number NO
OVERFLOW!!!
75
74
76
N Flag
Zero Flag (Z flag)
6811 treats all numbers as 2s complement binary numbers

Subtraction is performed using 2s complement arithmetic
N Flag is simply the MSB of the result
Value
Value of MSB
Value of N-flag
Z bit is set to a logic 1 when the

result is 0, otherwise Z=0.
77
Zero Flag Example 1
Half Carry (H flag)
Add 50 and -50, and determine zero flag is set or not.

LDAA
ADDA
Used only for BCD (Binary Coded Decimal)

operations. (They will be discussed later)
H-flag updated only by ABA, ADDA, ADDB,
ADCA, ADCB
To do decimal arithmetic, the 68HC11 does
arithmetic in binary and then uses H and C to
adjust the calculation to give a proper decimal
result.
79
#50
#-50
MSB
LSB
50
+ -50
The 8bit result is all zeros.

Therefore, Z flag is set. Note
also that C=1 and V=0.
78
80
Zero Flag Example 2

Add 50 and -47, and determine zero flag is set or not.
LDAA
ADDA
#50
#-47
MSB
LSB
50
+ -47
First Assembly Language

Example
Adding five numbers at address
$C100 - $C104 and put the result in
location $C105
Some bits are not zeros,

therefore, Z flag is clear.
Note that C=1 and V=0
81
Picture
Z Flag
All bits zero

Some bits are ones
1
0
increasing
addresses
Results of operation
Status of
Z Flag
83
82
$C100
$C101
$C102
..
$C105
84
Coding
Design
Clear accumulator A.
A Self contained
instruction.
We have to perform a running sum

operation (i.e. add the incoming number to a
variable in an iterative way)
What about accumulator A?
That is what accumulators are used for!
CLRA
ADDA
ADDA
ADDA
ADDA
ADDA
STAA
A A + [$C100]
$C100
$C101
$C102
$C103
$C104
$C105
A A + [$C101]
A A + [$C102]
A A + [$C103]
A A + [$C104]
[$C105] A
opcodes
accumulator
ans + [$C100]
ans + [$C101]
ans + [$C102]
ans + [$C103]
ans + [$C104]
ans to $C105
85
87
Machine Code Equivalent of the

Assembly Program
Implementation
clear
ans =
ans =
ans =
ans =
ans =
store
operands
...
Clear accumulator
(running sum)
CLRA
ADDA
ADDA
ADDA
ADDA
ADDA
STAA
Add the contents of

memory locations
to accumulator
Store the answer to
$C105
$C100
$C101
$C102
$C103
$C104
$C105
$4F
$BB
$BB
$BB
$BB
$BB
$B7
$C1
$C1
$C1
$C1
$C1
$C1
$00
$01
$02
$03
$04
$05
opcodes operands
86
$C000
$4F
$C001
$BB
$C002
$C1
$C003
$00
$C004
$BB
$C005
$C1
...
88
Improvement - 1
CLRA
ADDA
ADDA
ADDA
ADDA
ADDA
STAA
LDAA $C100
$C100
$C101
$C102
$C103
$C104
$C105
START
Saves 1 byte,
which may be quite
important for
systems with
limited memory
Clear Accumulator
#$C100
0,X
START
Add the byte at

location [X+0] to A
XX+1
Jump to the location
labeled by
START
91
Improvement: Using Loops

START
CLRA
LDX
ADDA
INX
JMP
#$C100
0,X
Therefore, we need a
comparison
operation and a
conditional branch
We have to use an
Index Register
(Indexed Addressing)
90
We need to
compare X with
$C105
START
Yes, we can!
X $C100
89
Can we iterate
through
the memory
locations?
$C100
$C101
$C102
$C103
$C104
$C105
CLRA
LDX
ADDA
INX
JMP
We need to jump
conditionally to
START to deal
with the infinite
loop
Improvement - 2
LDAA
ADDA
ADDA
ADDA
ADDA
STAA
Improvement :
Using Loops
Well, well, well.

We have a loop
that never stops.
If X = $C105 then
we continue,
otherwise we jump
to label START
92
CLRA
LDX
#$C100
START ADDA 0,X
INX
CPX
#$C105
............
S X H I N Z V C
The Final Program
Comparison
We need a
branch
instruction that
checks CCR

set if operation makes carry
set if operation makes overflow
set if the operation's result is zero
set if the result is a negative number
.......
if 3rd bit is set (for BCD numbers)
......
.....
Compare X
immediately with
value $C105
Jump 8 bytes
backward
PC PC -8
Comparison is a
non-destructive
subtraction
It sets the
appropriate bit in
Condition Code
Register (CCR)
S X H I N Z V C

set if operation makes carry
set if operation makes overflow
set if the operation's result is zero
set if the result is a negative number
.......
if 3rd bit is set (for BCD numbers)
......
.....
LDAA
$C100
LDX
#$C101
START ADDA
$F8 = -8
in 2s
complement
form
You must start
counting from the
next instruction
backward or
forward
0,X
INX
CPX
#$C105
BNE
START
STAA
0,X
93
Comparison
CLRA
LDX
#$C100
START ADDA 0,X
INX
CPX
#$C105
BNE
START
...........
$B6
$C1
$00
$CE
$C1
$01
$AB
$00
$08
$8C
$C1
$05
$26
$F8
$A7
$00
95
Example
Checks Z bit in
CCR. If it is 0
jumps to START
Fill a page (256 bytes) of memory with value of

address ($D000 = $D0, $D001 = $01, etc...)
If Z bit is 1, then
continues (i.e. exits
loop)
MEMORY
OUTPUT
$D000
$D0
$D001
$D002
$00
$D0
$D003
$02
$D004
$D0
$D005
$04
....
....
BNE stands for

Branch If Not
Equal
94
$D0FD
$FC
$D0FE
$D0
$D0FF
$FE
96
Example
First Version
We use index register X to point out the beginning
of the memory block. We store the value of X
to the location pointed by X and increment X twice
to move on.
LOOP
....
LDX
STX
INX
INX
CPX
BNE
....
#$D000
$0,X
Move a page of memory from $D000 to $D200
X Starting address
$33
$D002
$55
$D0FF
$23
$D200
$73
$D201
$33
$D202
$55
$D2FF
$23
XX+1
XX+1
#$D100
LOOP
X ?= $D100, changes Z flag

if Z bit = 0, go to the
address labeled as LOOP
97
Second Version (better)

LOOP
$73
$D001
[X + 0] X
LDAB
LDX
STX
ABX
CPX
BNE
....
$D000
#$02
#$D000
$0,X
The First Version

We need two pointers. 68HC11 has
two index registers IX and IY. Use one of them
for target, the other for source.
B2
X Starting address
[X + 0] X
XX+B
#$D100
LOOP

if Z bit = 0, go to the
LOOP
This version is better than

the first one, since ABX is
faster than two INX
instructions.
99
98
LDX
LDY
LDAA
STAA
INX
INY
CPX
BNE
....
#$D000
#$D200
$0,X
$0,Y
X source address
Y destination address
A [X + 0]
[Y + 0] A
XX+1
YY+1
#$D100
LOOP

if Z bit == 0, go to the
100

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Machine Instructions

An individual machine code is called a

e.g. the machine instruction to add 1 to the

The commands the CPU understands

Week 2: Addressing Modes

The set of all codes recognized by a

Week 2: Addressing Modes

A set of binary codes that are

A typical machine instruction consists of an

e.g. the machine instruction to add 2 to the

Week 2: Addressing Modes

Week 2: Addressing Modes

What Do/Can Machine Instructions Do?

We can group the instructions according to

Week 2: Addressing Modes

Instructions: Data Transfer

Week 2: Addressing Modes

Instructions: Flow Control

From where, to where?

Week 2: Addressing Modes

A computer program is not a lot of use

Week 2: Addressing Modes

68HC11 Register Set

Youll come across other types of

Every CPU contains a set of registers which

You need to know about these registers before

Example machine codes

This is the way a programmer needs to view

What does this mean?

Week 2: Addressing Modes

The Programmers Model

The 68HC11 CPU is the one well be

Week 2: Addressing Modes

Week 2: Addressing Modes

68HC11 Architecture: Programmers Model

Instruction: LDAA direct

Week 2: Addressing Modes

CCR Condition Code Register

Week 2: Addressing Modes

They perform the same operation, but the source is

op code for LDAA

Week 2: Addressing Modes

op code for LDAA

Why two instructions with the

Instruction: LDAA immediate

Week 2: Addressing Modes

Addressing Modes Example

LDAA immediate to load the value (decimal) 30 into

68HC11 is a big endian microprocessor.

LDAA direct to load the contents of address 30 into

Week 2: Addressing Modes

Data transfer between CPU and memory involves

Machine Language Execution

Week 2: Addressing Modes

Week 2: Addressing Modes

Assembly Machine Code

Machine Language Execution

Assembly language facilitates to write programs for humans.

Each machine language instruction consists of an operation code

Machine code equivalent

Week 2: Addressing Modes

The Instruction Execution Cycle

Instruction Code and Operands

LOAD: copy the content of a memory location into a