1, RISC vs CISC

RISC
Shorten execution time by reducing the
clock cycles per instruction
Simple instructions, few in number
Fixed length instructions
Complexity in compiler
Only LOAD/STORE instructions access
memory
Few addressing modes
DEC Alpha, AMD 29k, ARC, ARM, Atmel
AVR, Blackfin, Intel i860, MIPS, Motorola
88000, PA-RISC, PowerPC, SuperH,
SPARC, Ipad, Android.
Example:

CISC
Shorten execution time by reducing the
number of instruction per program
Many complex instructions
Variable length instructions
Complexity in microcode
Many instructions can access memory

RISC:

CISC:
mov ax, 10
mov bx, 5
mul bx, ax

begin

mov ax, 0
mov bx, 10
mov cx, 5
add ax, bx
loop begin

Many addressing modes

System 360, z/Architecture, PDP 11, VAX,
Motorola 68k, x86

The total clock cycles for CISC version might be:

(2 movs x 1 cycle) + (1 mul x 30 cycles)=32 cycles
While the clock cycles for the RISC version is:
(3 movs x 1 cycle) + (5 adds x 1 cycle) + (5 loops x 1 cycle) =13 cycles

2, ARM & THUMB Instructions Set

ARM
Tp lnh 32-bit
C li v hiu sut

THUMB
Tp lnh 16-bit
C li v mt m

ARM Processor s dng ng thi c 2 tp lnh ARM 32-bit v Thumb 16-bit

Mc nh, sau khi reset hoc start-up, ARM core s hot ng ARM
state. Trong qu trnh chy, nu gp cc lnh Branch, Exchange (BX,
BLX) hoc exception returns, n s chuyn sang THUMB state. Khi
chuyn i gia ARM state v THUMB state, mode v gi tr ca cc
thanh ghi khng i

Tp lnh ARM (c li v hiu sut)

- ngi lp trnh c th s dng 16 general-purpose register t
R0-R15, c chia thnh 3 nhm: Unbanked Register (R0-R7),
Banked Register (R8-R14), Program Counter (R15)
Tp lnh Thumb (c li v mt m)
- THUMB State Register Set l tp con ca ARM State Set. Ngi
lp trnh c th truy cp n 8 general-purpose register (R0-R7),
Program Counter (PC), stack pointer register (SP), link register
(LR) v CPSR trong THUMB State.
- Tp lnh Thumb-2 l s pha trn gia tp lnh 16 v 32 bit, t
c hiu sut ca cc lnh ARM 32 bit, ng thi ph hp vi
mt m cng nh tng thch ngc vi tp lnh gc Thumb
16 bit.

Tp lnh THUMB cho gi tr kt qu thp hn tp lnh ARM nhng m

cc kt qu ny chim mt t l ln hn.

Tp lnh THUMB tit kim c khng gian nh 30% v chy nhanh

hn 40% so vi tp lnh ARM.

Tp lnh THUMB khng c iu kin thc thi tr cc lnh r nhnh.

3, Kin trc Von-neumann & Harvard

Von-Neumann
Bao gm ALU, Memory(RAM), Von Neumann
Control Unit, Input and Output devices.
B nh d liu v b nh chng trnh chung

Khng th va c mt lnh, va truy cp d

liu t b nh cng lc
Thit k ny ca Von Neumann gii hn
tc thc thi ca chng trnh do ti mi
thi im ch thc thi c mt lnh.
Ph hp vi cc thit k tun t

Harvard
Dng trong DSP
Phn bit r rng b nh d liu v b nh
chng trnh.
C nhng ng truyn (bus) ring truy
cp vo b nh d liu v b nh chng
trnh.
C th va c mt lnh, va truy cp d
liu t b nh cng lc
Tc nhanh

Phn cng phc tp, chi ph cao

Nhng nm gn y, tc CPU tng ln rt nhiu ln so vi tc truy cp vo b

nh chnh. Ngi ta cn quan tm n vic gim s ln truy cp vo b nh m
bo tc hot ng ca CPU. Nu, trong cng mt lc, mi lnh ca CPU cn phi
truy cp vo b nh 1 ln, vy th vic tng tc CPU chng cn ngha g na,
bi v n lun lun b gii hn bi vic truy cp vo b nh.
B nh c th c thit k c tc truy cp cao, nhng n ng ngha vi vic
gi sn xut s cao. Gii php l cung cp mt dung lng nh b nh m, vi tc

 truy cp rt cao, v chng ta gi l cache (b nh m). Khi b nh CPU cn

tng tc ang nm trong cache, v vic tng tc vo tn t thi gian hn rt
nhiu ln so vi khi cache phi thay i v ly d liu t b nh chnh a vo. Vic
iu chnh cache l mt vn quan trng trong vic thit k my tnh.
Nhng thit k chip CPU tc cao ngy ny thng kt hp hai kin trc Harvard
v von Neumann. B nh cache trn chip c phn thnh cache chng trnh v
cache d liu. Kin trc Harvard c dng khi CPU truy cp vo cache. Tuy nhin,
trong trng hp khng c cache, d liu c ly t b nh chnh, m b nh chnh
khng c chia thnh vng nh chng trnh v vng nh d liu. Nh vy, kin
trc von Neumann c dng tm vc truy cp b nh chnh.

4, C bn v chu k lnh v ng dn lnh

Ging cu 10
5, Gii thiu chung v H thng nhng
L mt h thng chuyn dng, thng c kh nng t hnh v c thit k tch
hp vo 1 h thng ln hn thc hin mt chc nng ring bit no .
Kin trc tng th ca mt HTN:

Hardware Layer
3
2
Software Layer
System Software
Layer (OS, device driver) Application
(required)

6, Cc m hnh HTN & c im HTN

c im ca HTN:
a. Reliable
i. Reliability: h thng khng gp s c
ii. Maintainability: xc sut m mt h thng ang b s c c th
sa c trong mt khong thi gian nht nh.
iii. Availability: xc sut m h thng tnh trng sn sng phc v.
iv. Safety: m th thng b s c s khng gy thit hi.
v. Security: d liu mt khng b l v cc lin lc u c cc
chng thc c m bo.
b. Tnh hiu qu
i. Energy efficient
ii. Code-size efficient
iii. Run-time efficient
iv. Weight efficient
v. Cost efficient
c. Cc h thng nhng ch dnh cho 1 ng dng nht nh.

d. Cc h thng nhng c 1 giao din nht nh

e. Hydrid system
f. Nhiu h thng nhng phi tha mn nhng rng buc thi gian thc
(real-time constraint).
g. Thng thng 1h thng nhng thng kt ni vi mi trng vt l
bn ngoi thng qua cc cm bin,b thc thi.
h. Thng thng, cch thng nhngcng l cc h phn ng (reactive
system).
7, Ngn ng v m hnh khc nhau nh th no?
C 5 loi m hnh tnh ton:
- Sequential Program model: Statements, rulesfor composing statements, semantics
for executing them
- Communication process model: Multiple sequential programs running concurrently
- State machine model: For control dominated systems, monitors control inputs, sets
control outputs
- Dataflow model: For data dominated systems, transforms input data streams into
output streams
- Object-oriented model: For breaking complex software into simpler, well-defined
pieces

M hnh tnh ton l nhng khi thc hin nhng chc nng nht nh nh
(State machien, Sequent program, Data-flow) s c capture v m t bng
ngn ng lp trnh nh (C, C++, Java)
Nhiu ngn ng khc nhau c th capture 1 m hnh. Vd: sequential program
model -> C, C++, java
Mt ngn ng c th capture nhiu m hnh. Vd: C++ -> sequential program
model, object-oriented model, state machine model

8, Phn bit FSM Moore & Mealy

Moore: The FSM uses only entry actions, i.e., output depends only on the state. The
advantage of the Moore model is a simplification of the behavior.

Mealy: The FSM uses only input actions, i.e., output depends on input and state. The
use of a Mealy FSM leads often to a reduction of the number of states.
9, Phn bit cc loi ADC: c im v cc thc hot ng
Flash ADC (direct conversion ADC)

Vout=Vin*(2n-1)/Vref
S b so snh: 2n-1
N: phn gii

Successive approximation

10, Phn bit lung d liu v chu k lnh

Datapath Operations: gm 3 bc
+ Load: c gi tr t memory ghi vo
Register

+ ALU: ALU x l v tr ra kt qu vo
Register

+ Store: Ghi li kt qu sau php tnh Vo

memory

Instruction Cycle: 1 chu k lnh c

x l sau 5 bc
B1-Fetch: c instruction tip theo vo
thanh ghi IR
B2-Decode: Xc nh ngha ca
instruction
B3-Fetch operands: c d liu t
memory ghi vo datapath register
B4-Execute: ALU x l v tr kt qu ra
register
B5-Store results: Write data result from
register to memory

11, Cc chun giao tip thng c s dng trong H thng nhng

1. Yu cu:
C tnh hiu qu, kinh t.
C tnh an ton.
C bo mt cao.
C tnh bo tr.
C tnh phn on.
C tr v giao tip v bng tn thch hp.
2. Cc chun giao tip:
2.1.
Electrical robustness (och bit dch ra ting vit):

2.2.

2.3.
2.4.

Khi nim: Slide 64 Tun 3 (kh hiu vi chng).

Thun li:
- Loi b hu ht nhiu.
- Thay i mc in th m khng c nh hng.
- Gim c s quan trng ca nhng dy t.
- Tc nhanh hn.
Bt li:
- Yu cu in th m.
- Tng s lng dy v s kt ni.
ng dng:
- Tn hiu audio cht lng cao.
- USB, ISDN.
- Ethernet.
Mc hnh vi thi gian thc (Real time behavior)
CSMA/CD (carrier sense multiple access/ collision detection) khng
c thi gian p ng m bo.
Nhng s thay i:
o Token rings, token buses
o CSMA/CA (carrier sense multiple access/ collision avoidance).
Fault tolerance: Pht hin v sa cha li ca nhng giao thc Bus.
Privacy: M ha, nhng mng ring o

12, Memory, cc loi b nh, c im v u khuyt im

Memory, efficiency is again a concern:
-

Speed, predictable timing

Energy efficiency
Size
Cost
Other attributes(volatile vs.. persistent, etc)

Cc loi memory:
Mt d liu
khi mt in
Khng

Kh nng ghi

C xa

Xa nhiu ln

Tc

Gi thnh

C (high voltage)

Gii hn

c nhanh,
xa ghi chm
Nhanh

Va phi

Sector
(UV light)
Byte

DRAM

Byte

Va phi

Va phi

EEPRO
M

khng

C
(electrical signal)

c nhanh,
xa ghi chm

EPROM

Khng

C, cn thit b
chuyn dng
(electrical signal)

Byte
(electrica
l signal)
Ton b
(UV light)

Nhanh

Va phi

Loi
Flash
mem.
SRAM

Khng gii
hn
Khng gii
hn
Gii hn

Gii hn

PROM

khng

Mt ln, cn thit
b chuyn dng
(electrical signal)

Khng xa c

Nhanh

Va phi

13, Cc thnh phn ca RTOS

Gm 2 phn:
Phn li (kernel): thc hin vic lp lch (schedules tasks)
Tc v (tasks): L cc hot ng hin ti vi cc trng thi ring ca n (PC,
registers, stack, ect.)
14, Cc yu cu ca RTOS
-

Kch thc nh (lu tr ton b trong ROM)

S dng h thng ngt
Khng nht thit phi c cc c ch bo v
Tng tc truyn thng gia cc qu trnh
Khi cc qu trnh ng dng ang thc hin th cc yu cu h thng iu
hnh c th c thc hin thng qua cc li gi hm thay v s dng c ch
ngt mm

15, Tc v v cc trng thi ca tc v

Tasks = Code + Data + State
Trng thi ca nhim v c lu tr trong khi iu khin nhim v (Task Control
Block- TCB) khi nhim v khng c thc hin trn CPU
Cc trng thi ca tc v:
Executing: ang thc hin trn CPU
Ready: C th chy trn CPU nhng mt nhim v khc ang s dng CPU
Blocked: i s kin (I/O, signal, resource, etc.)
Dormant: To ra nhng cha c thc hin
Terminated: Khng cn tc ng na
RTOS thc hin mt c ch chuyn trng thi (a Finite State Machine ) cho mi
nhim v v qun l qu trnh chuyn trng thi.
16, Chu k ca tc v

Thi
gian
xut hin ai (arrival time) khon thi gian t lc s kin xy ra n lc
nhim v tng ng c kch hot.
Thi im bt u thc thi (released time) thi im sm nht task c
th sn sng bt u.
Thi im bt u thc hin (starting time) thi im m ti task bt
u thc hin.
Thi gian tnh ton (computation time) thi gian cn thit task thc
hin xong nhim v m khng b ngt.
Thi im hon thnh (finish time) thi im m ti task thc hin
xong nhim v ca mnh.
Thi gian ri ro (worse case) khon thi gian lu nht c th xy ra.
Thi im kt thc (due time) thi im m ti task phi hon thnh.
17, Cc k thut lp lch
First Come First Serve (FCFS): theo th t xut hin, khng c ngt.
Khng ph hp cho thi gian thc.
Shortest Job First (SJF): task c thi gian ngn thc hin trc. p dng
cho c task c ngt v khng ngt. p dng c ch tin on xc nh
mc u tin.
Rate Monotonic (RM): gn mc u tin da trn chu k ca chng. (chu k
nh -> u tin cao)
Earliest Deadline First (EDF): task c deadline gn nht c u tin.
Minimum Laxity First (MLF): u tin task cn t thi gian thc hin m
bo thc thi ng yu cu.

Round Robin (RR): Task lun phin thc hin trong mt khon thi gian
nht.