Softroniics

PAQCS: Physical Design-Aware Fault-Tolerant Quantum Circuit

Synthesis

Abstract:
Quantum circuits consist of a cascade of quantum gates. In a physical design-unaware
quantum logic circuit, a gate is assumed to operate on an arbitrary set of quantum bits (qubits),
without considering the physical location of the qubits. However, in reality, physical qubits have
to be placed on a grid. Each node of the grid represents a qubit. The grid implements the
architecture of the quantum computer. A physical constraint often imposed is that quantum gates
can only operate on adjacent qubits on the grid. Hence, a communication channel needs to be
built if the qubits in the logical circuit are not adjacent. In this paper, we introduce a tool called
the physical design-aware fault-tolerant quantum circuit synthesis (PAQCS). It contains two
algorithms: one for physical qubit placement and another for routing of communications. With
the help of these two algorithms, the overhead of converting a logical to a physical circuit is
reduced by 30.1%, on an average, relative to previous work. The optimization algorithms in
PAQCS are evaluated on circuits implemented using quantum operations supported by two
different quantum physical machine descriptions and three quantum error-correcting codes. They
reduce the number of primitive operations by 11.5%68.6%, and the number of execution cycles
by 16.9%59.4%.

Existing Method:
Current quantum technologies support a set of one-quantum bit (qubit) and two-qubit
quantum gates. A two-qubit gate enables interaction between the two qubits. However, a
physical realization of two-qubit gates typically requires that the two qubits be adjacent. When
the two qubits are far apart, a communication channel must be created between them. This
communication overhead not only increases the computation latency but also the probability of a
computation error. Quantum systems are fragile because when they interact with the
environment, the information stored in the system decoders, thus resulting in error and
consequent failure of computation.
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Proposed Method:
We introduce a tool called the physical design-aware fault-tolerant quantum circuit
synthesis (PAQCS). It contains two algorithms: one for physical qubit placement and another for
routing of communications. The optimization algorithms in PAQCS are evaluated on circuits
implemented using quantum operations supported by two different quantum physical machine
descriptions and three quantum error-correcting codes. They reduce the number of primitive
operations by 11.5%68.6%, and the number of execution cycles by 16.9%59.4%.

Applications:
1. Error-correcting codes
2. Digital signal processing

Advantages:
1. Reduce the number of primitives
2. Error correcting

System Configuration:In the hardware part a normal computer where Xilinx ISE 14.3 software can be easily
operated is required, i.e., with a minimum system configuration
HARDWARE REQUIREMENT
Processor

- Pentium III

Speed

- 1.1 GHz

RAM

- 1 GB (min)

Hard Disk
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Calicut||Coimbatore||Palakkad

- 40 GB
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9037291113, 9037061113

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Floppy Drive

- 1.44 MB

Key Board

- Standard Windows Keyboard

Mouse

- Two or Three Button Mouse

Monitor

- SVGA

SOFTWARE REQUIREMENTS
Operating System

:Windows95/98/2000/XP/Windows7

Front End

: Modelsim 6.3 for Debugging and Xilinx 14.3 for

Synthesis and Hard Ware Implementation

This softwares where Verilog source code can be used for design
implementation.

Softroniics
Calicut||Coimbatore||Palakkad

www.softroniics.in
9037291113, 9037061113