Simplified Datasheet for WM8731 Audio Codec

This document extracts only the essential information from the manufacturers datasheet for the
Wolfson WM8731/WM8731L audio codec device. In its entirety, the full datasheet is long and
complex, and it includes descriptions of modes and functions that are not relevant to the Fall
2031 DDL project. Students should be able to find everything they need here, but are welcome to
access the full datasheet if they are interested in learning about other capabilities.

Introduction
Throughout this document, any text enclosed in quotation marks is directly taken from the full
datasheet titled WM8731 / WM8731L Portable Internet Audio CODEC with Headphone Driver
and Programmable Sample Rates, version 3.4, by Wolfson Microelectronics plc 2004. Figures
taken from the same document are noted as such. Text or figures enclosed in a shaded block
near the right margin deviates from a specific description of the CODEC and instead notes very
specific implementation details related to either the DE2 hardware, the SCOMP implementation
provided as a starting point, or both. Thus, the document without the shaded blocks should read
roughly like a simplified generic datasheet for the CODEC. As the CODEC is introduced in the
following paragraph, an example of all of these formatting features is immediately given.
A CODEC is any device, including possibly a software
module, that performs the function of encoding or
decoding information. For example, movie player
software employs one or more codecs to play movies
encoded in different compressed formats.
The WM8731 or WM8731L (WM8731/L) are low
power stereo CODECs with an integrated headphone
driver. The WM8731/L is designed specifically for
portable MP3 audio and speech players and recorders.
The WM8731 is also ideal for MD, CD RW machines
and DAT recorders.

The WM8731 on the DE2

board is the small chip labeled
U1 near the row of colored
audio connectors. Its analog
capabilities are limited by its
connection to those
connectors, but it has a flexible
digital interface, using
dedicated pins on the Cyclone
II FPGA.

Stereo line and mono microphone level audio inputs are provided, along with a mute function,
programmable line level volume control and a bias voltage output suitable for an electret type
microphone.
Internal analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) allow the
device to convert at sampling rates from 8kHz to 96kHz, supporting digital word lengths from
16-32 bits.
Stereo audio outputs are buffered for driving headphones from a programmable volume control,
line level outputs are also provided along with anti-thump mute and power up/down circuitry.
The device is controlled via a 2 or 3 wire
serial interface. The interface provides
access to all features including volume
controls, mutes, de-emphasis and
extensive power management facilities.

The interface is configured to conform to the

I2C specification on the DE2 board, and an
I2C initialization VHDL device is provided to
students so that no reconfiguration or control
operations are required. This simply means
that students must adhere to the data formats,
volume, muting, and other settings that have
been preselected for them.

Figure 1: Block diagram (from WM8731 / WM8731L Portable Internet Audio CODEC with Headphone Driver and
Programmable Sample Rates, version 3.4, by Wolfson Microelectronics plc 2004).

Only certain aspects of the device, shown in its entirety in Figure 1, are necessary to utilize it as
an analog waveform generator, driven by a sequence of digital inputs. Specifically, the
DACDAT (DAC Digital Audio Input) pin needs to be driven with digital data, in a serial format
to be described, and various clocks are used as inputs and outputs, including MCLK (Master
Clock), DACLRC (DAC Sample Rate Left/Right Clock), and BCLK (Digital Audio Bit Clock).
With the Control Interface suitably preconfigured, manipulating this relatively small number of
pins is sufficient for generating analog signals at the left and right headphone outputs (LHPOUT,
RHPOUT).

Audio Signal Path

Analog Inputs
The CODEC includes three low noise inputs mono
microphone and stereo line. Line inputs have +12dB
to -34dB logarithmic volume level adjustments and
mute. The Microphone input has +6dB to -34dB
volume level adjustment. An electret microphone bias
level is also available. All the required input filtering
is contained within the device with no external
components required.

As preconfigured for the project,

the analog inputs are disabled,
since they would not be needed
purely for generation of an analog
waveform from digital data. Use
of these inputs would require
greater knowledge of the CODEC.

ADC
The WM8731/L uses a multi-bit oversampled
sigma-delta ADC.

Use of the ADC is beyond the scope of

the Fall 2012 DDL project.

DAC and DAC filters

A digital audio interface enables the user to send two
separate streams of digital data (left and right) to the two
DACs, passing through DAC filters along the way.
The DAC filters perform true 24 bit signal processing to
convert the incoming digital audio data from the digital
audio interface at the specified sample rate to multi-bit
oversampled data for processing by the analogue DAC.
The DAC digital filter can apply digital de-emphasis
under software control. The DAC can also perform a soft
mute where the audio data is digitally brought to a mute
level. This removes any abrupt step changes in the audio
that might otherwise result in audible clicks in the audio
outputs.

The soft mute and deemphasis features are

disabled in the preconfigured
code provided to students.
The DAC filter choices have
relatively little impact on the
output signal, and students
should not bother with
modifying this.

Analog Outputs
The WM8731/L provides two low impedance line
outputs LLINEOUT and RLINEOUT, suitable for
driving typical line loads of impedance 10K and
capacitance 50pF.
The WM8731/L has a stereo headphone output
available on LHPOUT and RHPOUT. The output is
designed specifically for driving 16 or 32 ohm
headphones with maximum efficiency and low power
consumption. The headphone output includes a high
quality volume level adjustment and mute function.

The LLINEOUT and RLINEOUT

outputs are not physically
connected on the DE2 board, but
their buffered versions LHPOUT
and RHPOUT appear on the
headphone output jack.
The preconfigured code has no
amplification set (gain = 1, or 0
dB). Changing this requires
altering the I2C device, and there
is no clear benefit in doing so.

Clocking Schemes
In a typical digital audio system there is only one
central clock source producing a reference clock to
which all audio data processing is synchronised. This
clock is often referred to as the audio systems Master
Clock. [An external clock signal can be applied]
directly through the XTI/MCLK input pin with no
software configuration necessary.
After optionally being divided by two, the Master
Clock becomes what is called the Core Clock.

The preconfigured code provides a

12 MHz clock signal as the Master
Clock.
There is no division by two, so the
terms Master Clock and Core
Clock are synonymous for the
preconfigured code.

Digital Audio Interfaces

WM8731/L may be operated in either one of the 4
offered audio interface modes. These are:
Right justified
Left justified
I2S
DSP mode
All four of these modes are MSB first and operate
with data 16 to 32 bits.
The interface may be clocked in either Master mode
or Slave mode. Master mode requires only one input
clock (the Master clock), and all other digital audio
interface clocks are generated by the device from the
Master clock.

The preconfigured code selects

DSP mode with 16-bit data. Only
the DSP mode is described in the
sections which follow. There is no
clear benefit in choosing any
other mode.
Master mode is preset in the
preconfigured code, too.
Changing to slave mode would
greatly increase workload and
complexity, requiring students to
generate more than one clock, and
is not allowed for the project.

The digital audio interface also receives the digital audio data for
the internal DAC digital filters on the DACDAT input. DACDAT
is the formatted digital audio data stream output to the DAC digital
filters with left and right channels multiplexed together. DACLRC
is an alignment clock that controls whether Left or Right channel
data is present on DACDAT. DACDAT and DACLRC are
synchronous with the BCLK signal with each data bit transition
signified by a BCLK high to low transition. DACDAT is always
an input. BCLK and DACLRC are outputs generated from the
Master Clock as noted above.
DSP mode is where the left channel MSB is available on either
the 1st or 2nd rising edge of BCLK (selectable by LRP) following
a LRC transition high. Right channel data immediately follows left
channel data.
DACLRC must always change on the falling edge of
BCLK.

LRP is set to 1 in the

preconfigured code,
making the required
timing appear exactly
as shown in the
figure below. Recall
that earlier it was
noted that the number
of bits was
preconfigured to 16,
so n=16 in that figure
below.

Figure 2: DSP mode (from WM8731 / WM8731L Portable Internet Audio CODEC with Headphone Driver and
Programmable Sample Rates, version 3.4, by Wolfson Microelectronics plc 2004).

Operating the digital audio interface in DSP mode allows ease of use for supporting the various
sample rates and word lengths. The only requirement is that all data is transferred within the
correct number of BCLK cycles to suit the chosen word length.
It is possible to change the polarity of various signals (e.g., change boundary of data bit to be a
low-to-high transition of BCLK), but there is no obvious reason to do so. It is also possible, but
similarly unlikely, to change the order of left vs. right channel data.
DACDAT is always an input. It is expected to be set low by the audio interface controller when
the WM8731/L is powered off or in standby.
the DACLRC and BCLK signals are outputs that default low.

Audio Data Sampling Rates

The WM8731/L provides for two modes of operation (normal
and USB) to generate the required DAC and ADC sampling rates.
Normal and USB modes are programmed under software control
.
In Normal mode, the user controls the sample rate by using an
appropriate MCLK and the sample rate control register setting.
The WM8731/L can support sample rates from 8ks/s up to 96ks/s.
In USB mode, the user must use a fixed MCLK of 12MHz to
generate sample rates from 8ks/s to 96ks/s. It is called USB mode
since the common USB (Universal Serial Bus) clock is at 12MHz
and the WM8731/L can be directly used within such systems.
WM8731/L can generate all the normal audio sample rates from
this one Master Clock frequency, removing the need for different
master clocks or PLL circuits.

The preconfigured
code is set for USB
mode. As already
noted, the required 12
MHz clock is
provided for MCLK.
All needed clocks in
Figure 2 are provided
BY THE CODEC, so
there is minimal work
done by the student
here.

The sample rate is set to be 48 kHz.

Oversampling is a measure of how many extra samples are generated (in excess of 48 kHz). The
selected oversampling rate of 250fs (250 times the sample rate of 48 kHz, or 12 MHz) is
consistent with the 12 MHz clock applied to the DAC. Put another way, input data is clocked at

the digital interface at a rate of 12 MHz (16-bit values for both the left and right channels), which
is 250 times the rate required to generate a 48 kHz-sampled signal.