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VALLIAMMAI ENGINEERING COLLEGE
DEPARTMENT OF ELECTRONICS & INSTRUMENTATION
EI2353:DIGITAL SYSTEM DESIGN-Question Bank(2Marks)
Staff Name: Ms.Z.JENIFER & D.ARBUTHA

Branch/Sec
:EIE/A&B
Year/Semester: III/ VI

UNIT I- DIGITAL LOGIC FAMILIES

PART A
1.What is meant by wired operation?
1.The outputs of two NAND gates or two NOR gates can be connected together to provide a specific
logic function. This type of logic is called wired logic or wired operation.
Example: Open-collector TTL NAND gates, when tied together, perform the wired-AND logic.

2.Wired operation is used to form common bus.

2.State the advantages and disadvantages of a totem-pole output.
Advantage: Operating speed is high.
Disadvantage: Output of two gates cannot be tied together to form wired-logic connection for the
purpose of forming a common-bus system.
3.Define Fan-in and Fan-out. .(May/June 2012)
Fan-in is the number of inputs to the gate which it can handle.
Fan-out is the number of loads the output of a gate can drive without effecting its operation.
4.State any two advantages of a CMOS logic family. .(May/June 2012)
. In case of bipolar memory chip the
1. Power dissipation per gate is very low i.e. about 0.05
power dissipation is in milliwatts.
2. CMOS memory chips has high noise immunity than bipolar memory chips.
36.Define the term fan out with respect to logic families.(Apr/May 2011)
Fan-out is the number of loads the output of a gate can drive without effecting its operation
6.Explain briefly why CMOS cannot drive the TTL directly. .(Nov/Dec 2011)
CMOS takes a lot less power and is therefore suitable for battery applications, but generally speaking
can't run as fast. TTL devices can drive more power into a load.CMOS chips can be damaged by static
electricity
7.Compare TTL, CMOS and ECL logic families with respect to power dissipation and
propagation delay. .(Apr/May 2011)

8.Which TTL family offers the lowest power and the fastest operation?(Nov/Dec 2011)
Totem pole TTL has the advantage of high speed and low power dissipation
9.How is saturation delay time reduced with schottky TTL? .(Nov/Dec 2012)
One way to reduce saturation delay time is with schottky TTL. The idea is to fabricate a schokky
diode along with each bipolar transistor of a TTL circuit. Because the schokky diode has a forward

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voltage of only 0.4V, it prevents the transistor from saturating fully. This virtually eliminates
saturation delay time, which means better switching speed.
10.List the salient features of ECL family. .(Nov/Dec 2012)
1. It is a nonsaturating logic. That is, the transistors in this logic are always operated in the active
region of their output characteristics. They are never driven to either cut-off or saturation,
whichmeans that logic LOW and HIGH states correspond to different states of conduction of
variousbipolar transistors.
2. The logic swing, that is, the difference in the voltage levels corresponding to logic LOW and
HIGHstates, is kept small (typically 0.85 V), with the result that the output capacitance needs to
becharged and discharged by a relatively much smaller voltage differential.
3.The circuit currents are relatively high and the output impedance is low, with the result that
theoutput capacitance can be charged and discharged quickly.
11.Which logic family performs better in a high-noise environment : CMOS or TTL? Why?
(May/June 2013)
CMOS performs better in a high-noise environment because CMOS has extremely low power
consumption and high noise immunity. It can operate in devices operated in noisy environments, such
as industrial plants.
12.What is the main advantage of ECL over other IC technologies? In what type of application
should ECL not be considered? (May/June 2013)
ECL's major disadvantage is that each gate continuously draws current, which means it requires (and
dissipates) significantly more power than those of other logic families, especially when quiescent.
ECL has a poor speed-power product, does not provide a high level of integration, has fast edge rates
requiring design for transmission-line effects in most applications
13.Classify the logic family by operation?
The Bipolar logic family is classified into Saturated logic and Unsaturated logic.
The RTL, DTL, TTL, I2L, HTL logic comes under the saturated logic family.
The Schottky TTL, and ECL logic comes under the unsaturated logic family
14.Mention the classification of saturated bipolar logic families.
The bipolar logic family is classified as follows:
RTL- Resistor Transistor Logic
DTL- Diode Transistor logic
I2L- Integrated Injection Logic
TTL- Transistor Transistor Logic
ECL- Emitter Coupled Logic
15.Why NAND and NOR gates are preferred over AND and OR logic gates(May/June 2014)
They are called universal gates as they can be used to design all other logic circuit elements like
XOR,NOR,etc. also these gates can be realized through easy combination of diodes thus making them
easy to use base elements in any chip designing project. With a combination NAND and NOR gates
alone, it's possible to create all other logic gates like AND, OR, XOR etc and you can design any logic
circuit.
16. Which is faster TTL or ECL? Which requires more power to operate?(May/June 2014)
ECL is fastest among because the transistors are used in difference amplifier configuration, in which
they
are
never
driven
into
saturation
and
thereby
the
storage time is eliminated. ECL's major disadvantage is that each gate continuously draws current,
which means it requires (and dissipates) significantly more power than those of other logic families,
especially when quiescent. ECL has a poor speed-power product, does not provide a high level of
integration, has fast edge rates requiring design for transmission-line effects in most applications
17. How schottky transistors are formed and state its use?
A schottky diode is formed by the combination of metal and semiconductor. The presence of schottky
diode between the base and the collector prevents the transistor from going into saturation. The
resulting transistor is called as schottky transistor. The use of schottky transistor in TTL decreases the
propagation delay without a sacrifice of power dissipation.
18. Why totem pole outputs cannot be connected together.
Totem pole outputs cannot be connected together because such a connection might produce excessive
current and may result in damage to the devices.
19. State advantages and disadvantages of TTL
Adv: Easily compatible with other ICs, Low output impedance
Disadv: Wired output capability is possible only with tristate and open collector types
Special circuits in Circuit layout and system design are required.
20. What are the types of TTL logic?

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1. Open collector output
2. Totem-Pole Output
3. Tri-state output.
PART B
1.(i) With neat sketch explain the operation of a two input TTL NAND gate.(10)
(ii) What are totem pole and open collector outputs?(6) (May/June 2012)
2.Explain the features of (i) ECL and (ii) I2L (May/June 2012)
3.Draw the circuit diagram of two inputs TTL NAND gate and explain its operation. Also explain TTLto-CMOS interface. (Apr/May 2011)
4.Draw the circuit of CMOS inverter and explain its operation. Also explain CMOS-to-TTL interface. .
(Apr/May 2011)
5.(i) Explain the transfer characteristics of CMOS gate.(8)
(ii)What are the different ways to drive a TTL load? With a schematic diagram discuss on any two
types of drive. (8) (Nov/Dec 2012)
6.(i) Discuss in detail on CMOS-TO-TTL interface.(10)
(ii)Show how the three-state buffer is used in design of computer buses.(6) (Nov/Dec 2012)
7. Draw the circuit diagram of two input TTL NOR gate and explain its operation. Also explain TTLTO-CMOS interface. (May/June 2013)
8.Draw the circuit of CMOS inverter and explain its operation. Also explain the precautionary steps
that one has to observe in handling CMOS devices. (May/June 2013)
9.Design and Describe a 8 bit carry look ahead adder using NMOS and ECL logics(May/June 2014)
10.Design a 4:1 Mux using TTL and CMOS logics. Assess their performances in terms of number of
devices used ,delay time and power consumption. Also discuss about TTL to CMOS
interface.(May/June 2014)

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UNIT II-PROGRAMABLE LOGIC DEVICES
PART A
1.State the difference between PLA and PAL (May/June 2012)
S.No PAL
PLA
1.
And array is programmable and OR Both AND and OR arrays are is
array is fixed
programmable.
2.
Function can be easily implemeted
Costliest and complex than PROMs.
2.Implement the following function using a suitable decoder and an OR gate
F(A,B) = (0,1,2) (May/June 2012)
Use 2 x 4 decoder. The inputs of the decoder is represented with A& B. The outputs of the
decoder is represented with 0,1,2 & 3. The output lines 0,1 & 2 are given to 3 input OR gate. The
output of the OR gate represent function F. (Diagram can be drawn with this information)
3.Give the advantages of PAL over PLA (Nov/Dec 2011)
* Less board space
Fewer printed circuit board
Smaller enclosures
Lower power requirements(i.e. smaller power supplies)
Faster and less costly assembly processes
Higher reliabilty(fewer ICs and circuit connections=>easier troubleshooting)
Availability of design software
Increase in speed
Better security(copying is less likely to take place)
Low production cost as compare to PLA
More flexibility to designer
Modification can be carried out within a short span of time
Implementation of combinational and sequential circuits can be done with the help of PAL.
For given internal complexity, a PAL can have larger inputs and implement a number of
functions.
4.Compare FPGA and CPLD (Nov/Dec 2011)
COMPLEX PROGRAMABLE LOGIC DEVICE(CPLD) has less gate count as it is made of
EPROM,flash technologies.
FIELD PROGRAMABLE GATE ARRAY(FPGA) are large gate count devices and is made of
SRAM, antifuse technologies. Hence their architecture is also different.
5.What is the function of a decoder? .(Nov/Dec 2012)
A decoder is a circuit that changes a code into a set of signals. A common type of decoder is
the line decoder which takes an n-digit binary number and decodes it into 2ndata lines.
6.How does a PLA differ from PAL? .(Nov/Dec 2012)(May/June 2014)
In PLA both AND gate and OR gates are programmed whereas in PAL only AND gates are
programmable but it is less flexible than PLA
7.List two advantages of programmable logic over fixed function logic. (Apr/May 2011)
(May/June 2013)
Programmable logic devices offer a number of important advantages over fixed logic devices,
including:
Design Flexibility: PLDs offer customers much more flexibility during the design cycle because
design iterations are simply a matter of changing the programming file, and the results of design
changes can be seen immediately in working parts.
Improved Reliability :Lower power plus fewer interconnections and packages translate
into
greatly improved system reliability.
Lower Power: CMOS and fewer packages combine to reduce power consumption.
Reduced complexity: Since PLDs consume lower power requirements less board space
simpler testing procedures .
PLDs are field- programmable i. e., can be programmed outside of the manufacturing
environment
PLDs are erasable and reprogrammable.i.e allows updating a device or correction of errors and
allows to reuse the device for a different design the ultimate in re-usability!
8.What does CPLD stand for? How is it different from the term PLD(Apr/May 2011)
,(May/June 2013)

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CPLD is a collection of individual PLDs on a single chip, with a programmable
interconnection structure that allows the PLD to get connected as the user wants. The sub blocks IOblocks, PLD blocks, and programmable interconnect
9.List the features of PLD .
No customized mask layers or logic cells
Fast design turnaround
A single large block of programmable interconnect
A matrix of logic macro cells that usually consist of programmable array logic followed by a
flip flop or latch.
10.What are the types of PLDs.
ROM, PROM, EPROM, EEPROM, UVPROM., Masked ROM, PAL,PLA etc.
11.Essential features of FPGA.
None of the mask layers are customized
Has a method for programming the basic logic cells & interconnect
The core is a regular array of programmable basic logic cells that can implement both
combinational & sequential logic
A matrix of programmable interconnect surrounds the basic logic cells
Programmable I/o cells surround the core
Design turnaround is few hours.
12.What is PLD?
A digital integrated circuit that can be programmed by the user to implement any digital logic
function .
13.What is CPLD? List a few CPLD Devices?(May/June 2014)
CPLD's have a much higher capacity than simple PLDs, permitting more complex logic circuits
to be programmed into them. A typical CPLD is equivalent of from 2 to 64 simple PLDs. The
development of these devices followed simple PLD as advances in technology permitted higher density
chips to be implemented. There are several forms of CPLD, which vary in complexity and
programming capability. CPLDs typically come in 44 to 160 pin packages depending on the
complexity.
14. What is FPGA?
FPGA are different from simple PLDs and CPLDs in their internal organization and have the
greatest logic capacity. FPGAs are consists of an array of anywhere from 64 to 1000s of logic gate
groups that are sometimes called logic blocks. Two basic classes of FPGAs are fine grained and course
grained .The course grained FPGA has large logic blocks and fine grained FPGAs has much smaller
logic blocks. FPGAs are come in packages up to 1000 pins are more.
15.What is PAL & PLA?
Programmable Array Logic (PAL), has programmable logic with a fixed OR matrix and
programmable AND matrix
Programmable Logic Array (PLA), has programmable logic with a programmable OR matrix
and programmable AND matrix.
16.Why was PAL Developed?
To overcome certain disadvantages of PLA , such as longer delays due to additional fusible
links that results from using two programmable arrays and more circuit complexity.
17.Why the input variables to PAL are buffered?
To prevent loading by the large number of AND gate inputs to which available or its
complement can be connected.
18.What type of gate is used as programmable inversion in FPGAs?
EX-OR gates are used for programmable inversion in FPGAs
19.Mention the application of ROM devices.
It is used to design combinational logic circuits based on their truth tables.
20Give the comparison between PROM and PLA.
S.No PROM
PLA
1.
And array is fixed and OR array is Both AND and OR arrays are is
programmable
programmable.
2.
Cheaper and simple to use.
Costliest and complex than PROMs.

PART B
1.Realize the following function using (i) PAL and (ii) PLA (8 + 8)

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F(A,B,C,D) = m(0,2,5,7,8,10,11,14) (May/June 2012)
2.(i)Implement the following function using suitable multiplexer F(A,B,C)= m(0,2,4,6) (8)
(ii)Design a two bit up counter using D Flip Flops and implement it using suitable PAL(8)
(May/June 2012)
3.(i) Design a circuit that realizes the following three functions using a decoder and three OR gates (8)
(Nov/Dec 2011)
F1(A,B,C) = m (1,3,7) , F2 (A,B,C) = m (2,3,5) F3 (A,B,C) = m (0,1,5,7)
(ii) Use 4 x 1 multiplexer to implement logic function f(x1,x2,x3) = m (0,1,6), choosing x1 and x3
as select inputs. (8) (Nov/Dec 2011)
4.(i) Explain the design of combinational and sequential logic circuits using PLA with an example (8)
(Nov/Dec 2011)
(ii) How is FPGA useful in the implementation of logic circuits? (8) (Nov/Dec 2011)
5.Realize the sum of product expression Y = m(0,5,10,15) using 8:1 multiplexer. Draw a ROM
circuit that produces the following outputs.
Y0 = ABC + ABC + A(BC) + ABC
Y1 = ABC + ABC + ABC and Y2 = ABC + ABC (APR/MAY 2011)
6.(i) Implement the function F = (x1,x2,x3,x4) = (0,1,3,4,8,9,15) with multiplexers where the
following variables are connected in the specified order to selection lines s2,s1,s0 respectively.(8)
(1) x1,x2,x3
(2) x2,x3,x4
(ii)Compare a ROM implementation with a PLA implementation of the circuits with output
function. F1 (0,1,6,7) =
F2 (1,3,5,6,7) =
F3 (1,2,3) =
(8) (Nov/Dec
2012)
7.(i) Explain the schematic design of programmable interconnect and basic logic element of typical
FPGA. (8)(May/June 2014)(16)
(ii)Discuss on the design of hexadecimal counter using PLAs and flip flops.(8) (Nov/Dec 2012)
8.Realize the sum of product expression Y = m(0,5,10,15) using 8:1 multiplexers. (May/June 2013)
9. Write short notes on:
(i) Field programmable gate array.
(8)
(ii)EPROM
(8)
10.(i) With Example Illustrate how multiplexers can be used to realize logic functions(6)
(ii)Realize the following set of simultaneous equation using PAL,PLA and PROM.Compare these
Programming Technologies(10)
F1(W,X,Y,Z)=XYZ+WXY+WYZ
F2(W,X,Y,Z)=XYZ+WXYZ+WYZ+XYZ
F3(W,X,Y,Z)=XYZ+XYZ+WXYZ (May/June 2014)

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UNIT III- DIGITAL MEMORIES
PART A
1.What are the different types of memory? (May/June 2012)
Based on access type: Random access, Sequential access
Based on physical characteristics:ROM, RAM, PROM, EPROM, EEPROM
Based on fabrication technology: Bipolar memory devices, Unipolar memory
devices.
2.Define Read and Write operations (May/June 2012)
It is simply defined as , storing data into the memory is called WRITE operation. Taking data
from the memory is called READ operation.
3.Compare between SRAM and DRAM( Nov/Dec 2011) , (Nov/Dec 2012) ,(May/June 2014)
Static RAM
Dynamic RAM
Flip-flop is the basic element of Capacitor is the basic element of
static RAM
dynamic RAM
Data is stored in terms of voltage
Data is stored in terms of charge
Contains less memory cells per unit Contains more memory cells per unit
area, i.e.density is low.
area, i.e.density is high.
Access time is less.Static memory is Access time is more.Dynamic
faster than dynamic. RAM
memory is slower than static RAM.
Cells composed of TTL or Cells composed of MOSFET.
MOSFET.
Refereshing circuit is not required.
Refereshing circuit is required.
Cost is ess.
Cost is high.
Power consumption is less.
Power consumption is more.
4.What is the advantage of EPROM over PROM? ( Nov/Dec 2011)
PROM: Programmable Read Only Memory user can program (write) the PROM through
special PROM programmer. It can be written (programmed) once only, user cannot rewrite this
memory.
EPROM : Erasable Programmable ROM. This memory stores a bit by charging the floating gate
of an FET. The chip can be reused may times i.e., user can write this memory many time. Erasing is
done using UV light through a window over the memory chip called quartz window. Erasing process
cannot be done byte by byte or block by block, entire information will be erased at once,- after
exposing the ROM in U.V. light. Therefore, erasing process is slower and time consuming it takes 15
to 20 minutes.
5.Determine the number of inputs, the number of outputs, and the type of output for each of the
following PAL part number (a) PAL 12H6 (b) PAL 16L2 (Apr/May 2011)
(a) PAL 12H6 - 12 inputs , 6-outputs, type of output: Active high
(b) PAL 16L2 - 16 inputs , 2-outputs, type of output: Active low
6.What would be the structure of the binary address for a memory system having a capacity of
1024 bits? (Apr/May 2011), (May/June 2013)
Address bus width = 10
(2no.of address lines=Memory capacity)
Address range or Structure:
Low bits:00 0000 0000
High bits:11 1111 1111
7.List different types of ROMs available and their application areas. . (Nov/Dec 2012)
There are five different types of ROM's available. They are
1.Masked ROM mainly used to distribute firmware
2.PROM These types of memories are frequently seen in video game consoles, mobile phones,
radio-frequency identification (RFID) tags, implantable medical devices, high-definition multimedia
interfaces (HDMI) and in many other consumer and automotive electronics products.
3.EPROM widely used in Personal Computers
4.EEPROM real-time clocks, digital potentiometers, digital temperature sensors
5.Flash ROM personal computers, PDAs, digital audio players, digital cameras, mobile phones,
synthesizers, video games, scientific instrumentation, industrial robotics, medical electronics
8.Mention two differences between PLD and ROM. (May/June 2013)
PLD can be considered as PLA
1. In PLA both AND and OR arrays are configurable unlike in ROM, whereas only the OR gates
array is configurable.

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2. PLA has the capability to take dont care terms (Boolean overlaps) into account in which ROMs
are incapable.
3. ROM has all the combinations of product terms, and therefore, considered as the most general
purpose combinational logic device in contrast to PLA, which doesnt have all the combinations.
9.What is a FIFO Memory?(May/June 2014)
FIFO, or First In, First Out, is a method that relates to the organization and manipulation of
data according to time and prioritization. In essence, the queue processing technique is done as per a
first-come, first-served behaviour. The algorithm of the operating system scheduling gives every
process CPU time according to the order it comes. Each item is stored in a queue data structure. The
first data which is added to the queue will be the first data to be removed. Processing continues to
proceed sequentially in this same order. FIFO is used for synchronization purposes in computer and
CPU hardware. FIFO is generally implemented as a circular queue, and thus has a read pointer and a
write pointer. A synchronous FIFO uses the same clock for reading and writing. An asynchronous
FIFO, however, uses separate clocks for reading and writing.
10.What is RAM,SRAM , DRAM & MROM?
RAM: A type of memory device where the data can be accessed in any order (randomly), the
term usually refers to random access read/write memory.
SRAM:A RAM that can retain data indefinitely as long as electrical power is available to the
chip.
DRAM: A RAM that can not retain data for more than a few milliseconds without being
refreshed.
MROM:A type of memory where the stored data are permanently stored into the memory
device during the manufacturing process
11.What is flash memory?
A non volatile type of memory that can be programmed and erased in sectors, rather than at a
time.
12. What is ROM?
Read Only Memory is a memory is a memory device in which, permanent binary information is
stored. The binary information must be specified by the designer and is then embedded in the unit to
form the required interconnection pattern stays within the unit, even when the power is turned off and
on again.
13. What is access and cycle time.
The access time of memory is the time required to select a word and read it. The cycle time of
memory is the time required to complete a write operation.
14.Differentiate volatile and non-volatile memory?
Volatile memory
Non-Volatile memory
They are memory units which lose storedIt retains the stored information when power i
information when power is turned off.
turned off.
eg. DRAM
eg. Magnetic disc and ROM.
15.Mention some applications of EEPROM?
The EEPROM is used to store data permanently and can be quickly erased.This property of the
EEPROM makes it useful in
-Microcontrollers, USB storage devices, Home appliances, Calculators and digital diaries.
16. What are the advantages of RAM?
The advantages of RAM are
a. Non-destructive read out
b. Fast operating speed
c. Low power dissipation
d. Compatibility
e. Economy
17. Define address and word:
In a ROM, each bit combination of the input variable is called on address. Each bit
combination that comes out of the output lines is called a word.
18.Explain DRAM?
The dynamic RAM (DRAM) is an operating mod, which stores the binary information in the
form of electric charges on capacitors.
The capacitors are provided inside the chip by MOS transistors.
The stored charges on the capacitors tend to discharge with time and the
capacitors must be tending to discharge with time and the capacitors must be

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periodically recharged by refreshing the dynamic memory.
DRAM offers reduced power consumption and larger storage capacity in a
single memory chip.
19.Explain SRAM?
Static RAM (SRAM) consists of internal latches that store the binary information. The stored
information remains valid as long as the power is applied to the unit. SRAM is easier to use and has
shorter read and write cycle.The memory capacity of a static RAM varies from 64 bit to 1 mega bit.
20.Explain EPROM?
EPROM is MOS circuitry the stored data can be erased by exposing the chip to UV light via
its quartz window for 15 to 20 minutes. It is not possible to erase selective information.
PART-B
1.(i) What is a ROM? Draw the ROM cell and explain its operation (8)
(ii) Explain the operation of SRAM and DRAM (8) (May/June 2012)
2.What is Memory expansion? Construct a 2K x 8 memory from 1K x 8 memories (May/June 2012)
3.Draw a basic logic diagram for a 512 x 8 bit static RAM., showing all the inputs and outputs. Also,
memtion the capacity of a DRAM that has twelve address lines. (Apr/May 2011)
4.Give two valid differences between SRAM and DRAM. Use 16k x 8 DRAM to build 64k x 8
DRAM, show the logic diagram (Apr/May 2011)
5.(i) Discuss on the design of 64 x 64 memory.(8)
(ii)Show how two 16 x 4 memory can be connected to implement 16 x 8 memory.(4)
(iii)Comment on programming of ROMs.(4) (Nov/Dec 2012)
6.(i) Demonstrate with a timing diagram, the access time of PROM.(4)
(ii)How many address lines are required for a memory that has following number of bits?
(1) 1024
(2) 4098
(3) 256
(4) 16,384
(4)
(iii)With a typical three-transistor DRAM cell explain the Read and write operation with timing
diagram. (8) (Nov/Dec 2012)
7.Draw a basic logic diagram for a 256 x 8 bit static RAM, showing all the inputs and outputs. Also,
mention the capacity of a DRAM that has twelve address lines. (May/June 2013)
8. Give two valid differences between SRAM and DRAM. Use 16k x 8 DRAM to built 64k V x 8
DRAM, show the logic diagram. (May/June 2013)
9.(i) Design a CMOS SRAM and describe its operation(8)
(ii) Draw the schematic diagram of a SRAM cell array and explain its operation(8) (May/June 2014)
10.(i) Design a 64x16 ROM using 16x4 ROM(8)
(ii) What are the salient features of EEPROM? Draw and explain the structure and programming of
EEPROM (8) (May/June 2014)

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UNIT IV- DIGITAL SYSTEM DESIGN CASE STUDIES
PART-A
1.What are the types of DVM? (May/June 2012)
Portable analog multimeter, Handheld DMM, Benchtop DMM
2.List any two advantages of Flash Memory(May/June 2012)
It is a improved version of EEPROM. In EEPROM erase and write operation at a byte level
whereas FLASH memory erase or write its data in entire blocks, which makes it a very fast memory
compared to EEPROM.It stores an electrical charge for extended period of time( 2 to 10 years) even
without connecting to power supply.
3.How do you initiate the A/D converter for its conversion? (Nov/Dec 2011)
An analog-to-digital converter (abbreviated ADC, A/D or A to D) is a device that converts
the input continuous physical quantity to a digital number that represents the quantity's amplitude.
4.How is the timing for a 4-digit display chosen if it has a repetition rate of 100 Hz? (Nov/Dec 2011)
An repetition rate of 100 Hz means all digits must be serviced once every 1/100=0.01seconds.
Dividing the time equally among the 4-digits means that each digit will be ON for 0.01/4=0.0025
seconds and OFF for 0.0075 seconds.
5.Draw the block diagram of a basic frequency counter (May/June 2013)

6.State the need for control waveforms in multiplexing days(May/June 2014)

In multiplexing displays , by means of control wave forms we can infer which input
is going as an output and which act as stand by.
7.What is PRBS generator?
A periodic test signal having noise- like properties, popularly termed as Pseudo Random
Noise has become increasingly as a substitute for random noise. Pseudo Random Binary Sequence
(PRBS) is one form of this noise which can be easily generated in laboratory. Noise is required
nowadays as a test signal.
8.What is Gaussian noise source?
Gaussian noise is required for testing analog systems. This noise is obtained by passing the
PRBS waveform through a suitable low-pass filter. The cut-off frequency of this filter has to be about
1/20 of the clock frequency of the PRBS generator so as to give a reasonably Gaussian characteristic
for the noise generated.
9.Suppose that the unknown input signal of basic frequency counter is a 7.50-kHz
square wave.What will the display indicate if the GATE ENABLE time is t=0.1s?
what if t=1,and then t=10s?
t=0.1s the counter will count up to 7500(transitions per second)x0.1(second)=750.
t=0.1s the counter will count up to 7500(transitions per second)x1(second)=7500.
t=0.1s the counter will count up to 7500(transitions per second)x10(second)=75,000.
10.What is multiplexing display?
Multiplexing is a technique used to reduce indicator power requirements.
11.Show how to multiplex a commonanode- type display.

12.Mention the application of Display units.

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D.C. excited plasma displays- Indicators, small, medium and large displays, small group viewing, flat
panel.Electro- luminescent displays- Indicators, small displays, flat panel.LED displays- Indicators,
small displays, flat panel.LC displays- Indicators, small displays, individual viewing, flat panel.
13.Mention some applications of PRBS generator.
For the evaluation of multichannel PCM systems, studies on biomedical phenonena, vibration testing,
aerodynamics, seismology.
14.Explain the meaning of an accuracy of plus or minus one count applied to the
Measurement in a frequency counter.Eg: Let the maximum count is 500.
Plus or minus one count means the display could read 499,500,501 after the measurement period.
15.Explain the DISPLAY ranges for the four-decimal-digit period measurement
instrument.
Eg: If the CLOCK pulses switched to the 1-micoseconds position , each count of COUNTER
represents 1micro-seconds.Therefore full scale of 99991micro-seconds.
16. An ADC3511 is connected with a reference voltage of +2V dc. What will be the duty
Cycle held in the counter for an analog input of 1.25V dc? (May/June 2013),(April/May 2011)
DUTY CYCLE=Vi/Vref = 1.25/2.00 = 0.625
17.What happen if the pulse width is decreased in the multiplexing display?
As the pulse width is decreased, the display brightness will also decrease.
18.What does the terms SPAN and offset mean with reference to ADC? (Nov/Dec 2012)
AV = DN * Step Size + Offset = (DN / 2n )* Span + Offset
DN = (AV - Offset) / Step Size = (AV - Offset) * 2n / Span
Offset: minimum analog value
Span (or Range): difference between maximum and minimum analog values Max - Min
19.What is the basic difference between time and frequency measurement? (Nov/Dec 2012)
Time is the marking of an event with respect to a reference origin. A time interval is a measurement of
duration. The time of an event might be measured by hours, minutes, seconds, and a calendar date,
while a time interval might be measured by the number of seconds between two events.
Frequency is the measure of the number of events that occur within a time interval, such as the number
of oscillations of a voltage waveform within one second
20.List the features of flash memory.(May/June 2014)
Flash memory is an electronic non-volatile computer storage medium that can be electrically
erased and reprogrammed. Flash memory is a type of electronically erasable programmable read-only
memory (EEPROM), memory chips that retain information without requiring power. (This is different
from flash RAM, which does need power to retain data.) Regular EEPROM erases content byte by
byte; most flash memory erases data in whole blocks, making it suitable for use with applications where
large amounts of data require frequent updates
Flashprovides nonvolatile storage.The contents of flash may be overwritten.
PART-B
1. Discuss in detail about the operation of a Digital Voltmeter with neat sketch (May/June 2012)
2. (i) With an example, explain the PRBS generator (8)
(ii)Write a note on time and frequency measurement.(8) (May/June 2012)
3. (i) With a neat block diagram explain the working of frequency counter(8)
(ii)Discuss on multiplexing displays using common-anode and common-cathode type LED sevensegment indicator(8) (Nov/Dec 2011)
4. With a neat diagram explain how will you construct four decimal digit time period measurement
instruments. (Apr/May 2011).
5. Discuss in detail on : (i) Multiplexing of Displays (8) (ii) Time measurement (8) (Nov/Dec 2012)
6. (i) With a neat circuit diagram explain the functionality of digital voltmeter. (8)
(ii)With the circuit diagram explain the operation of 4-bit PRBS generator. Give the PRBS output
for continous 16 clock cycles. (8) (Nov/Dec 2012)
7. With a neat functional diagram explain four decimal digit multiplxed display. (May/June 2013)
8. Explain in detail the design of digital voltmeter. Mention few factors that decide the resolution of
the digital voltmeter (May/June 2013)
9.(i) Explain the design aspects and digital logic implementation of PRBS Generator(8)
(ii) How are displays multiplexed and interfaced?(8)(May/June 2014)
10.Describe the digital logic implementation of electronic frequency counter and analyze its
performance measures(16) (May/June 2014)

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UNIT V-DESIGN FOR TESTABILITY
PART A
1.
What is testability?
Testability is a design characteristic that influences various cost associated with testing. It allows :
1)The status of the device (normal inoperable, degraded) to be determined.
2)isolation of the faults within the device to be performed quickly.
To reduce the test time and cost , the cost effective development of the tests to be
determine this status.
2.
Mention the two important attributes related to testability.
The controllability and observability.
3.What is the impact of accessibility on testing?
Sequential logic is much more difficult than combinational logic.
Control logic is more difficult to test than data-patch logic.
Random logic is more difficult to test than structured, bus- oriented designs.
Asynchronous designs are much more difficult to test than synchronous design.
4.Give short notes on Ad Hoc design for testability techniques.
Ad Hoc design for testability does not follow any algorithmic procedure for testing. They do
not deal with a total design methodology that ensures ease of test generation, and they can be used at
the designers option where applicable. Their goal is to increase controllability, observability, and/or
predictability.
5.Explain the concepts of DFT testing techniques?
Test points
Initialization
Monostable multivibrators
Oscillators and clocks
Counters /Shift registers
Partitioning large circuits
Logical redundancy
Breaking global feedback paths
6.What is the need of Scan registers?
By using test points one can easily enhance the observability and controllability of circuit. But
enhancement can be costly in terms of I/O pins. Another way to enhance the observability and
controllability is by using a Scan Register (SR). The use of scan registers to replace I?O pins deals
with a trade off between test time, area overhead, and I/O pins.
7.What are the types of Scan designs?
There are several forms of scan designs; they differ primarily in how the scan cells are designed.
Three generic forms of scan designs are
Full Serial Integrated Scan
Isolated serial Scan
Nonserial Scan
8Define Predictability.
Predictability is the ability to obtain the known output values in response t to given input stimuli.
9.What is test access port. Mention its significance (May/June 2014)
A tap (an acronym for Test Access Port) is used to create a permanent access port for passive
monitoring of a network. The TAP lines are responsible for sending the proper signal
sequences to control the scanning or testing states.
10.Define controllability and observability(May/June 2012)
Controllability is the ability to establish a specific signal value at each node in a circuit by
setting values on the circuits inputs.
Observability is the ability to determine the signal value at any node in a circuit by controlling the
circuits inputs and observing its outputs.
11.Give the importance of testability measures.
Testability figures can guide the designers to improve the testability of their circuits.
Test generation algorithms using heuristics usually apply a kind of testability measure to their
heuristic operations (e.g., in making search decisions).
Controllability is the ability to establish a specific signal value at each node in a circuit by
setting values on the circuits inputs.
Observability is the ability to determine the signal value at any node in a circuit by controlling

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the circuits inputs and observing its outputs.
12.What do you infer from controllability in a digital circuit? (Nov/Dec 2011)
It allows the designer to interact with the design and to change execution flows and infer the root
causes of circuit errors much more quickly.
13.When do we go for scan methods based testing? (May/June 2013), (Nov/Dec 2011)
In designing the modules such as complex chips or PCBs, it is often useful for purposes of
testing and fault isolation to be able to isolate one module from the others. This can be done using the
concept of boundary scan.
14.When is a circuit said to have poor random observability? (Apr/May 2011)
A circuit often has poor random observability if it requires a unique input pattern or a lengthy
complex sequence of input patterns to propagate the state of one or more nodes to the outputs of the
circuit.
15.Give the principle of scan based test techniques(May/June 2014)
Scan-path design is to reduce test generation complexity for circuit containing storage devices and
feedback path with combinational logic.The purpose is to Set any internal state easily and to Observe
any state through a distinguishing sequence.The principle of scan path is Each input to the FF is
considered an output of the combinatorial circuit and each output of the FF is an input to the circuit.
16.When is a circuit said to have poor random controllability?
A circuit node usually has poor random controllability if it requires a unique input pattern to
establish the state of the node. A node usually has poor controllability if a lengthy sequence of inputs
is required to establish its state.
17.What is Test vector?
An input combination in which the presence of a fault produces an output different from the
fault free output.
18.Mention some methods to generate test vectors.
Fault table method, ATPG algorithm , Path sensitization method etc.
19.Mention few electrical faults and logical faults (Nov/Dec 2012)
Logical Faults are: Single/multiple stuck-at (most used), CMOS stuck-open, CMOS stuck-on,
AND / OR Bridging faults
Electrical faults are due to short, opens, transistor stuck on, stuck open, excessive steady state
currents, resistive shorts and open.
20.Define the term controllability and observability with respect to design for testing of logic
circuits. (May/June 2013)
1. Controllability - Being able to set up known internal states.
2. Combinatorial Testability - Being able to generate all states to fully exercise all combinations
of circuit states.
3. Observability - Being able to observe the effects of a state change as it occurs (preferably at the
system primary outputs)
PART -B
1.Explain the Generic Scan BASED Designs? (May/June 2012)
2.Discuss in detail about board level and system DFT approaches. (May/June 2012)
3.Discuss in detail about digital circuit testing by applying test vectors and by in-circuit testing
(Nov/Dec 2011)
4.(i)Discuss how scan methods are employed in testing to provide controllability and observability
(10)
(ii)Explain the system level DFT approach (6) (Nov/Dec 2011)
5.Explain the following Ad Hoc Design for testability techniques (i) Test points (ii) Initialization and
(iii) Oscillators and clocks. (Apr/May 2011)
6.Discuss on Ad Hoc testable design techniques (Nov/Dec 2012)
7.Discuss on scan-based technique with a suitable example (Nov/Dec 2012)
8.Explain the concept of (i) Full Serial Integrated Scan and (ii) Isolated Serial Scan (May/June 2013)
9.Explain in detail about various types of cross point fault that occur in PLAs and also explain how
test generation can be achieved in testing a PLA(16)(May/June 2014)
10.(i)Describe briefly the various DFT Schemes used in digital circuits (10)
(ii)Write a Technical Note on Adhoc design for testing techniques.(6)(May/June2014)

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