POLITEKNIK SULTAN HAJI AHMAD SHAH KUANTAN

DEPARTMENT OF ELECTRICAL ENGINEERING

DEE6113 CMOS IC DESIGN

Practical Work 5

Layout Design and Simulation of Exclusive

OR (XOR) Gates
Registration
No.

No

Name

Practical
Work Report
(Cognitive)

Practical Skill
Marks
(Psychomotor)

Total
Marks

1.

/ 30

/ 70

/ 100

2.

/ 30

/ 70

/ 100

CLASS

LECTURER NAME

: PN. NOORFOZILA BINTI BAHARI

DATE SUBMITTED

(Note: Submit this page along with the practical skill rubric after each Practical Work is completed)

Practical Work Report Marks Distribution

Report format:
1.

Title and Outcomes

/4

2.

Result

/ 14

3.

Discussion

/8

4.

Conclusion

/4
TOTAL :

/ 30

DEE6113 CMOS IC Design

PRACTICAL WORK 5
5.1 TITLE :

Layout Design and Simulation of XOR Logic Gate.

5.2 LEARNING OUTCOMES

At the end of this practical work session, the student should be able to:
a. design the layout of 2 input XOR gate.
b. simulate the layout of 2 input XOR gate.
c. design the layout of IC 4070 (XOR gate IC).

5.3 EQUIPMENT/TOOLS
PC Set & Microwind 2.6a software

5.4 THEORY
1. The output of XOR gate is high when either of inputs A or B is high, but the output is
low if both A and B are low/high.

Figure 5.1 : XOR gate

Figure 5.2 : XOR gate truth table

2. From the truth table, the Boolean equation is:

Out =
= AB

5.5 PROCEDURE
Part A : Designing the layout of 2-input XOR gate
1. Based on the Boolean equation of XOR gate, draw the CMOS static logic diagram of XOR
gate.

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DEE6113 CMOS IC Design

Figure 5.3 : XOR gate static logic diagram

2. From the CMOS static logic diagram you have drawn in (1), draw a stick diagram of 2-input
XOR gate using Eulers path method.

Figure 5.4 : 2-input XOR gate stick diagram

3. Open the Microwind Editor window.
4. Select the Foundry file from File menu. Select cmos012.rul file.
5. Draw the layout of 2 input XOR gate based on the stick diagram in Figure 5.4.
Use : NMOS size - W=6, L=2
PMOS size - W=12, L=2
6. The layout of 2-input XOR gate is shown in Figure 5.5.

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DEE6113 CMOS IC Design

Figure 5.5 : 2-input XOR gate layout

7. Run DRC. Make sure that the layout conforms to all the design rules.
Part B : Simulating the layout of 2-input XOR gate .
1. Add clock to input A and input B of the layout. To observe the output, add Visible Node icon
at the output.
2. Save your layout.
3. Simulate the inverter layout. Get the the timing diagram of the 2-input XOR gate. The
timing diagram fo 2-input XOR gate is shown in figure 5.6.

Figure 5.6 : 2-input XOR gate timing diagram

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DEE6113 CMOS IC Design

4. Produce a truth table of 2-input XOR gate based on the timing diagram produced in step 3.
5. Measure the optimized area of the layout (the unit is lambda2).

Part C : : Designing the layout of IC 4070 (XOR gate IC).

1. Design the layout of IC 4070 based on the CMOS IC logic gates shown in figure 5.7.

Figure 5.7 : Internal Structure of IC 4070 Quad XOR Gate

2. Do the DRC to ensure that your design follows all the design rules.
3. Measure the optimized area of the layout (the unit is 2).

5.6 RESULTS
In your report, include the results for the following:
1. the CMOS static logic diagram of 2-input XOR gate (show all the steps how to get the logic
diagram).
(2 marks)
2.

the stick diagram of 2-input XOR gate using Eulers path (show all the steps how to get the
stick diagram).
(2 marks)

3.

the layout of 2-input XOR gate (without any DRC error).

(2 marks)

4.

the timing diagram of 2-input XOR gate.

(2 marks)

5.

a truth table of 2-input XOR gate based on the timing diagram produced.
(2 marks)

6. the layout of IC 4070 (without any DRC error).

7.

the optimized area of the IC layout (the unit is 2).

(2 marks)
(2 marks)

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DEE6113 CMOS IC Design

5.7 DISCUSSION
1.

What is the function of XOR gate in digital circuit?

(2 marks)

2.

Draw an equivalent circuit for 2-input XOR using only three basic gates ( NAND, OR and
NOT gate).
(4 marks)

3.

Produce a truth table for a 3-input XOR gate.

(2 marks)

5.8 CONCLUSON
Write TWO (2) conclusions for the practical work that you have done.
(4 marks)

Page | 5

DEE6113 CMOS IC Design

PRACTICAL SKILL ASSESSMENT RUBRIC

DEE6113 CMOS IC DESIGN
PRACTICAL WORK 5
Student Name :

Class :
Date :

Student ID# :

ASPECTS

A.

Technology feature

B.

Design rule

C.

Transistor size

D.

Metal layers

E.
F.

No DRC error
display
Layout Design
input / output /
floorplan

EXCELLENT
4-5
Use correct technology feature
for ALL parts of the layout.
Follow lambda design rule for
minimum width and spacing for
ALL polygons.
Use correct PMOS and NMOS
transistor size.
Use correct number of metal
layers and width.
Able to produce No DRC error
display for ALL layouts.

SCORE DESCRIPTION
MODERATE
2-3
Use correct technology feature
for parts of the layout.

POOR
1

SCALE

Use other technology feature.

x1

Follow lambda design rule for

MANY of the polygons.

Follow lambda design rule for

ONLY a few of the polygons.

x1

Use acceptable PMOS and NMOS

transistor size.
Use correct metal layers but
incorrect width.
Able to produce No DRC error
display for some of the layouts.

Use incorrect PMOS and

NMOS transistor size.
Use incorrect metal layers and
width.
Not able to produce No DRC
error display at ALL.
Produce acceptable floorplan
and input / output layout
design.
Not able to produce any
simulation for ALL of the
layouts.
Produce large layout size (end
product).

Produce good floorplan and

input / output layout design.

Produce appropriate floorplan

and input / output layout design.

Layout simulation

Able to produce the simulation

of ALL layouts correctly.

Able to produce the simulation

for some of the layouts correctly.

H.

Layout size (end

product)

Produce small layout size (end

product).

Produce acceptable layout size

(end product).

TOTAL

SCORE

x2
x2
x2
x2

x2
x2
/ 70

..
Supervisor Name & Signature