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Career Episode

- Name

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Contents
CAREER EPISODE NARRATIVE 1..............................................................................2
CAREER EPISODE NARRATIVE 2..............................................................................3
CAREER EPISODE NARRATIVE 3..............................................................................3

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CAREER EPISODE NARRATIVE 1

4 Bit Ripple Carry Adder using NORA

Introduction
C.E.1.1
Chronology: January 2007- April 2007
Geographical location: <name of Organisation>
Title: Student (Bachelor in Electronics and Communication Engineering)
C.E.1.2
Due to my interest in IC (Integrated Circuit) design, in my final year of Bachelors in
Electronic and electronic and Communication Engineering at Sri Muthukumaran Institute
of Technology (Affiliated College of Anna University), Chennai, Tamilnadu, India. During
the final semester I gained the concepts of IC design using the Cadence tool. After
designing few basic circuits, the lecturer had assigned me a project to design a 4 Bit
Ripple Carry Adder using NORA (No Race) logic with the circuit functionality, low power
dissipation, speed and device count in my
Background
C.E.1.3
The Hierarchy of people involved:

Professor

Project Supervisor

Student

C.E.1.4
I was assigned to design a 4 Bit Ripple Carry Adder using NORA logic which is one of
the prominent low power design technique for digital circuits. CMOS (Complementary
Metal Oxide Semiconductor) logic has been known to have negligible static power
dissipation. However, this is valid as long as threshold voltage is not too low. Moreover, it
has low speed and consumes large area because of n-input; twice the number of
transistors is required. As a result, it is sometimes desirable to have faster and smaller
logic gates at the cost maybe of parameters such as noise margins, power dissipation

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etc. to overcome these disadvantages I had implemented a logic circuit style called
NORA-CMOS. It is constructed by cascading N and P blocks followed by C 2MOS
(Clocked CMOS) latch. It consists of alternating CLKNOT and CLK section. When
CLK=1 (evaluation mode in CLK section), the C 2MOS latches operates like an inverter.
When CLK=0, the latch moves into hold state because the output NMOS and PMOS
transistors are off. In this case, the old data is latched at the output. This latch is used to
avoid signal race.
C.E.1.5
As the given project was individual one, I had to implement 4 bit Ripple Carry Adder
with a low power design technique in this project so I started gathering information from
IEEE papers, journals regarding a low power technique and understanding the different
techniques like Static Logic, Domino Logic, and Pipelining etc and the differences in
between the techniques. The main objective of this project was to reduce the area of the
IC hence low power consumption with high speed. I had used Cadence analog artist to
implement this project which is a very famous tool for IC design. To complete the project
successfully I discussed with my project supervisor and divided this project into few
sections.
These are:
1.
2.
3.
4.
5.

Design an Inverter with full functionality.

Design a 1 Bit Adder using NORA logic.
Verify the functionality and optimize the 1-Bit Adder for low power and area.
Design the 4 bit Ripple Carry Adder.
Deal with the different cascading issues.

C.E.1.6
My duties included as follows
To understand the basic MOSFET (Metal Oxide Semi Conductor Field Effect
Transistors)-transistors operations and its performance parameters.
To Study the various aspects of the Cadence tool with reference to the design
and simulation.
Understanding the behavior of MOS transistors behavior with regards to change
of the different specific technology library files.
Understanding various low power design techniques and differences.
Mathematically calculate the values like transistors width and length ratio, tail
currents, node voltages etc
After making symbol of each block designing the 4 Bit Ripple Carry adder.
Simulating and analyzing the results of the design.
Discussion with the project guide on ways to improve the design and optimize
performance.
Preparing a project report to explain the circuit diagram based on low power
technique and its simulation result obtained.

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Personal workplace activity

C.E.1.7
I started off the project by studying the various low power design techniques and their
approach in digital domain. I chose the best technique by comparing the various aspects
of design that suit my requirements. To design the main circuit diagram, it had to be
design and simulate some different block like CMOS Inverter and one bit adder using
NORA logic. It combines C2MOS pipeline registers and NORA dynamic logic function
blocks. Each module consists of a block of combinational logic that can be a mixture of
static and dynamic logic, followed by a C 2MOS latch. Logic and latches are clocked in
such a way that both are simultaneously in either evaluation, or hold (precharge) mode.
A block that is in evaluation when CLK (clock) is 1 is called a CLK module, while the
inverse is called a CLKNOT module. A NORA data path consists of a chain of alternating
CLK and CLKNOT modules. While one class of modules is precharging with its output
latch in hold mode, preserving the previous output value, the other class is evaluating.
Data is passed in pipelined fashion from module to module.
C.E.1.8
As there are many digital circuits which work on combination logic and are very
commonly used in digital technologies. Hence, low power circuits reduce the cost of the
chip and attract customer to use the technology which plays a vital role in social and
economical environment. So, to implement this design I had to design each block very
carefully in terms of low power. To design a 1 bit adder I used the Karnaugh map
technique to simplify the equation. After implementing the equation in cadence tool I had
defined the values of the transistors width and length, pulse width and period and
applied on it to work the circuit properly. Once I got the correct output of the inverter and
1 bit adder then I made the symbol and cascaded to make the desired project as a
whole. Usually, in this logic if clock has low rise and fall times then both PMOS and
NMOS may conduct and there will be race problem. So, I had applied 6 times time
propagation delay of rise and fall time. After the execution the design I had simulated the
design to check and analyze the output.
C.E.1.9
The main objective of this project was designing 4 Bit Ripple Carry Adder with less
hungry of power, area and high speed. After simulation it was generating wrong output in
few states in the sum part and I was getting little glitches in the output of both parts that
consumes more power. I had frequent meetings with the project guide regarding
optimization and different method of implementation to overcome the problem. The
problem was that which signal is coming from the carry part of the PDN (Pull down
Network) node (as I designed) to the sum part that executes in the logic after arrival of
the clock signal. I had defined the delay and applied in the clock signal so that both
signal can arrive to the sum part at the same time . On the point of optimization, I had
given the attention to the propagation delay, rise time, fall time, power consumption
based on speed of incoming signals and different voltage supply. After optimization and
implementation through this 4 Bit Ripple Carry adder, I was getting the correct output of
every state. The simulation was done for minimum and maximum frequencies for
different voltage supplies. Power consumption was noted and was compared with every
other specification. This proved that the design had been correctly implemented and met
the main issue (Low Power Consumption) in respect of speed and voltage supply.

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C.E.1.10
As the other aim of the project was to reduce the area, by careful observation and by
guidelines of the project supervisor I reduced one transistor from each latch. The reason
is that during recharge phase (CLK=0), the output node of carrys and different nodes
are set to ground and VDD respectively. Thus the transistor NMOS of different part and
PMOS of carry part are turned off. As a result the clocked transistors can be removed
from the latch. Consequently this optimization provided to reduce the area, hence
reduced the power. Finally, I did my circuit working functionally correct and it consumes
450uW with the operating voltage of 2 V and the speed was 1.5 GHz. I used 150
transistors to design the 4- bit Ripple Carry Adder and successfully completed my
project.
C.E.1.11
In order to complete this project successfully I discussed with my project supervisor
frequently and I also discussed with him about process variation, time to market,
fabricate the chip in terms of business environment. Since this is a small module and this
circuit was consuming less power and less area with high speed, it was success in terms
of commercial and financial aspects.
Summary
C.E.1.12
The assigned project was successful, as the output and other constraints I achieved as
per the required specifications. After completing this project I made a detailed project
report and submitted it to the department and presented a seminar in front of the
supervisor and other students. I had explained the differences the NORA logic with other
low power design techniques. This project helped me to understand the low power
design approach which is widely used today in many different digital domains. I could
closely study the working of a technology currently in use.

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CAREER EPISODE NARRATIVE 2

Developing IVRS for xxxxxxxx
Introduction:
CE 2.1
In xxxxxxx , our utmost focus is laid on accuracy and quality assurance. During my term
in the organization as an engineer, my responsibilities included to design and develop
telecommunications and computer networking to augment the infrastructure for the rapid
growth of the Indian economy. This career episode summarizes the experience I have
gained during my employment has a engineer and I also took measures to mention
every detail about my experience in this report
Chronology: 25th May 2007 to February 25th 2009
Geographical location: XXXXXXX Private Limited
xxxxxxxxxxxxxxxxx
Kushaiguda, Hyderabad, India
Web: www.xxxxxxx.com

Background
CE 2.2
An IVRS is a unique blend of communication and software field. It is an electronic device
through which information is made available related to any topic about a particular
organization or process.IVR technology is extensively used in the area of
telecommunications. Nowadays, it is also being introduced in automobile systems for
hands free operation.
C.E.2.3
The policy in our organization is to strive for accuracy and develop quality and achieve
excellence. As the design of IVRS is based on communication and software fields, there
is a need to incorporate the best features in both of these streams.

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CE 2.4
For the efficient design of Interactive voice response system, a multidiscipline team was
formed in our organization. Coordination of work was established between the
development team and quality assurance team for improving the preciseness and to
make further technical corrections.
CE 2.5
I divided the whole process of design of an IVRS into two sections namely
1. Hardware section
2. Software section
Hardware Section
1) Relay: For switching between the ring detector and the DTMF decoder.
2) Ring detector: To detect the presence of incoming calls.
3) DTMF decoder: To convert the DTMF tones to 4 bit BCD codes.
4) Micro controller: To accept the BCD calls, process them and transmit them
serially to the PC.
5) Level Translator: To provide the interface between PC and micro controller.
6) Personal Computer: To store the data base and to carry out the text to speech
conversion.
7) Audio Amplifier: To provide audio amplification to standard output and to act as a
buffer between the telephone line and sound card.
Software Selection
1) Visual Basics 6.0
2) Oracle 8.0
3) Microsoft Agent

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CE 2.6
With the assistance of individuals having expertise in design, I assembled the hardware
and devised a suitable software programming code for integrating it with hardware.
C.E.2.7
The main aim of this project is to develop a user friendly and faster self service to speak
with customer service agents and also to reduce the cost of customer servicing.
My duties included as follows

To program the 8751 micro controller to control the operations of the IVRS like
switching a relay to the DTMF and sending a signal to the PC via RS232
To design a ring detector for detecting the ring of the telephone with the help of
op-amp 311
To send an input sign al to DTMF after blocking the DC in the line so that the
code is converted to 4 BCD digits.
To insert an audio amplifier as a buffer between the telephone line and the sound
card so that it protect the sound card from high voltage
To connect the telephone line to the ring detector with a relay,so that the call is
not processed by the micro-controller.
To develop a visual basic program for the serial transmission of the micro
controller to the PC via RS 232

PERSONAL WORKPLACE ACTIVITY:

CE 2.8
During the process of development, I assisted the involved team members in integrating
the components to build a device with easy and flexible interactive communication
features. I highlighted the technical circumstances and factors which can lead to failure
or the damage of the individual components in the device.
CE 2.9
In order to build a perfect automated system of IVRS , an analysis was done on the
callers demands and service requests. During this process, I identified the following
limitations with respect to IVRS.

Defects of the Public Switched Telephone Network (PSTN) is applicable to IVRS

also.
Visual basic, the software used is platform dependent.
In its present condition IVRS cannot be used in internet applications.
The security measures adopted are also not up to the mark.

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CE 2.10
Benefits of IVRS

The additions of speech recognition capabilities help IVRS owners derive more
benefit from their investment in existing IVRS resource.
Motivating organizations to embrace speech solutions is the potential for
dramatic reductions in operational cost.
Increased automation frees the customer service agents from any routine
administrative tasks and reduces cost related to customer service staffing. That is
fewer agents are able to serve more customers.
Resources that have been developed to support an internet presence can
support an IVRS as well. Thus organizations can use some of the same data
modules bid for speech enabled IVRS application for their intranets. This could
deliver a high degree of code reuse.

CE 2.11
An important phase in the development of IVRS is the programming of micro-controller.
The 8751 is the heart of the IVRS system. It controls the various operations of the IVRS
system. With proper programming of 8751, I ensured that micro controller takes
necessary measures for the functions of the computers in case of any damage or
malfunctioning.
CE 2.12
During the testing phase of the project, our team encountered technical difficulties in
software support. I interacted with the programming team and built a good coordination
between the developer and programmers to get an efficient response from the software.
I identified the interfacing problems (hardware and software) and strived to rectify them
by stabling a good synchronization between the two involved teams.
CE 2.13
Our company products compiles with constitutional and company policies, standards,
and procedures in respect of health, quality, safety and environment.
SUMMARY:
CE 2.14
My writing skills were utilized for providing technical documents like a procedure
document, User manuals which helped the end user understand about the product
C.E 2.15

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For the successful completion of the project, the coordination between different teams
played a major role. Each team was assigned a specific job as well as responsibilities
and deadline for its execution.
C.E.2.16
The final developed product met the global standards of proficiency and precision
C.E 2.17
During this process, I acquired knowledge about the various departments, mode of
working and levels of control. With the proper functioning and utilization of IVRS, any
company can meet the demands of its customers thereby increasing its growth in
business.

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CAREER EPISODE NARRATIVE 3

RAILWAY TRACTION
REMOTE TERMINAL UNIT

Introduction
CE 3.1 I was an engineer with 20months of work experience in xxxxxxxxxxxxxx Ltd.
This organization today spur on by the importance laid on telecommunications and
computer networking. I worked on the project xxxxxxxxxxxxxxxxxx (RTU) Model No:
9035 64\65 is essentially a Data Acquisition System with built-in control features
required for Supervisory Control and Data Acquisition (SCADA) applications. The
duration of the project was may25th 2007 to February 25th 2009.
Geographical location:

xxxxxxxxx Private Limited

xxxxxxxxxxxxx
Kushaiguda, Hyderabad, India
Web: www.xxxxxxxxxxxxx.com

CE 3.2 SCADA systems are designed to monitor and control geographically remote AC
Traction power system facilities for one or more control centers of Indian Railways. As an
engineer, I manage a team in performing the activities and validate the RTU functions
with the help of a simulator and corresponding software.
Background
CE3.3 In xxxxxxxxxxxxx Pvt Ltd, we manufacture network systems and accessories to
support the Data Transmission Network products. The xxxxxxxxxxxxxx deals with both
hardware and software aspects such as general hardware tests, isolated test for each
module and software tests.
CE3.4 I was focused on testing the RTU functionality, using the predefined procedures.
And to describe the steps to be followed to verify the specifications and reliable
performance of RTU The work involves updating the product status, indentify the errors,
testing, and things like that.
CE 3.5 What I did involved validating the units, check with the process control and keep
informing the failure nodes. With me representing the testing team I used to develop
control by utilizing all the available information to gain a better understanding of
processes such as:
failure modes and effective analysis
Connections to the HOST Simulator
Optimization Procedures
Electrical connectivity
routing
protection for internal wiring

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CE 3.6 My job included as follows,

To understand the basic RTU operations and also verify the specifications and its
reliable performance.
To Study the various aspects of the unit with reference to the design and
simulation.

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Use a wide range of tools, techniques, and equipment (including software)

appropriate to their specific discipline

To monitor the signals and their performance of the RTUs

Ability to assess and manage risks

Analytical in the formulation and solutions of problems

Understanding various design techniques and differences.

Check for all mechanical features of the unit completely

Test the power supply

Understanding the behavior of TSS, SP and SSP RTUs

Simulating and analyzing the results of the design.

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PERSONAL WORKPLACE ACTIVITY:

CE 3.7
Throughout my project, I was involved at every level of validationfrom hardware to
software tests and everything in between. This often helped me to know about the entire
specifications and implementation of the product. My main focus was to discover all the
problems identified which undergoing the phases in testing.
As the project was a team work, I used to perform the following activities to identify the
failures and their consequences, unit/process failure mode.
I am responsible to ensure the completion of the team activities

I prepared a document listing all the potential failure modes and the
manufacturing errors

I identified the causes of malfunctioning in power supply systems and Digital

input signal conditioning card

I developed new ways of testing the TVM functionality

I was responsible for the effective performance of the MODEM and the electrical
connectivity of the system

I developed the test procedure for the protocol implemented between HOST
(RCC) and RTU.

I too contributed to this project by reducing this calculated risk through corrective
actions.

CE 3.8
Benefits of RTU
RTU helps monitor and control geographically remote AC Traction power system

Validate an accurate probability of failure

Developed controls to eliminate dangerous failure modes, to eradicate system

failures.

Achieve better consistency

CE 3.9
The SCADA system was divided into three parts. These are Host system,
Communication Interfaces and Railway Traction Remote Terminal Unit (RTU). The RTU
is the Front-end device for acquiring the field data and providing recommended control

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action. The RTUs of the system are intelligent microprocessor based systems meant for
installation in the electrified section of Indian Railways at the controlled posts, one each
for traction sub stations and sectioning and paralleling.
CE 3.10
The main aim of this project was to validate all the functions of RTU. It included the
hardware testing, general testing, testing isolated units and finally testing the software
integrated with the product. Finally, I could complete my work implementing all the
general and isolated tests for a better functioning product. In addition this I was assigned
to check the functionality of the other supported devices like modem, Power supply, IED
and DOSC etc... And end the project successfully.
CE 3.11 For completing the project successfully, I discussed with my superior frequently
and I also discussed with him about procedure, implemented techniques to identify any
minute errors.
CE 3.12 Through the process of validating the techniques, we accomplished the
following goals:
Were able to reduce the product updates
Communicating with the senior project managers proved to be an excellent
technique in successful execution.
CE 3.13
For any non-compliance results, I would identify the source, check it and report to the
concerns. And all the products developed by Merritronix Pvt Ltd met the global standards
of proficiency and precision
Summary
CE 3.14
Meeting the time lines and the best quality was the main factor for a successful
implementation. Validating the controls and the hardware techniques of the Remote
terminal unit was done by me, but the complete team was responsible to meet the times
lines with a great valued product.
CE 3.15
We knew how to work as a team, plan, conduct good meetings, manage details, gather
useful data, analyze the data, communicate the results and implement changes. With
the commitment and involvement of my team members, I had the following advantages:
Increased tolerance to handle any complex tasks

14

Able to experience and learn new methods in testing or validating a unit

Effective communication to coordinate with the team activities

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