B.

TECH TITLES 2015

1.

Efficient Error Detection and Correction Using Decimal Matrix Code for Memory Reliability

2.

FPGA Based N-Bit LFSR To Generate Random Sequence Number

3.

Implementation Of High Speed Low Power Vedic Multiplier Using Reversible Logic

4.

UART Serial Communication Module Design and Simulation Based on VHDL

5.

Radix-8 Modified Booth Recorder For High Speed Add-Multiply Operator

6.

Design of High Speed Multiplier Using Vedic Mathematics Technique

7.

Convolution and Deconvolution Using Vedic Mathematics

8.

Efficient Computing Techniques using Vedic Mathematics Sutras

9.

Design and Implementation of Partial Reconfigurable Fir Filter Using Distributed Arithmetic
Architecture

10. Realization of LMS Adaptive Algorithm Using Verilog HDL For Low Complexity
11. Detection and Correction of Multiple Cell Upsets in Static Random Access Memories Using

Decimal Matrix Code

12. Design of Floating Point Multiplier Using Vedic Mathematics
13. Approximate Compressors for 32 X 32 Bit Multiprecision Multipliers
14. Error Detection and Correction in SRAM Cell Using Decimal Matrix Code
15. Analysis Of Various MCM Algorithms For Reconfigurable RRC Fir Filter
16. Design of ALU using reversible logic based Low Power Vedic Multiplier
17. A Novel Method for Area Efficient N-Bit Full Comparator Using Quantum-Dot Cellular

Automata
18. A Novel Approach for Parallel CRC Generation for High Speed Application
19. Reliability of Memory Storage System Using Decimal Matrix Code and Meta-Cure

20. Review of LP-TPG Using LP-LFSR for Switching Activities

21. Purpose of Low-Power Linear Feedback Shift Register (LFSR) by using Bipartite and Random

Injection Method for Low Power BIST

22. VLSI Implementation of ALU using Reversible Logic with Vedic Mathematics
23. Design Of Compact Reversible Low Power N-Bit Binary Comparator Using Reversible Gates
24. Design A Low Power eight-bit Reversible Parallel Binary Adder/Sub tractor
25. Design of Low Power Optimized Filter Architecture using VLSI Technique
26. Area optimization Technique for Multi-standard DUC
27. Design of Reversible Code Converters for Quantum Computer based Systems
28. Design and FPGA Implementation of Optimized 32- Bit Vedic Multiplier and Square

Architectures