Module Code: 14ELEC17H

Module Title: VLSI Technology

Module Leader: Dr. Hassan Mostafa

Semester : ONE

Total mark : 100

Instructions:
1. Answer all questions.
2. The exam consists of 2 questions in Four pages including this cover page.
3. A formula sheet is attached at end of this booklet.
4. The exam allowed time is ONE hour.
5. Electronic calculators are allowed.
6. Clearly show all steps used in your solutions.
7. The allocation of marks is shown in brackets next to each question.
8. This is a closed book exam.

Question

Total Mark

50

50

100

Mark
Out of

Question#1(50
marks)
Qu. 1: (50 marks)

(10 marks)

(15 marks)

(10 marks)

(15 marks)

Question
#2 (50
marks)
Qu. 2: (50
marks)

a) By deriving the Boolean expressions for circuits A and B, show that they implement the
same logic function and state what it is.
(5 marks)

(5 marks)

(10 marks)

(5 marks)

(5 marks)

(5 marks)
g) Draw the stick diagram for Circuit A and estimate the required layout area assuming
130nm CMOS technology.
(15 marks)
7

Answer:
1.a.

10 marks
1.b.

15 marks

1.c.

10 marks

1.d.

15 marks

Answer:

2.a.

5 marks

2.b.

5 marks
2.c.

10 marks

2.d.

5 marks

2.e.

5 marks
2.f.

5 marks
2.g.

The area is estimated as 6*8 x 6*8 = 48 x 48

Since =65nm for 130nm CMOS technology
Estimated layout area = 3.12m x 3.12m
15 marks

Formula sheet:
-------------------You may make use of the following formulas--------------------

MOSFET UNIFIED MODEL:

50% propagation delay = 0.69 RC

10