A

LCFC Confidential

tia

ACLUA M/B Schematics Document

2

on
fid

en

Intel Haswell/Broadwell U-Processor with DDRIIIL + NV (N15V-GM/N15S-GT) GPU

2013-12-26
REV:0.3

Title

LC Future Center Secret Data

Security Classification
Issued Date

2013/08/08

Deciphered Date

Cover Page

2013/08/05

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Size Document Number

Custom
Date:

PDF created with pdfFactory Pro trial version www.pdffactory.com

Rev
1.0

ACLUA

Thursday, December 26, 2013

Sheet
E

of

59

LCFC confidential

NV (N15V-GM/N15S-GT)
GB2B-64 Package
Page 18~28

PCI-Express
4x Gen2

PCIe Port5

Memory BUS (DDR3L)

Dual Channel

VRAM 256/128*16
DDR3L*8 4GB/2GB/1GB

File Name : ACLUA

DDR3L-SO-DIMM X2
Page 14,15

1.35V DDR3L 1600 MT/s

UP TO 8G x 2

Page 24~27

HDMI

HDMI Conn.

USB Left

Page 34

USB 3.0 1x
DPx2 Lane

DP to VGA

VGA Conn.

USB 2.0 2x

Intel MCP

Page 35 Parade PS8613

USB 2.0 Port2

USB 2.0 1x

USB2.0 1x

Int. Camera

tia

eDP x2 Lane

eDP Conn

USB2.0 Port5

Haswell U 15W /
Broadwell U 15W

en

Int. MIC Conn.

Page 33

USB2.0 1x

SATA HDD
Page 42

SATA Gen3
SATA Port0

Page 42

SATA Gen1
SATA Port1

LAN Realtek

RJ45 Conn.

RTL8111GUL (1G)
RTL8106EUL (10M/100M)

Page 38
3

Page 37

BGA-1168
40mm*24mm

USB 2.0 1x

PCIe 1x

PCIe Port3

PCIe 1x

SPI BUS

Page 3~13

Page 43

SPK Conn.

Codec

Page 33

USB2.0 Port4
2

USB Right
Cardreader Realtek
RTS5170 USB2.0 Port3

SD/MMC Conn.
USB Board

NGFF Card
WLAN&BT
PCIe Port4
USB2.0 Port6

Page 40

HD Audio

Conexant CX20752

Touch Screen

USB2.0 Port0

USB2.0 1x

on
fid

SATA ODD

Page 41

Page 36

USB 3.0 Port1

USB 2.0 Port1

POWER BOARD

Page 07

SPI ROM 4MB

for reserve

Page 43

USB Board

Page 07

EC
ITE IT8586E-LQFP

Sub-board ( for 15")

Page 44

POWER BOARD

HP&Mic Combo Conn.

USB Board

Touch Pad

Page 45

Int.KBD

Page 45

USB Board

Thermal Sensor
NCT7718W

Issued Date

Title

LC Future Center Secret Data

2013/08/08

Block Diagram

2013/08/05

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Size
Document Number
Custom
Date:

PDF created with pdfFactory Pro trial version www.pdffactory.com

ODD Board

Page 39

Security Classification

Sub-board ( for 14")

SPI ROM
8MB

Rev
1.0

ACLUA

Thursday, December 26, 2013

E

Sheet

of

59

Voltage Rails ( O --> Means ON

, X --> Means OFF )

+5VS

Power Plane

+1.35VS
+1.05VS

+3VALW

SLP_S1# SLP_S3# SLP_S4# SLP_S5#

+VALW

+V

+VS

HIGH

HIGH

HIGH

HIGH

ON

ON

ON

ON

S1(Power On Suspend)

LOW

HIGH

HIGH

HIGH

ON

ON

ON

LOW

S3 (Suspend to RAM)

LOW

LOW

HIGH

HIGH

ON

ON

OFF

OFF

S4 (Suspend to Disk)

LOW

LOW

LOW

HIGH

ON

OFF

OFF

OFF

S5 (Soft OFF)

LOW

LOW

LOW

LOW

ON

OFF

OFF

OFF

Full ON

+1.5VS

SIGNAL

STATE

+3VS

Clock

+0.675VS

+3VALW_PCH

B+

CPU_CORE

+1.35V

+5VALW

+VGA_CORE

State

+3VGS
+1.8VGS
+1.35VGS

USB Port Table

+0.95VGS

BOM Structure Table

S3

USB Port (Right Side)

USB Port1 (Left Side)

USB Port2 (Left Side)

Cardreader

S5 S4/AC Only

O
O

TOUCH PANEL

Camera

NGFF(WLAN)

S5 S4
AC & Battery
don't exist

on
fid

S5 S4
Battery only

USB Port1 (Left Side)

en

S3
Battery only

tia

S0

USB 3.0
XHCI

USB 2.0
EHCI1

BOM Structure
@
14@
15@
100M@
GIGA@
OPT@
N15SGT@
N15VGM@
GC6@
RANKA@
RANKB@
UMA@
TS@
AOAC@
ME@

BTO Item
Not stuff
For 14" part
For 15" part
100M LAN Part
GIGA LAN Part
Discrete GPU SKU part

For N15S-GT GPU part

For N15V-GM part
GC62.0 support part
For VRAM RankA part
For VRAM RankB part
UMA SKU part
For support touch panel sku part
AOAC support part
ME part(connector, hole)

PCIE PORT LIST

SMBUS Control Table

Port

EC_SMB_CK1
EC_SMB_DA1

IT8586E
+3VALW

EC_SMB_CK2

IT8586E

EC_SMB_DA2

+3VS

PCH_SMB_CLK
PCH
PCH_SMB_DATA +3VALW_PCH

EC SM Bus1 address
4

VGA

Device

BATT

IT8586E

+3VALW

+3VGS

+3VS

+3VS

0X16

Charger

0001 0010 b

charger

+3VS

PCH

TP
Module

EC SM Bus2 address

+3VS

+3VALW_PCH

+3VALW_PCH

Device

Address

DDR DIMMA

1010 000Xb

1001_100xb

DDR DIMMB

1010 010Xb

VGA

0x41(default)

Wlan

Rsvd

PCH

need to update

Thermal Sensor NCT7718W

Device
3

1
2
3
4
5
6

LAN
WLAN
Discrete GPU

PCH SM Bus address

Address

Device

Smart Battery

SODIMM

Thermal
Sensor

SOURCE

WLAN
WiMAX

Issued Date

Title

LC Future Center Secret Data

Security Classification
2013/08/08

2013/08/05

Deciphered Date

Notes List

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Thursday, December 26, 2013
Date:

Rev
1.0

ACLUA

PDF created with pdfFactory Pro trial version www.pdffactory.com

Sheet

of

59

UC1A

34
34
34
34
34
34
34
34

HDMI D2

HDMI D1
HDMI D0
HDMI CLK

HDMI_TX2HDMI_TX2+
HDMI_TX1HDMI_TX1+
HDMI_TX0HDMI_TX0+
HDMI_CLKHDMI_CLK+

35
35
35
35

DP TO VGA Converter

VGA_TX0VGA_TX0+
VGA_TX1VGA_TX1+

HDMI_TX2HDMI_TX2+
HDMI_TX1HDMI_TX1+
HDMI_TX0HDMI_TX0+
HDMI_CLKHDMI_CLK+

C54
C55
B58
C58
B55
A55
A57
B57

VGA_TX0VGA_TX0+
VGA_TX1VGA_TX1+

C51
C50
C53
B54
C49
B50
A53
B53

DDI1_TXN0
DDI1_TXP0
DDI1_TXN1
DDI1_TXP1
DDI1_TXN2
DDI1_TXP2
DDI1_TXN3
DDI1_TXP3

HSW_ULT_DDR3L

EDP_TXN0
EDP_TXP0
EDP_TXN1
EDP_TXP1

DDI

EDP_TXN2
EDP_TXP2
EDP_TXN3
EDP_TXP3

EDP

DDI2_TXN0
DDI2_TXP0
DDI2_TXN1
DDI2_TXP1
DDI2_TXN2
DDI2_TXP2
DDI2_TXN3
DDI2_TXP3

EDP_AUXN
EDP_AUXP
EDP_RCOMP
EDP_DISP_UTIL

C45
B46
A47
B47

CPU_EDP_TX0CPU_EDP_TX0+
CPU_EDP_TX1CPU_EDP_TX1+

CPU_EDP_TX0CPU_EDP_TX0+
CPU_EDP_TX1CPU_EDP_TX1+

33
33
33
33

C47
C46
A49
B49
A45
B45

CPU_EDP_AUX#
CPU_EDP_AUX

D20
A43

EDP_COMP
LCD_BKLT_CTRL_R

CPU_EDP_AUX#
CPU_EDP_AUX

1
1

RC1
RC2

33
33

2 24.9_0402_1%
2 0_0402_5%

+VCCIOA_OUT

INVT_PWM

+VCCIOA_OUT & EDP_COMP :

Trace Width: 20mil
Space: 25mil
Max length: 100mil
33

1 OF 19

tia

HASWELL-ULT-DDR3L_BGA1168

HSW_ULT_DDR3L

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
@ PAD

OPT@2 1K_0402_5%
OPT@2 0_0402_5%

GPIO53

DDPB_HPD
DDPC_HPD
EDP_HPD

C8
A8
D6

VGA_AUX#

VGA_AUX

HDMI_HPD
VGA_HPD
EDP_HPD

HDMI_HPD
VGA_HPD

RC37
100K_0402_5%
@

EDP_HPD

1 QC4

10K_0804_8P4R_5%

+3VS

RC9
1M_0402_5%
@

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

+3VS

N15VGM@
2

10K_0402_5%

GPIO52

RC11

10K_0402_5%

GPIO53

RC14

10K_0402_5%

PXS_PWREN_R

RC15

10K_0402_5%

PXS_RST#_R

CPU_EDP_HPD

33

2N7002KW_SOT323-3
RC13
100K_0402_5%
@
RC16 1

RC10

After confirm with vendor, HPD

has internal pull-down ~100K at
PS8613, just reserve in case.
RC37 can be removed next phase
if no issue.

8
7
6
5

34
35

+3VS

RPC1

1
2
3
4

35

+3VS

35

VGA_AUX

GPIO55
GPIO52
GPIO54
GPIO51
GPIO53

VGA_AUX#

HASWELL-ULT-DDR3L_BGA1168

QC13
2N7002KW_SOT323-3

U7
L1
L3
R5
L4

C5
B6
B5
A6

9 OF 19

2
1

19

BOARD_ID3
GPIO52
PXS_PWREN_R
PXS_RST#_R
GPIO53

DDPB_AUXN
DDPC_AUXN
DDPB_AUXP
DDPC_AUXP

34
34

CC96
.1U_0402_10V6-K
@

BOARD_ID3
GPIO52

PCIE

DDPB_CLK
DDPB_DATA

RC170 1
@
2
0_0402_5%

VGA_GATE#

44

19

DISPLAY

2.2K_0804_8P4R_5%

DDPx_CTRLDATA
The signal has a weak internal pull-down.
H
Port is detected.
L
Port is not detected.

1
1

RC7
RC8

DDPB_CTRLCLK
DDPB_CTRLDATA
DDPC_CTRLCLK
DDPC_CTRLDATA

DDPB_CLK
DDPB_DATA
DDPC_CLK
DDPC_DATA

PXS_PWREN
PXS_RST#

PXS_PWREN
PXS_RST#

PIRQA/GPIO77
PIRQB/GPIO78
PIRQC/GPIO79
PIRQD/GPIO80
PME

eDP SIDEBAND

on
fid

9
21,58
19

TC1

U6
P4
N4
N2
AD4

EDP_BKLCTL
EDP_BKLEN
EDP_VDDEN

B9
C9
D9
D11

PCH_EDP_PWM
PCH_ENBKL
PCH_ENVDD

33
33

B8
A9
C6

en

33

PCH_EDP_PWM
PCH_ENBKL
PCH_ENVDD

DDPC_CLK
DDPC_DATA
DDPB_CLK
DDPB_DATA

8
7
6
5

UC1I

+3VS
RPC19

1
2
3
4

0_0402_5%

Reserve for NV GPU

RC27

10K_0402_5%

GPIO52

RC30

10K_0402_5%

GPIO53

RC17

100K_0402_5%

PXS_PWREN_R

RC18

100K_0402_5%

PXS_RST#_R

Issued Date

Title

LC Future Center Secret Data

Security Classification
2013/08/08

2013/08/05

Deciphered Date

MCP (DDI,EDP)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Thursday, December 26, 2013
Date:

Rev
1.0

ACLUA

PDF created with pdfFactory Pro trial version www.pdffactory.com

Sheet

of

59

HSW_ULT_DDR3L

UC1B

+1.05V_VCCST
1
2

RC19
62_0402_1%

44,51,52

H_PROCHOT#

1
1

TC2 @
TC3 @

44

56_0402_5%

H_PECI

2 RC20

1
2 RC21
10K_0402_5%

PROC_DETECT
CATERR
PECI

PROCHOT

C61

CPU_PROCPWRGD

PRDY
PREQ
PROC_TCK
PROC_TMS
PROC_TRST
PROC_TDI
PROC_TDO

JTAG

K63

H_PROCHOT#_R

MISC

THERMAL

PROCPWRGD

BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7

RC22
470_0402_5%
AU60
SM_RCOMP_0
AV60
SM_RCOMP_1
AU61
SM_RCOMP_2
CPU_DRAMRST#_R AV15
AV61
SM_PG_CNTL1

2
CPU_DRAMRST#

2 0_0402_5%
@

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
SM_DRAMRST
SM_PG_CNTL1

XDP_PRDY#
XDP_PREQ#
XDP_TCLK
XDP_TMS
XDP_TRST#
XDP_TDI
XDP_TDO

1
1
1
1
1
1
1

J60
H60
H61
H62
K59
H63
K60
J61

XDP_BPM0#
XDP_BPM1#
XDP_BPM2#
XDP_BPM3#
XDP_BPM4#
XDP_BPM5#
XDP_BPM6#
XDP_BPM7#

1
1
1
1
1
1
1
1

DDR3L

HASWELL-ULT-DDR3L_BGA1168

RC24

SM_RCOMP_2

RC25

SM_RCOMP_1

200_0402_1%

RC26

SM_RCOMP_0

TC11
TC12
TC13
TC14
TC15
TC16
TC17
TC18

PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD

@
@
@
@
@
@
@
@

+3VALW

RC28
100K_0402_5%

CPU_DRAMPG_CNTL

+1.35V
RC3

on
fid

1
2
1K_0402_5%

2
B

en

@
@
@
@
@
@
@

tia

121_0402_1%

PAD
PAD
PAD
PAD
PAD
PAD
PAD

2 OF 19

CC1
0.01U_0402_25V7K

100_0402_1%

TC4
TC5
TC6
TC7
TC8
TC9
TC10

14,15

RC23 1

J62
K62
E60
E61
E59
F63
F62

PWR

+1.35V

PROC_DETECT# D61
K61
CATERR#
N62
H_PECI

55

+1.35V

QC14

MMBT3904WH_SOT323-3

RC31 1

SM_PG_CNTL1

CD1
.1U_0402_10V6-K
@

G
S

1
3
2

RC29
10K_0402_5%
@

PJA138K_SOT23-3

RD1

2 66.5_0402_1%

DDRA_ODT0

DDR_ODT

RD2

2 66.5_0402_1%

DDRA_ODT1

RD3

2 66.5_0402_1%

DDRB_ODT0

RD4

2 66.5_0402_1%

DDRB_ODT1

2013/08/05

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

PDF created with pdfFactory Pro trial version www.pdffactory.com

14

DDRA_ODT1

14

DDRB_ODT0

15

DDRB_ODT1

15

Title

LC Future Center Secret Data

2013/08/08

MCP (MISC,THERMAL,JATG)
Size
Document Number
Custom
Date:

DDRA_ODT0

Security Classification
Issued Date

QC5
D

2 0_0402_5%

Rev
1.0

ACLUA

Thursday, December 26, 2013

1

Sheet

of

59

14

DDRB_DQ[0..15]

DDRA_DQ[16..31]

15

DDRB_DQ[16..31]

AH63
AH62
AK63
AK62
AH61
AH60
AK61
AK60
AM63
AM62
AP63
AP62
AM61
AM60
AP61
AP60
AP58
AR58
AM57
AK57
AL58
AK58
AR57
AN57
AP55
AR55
AM54
AK54
AL55
AK55
AR54
AN54
AY58
AW58
AY56
AW56
AV58
AU58
AV56
AU56
AY54
AW54
AY52
AW52
AV54
AU54
AV52
AU52
AK40
AK42
AM43
AM45
AK45
AK43
AM40
AM42
AM46
AK46
AM49
AK49
AM48
AK48
AM51
AK51

SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

SA_CLK#0
SA_CLK0
SA_CLK#1
SA_CLK1
SA_CKE0
SA_CKE1
SA_CKE2
SA_CKE3
SA_CS#0
SA_CS#1
SA_ODT0
SA_RAS
SA_WE
SA_CAS
SA_BA0
SA_BA1
SA_BA2
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15

DDR CHANNEL A

SA_DQSN0
SA_DQSN1
SA_DQSN2
SA_DQSN3
SA_DQSN4
SA_DQSN5
SA_DQSN6
SA_DQSN7
SA_DQSP0
SA_DQSP1
SA_DQSP2
SA_DQSP3
SA_DQSP4
SA_DQSP5
SA_DQSP6
SA_DQSP7
SM_VREF_CA
SM_VREF_DQ0
SM_VREF_DQ1

AU37
AV37
AW36
AY36
AU43
AW43
AY42
AY43
AP33
AR32
AP32

SA_ODT0

AY34
AW34
AU34

TC19

DDRA_CLK0#
DDRA_CLK0
DDRA_CLK1#
DDRA_CLK1

14
14
14
14

DDRA_CKE0
DDRA_CKE1

14
14

DDRA_CS0#
DDRA_CS1#

14
14

AU36
AY37
AR38
AP36
AU39
AR36
AV40
AW39
AY39
AU40
AP35
AW41
AU41
AR35
AV42
AU42

DDRA_MA0
DDRA_MA1
DDRA_MA2
DDRA_MA3
DDRA_MA4
DDRA_MA5
DDRA_MA6
DDRA_MA7
DDRA_MA8
DDRA_MA9
DDRA_MA10
DDRA_MA11
DDRA_MA12
DDRA_MA13
DDRA_MA14
DDRA_MA15

AJ61
AN62
AM58
AM55
AV57
AV53
AL43
AL48

DDRA_DQS#0
DDRA_DQS#1
DDRB_DQS#0
DDRB_DQS#1
DDRA_DQS#2
DDRA_DQS#3
DDRB_DQS#2
DDRB_DQS#3

AJ62
AN61
AN58
AN55
AW57
AW53
AL42
AL49

DDRA_DQS0
DDRA_DQS1
DDRB_DQS0
DDRB_DQS1
DDRA_DQS2
DDRA_DQS3
DDRB_DQS2
DDRB_DQS3

DDRA_DQ[32..47]

PAD @
DDRA_RAS#
DDRA_W E#
DDRA_CAS#

AU35
AV35
AY41

14

DDRA_BS0#
DDRA_BS1#
DDRA_BS2#
DDRA_MA[0..15]

14
14
14

15

DDRB_DQ[32..47]

14
14
14
14

14

DDRA_DQ[48..63]

AP49
AR51
AP51

15

DDRB_DQ[48..63]

DDR_SM_VREFCA
DDR_SA_VREFDQ
DDR_SB_VREFDQ

14
14
15

SMVREF
WIDTH:20MIL
SPACING: 20MIL

DDRA_DQS#[0..7]
DDRA_DQS[0..7]

3 OF 19

DDRA_DQS#[0..7]
DDRA_DQS[0..7]

AY31
AW31
AY29
AW29
AV31
AU31
AV29
AU29
AY27
AW27
AY25
AW25
AV27
AU27
AV25
AU25
AM29
AK29
AL28
AK28
AR29
AN29
AR28
AP28
AN26
AR26
AR25
AP25
AK26
AM26
AK25
AL25
AY23
AW23
AY21
AW21
AV23
AU23
AV21
AU21
AY19
AW19
AY17
AW17
AV19
AU19
AV17
AU17
AR21
AR22
AL21
AM22
AN22
AP21
AK21
AK22
AN20
AR20
AK18
AL18
AK20
AM20
AR18
AP18

HSW_ULT_DDR3L

SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

SB_CK#0
SB_CK0
SB_CK#1
SB_CK1
SB_CKE0
SB_CKE1
SB_CKE2
SB_CKE3
SB_CS#0
SB_CS#1
SB_ODT0
SB_RAS
SB_WE
SB_CAS
SB_BA0
SB_BA1
SB_BA2

4 OF 19

DDR CHANNEL B

SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15
SB_DQSN0
SB_DQSN1
SB_DQSN2
SB_DQSN3
SB_DQSN4
SB_DQSN5
SB_DQSN6
SB_DQSN7
SB_DQSP0
SB_DQSP1
SB_DQSP2
SB_DQSP3
SB_DQSP4
SB_DQSP5
SB_DQSP6
SB_DQSP7

AM38
AN38
AK38
AL38
AY49
AU50
AW49
AV50
AM32
AK32
AL32 SB_ODT0

TC20

DDRB_CLK0#
DDRB_CLK0
DDRB_CLK1#
DDRB_CLK1

15
15
15
15

DDRB_CKE0
DDRB_CKE1

15
15

DDRB_CS0#
DDRB_CS1#

15
15

PAD @

AM35
AK35
AM33

DDRB_RAS#
DDRB_W E#
DDRB_CAS#

AL35
AM36
AU49
AP40
AR40
AP42
AR42
AR45
AP45
AW46
AY46
AY47
AU46
AK36
AV47
AU47
AK33
AR46
AP46

DDRB_MA0
DDRB_MA1
DDRB_MA2
DDRB_MA3
DDRB_MA4
DDRB_MA5
DDRB_MA6
DDRB_MA7
DDRB_MA8
DDRB_MA9
DDRB_MA10
DDRB_MA11
DDRB_MA12
DDRB_MA13
DDRB_MA14
DDRB_MA15

AW30
AV26
AN28
AN25
AW22
AV18
AN21
AN18

DDRA_DQS#4
DDRA_DQS#5
DDRB_DQS#4
DDRB_DQS#5
DDRA_DQS#6
DDRA_DQS#7
DDRB_DQS#6
DDRB_DQS#7

AV30
AW26
AM28
AM25
AV22
AW18
AM21
AM18

DDRA_DQS4
DDRA_DQS5
DDRB_DQS4
DDRB_DQS5
DDRA_DQS6
DDRA_DQS7
DDRB_DQS6
DDRB_DQS7

15
15
15

DDRB_BS0#
DDRB_BS1#
DDRB_BS2#
DDRB_MA[0..15]

15
15
15
15

DDRB_DQS#[0..7]

14

DDRB_DQS[0..7]

14

DDRB_DQS#[0..7]
DDRB_DQS[0..7]

15
15

HASWELL-ULT-DDR3L_BGA1168

HASWELL-ULT-DDR3L_BGA1168

DDRA_DQ32
DDRA_DQ33
DDRA_DQ34
DDRA_DQ35
DDRA_DQ36
DDRA_DQ37
DDRA_DQ38
DDRA_DQ39
DDRA_DQ40
DDRA_DQ41
DDRA_DQ42
DDRA_DQ43
DDRA_DQ44
DDRA_DQ45
DDRA_DQ46
DDRA_DQ47
DDRB_DQ32
DDRB_DQ33
DDRB_DQ34
DDRB_DQ35
DDRB_DQ36
DDRB_DQ37
DDRB_DQ38
DDRB_DQ39
DDRB_DQ40
DDRB_DQ41
DDRB_DQ42
DDRB_DQ43
DDRB_DQ44
DDRB_DQ45
DDRB_DQ46
DDRB_DQ47
DDRA_DQ48
DDRA_DQ49
DDRA_DQ50
DDRA_DQ51
DDRA_DQ52
DDRA_DQ53
DDRA_DQ54
DDRA_DQ55
DDRA_DQ56
DDRA_DQ57
DDRA_DQ58
DDRA_DQ59
DDRA_DQ60
DDRA_DQ61
DDRA_DQ62
DDRA_DQ63
DDRB_DQ48
DDRB_DQ49
DDRB_DQ50
DDRB_DQ51
DDRB_DQ52
DDRB_DQ53
DDRB_DQ54
DDRB_DQ55
DDRB_DQ56
DDRB_DQ57
DDRB_DQ58
DDRB_DQ59
DDRB_DQ60
DDRB_DQ61
DDRB_DQ62
DDRB_DQ63

15

DDRA_DQ0
DDRA_DQ1
DDRA_DQ2
DDRA_DQ3
DDRA_DQ4
DDRA_DQ5
DDRA_DQ6
DDRA_DQ7
DDRA_DQ8
DDRA_DQ9
DDRA_DQ10
DDRA_DQ11
DDRA_DQ12
DDRA_DQ13
DDRA_DQ14
DDRA_DQ15
DDRB_DQ0
DDRB_DQ1
DDRB_DQ2
DDRB_DQ3
DDRB_DQ4
DDRB_DQ5
DDRB_DQ6
DDRB_DQ7
DDRB_DQ8
DDRB_DQ9
DDRB_DQ10
DDRB_DQ11
DDRB_DQ12
DDRB_DQ13
DDRB_DQ14
DDRB_DQ15
DDRA_DQ16
DDRA_DQ17
DDRA_DQ18
DDRA_DQ19
DDRA_DQ20
DDRA_DQ21
DDRA_DQ22
DDRA_DQ23
DDRA_DQ24
DDRA_DQ25
DDRA_DQ26
DDRA_DQ27
DDRA_DQ28
DDRA_DQ29
DDRA_DQ30
DDRA_DQ31
DDRB_DQ16
DDRB_DQ17
DDRB_DQ18
DDRB_DQ19
DDRB_DQ20
DDRB_DQ21
DDRB_DQ22
DDRB_DQ23
DDRB_DQ24
DDRB_DQ25
DDRB_DQ26
DDRB_DQ27
DDRB_DQ28
DDRB_DQ29
DDRB_DQ30
DDRB_DQ31

UC1D

tia

HSW_ULT_DDR3L

en

DDRA_DQ[0..15]

on
fid

UC1C

14

Issued Date

Title

LC Future Center Secret Data

Security Classification
2013/08/08

Deciphered Date

2013/08/05

MCP (DDR3L)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Thursday, December 26, 2013
Date:

Rev
1.0

ACLUA

PDF created with pdfFactory Pro trial version www.pdffactory.com

Sheet

of

59

RTC_X1
+3VS
RTC_X2

32.768KHZ_12.5PF_200458-PG14
CC4
15P_0402_50V8J

RC33
RC34

1
1

RPC2

YC1

CC3
1U_0402_10V6K

VCCRTC

1 10M_0402_5%

RC32

2 20K_0402_1%
2 20K_0402_1%

1
2
3
4

ODD_DETECT#
SATA0GP
SATA2GP
SATA3GP

JME1
SHORT PADS
@
SRTC_RST#
RTC_RST#

CC5
18P_0402_50V8J
CC6
1U_0402_10V6K

10K_0804_8P4R_5%

JCMOS1
SHORT PADS
@

UC1E

SML0_CLK

RC35

SML0_DATA

RC36

43
43
43
43

HDA_BITCLK_AUDIO
HDA_SYNC_AUDIO
HDA_RST_AUDIO#
HDA_SDIN0

43
44

HDA_SDOUT_AUDIO
ME_FLASH

2 33_0402_5%
2 33_0402_5%
2 33_0402_5%

RC45 1
RC46 1

2 33_0402_5%
2 0_0402_5%
@

@
@
@
@
@

TC32
TC33
TC34

@ 1
@ 1
@ 1

AW8
AV11
AU8
AY10
AU12
AU11
HDA_SDOUT
TC21 @ 1 AW10
TC22 @ 1 AV10
AY8
TC23 @ 1
HDA_BCLK
HDA_SYNC
HDA_RST#
HDA_SDIN0

PCH_JTAG_TRST#
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS

HDA_SDIN0

1
1
1
1
1

TC24
TC25
TC26
TC28
TC30

SATA_RN0/PERN6_L3
SATA_RP0/PERP6_L3
SATA_TN0/PETN6_L3
SATA_TP0/PETP6_L3

RTC

SATA_RN1/PERN6_L2
SATA_RP1/PERP6_L2
SATA_TN1/PETN6_L2
SATA_TP1/PETP6_L2

RC42 1
RC43 1
RC44 1

HDA_SDO This signal has a weak internal pull-down.

0 = Enable security measures defined in the Flash Descriptor.
1 = Disable Flash Descriptor Security(override). This strap
should only be asserted high during external pull-up in
manufacturing/debug environments ONLY.

RTCX1
RTCX2
INTRUDER
INTVRMEN
SRTCRST
RTCRST

PCH_JTAGX

AU62
AE62
AD61
AE61
AD62
AL11
AC4
AE63
AV2

HDA_BCLK/I2S0_SCLK
HDA_SYNC/I2S0_SFRM
HDA_RST/I2S_MCLK
AUDIO
HDA_SDI0/I2S0_RXD
HDA_SDI1/I2S1_RXD
HDA_SDO/I2S0_TXD
HDA_DOCK_EN/I2S1_TXD
HDA_DOCK_RST/I2S1_SFRM
I2S1_SCLK

SATA

SATA_RN2/PERN6_L1
SATA_RP2/PERP6_L1
SATA_TN2/PETN6_L1
SATA_TP2/PETP6_L1
SATA_RN3/PERN6_L0
SATA_RP3/PERP6_L0
SATA_TN3/PETN6_L0
SATA_TP3/PETP6_L0
SATA0GP/GPIO34
SATA1GP/GPIO35
SATA2GP/GPIO36
SATA3GP/GPIO37

PCH_TRST
PCH_TCK
PCH_TDI
PCH_TDO
PCH_TMS
RSVD1
RSVD2
JTAGX
RSVD0

J5
H5
B15
A15

SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
SATA_PTX_DRX_N0
SATA_PTX_DRX_P0

SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
SATA_PTX_DRX_N0
SATA_PTX_DRX_P0

42
42
42
42

HDD

J8
H8
A17
B17

SATA_PRX_DTX_N1
SATA_PRX_DTX_P1
SATA_PTX_DRX_N1
SATA_PTX_DRX_P1

SATA_PRX_DTX_N1
SATA_PRX_DTX_P1
SATA_PTX_DRX_N1
SATA_PTX_DRX_P1

42
42
42
42

ODD

J6
H6
B14
C15
F5
E5
C17
D17

SATA_IREF
RSVD3
RSVD4
SATA_RCOMP
SATALED

JTAG

V1
U1
V6
AC1

CC7
10P_0402_50V8J

1
2
3
4

SMB_ALERT#
SML0_ALERT#
SML1_ALERT#

8
7
6
5
10K_0804_8P4R_5%

INTVRMEN
H Integrated VRM enable (Default)
L Integrated VRM disable
(INTVRMEN should always be pull high.)

2 1K_0402_5% HDA_SDOUT

For EMI

1 1M_0402_5%
1 330K_0402_5%

AW5
AY5
AU6
AV7
AV6
AU7

tia

2
2

RTC_X1
RTC_X2
SM_INTRUDER#
INTVRMEN
SRTC_RST#
RTC_RST#

SATA0GP
ODD_DETECT#
SATA2GP
SATA3GP

A12
L11
K10
C12 SATA_RCOMP RC48
U3 SATALED#
RC49

ODD_DETECT#

2
1

42

1 3.01K_0402_1%
2 10K_0402_5%

IREF&RCOMP
Width: 12-15Mil
Space:12Mil
Length: 500Mil

+1.05VS_PSATA3PLL

+3VS

en

+3VALW _PCH

1 2.2K_0402_5%
RPC22

RC39
RC41

1 2.2K_0402_5%

HSW_ULT_DDR3L

VCCRTC

+3VALW _PCH

CRYSTAL
1, Space 15MIL
2, No trace under crystal
3, Place on oppsosit side of MCP for temp influence

RC47

8
7
6
5

5 OF 19

2
2
2
2
2
2
2
2

33_0402_5%
15_0402_5%
0_0402_5%
0_0402_5%
33_0402_5%
15_0402_5%
15_0402_5%
33_0402_5%

AA3
Y7
Y4
AC2
AA2
SPI_SI_R
AA4
SPI_SO_R
Y6
SPI_W P#_R
SPI_HOLD#_R AF1
SPI_CLK_R
SPI_CS0#_R
SPI_CS1#_R

SPI_CLK
SPI_CS0
SPI_CS1
SPI_CS2
SPI_MOSI
SPI_MISO
SPI_IO2
SPI_IO3

SPI

SMBALERT/GPIO11
SMBCLK
SMBDATA
SML0ALERT/GPIO60
SML0CLK
SML0DATA
SML1ALERT/PCHHOT/GPIO73
SML1CLK/GPIO75
SML1DATA/GPIO74

C-LINK

CL_CLK
CL_DATA
CL_RST

AN2
AP2
AH1
AL2
AN1
AK1
AU4
AU3
AH3

SMB_ALERT#
PCH_SMB_CLK
PCH_SMB_DATA
SML0_ALERT#
SML0_CLK
SML0_DATA
SML1_ALERT#
PCH_SML1_CLK
PCH_SML1_DAT

AF2
AD2
AF4

DIMM1, DIMM2, NGFF

+3VALW _PCH

+3VS

+3VS

RC56
2.2K_0402_5%

RC57
2.2K_0402_5%

@
@

SMBUS

LPC

RC58
2.2K_0402_5%

SPI_SI
SPI_SO

RC1731
RC50 1
RC51 1
RC1741
RC1751
RC52 1
RC53 1
RC1771

LAD0
LAD1
LAD2
LAD3
LFRAME

44
44

SPI_CLK_1
SPI_CLK
SPI_CS0#
SPI_CS1#
SPI_SI_1
SPI_SI
SPI_SO
SPI_SO_1

SPI_CLK
SPI_CS0#

on
fid

44

44
44

AU14
AW12
AY12
AW11
AV12

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#

HSW_ULT_DDR3L

UC1G

44
44
44
44

HASWELL-ULT-DDR3L_BGA1168

RC59
2.2K_0402_5%

SPI_W P#_R

RC54 1

2 33_0402_5%

SPI_W P#

SPI_HOLD#_R

RC55 1

2 33_0402_5%

SPI_HOLD#

SPI_SO

SPI_W P#

CS#
DO
WP#

CLK

GND

DI

SPI_HOLD#

SPI_CLK

SPI_SI

2
G

CC8
.1U_0402_10V6-K

14,15,40

GPU, EC, Thermal Sensor

+3VALW _PCH

+3VS

RC63
2.2K_0402_5%

RC62
2.2K_0402_5%

+3V_SPI

SPI_HOLD#_1
+3VS

2
RC1711
0_0402_5%

WP(IO2)

CLK

GND

DI(IO0)

2
8
7

PCH_SML1_CLK
SPI_HOLD#_1

SPI_CLK_1

SPI_SI_1

QC3A

EC_SMB_CK2

2N7002KDW H_SOT363-6
CC97
.1U_0402_10V6-K
@

19,39,44

VCC

DO(IO1) HOLD/RST(IO3)

CS

PCH_SML1_DAT

QC3B

SPI_SO_1

SPI_CS1#

SPI_W P#_1

EC_SMB_DA2

2 33_0402_5%

SMB_DATA_S3

VCC
HOLD#

UC6

+3VALW _PCH
RC178 1

2N7002KDW H_SOT363-6

+3V_SPI
RC180
1K_0402_5%
@

SPI_W P#_1
SPI_HOLD#_R

QC2B

1
2 33_0402_5%

D
PCH_SMB_DATA

1
RC176 1

14,15,40

W 25Q64FVSSIG_SO8

2
SPI_W P#_R

SMB_CLK_S3

UC3
SPI_CS0#

+3V_SPI

2N7002KDW H_SOT363-6

+3V_SPI

RC179
1K_0402_5%
@

QC2A

1
RC61
1K_0402_5%

RC60
1K_0402_5%

PCH_SMB_CLK

HASWELL-ULT-DDR3L_BGA1168

+3V_SPI

7 OF 19

W 25Q32FVSSIG_SO8

19,39,44

2N7002KDW H_SOT363-6

2
RC1721
@
0_0402_5%

Issued Date

Title

LC Future Center Secret Data

Security Classification

+3V_SPI
1. If support DS3, connect to +3VS and don't support EC mirror code;
2. If don't support DS3, connect to +3VALW_PCH and support EC mirror code.

2013/08/08

Deciphered Date

2013/08/05

MCP (RTC&AUDIO&SATA&SMBUS)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Date:
5

PDF created with pdfFactory Pro trial version www.pdffactory.com

Document Number

Rev
1.0

ACLUA
Thursday, December 26, 2013
1

Sheet

of

59

+3VS

RC71
RPC3

1 1M_0402_5%

YC2

1
2
3
4

8
7
6
5

PCIE_CLKREQ1#
PCIE_CLKREQ0#
PCIE_CLKREQ5#

2
1

XTAL24_IN

GND1

OSC2

OSC1

GND2

XTAL24_OUT

24MHZ_6PF_7V24000032

LAN_CLKREQ#
WLAN_CLKREQ#
SYS_RESET#
PM_CLKRUN#

CC12
4.7P_0402_50V8-J

1
8
7
6
5

CC11
4.7P_0402_50V8-J

RPC4
1
2
3
4

10K_0804_8P4R_5%
D

HSW_ULT_DDR3L

UC1F

10K_0804_8P4R_5%
2 10K_0402_5%

GPU_CLKREQ#
C43
C42
U2

PCIE_CLKREQ0#

PCIE CLK2

LAN

37
37
37

CLK_PCIE_LAN#
CLK_PCIE_LAN
LAN_CLKREQ#

PCIE CLK3

WLAN

40
40
40

CLK_PCIE_WLAN#
CLK_PCIE_WLAN
WLAN_CLKREQ#

19
19
19

CLK_PCIE_GPU#
CLK_PCIE_GPU
GPU_CLKREQ#

CLK_PCIE_LAN#
CLK_PCIE_LAN
LAN_CLKREQ#

C41
B42
AD1

CLK_PCIE_WLAN#
CLK_PCIE_WLAN
WLAN_CLKREQ#

B38
C37
N1

CLK_PCIE_GPU#
CLK_PCIE_GPU
GPU_CLKREQ#

A39
B39
U5

PCIE_CLKREQ5#

B37
A37
T2

RSVD5
RSVD6
DIFFCLK_BIASREF

CLKOUT_PCIE_N1
CLKOUT_PCIE_P1
PCIECLKRQ1/GPIO19

TESTLOW_C35
TESTLOW_C34
TESTLOW_AK8
TESTLOW_AL8

CLOCK

CLKOUT_PCIE_N2
CLKOUT_PCIE_P2
PCIECLKRQ2/GPIO20

SIGNALS

CLKOUT_PCIE_N3
CLKOUT_PCIE_P3
PCIECLKRQ3/GPIO21

CLKOUT_LPC_0
CLKOUT_LPC_1
CLKOUT_ITPXDP
CLKOUT_ITPXDP_P

CLKOUT_PCIE_N4
CLKOUT_PCIE_P4
PCIECLKRQ4/GPIO22
CLKOUT_PCIE_N5
CLKOUT_PCIE_P5
PCIECLKRQ5/GPIO23

+3VALW

6 OF 19

AC_PRESENT_R

RC75

2 10K_0402_5%

PCH_GPIO72

RC76

2 10K_0402_5%

WAKE#

RC78

2 10K_0402_5%

SUSWARN#_R

RC90

2 10K_0402_5%

PCH_GPIO72

HASWELL-ULT-DDR3L_BGA1168

on
fid

+3VALW_PCH

UC1H

SYS_PWROK
PCH_PWROK

44

EC_RSMRST#
SUSWARN#
PBTN_OUT#

RC139
RC126
RC83
RC84

RC85
RC86
RC87

1
1
1
1
1

1
1
1

@
@
@
@
@

@
@

2 0_0402_5%
2
2
2
2

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

2 0_0402_5%
2 0_0402_5%
2 0_0402_5%

@
2
1000P_0402_50V7K

CC103
1

@
2
PCH_DPWROK_R
1000P_0402_50V7K

PCH_PWROK

@
1

2 1000P_0402_50V7K

RC91 1

2 10K_0402_5%

SYS_PWROK
44

RPC21
1
2
3
4
A

8
7
6
5

100K_0402_1% 2

AW6
AV4
AL7
AJ8
AN4
1 AF3
1 AM5

RC88

AC_PRESENT

SUSACK
SYS_RESET
SYS_PWROK
PCH_PWROK
APWROK
PLTRST

RSMRST
SUSWARN/SUSPWRDNACK/GPIO30
PWRBTN
ACPRESENT/GPIO31
BATLOW/GPIO72
SLP_S0
SLP_WLAN/GPIO29

44,53

1 RC92

PLT_RST#_R

1 RC94

PCH_DPWROK_R

1K_0402_5%

2 RC95

SUSCLK

10K_0402_5%

1 RC105

GPU_CLKREQ#

MCP_TESTLOW1
MCP_TESTLOW2
MCP_TESTLOW3
MCP_TESTLOW4

AN15
AP15

CLK_PCI_EC_R

RC73

3.01K_0402_1%

1 22_0402_5%

DIFFCLK_BIASREF
Width: 12-15Mil
Space:12Mil
Length: 500Mil

CLK_PCI_EC

ACIN#

8
7
6
5

MCP_TESTLOW1
MCP_TESTLOW2
MCP_TESTLOW3
MCP_TESTLOW4

1
2
3
4

10K_0804_8P4R_5%

VCCRTC

RC77
330K_0402_5%

DSWODVREN

RC80
330K_0402_5%
@

DSWVRMEN
DPWROK
WAKE
CLKRUN/GPIO32
SUS_STAT/GPIO61
SUSCLK/GPIO62
SLP_S5/GPIO63
SLP_S4
SLP_S3
SLP_A
SLP_SUS
SLP_LAN

RC182

RC81
RC82

1
1

2 0_0402_5%

AW7
AV5
AJ5

DSWODVREN
PCH_DPWROK_R
WAKE#

V5
AG4
AE6
AP5

PM_CLKRUN#
SUS_STAT#
SUSCLK
PM_SLP_S5#

AJ6
AT4
AL5
AP4
AJ7

PM_SLP_S4#_R
PM_SLP_S3#_R

RC140
RC141

1
1

@
@

2 0_0402_5%
2 0_0402_5%

PM_SLP_SUS#_R

RC89

2 0_0402_5%

EC_RSMRST#

Reserve for DS3

1 @

@
@

2 0_0402_5%
2 0_0402_5%

DPWROK_EC
PCIE_WAKE#

44
9,37,40,44

DSWODVREN - On Die DSW VR Enable

H Enable
L Disable
B

TC37
SUSCLK
PM_SLP_S5#

1
TC40

40
44

PM_SLP_S4#
PM_SLP_S3#

44
44

PM_SLP_SUS#

44

Reserve for DS3

@ PAD

8 OF 19

2 0_0402_5%

AC_PRESENT_R

2
G

QC8
2N7002KW_SOT323-3

Issued Date

Title

LC Future Center Secret Data

Security Classification
2013/08/08

2013/08/05

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MCP (Clock,PM)
Size
Document Number
Custom
Date:

RPC5

44

B35
A35

HASWELL-ULT-DDR3L_BGA1168

PCH_PWROK
PCH_RSMRST#_R

10K_0804_8P4R_5%
100K_0402_5% 2

PCH_RSMRST#_R
SUSWARN#_R
PBTN_OUT#_R
AC_PRESENT_R
PCH_GPIO72
TC38
@ PAD
TC39
@ PAD

CC104
1

CC101

AK2
AC3
AG2
AY7
AB5
AG7

SUSACK#_R
SYS_RESET#
SYS_PWROK_R
PCH_PWROK_R
APWROK
PLT_RST#_R

44
44

PLT_RST#

HSW_ULT_DDR3L

19,37,40,44

RC79

44
10,44

SUSACK#

C35
C34
AK8
AL8

SYSTEM POWER MANAGEMENT

Reserve for DS3

44

+1.05VS_PLPTCLKPLL
2
RC72

2 10K_0402_5%

DIFFCLK_BIASREF

XTAL24_IN
XTAL24_OUT

K21
M21
C26

en

RC74

A25
B25

GPU

B41
A41
Y5

XTAL24_IN
XTAL24_OUT

PCIE CLK4

PCIE_CLKREQ1#

CLKOUT_PCIE_N0
CLKOUT_PCIE_P0
PCIECLKRQ0/GPIO18

tia

RC120

PDF created with pdfFactory Pro trial version www.pdffactory.com

Rev
1.0

ACLUA

Thursday, December 26, 2013

1

Sheet

of

59

H_THRMTRIP#_R

1
+3VALW_PCH

42
42

RPC6

8
7
6
5

1
2
3
4

8,37,40,44

PCH_GPIO8

ODD_DA#
ODD_EN
PCIE_WAKE#

1
@
2
0_0402_5%

RC110

PCH_GPIO28
PCH_GPIO26

10K_0804_8P4R_5%
RPC7

8
7
6
5

1
2
3
4

PCH_GPIO57
PCH_GPIO56
PCH_GPIO58
PCH_GPIO59

22,44

VGA_PWRGD

10K_0804_8P4R_5%
RPC8

8
7
6
5

1
2
3
4

PCH_GPIO47
PCH_GPIO44
PCH_GPIO13
PCH_GPIO14

44

EC_SMI#

EC_SMI#

RC111 1

PCH_GPIO56
PCH_GPIO57
PCH_GPIO58
PCH_GPIO59
PCH_GPIO44
PCH_GPIO47
VGA_PWRGD
PCH_GPIO49
PCH_GPIO50
PCH_GPIO71
PCH_GPIO13
PCH_GPIO14
PCH_GPIO25
PCH_GPIO45
PCH_GPIO46

AG6
AP1
AL4
AT5
AK4
AB6
U4
Y3
P3
Y2
AT3
AH4
AM4
AG5
AG3

PCH_GPIO9
PCH_GPIO10
PCH_GPIO33
PCH_GPIO70
PCH_GPIO38
BOARD_ID2
PCH_BEEP

RPC9

1
2
3
4

P1
AU2
AM7
AD6
Y1
T3
AD5
AN5
AD7
AN3

0_0402_5%

10K_0804_8P4R_5%

8
7
6
5

PCH_GPIO76
PCH_GPIO8
PCH_GPIO12
PCH_GPIO15
BOARD_ID0
ODD_DA#
ODD_EN
DS3_WAKE#
PCH_GPIO28
PCH_GPIO26

PCH_GPIO45
PCH_GPIO46
PCH_GPIO10
PCH_GPIO9

43

PCH_BEEP

AM3
AM2
P2
C4
L2
N5
V2

BMBUSY/GPIO76
GPIO8
LAN_PHY_PWR_CTRL/GPIO12
GPIO15
GPIO16
GPIO17
GPIO24
GPIO27
GPIO28
GPIO26
GPIO56
GPIO57
GPIO58
GPIO59
GPIO44
GPIO47
GPIO48
GPIO49
GPIO50
HSIOPC/GPIO71
GPIO13
GPIO14
GPIO25
GPIO45
GPIO46

CPU/
MISC

GPIO

SERIAL IO

GPIO9
GPIO10
DEVSLP0/GPIO33
SDIO_POWER_EN/GPIO70
DEVSLP1/GPIO38
DEVSLP2/GPIO39
SPKR/GPIO81

THRMTRIP
RCIN/GPIO82
SERIRQ
PCH_OPI_RCOMP
RSVD7
RSVD8

GSPI0_CS/GPIO83
GSPI0_CLK/GPIO84
GSPI0_MISO/GPIO85
GSPI0_MOSI/GPIO86
GSPI1_CS/GPIO87
GSPI1_CLK/GPIO88
GSPI1_MISO/GPIO89
GSPI_MOSI/GPIO90
UART0_RXD/GPIO91
UART0_TXD/GPIO92
UART0_RTS/GPIO93
UART0_CTS/GPIO94
UART1_RXD/GPIO0
UART1_TXD/GPIO1
UART1_RST/GPIO2
UART1_CTS/GPIO3
I2C0_SDA/GPIO4
I2C0_SCL/GPIO5
I2C1_SDA/GPIO6
I2C1_SCL/GPIO7
SDIO_CLK/GPIO64
SDIO_CMD/GPIO65
SDIO_D0/GPIO66
SDIO_D1/GPIO67
SDIO_D2/GPIO68
SDIO_D3/GPIO69

D60
V4
T4
AW15
AF20
AB21

H_THRMTRIP#_R RC124 1
KBRST#
SERIRQ
RC106 2
OPI_COMP
1 @

R6
L6
N6
L8
R7
L5
N7
K2
J1
K3
J2
G1
K4
G2
J3
J4
F2
F3
G4
F1
E3
F4
D3
E4
C3
E2

PCH_GPIO83
BOARD_ID1
PCH_GPIO85
PCH_GPIO86
PCH_BT_OFF#
PCH_WLAN_OFF#
PCH_GPIO89
PCH_GPIO90
PCH_GPIO91
PCH_GPIO92
PCH_GPIO93
PCH_GPIO94
PCH_GPIO0
PCH_GPIO1
PCH_GPIO2
PCH_GPIO3
PCH_GPIO4
PCH_GPIO5
PCH_GPIO6
PCH_GPIO7
RC112 1
PCH_GPIO64
PCH_GPIO65
PCH_GPIO66
PCH_GPIO67
CMOS_ON#
PCH_GPIO69

10 OF 19

10K_0804_8P4R_5%
HASW ELL-ULT-DDR3L_BGA1168
C

+3VS

2 10K_0402_5%

ODD_DA#

RPC10

8
7
6
5

1
2
3
4

19

PCH_GPIO33
PCH_GPIO49
PCH_GPIO50
PCH_GPIO76

19
19

10K_0804_8P4R_5%

19

PCIE_CRX_GTX_N[0..3]
PCIE_CRX_GTX_P[0..3]
PCIE_CTX_C_GRX_N[0..3]
UC1K

PCIE_CTX_C_GRX_P[0..3]

HSW_ULT_DDR3L

RPC11

8
7
6
5

1
2
3
4

PCH_GPIO83
PCH_GPIO38
PCH_GPIO70
PCH_GPIO85

PCIE_CTX_C_GRX_N0
PCIE_CTX_C_GRX_P0

.1U_0402_10V6-K
.1U_0402_10V6-K

OPT@ 1
OPT@ 1

2 CC16
2 CC14

PCIE_CRX_GTX_N0
PCIE_CRX_GTX_P0

F10
E10

PCIE_CTX_GRX_N0
PCIE_CTX_GRX_P0

C23
C22

PCIE_CRX_GTX_N1
PCIE_CRX_GTX_P1

F8
E8

PCIE_CTX_GRX_N1
PCIE_CTX_GRX_P1

B23
A23

PCIE_CRX_GTX_N2
PCIE_CRX_GTX_P2

H10
G10

PCIE_CTX_GRX_N2
PCIE_CTX_GRX_P2

B21
C21

RPC12

8
7
6
5

1
2
3
4

PCH_GPIO89
PCH_GPIO90
PCH_GPIO91
PCH_GPIO92

GPU

10K_0804_8P4R_5%

1
2
3
4

PCH_GPIO93
PCH_GPIO1
PCH_GPIO94
PCH_GPIO0

10K_0804_8P4R_5%

.1U_0402_10V6-K
.1U_0402_10V6-K

OPT@ 1
OPT@ 1

2 CC15
2 CC17

PCIE_CTX_C_GRX_N2
PCIE_CTX_C_GRX_P2

.1U_0402_10V6-K
.1U_0402_10V6-K

OPT@ 1
OPT@ 1

2 CC18
2 CC19

PCIE_CTX_C_GRX_N3
PCIE_CTX_C_GRX_P3

.1U_0402_10V6-K
.1U_0402_10V6-K

OPT@ 1
OPT@ 1

2 CC20
2 CC21

PCIE5

RPC13

8
7
6
5

PCIE_CTX_C_GRX_N1
PCIE_CTX_C_GRX_P1

RPC14

8
7
6
5

1
2
3
4

PCH_GPIO3
PCH_GPIO2
PCH_GPIO4
PCH_GPIO5

LAN

PCIE3

10K_0804_8P4R_5%
RPC15

8
7
6
5

1
2
3
4

PCH_GPIO64
PCH_GPIO6
PCH_GPIO65
PCH_GPIO7

WLAN

PCIE4

37
37

PCIE_PRX_DTX_N3
PCIE_PRX_DTX_P3

37
37

PCIE_PTX_C_DRX_N3
PCIE_PTX_C_DRX_P3

40
40

PCIE_PRX_DTX_N4
PCIE_PRX_DTX_P4

40
40

PCIE_PTX_C_DRX_N4
PCIE_PTX_C_DRX_P4

CC22 1
CC23 1

CC24 1
CC25 1

2 .1U_0402_10V6-K
2 .1U_0402_10V6-K

2 .1U_0402_10V6-K
2 .1U_0402_10V6-K

1
2
3
4

PCH_GPIO67
PCH_GPIO69
PCH_GPIO71

PCIE_PRX_DTX_N3
PCIE_PRX_DTX_P3

G11
F11

PCIE_PTX_DRX_N3
PCIE_PTX_DRX_P3

C29
B30

PCIE_PRX_DTX_N4
PCIE_PRX_DTX_P4

F13
G13

PCIE_PTX_DRX_N4
PCIE_PTX_DRX_P4

B29
A29

B31
A31

+3VS

RC119
RPC18
CMOS_ON#
PCH_WLAN_OFF#
PCH_BT_OFF#
KBRST#

+1.05VS_PUSB3PLL

8
7
6
5

B22
A21

F15
G15

10K_0804_8P4R_5%

1
2
3
4

E6
F6

PCIE_CTX_GRX_N3
PCIE_CTX_GRX_P3

C30
C31

RPC16

8
7
6
5

PCIE_CRX_GTX_N3
PCIE_CRX_GTX_P3

G17
F17

10K_0804_8P4R_5%

1 3.01K_0402_1%

PCIE_RCOMP&PCIE_IREF
Width 12~15Mil
Space >12Mil
Length 500Mil

USB2N0
USB2P0

PETN5_L0
PETP5_L0

USB2N1
USB2P1

PERN5_L1
PERP5_L1

USB2N2
USB2P2

PETN5_L1
PETP5_L1

USB2N3
USB2P3

PERN5_L2
PERP5_L2

USB2N4
USB2P4

on
fid

10K_0804_8P4R_5%

PERN5_L0
PERP5_L0

PCIE_RCOMP

E15
E13
A27
B27

PETN5_L2
PETP5_L2

USB2N5
USB2P5

PERN5_L3
PERP5_L3

USB2N6
USB2P6

PETN5_L3
PETP5_L3

USB2N7
USB2P7

PERN3
PERP3
PETN3
PETP3

USB3RN1
USB3RP1

PCIE

USB

USB3TN1
USB3TP1

PERN4
PERP4

USB3RN2
USB3RP2

PETN4
PETP4

USB3TN2
USB3TP2

H_THRMTRIP#
KBRST#
44
SERIRQ
44

149.9_0402_1%
TC41

AN8
AM8

USB20_N0
USB20_P0

AR7
AT7

USB20_N1
USB20_P1

AR8
AP8

USB20_N2
USB20_P2

AR10
AT10

USB20_N3
USB20_P3

AM15
AL15

USB20_N4
USB20_P4

AM13
AN13

USB20_N5
USB20_P5

AP11
AN11

USB20_N6
USB20_P6

19
4

BOARD_ID3

PCH_BT_OFF#
PCH_WLAN_OFF#

BOARD_ID0

40

EC_SCI#

CMOS_ON#

C33
B34

USB30_TX_N1
USB30_TX_P1

USBRBIAS
USBRBIAS
RSVD11
RSVD12

PERN2/USB3RN4
PERP2/USB3RP4
PETN2/USB3TN4
PETP2/USB3TP4

OC0/GPIO40
OC1/GPIO41
OC2/GPIO42
OC3/GPIO43

RSVD9
RSVD10
PCIE_RCOMP
PCIE_IREF

2
RC123
10K_0402_5%

BOARD_ID2

BOARD_ID3

Reserve

Reserve

N15S-GT single rank

Description

Reserve

Reserve

N15S-GT Dual rank

Reserve

Reserve

14 panel

Reserve

Reserve

15 panel

+3VALW_PCH
PCH_GPIO15

RC114

2 1K_0402_5%

GPIO15, Internal PD
1: INTEL ME TLS W/ Confidentiality
*0: INTEL ME TLS W/O Confidentiality

USB20_N0
USB20_P0

45
45

RIGHT USB (2.0)

USB20_N1
USB20_P1

41
41

LEFT USB (3.0)

USB20_N2
USB20_P2

41
41

LEFT USB (2.0)

USB20_N3
USB20_P3

45
45

Card reader

USB20_N4
USB20_P4

33
33

Touch panel

USB20_N5
USB20_P5

33
33

Camera

USB20_N6
USB20_P6

40
40

BT

+3VS
PCH_GPIO66

RC113

2 1K_0402_5%

GPIO66, Internal 20K PD

1: Enable Top Swap Mode
*0: Disable Top Swap Mode(default)

+3VS

PCH_GPIO86

USB30_RX_N1
USB30_RX_P1

RC109
10K_0402_5%

33

AR13
AP13
G20
H20

RC108
10K_0402_5%
14@

44

USB30_RX_N1
USB30_RX_P1

41
41

USB30_TX_N1
USB30_TX_P1

41
41

RC115

1 1K_0402_5%

RC116

1 1K_0402_5%

1 1K_0402_5%

GPIO86, Internal PD
1: LPC
*0: SPI

LEFT USB (3.0)

E18
F18
B33
A33

+3VS

PERN1/USB3RN3
PERP1/USB3RP3
PETN1/USB3TN3
PETP1/USB3TP3

BOARD_ID1

2 0_0402_5%

RC121
10K_0402_5%
@

40
0

RC102
10K_0402_5%
@

RC107
10K_0402_5%
@

OPI_RCOMP
Width 20Mil
Space 15Mil
Length 500Mil

en

RC125

2 0_0402_5%
@

ODD_EN

2 10K_0402_5%

RC101
10K_0402_5%
15@

tia

RC103
D

BOARD_ID0
BOARD_ID1
BOARD_ID2
BOARD_ID3

RC100
10K_0402_5%
@

RC104
1K_0402_5%

+3VALW_PCH

HSW_ULT_DDR3L

UC1J

+3VS

+1.05V_VCCST

@ 2

SDM10U45LP-7_DFN1006-2-2

PCH_GPIO14

2 @

1
2
0_0402_5%

DC2

RC96

EC_LID_OUT#

PCH_GPIO12
DS3_WAKE#
PCH_GPIO25

2 10K_0402_5%
2 10K_0402_5%
2 10K_0402_5%

1
1
1

CC102

RC97
RC98
RC99

.01U_0402_16V7-K

44

+3VALW

PCH_BEEP

AJ10
AJ11
AN10
AM10

USBRBIAS

AL3
AT1
AH2
AV3

USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#

RC118

2
1
22.6_0402_1%

USB_OC1#
USB_OC2#

RC117

GPIO81, No Reboot, Internal PD

1: Enabled No Reboot Mode
*0: Disable No Reboot Mode

USBRBIAS
Width 20Mil
Space 15Mil
Length 500Mil

41
45
+3VALW_PCH

RPC17

8
7
6
5

USB_OC0#
USB_OC1#
USB_OC3#
USB_OC2#

11 OF 19
HASW ELL-ULT-DDR3L_BGA1168

1
2
3
4

10K_0804_8P4R_5%
10K_0804_8P4R_5%
RC122

2 10K_0402_5%

SERIRQ

RC181

2 10K_0402_5%

VGA_PWRGD

Issued Date

Title

LC Future Center Secret Data

Security Classification
2013/08/08

Deciphered Date

2013/08/05

MCP (GPIO,USB,PCIE)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Monday, December 30, 2013
Date:

Rev
1.0

ACLUA

PDF created with pdfFactory Pro trial version www.pdffactory.com

Sheet

of

59

CPU_CORE

CPU_VR_ON

+1.05VS
RC129

1 150_0402_1%

PW R_DEBUG

2
LC1 1
UPB100505T-121Y-N

12 OF 19

59

CPU_SVID_CLK

1
CPU_SVID_CLK_R

2 0_0402_5%

CPU_SVID_DAT_R

59

CPU_SVID_DAT

1
3
1

QC6B
G
S

0_0402_5%

2
G
1

QC6A

CC140
1000P_0402_50V7K
@

1
+

2
@

For RF

RC145
10K_0402_5%
@

+3VALW

RC146
10K_0402_5%

0_0402_5%
2
1
RC147
@

CPU_VR_READY

44,59

VR_CPU_PW ROK

2
1

CC141
100P_0402_50V8J
@

2N7002KDW H_SOT363-6
QC7A

G
0_0402_5%

1
2N7002KDW H_SOT363-6
QC7B

2N7002KDW H_SOT363-6
CC46
0.01U_0402_16V7K
@

+1.05V_VCCST

RC148

PCH_PW ROK

RC144
10K_0402_5%

2N7002KDW H_SOT363-6

RC138
8,44

VCCST_PW RGD

RC136
10K_0402_5%

CPU_VR_ON

RC137
1K_0402_5%

+3VALW

+1.05V_VCCST

CPU_SVID_ALERT#_R

2 0_0402_5%

RC135

1 43_0402_5%
@

CC49
0.01U_0402_16V7K
@

RC134

VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
HASWELL-ULT-DDR3L_BGA1168

2
RC133

VCCST1
VCCST2
VCCST3

CC42
.1U_0402_10V6-K
@

For RF

RC132
130_0402_1%

1
CPU_SVID_ALERT#

+1.05VS

RC131
75_0402_1%

59

AC22
AE22
AE23
AB57
AD57
AG57
C24
C28
C32

CC40
1U_0402_10V6K

on
fid

SVID
1, Stripline Line, No More Than 6000Mil
2, Alert# Route Between CLK and Data
3, CLK Length<Data Length<CLK Length + 2000Mil
4, Space at least 18Mil

CPU_CORE

33P_0402_50V8J
@
CC2

1
CC39
22U_0805_6.3V6M

VCCST(0.1A)

+1.35V_CPU

33P_0402_50V8J

+1.05V_VCCST

CD@

HW 4PCS 2.2UF CAP Mounted

HW 6PCS 10UF CAP Mounted
PWR 2PCS 470U Near VR Output

+1.05VS

VSS344
PWR_DEBUG
VSS345
RSVD_TP1
RSVD_TP2
RSVD_TP3
RSVD_TP4
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29

CC38

@ TC56
@ TC57
@ TC58
@ TC59
@ TC60
@ TC61
@ TC62
@ TC63
@ TC64

1
1
1
1
1
1
1
1
1

D63
H59
P62
P60
P61
N59
N61
T59
AD60
AD59
AA59
AE60
AC59
AG58
U59
V59

1.35V_CPU(1.4A)

33P_0402_50V8J

2
1
10K_0402_5%

1
1
1

HSW ULT POWER

CC37

RC130

@ TC53
@ TC54
@ TC55

VIDALERT
VIDSCLK
VIDSOUT
VCCST_PWRGD
VR_EN
VR_READY

59

L62
N63
L63
B59
F60
C59

CPU_SVID_ALERT#_R
CPU_SVID_CLK_R
CPU_SVID_DAT_R
VCCST_PW RGD
CPU_VR_ON
CPU_VR_READY

VCC_SENSE
RSVD17
VCCIO_OUT
VCCIOA_OUT
RSVD18
RSVD19
RSVD20

For cost down, change to X5R.

2
1

@ TC50
@ TC51
@ TC52

VCC1
RSVD15
RSVD16

CC41
330U_2.5V_M

1
1
1

E63
AB23
A59
E20
AD23
AA23
AE59

CC33
10U_0603_6.3V6M

F59
N58
AC58

CC32
10U_0603_6.3V6M

+VCCIOA_OUT
CC36
4.7U_0603_10V6-K
@

1
1

CC31
10U_0603_6.3V6M

@ TC47
@ TC48

2 0_0402_5%

CC35
10U_0603_6.3V6M

CPU_VCC_SENSE

CD@

CC30
10U_0603_6.3V6M

59

RC127
100_0402_1%

RC128

CC34
10U_0603_6.3V6M

VCC_SENSE
Length Match: <25Mil
Space: More Than 25Mil
GND Reference
+VCCIO_OUT

CPU_CORE

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11

AH26
AJ31
AJ33
AJ37
AN33
AP43
AR48
AY35
AY40
AY44
AY50

+1.35V_CPU

C36
C40
C44
C48
C52
C56
E23
E25
E27
E29
E31
E33
E35
E37
E39
E41
E43
E45
E47
E49
E51
E53
E55
E57
F24
F28
F32
F36
F40
F44
F48
F52
F56
G23
G25
G27
G29
G31
G33
G35
G37
G39
G41
G43
G45
G47
G49
G51
G53
G55
G57
H23
J23
K23
K57
L22
M23
M57
P57
U57
W57

VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68

CC29
2.2U_0603_10V6-K

JUMP_43X79

RSVD13
RSVD14

CC28
2.2U_0603_10V6-K

JC1

L59
J58

CC27
2.2U_0603_10V6-K

1
1

@ TC45
@ TC46

CC26
2.2U_0603_10V6-K

+1.35V_CPU

Need short

CPU_CORE

HSW_ULT_DDR3L

UC1L

+1.35V

tia

en

Issued Date

Title

LC Future Center Secret Data

Security Classification
2013/08/08

2013/08/05

Deciphered Date

MCP (Power)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Monday, December 30, 2013
Date:

Rev
1.0

ACLUA

PDF created with pdfFactory Pro trial version www.pdffactory.com

Sheet

10

of

59

+3VALW _PCH

1.741A

VCCRTC
HSIO

RTC

VCCSUS3_3[5]
VCCRTC
DCPRTC

1U_0402_10V6K

2 CC59 +1.05VS_DCPSUS3

J13

VCCSPI

OPI

+1.05VS

1U_0402_10V6K

2 CC60 +1.05VS_DCPSUS2

AH13

USB3

DCPSUS3
VCCHDA
VRM

DCPSUS2

CORE

+3VALW _PCH

VCCDSW 3_3

+3VS

VCC3_3[1:4]

41mA

GPIO/LPC

VCCTS1_5
VCC3_3[3]
VCC3_3[4]

THERMAL SENSOR

+1.05VS_PLPTVCC1P05
+1.05VS_PLPTCLKPLL

TC66
TC67

@ 1
@ 1

+3VALW _PCH

J18
K19
A20
J17
R21
T21
K18
M20
V21
AE20
AE21

VCCCLK[1]
VCCCLK[2]
VCCACLKPLL
VCCCLK[3]
VCCCLK[4]
VCCCLK[5]
RSVD31
RSVD32
RSVD33
VCCSUS3_3[3]
VCCSUS3_3[4]

SERIAL IO

VCCSDIO[1]
VCCSDIO[2]

SUS OSCILLATOR

DCPSUS4

+3VS

+1.05VS

2
1
@
0_0402_5%

0_0402_5% 2

VCCHDA

Need short
1

JC2

USB2

AC20
AG16
AG17

+1.05VS_PUSB3PLL

2
LC2 1
2.2UH_CIG10W 2R2MNC_20%

+1.05VS_PUSB3PLL
1

JUMP_43X79

RC152

CC78
22U_0805_6.3V6M

+3VS
RC153
+3V_SPI
B

2
1
@
0_0402_5%

0_0402_5% 2

VCCSPI

CC79
22U_0805_6.3V6M

CC80
1U_0402_10V6K

+1.05VS_PSATA3PLL

CC85
22U_0805_6.3V6M

+PCH_DCPSUSBYP

42mA

CC86
22U_0805_6.3V6M

For Intel recommend, place one 0.47uF

capacitor to address temporary inrush
current.(DOC.489999)

CD@

+1.05VS_PLPTVCC1P05

+1.05VS_PLPTCLKPLL

185mA

1
CC81
22U_0805_6.3V6M

1
CC100
22U_0805_6.3V6M

1
CC82
22U_0805_6.3V6M

1
CC83
22U_0805_6.3V6M

CC84
1U_0402_10V6K

+1.05VS_PLPTCLKPLL

31mA

2
LC5 1
2.2UH_CIG10W 2R2MNC_20%

CC87
1U_0402_10V6K

2 0.47U_0402_25V6K

+1.05VS_PLPTVCC1P05

2
LC3 1
2.2UH_CIG10W 2R2MNC_20%

CC90 1

+1.05VS

41mA

+1.05VS_PSATA3PLL

2
LC4 1
2.2UH_CIG10W 2R2MNC_20%

RC154

VCCDSW 3_3

+1.05VS_VCCHSIO

1U_0402_10V6K
2
1 @
CC73

+1.05VS_DCPSUS4

on
fid

RC151

17mA

CC77
1U_0402_10V6K

RSVD34
VCC1_05[8]
VCC1_05[9]

VCCDSW 3_3

+3VALW _PCH

1U_0402_10V6K

AB8

13 OF 19

2
1
0_0402_5%

VCCSDIO

U8
T9

HASWELL-ULT-DDR3L_BGA1168

RC150

1 @

+3VS

+1.05VS

+3VL

2
1
@
0_0402_5%

3mA

LPT LP POWER

CD@

RC149

CC66

+1.05VS

CC74
1U_0402_10V6K

CC76
1U_0402_10V6K

CC75
1U_0402_10V6K

+3VALW

+1.05VS_DCPSUS1

VCCTS1_5

1U_0402_10V6K
2
1
CC61

+PCH_DCPSUSBYP

+1.5VS

J15
K14
K16

+1.05VS

+3VS

+1.05VS

VCCSUS3_3[1]
VCCSUS3_3[2]
VCCDSW3_3
VCC3_3[1]
VCC3_3[2]

CC72
0.1U_0402_10V7K

AC9
AA9
AH10
V8
W9

114mA
CC71
22U_0805_6.3V6M

CC70 @
1U_0402_10V6K

CC67
22U_0805_6.3V6M

65mA

VCCDSW

J11
H11
H15
AE8
AF22
AG19
AG20
AE9
AF9
AG8
AD10
AD8

658mA

tia

VCCSUS3_3[1:5]

VCCASW[1:5]

22U_0805_6.3V6M
CC69
@

VCC1_05[3]
VCC1_05[4]
VCC1_05[5]
VCC1_05[6]
VCC1_05[7]
DCPSUSBYP[1]
DCPSUSBYP[2]
VCCASW[3]
VCCASW[4]
VCCASW[5]
DCPSUS1[1]
DCPSUS1[2]

HDA

AG14
AG13

0.1U_0402_10V7K

en

10U_0603_6.3V6M
CC65

AH14

18mA

1mA

1U_0402_10V6K
CC68

CC62
1U_0402_10V6K

11mA

VCCSPI

Y8

1U_0402_10V6K
CC64

VCCHDA

CC52

1U_0402_10V6K
CC63

VCCHDA

VCCRTC
+DCPRTC

VCCSPI
SPI

RSVD30
VCCAPLL[1]
VCCAPLL[2]

VCCASW[1]
VCCASW[2]
@

AH11
AG10
AE7

1U_0402_10V6K
CC57

Y20
AA21
W21

+1.05VS_POPIPLL

CC50
1U_0402_10V6K

0.1U_0402_10V7K
CC56

+1.05VS_PUSB3PLL
+1.05VS_PSATA3PLL

VCCHSIO[1]
VCCHSIO[2]
VCCHSIO[3]
VCC1_05[1]
VCC1_05[2]
VCCUSB3PLL
VCCSATA3PLL

CC58 @
0.1U_0402_10V7K

VCC1_05[1:9]

K9
L10
M9
N8
P9
B18
B11

0.1U_0402_10V7K
CC55

CC54
1U_0402_10V6K

CC51
1U_0402_10V6K

CC53
1U_0402_10V6K

+1.05VS

1.838A

VCCHSIO

HSW_ULT_DDR3L

UC1M

+1.05VS_VCCHSIO

1
CC88
22U_0805_6.3V6M

1
CC95
22U_0805_6.3V6M

1
CC98
22U_0805_6.3V6M

1
CC99
22U_0805_6.3V6M

CC89
1U_0402_10V6K

+1.05VS_POPIPLL
@
LC6 1

+1.05VS_POPIPLL

2
0_0603_5%

CC91
33P_0402_50V8J
@

57mA

CC92
47U_0805_4V6-M
2@

CC93
47U_0805_4V6-M
2@

CC94
1U_0402_10V6K

For RF

Issued Date

Title

LC Future Center Secret Data

Security Classification
2013/08/08

2013/08/05

Deciphered Date

MCP (Power2)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Thursday, December 26, 2013
Date:

Rev
1.0

ACLUA

PDF created with pdfFactory Pro trial version www.pdffactory.com

Sheet

11

of

59

HSW_ULT_DDR3L

VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256

AV59
AV8
AW16
AW24
AW33
AW35
AW37
AW4
AW40
AW42
AW44
AW47
AW50
AW51
AW59
AW60
AY11
AY16
AY18
AY22
AY24
AY26
AY30
AY33
AY4
AY51
AY53
AY57
AY59
AY6
B20
B24
B26
B28
B32
B36
B4
B40
B44
B48
B52
B56
B60
C11
C14
C18
C20
C25
C27
C38
C39
C57
D12
D14
D18
D2
D21
D23
D25
D26
D27
D29
D30
D31

UC1P

D33
D34
D35
D37
D38
D39
D41
D42
D43
D45
D46
D47
D49
D5
D50
D51
D53
D54
D55
D57
D59
D62
D8
E11
E17
F20
F26
F30
F34
F38
F42
F46
F50
F54
F58
F61
G18
G22
G3
G5
G6
G8
H13

HSW_ULT_DDR3L

VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS287
VSS288
VSS289
VSS290
VSS291
VSS292
VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299

VSS300
VSS301
VSS302
VSS303
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS314
VSS315
VSS316
VSS317
VSS318
VSS319
VSS320
VSS321
VSS322
VSS323
VSS324
VSS325
VSS326
VSS327
VSS328
VSS329
VSS330
VSS331
VSS332
VSS333
VSS334
VSS335
VSS336
VSS337

16 OF 19
HASWELL-ULT-DDR3L_BGA1168

V58
AH46
V23
E62
AH16

RC158

RC159
100_0402_1%

PDF created with pdfFactory Pro trial version www.pdffactory.com

59

Title

LC Future Center Secret Data

2013/08/08

2013/08/05

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
3

CPU_VSS_SENSE

VSS_SENSE
Length Match: No More Than 25Mil
Space: More Than 25Mil
GND Reference

MCP (VSS)
Size
Document Number
Custom
Date:

2 0_0402_5%

Security Classification
Issued Date

VSS338
VSS339
VSS340
VSS_SENSE
VSS341

H17
H57
J10
J22
J59
J63
K1
K12
L13
L15
L17
L18
L20
L58
L61
L7
M22
N10
N3
P59
P63
R10
R22
R8
T1
T58
U20
U22
U61
U9
V10
V3
V7
W20
W22
Y10
Y59
Y63

VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192

15 OF 19
HASWELL-ULT-DDR3L_BGA1168

14 OF 19
HASWELL-ULT-DDR3L_BGA1168

VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128

AP22
AP23
AP26
AP29
AP3
AP31
AP38
AP39
AP48
AP52
AP54
AP57
AR11
AR15
AR17
AR23
AR31
AR33
AR39
AR43
AR49
AR5
AR52
AT13
AT35
AT37
AT40
AT42
AT43
AT46
AT49
AT61
AT62
AT63
AU1
AU16
AU18
AU20
AU22
AU24
AU26
AU28
AU30
AU33
AU51
AU53
AU55
AU57
AU59
AV14
AV16
AV20
AV24
AV28
AV33
AV34
AV36
AV39
AV41
AV43
AV46
AV49
AV51
AV55

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64

UC1O

AJ35
AJ39
AJ41
AJ43
AJ45
AJ47
AJ50
AJ52
AJ54
AJ56
AJ58
AJ60
AJ63
AK23
AK3
AK52
AL10
AL13
AL17
AL20
AL22
AL23
AL26
AL29
AL31
AL33
AL36
AL39
AL40
AL45
AL46
AL51
AL52
AL54
AL57
AL60
AL61
AM1
AM17
AM23
AM31
AM52
AN17
AN23
AN31
AN32
AN35
AN36
AN39
AN40
AN42
AN43
AN45
AN46
AN48
AN49
AN51
AN52
AN60
AN63
AN7
AP10
AP17
AP20

tia

HSW_ULT_DDR3L

on
fid

UC1N

A11
A14
A18
A24
A28
A32
A36
A40
A44
A48
A52
A56
AA1
AA58
AB10
AB20
AB22
AB7
AC61
AD21
AD3
AD63
AE10
AE5
AE58
AF11
AF12
AF14
AF15
AF17
AF18
AG1
AG11
AG21
AG23
AG60
AG61
AG62
AG63
AH17
AH19
AH20
AH22
AH24
AH28
AH30
AH32
AH34
AH36
AH38
AH40
AH42
AH44
AH49
AH51
AH53
AH55
AH57
AJ13
AJ14
AJ23
AJ25
AJ27
AJ29

en

Rev
1.0

ACLUA

Thursday, December 26, 2013

1

Sheet

12

of

59

UC1Q

TC70

TC73

DC_TEST_AY2_AW2
DC_TEST_AY3_AW3
TP_DC_TEST_AY60
DC_TEST_AY61_AW61
DC_TEST_AY62_AW62
TP_DC_TEST_B2
DC_TEST_A3_B3
DC_TEST_A61_B61
DC_TEST_B62_B63

@ 1
@ 1

DC_TEST_C1_C2

AY2
AY3
AY60
AY61
AY62
B2
B3
B61
B62
B63
C1
C2

HSW_ULT_DDR3L

DAISY_CHAIN_NCTF_AY2
DAISY_CHAIN_NCTF_AY3
DAISY_CHAIN_NCTF_AY60
DAISY_CHAIN_NCTF_AY61
DAISY_CHAIN_NCTF_AY62
DAISY_CHAIN_NCTF_B2
DAISY_CHAIN_NCTF_B3
DAISY_CHAIN_NCTF_B61
DAISY_CHAIN_NCTF_B62
DAISY_CHAIN_NCTF_B63
DAISY_CHAIN_NCTF_C1
DAISY_CHAIN_NCTF_C2

DAISY_CHAIN_NCTF_A3
DAISY_CHAIN_NCTF_A4

17 OF 19

DAISY_CHAIN_NCTF_A60
DAISY_CHAIN_NCTF_A61
DAISY_CHAIN_NCTF_A62
DAISY_CHAIN_NCTF_AV1
DAISY_CHAIN_NCTF_AW1
DAISY_CHAIN_NCTF_AW2
DAISY_CHAIN_NCTF_AW3
DAISY_CHAIN_NCTF_AW61
DAISY_CHAIN_NCTF_AW62
DAISY_CHAIN_NCTF_AW63

A3
A4

DC_TEST_A3_B3
TP_DC_TEST_A4

A60
A61
A62
AV1
AW1
AW2
AW3
AW61
AW62
AW63

TP_DC_TEST_A60
DC_TEST_A61_B61
TP_DC_TEST_A62
TP_DC_TEST_AV1
TP_DC_TEST_AW1
DC_TEST_AY2_AW2
DC_TEST_AY3_AW3
DC_TEST_AY61_AW61
DC_TEST_AY62_AW62
TP_DC_TEST_AW63

1 @

TC71

1 @

TC72

1 @
1 @
1 @

TC74
TC75
TC76

1 @

TC77

HASWELL-ULT-DDR3L_BGA1168

TC88

@ 1
@ 1
@ 1

AT2
AU44
AV44
D15

@ 1

F22
H22
J21

RSVD42
RSVD43
RSVD44
RSVD45

RSVD35
RSVD36
RSVD37
RSVD38

RSVD46
RSVD47
RSVD48
RSVD49
RSVD50
RSVD51
RSVD52

RSVD39
RSVD40
RSVD41

18 OF 19

UC1S

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15

AC60
AC62
AC63
AA63
AA60
Y62
Y61
Y60
V62
V61
V60
U60
T63
T62
T61
T60

TC123
TC124
TC125
TC127

@
@
@
@

1
1
1
1

CFG16
CFG18
CFG17
CFG19

AA62
U63
AA61
U62

1 49.9_0402_1%
TC129

CFG_RCOMP&TD_IREF
Width 20Mil
Space 15Mil
Length 500Mil
2
RC166

CFG_RCOMP

@ 1

TC135
@ 1
1
8.2K_0402_1%

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15

V63
A5

TD_IREF

RSVD_TP5
RSVD_TP6

on
fid

RC163

@
@
@
@
@
@
@
@
@
@
@
@
@
@
@
@

E1
D1
J20
H18
B12

RSVD_TP7
RSVD_TP8
RSVD58

RSVD_TP9
RSVD_TP10
RSVD_TP11

RESERVED

RSVD59

RSVD60
RSVD61
PROC_OPI_RCOMP

CFG16
CFG18
CFG17
CFG19

RSVD62
RSVD63

CFG_RCOMP

VSS342
VSS343

RSVD53

RSVD64
RSVD65

RSVD54
RSVD55
RSVD56
RSVD57
TD_IREF

TC96
TC98
TC99
TC100
TC102
TC104
TC106
TC108
TC109
TC111
TC113
TC114
TC116
TC117
TC119
TC120

HSW_ULT_DDR3L

1 @

AL1
AM11
AP7
AU10
AU15
AW14
AY14

en

HASWELL-ULT-DDR3L_BGA1168

N23
R23
T23
U10

TC78
TC82
TC84

HSW_ULT_DDR3L

TC83

tia

UC1R

1 @

TC86

1 @

TC93

AV63
AU63

1 @
1 @

TC97
TC101

C63
C62
B43

1 @
1 @
1 @

TC103
TC105
TC107

A51
B51

1 @
1 @

TC110
TC112

L60

1 @

TC115

N60

1 @

TC118

1 @

TC126

W23
Y22
AY15

PROC_OPI_COMP

AV62
D58

CFG3

RC160

1 1K_0402_1%

CFG3
*1: Disable
0: Enable, Set DFX Enabled BIT
In Debug Interface MSR

CFG4

RC162

2
1
49.9_0402_1%

PROC_OPI_RCOMP
Width 20Mil
Space 15Mil
Length 500Mil

RC161

1 1K_0402_1%

CFG4
*L: eDP enable
H: eDP disable

P22
N21
P20
R20
CFG0

RC164

1 1K_0402_1%

CFG1

RC165

1 1K_0402_1%

CFG8

RC167

1 1K_0402_1%

CFG9

RC168

1 1K_0402_1%

CFG10

RC169

1 1K_0402_1%

19 OF 19

HASWELL-ULT-DDR3L_BGA1168

Issued Date

Title

LC Future Center Secret Data

Security Classification
2013/08/08

2013/08/05

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MCP (OTHER)
Size
Document Number
Custom
Date:

PDF created with pdfFactory Pro trial version www.pdffactory.com

Rev
1.0

ACLUA

Thursday, December 26, 2013

1

Sheet

13

of

59

DDR_SA_VREFDQ

DDR3 SO-DIMM A

+1.35V
+1.35V

DDRA_DQ[0..63]

DDRA_DQS[0..7]

+1.35V

DDRA_DQS#[0..7]

3A@1.5V

RD11
1.82K_0402_1%

1
1

CD@
2

CD20
220U_6.3V_M
@

Note:
VREF trace width:20 mils at least
Spacing:20mils to other signal/planes
Place near DIMM scoket
2 0_0402_5%
1

DDR_SM_VREFCA

6
B

CD21
0.022U_0402_16V7-K

RD12
24.9_0402_1%

DDRA_DQ44
DDRA_DQ45

Layout Note:
Place near DIMM

(10U_0603_6.3V)*2
(.1U_0402_10V)*4

DDRA_DQ46
DDRA_DQ47
DDRA_DQ52
DDRA_DQ53

+0.675VS

DDRA_DQS#7
DDRA_DQS7

1
CD@
2

1
CD@
2

10U_0603_6.3V6M

DDRA_DQ60
DDRA_DQ61

CD65

DDRA_DQ54
DDRA_DQ55

10U_0603_6.3V6M

15

CD64

CD@
2

1U_0402_6.3V6K

CD59

CD@
2

1U_0402_6.3V6K

CD58

CD@
2

1U_0402_6.3V6K

CD57

1U_0402_6.3V6K

CD56

.1U_0402_10V6-K

RD10 1

+VREF_CA
+VREF_CA

.1U_0402_10V6-K

LCN_DAN06-K4406-0103
ME@

RD9
1.82K_0402_1%

Trace width:20 mils

Space:20mils

CD27

GND2
BOSS2

206
208

+1.35V

CD23
2.2U_0603_6.3V6K
CD@

DDRA_DQS#5
DDRA_DQS5

CD19

.1U_0402_10V6-K

DDRA_DQ38
DDRA_DQ39

CD18

.1U_0402_10V6-K

+VREF_CA

DDRA_DQ36
DDRA_DQ37

CD17

.1U_0402_10V6-K

DDRA_ODT1

CD16

6
5

CD15

DDRA_CS0#
DDRA_ODT0

10U_0603_6.3V6M

6
6

CD14

DDRA_ODT1

DDRA_BS1#
DDRA_RAS#

.1U_0402_10V6-K

GND1
BOSS1

DDRA_CS0#
DDRA_ODT0

DDRA_CLK1
DDRA_CLK1#

CD26

205
207

DDRA_BS1#
DDRA_RAS#

.1U_0402_10V6-K

@
0_0402_5%
RD14

CD29
.1U_0402_10V6-K

DDRA_CLK1
DDRA_CLK1#

CD25

CD28
2.2U_0603_6.3V6K

DDRA_MA2
DDRA_MA0

CD@
2

.1U_0402_10V6-K

DDRA_MA6
DDRA_MA4

CD@
2

CD24

+3VS

DDRA_MA11
DDRA_MA7

CD22
.1U_0402_10V6-K

DDRA_CKE1

DDRA_MA15
DDRA_MA14

10U_0603_6.3V6M

DDRA_CKE1

CD13

DDRA_CS1#

DDRA_DQ30
DDRA_DQ31

10U_0603_6.3V6M

+1.35V

DDRA_DQS#3
DDRA_DQS3

CD12

DDRA_WE#
DDRA_CAS#

DDRA_DQ28
DDRA_DQ29

10U_0603_6.3V6M

6
6

DDRA_DQ22
DDRA_DQ23

CD11

DDRA_BS0#

OSCON (220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y0J)
(10uF_0603_6.3V)*8
(1U_0402_6.3V)*4
(.1U_0402_10V6-K)*4

Layout Note:
Place near DIMM

10U_0603_6.3V6M

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

DDRA_DQ20
DDRA_DQ21

CD10

DDRA_CLK0
DDRA_CLK0#

CKE1
VDD_2
A15
A14
VDD_4
A11
A7
VDD_6
A6
A4
VDD_8
A2
A0
VDD_10
CK1
CK1#
VDD_12
BA1
RAS#
VDD_14
S0#
ODT0
VDD_16
ODT1
NC_2
VDD_18
VREF_CA
VSS_28
DQ36
DQ37
VSS_30
DM4
VSS_32
DQ38
DQ39
VSS_34
DQ44
DQ45
VSS_35
DQS5#
DQS5
VSS_38
DQ46
DQ47
VSS_40
DQ52
DQ53
VSS_42
DM6
VSS_44
DQ54
DQ55
VSS_46
DQ60
DQ61
VSS_48
DQS7#
DQS7
VSS_50
DQ62
DQ63
VSS_52
EVENT#
SDA
SCL
VTT_2

5,15

10U_0603_6.3V6M

6
6

DDRA_BS2#

CKE0
VDD_1
NC_1
BA2
VDD_3
A12/BC#
A9
VDD_5
A8
A5
VDD_7
A3
A1
VDD_9
CK0
CK0#
VDD_11
A10/AP
BA0
VDD_13
WE#
CAS#
VDD_15
A13
S1#
VDD_17
TEST
VSS_27
DQ32
DQ33
VSS_29
DQS4#
DQS4
VSS_31
DQ34
DQ35
VSS_33
DQ40
DQ41
VSS_36
DM5
VSS_37
DQ42
DQ43
VSS_39
DQ48
DQ49
VSS_41
DQS6#
DQS6
VSS_43
DQ50
DQ51
VSS_45
DQ56
DQ57
VSS_47
DM7
VSS_49
DQ58
DQ59
VSS_51
SA0
VDDSPD
SA1
VTT_1

CPU_DRAMRST#

DDRA_DQ14
DDRA_DQ15

10U_0603_6.3V6M

73
75
77
79
DDRA_BS2#
81
83
DDRA_MA12
85
DDRA_MA9
87
89
DDRA_MA8
91
DDRA_MA5
93
95
DDRA_MA3
97
DDRA_MA1
99
101
DDRA_CLK0
103
DDRA_CLK0#
105
107
DDRA_MA10
109
DDRA_BS0#
111
113
DDRA_WE#
115
DDRA_CAS#
117
119
DDRA_MA13
121
DDRA_CS1#
123
125
127
129
DDRA_DQ32
131
DDRA_DQ33
133
135
DDRA_DQS#4
137
DDRA_DQS4
139
141
DDRA_DQ34
143
DDRA_DQ35
145
147
DDRA_DQ40
149
DDRA_DQ41
151
153
155
157
DDRA_DQ42
159
DDRA_DQ43
161
163
DDRA_DQ48
165
DDRA_DQ49
167
169
DDRA_DQS#6
171
DDRA_DQS6
173
175
DDRA_DQ50
177
DDRA_DQ51
179
181
DDRA_DQ56
183
DDRA_DQ57
185
187
189
191
DDRA_DQ58
193
DDRA_DQ59
195
1
2 0_0402_5% 197
@
RD13
199
201
203
DDRA_CKE0

DDRA_CKE0

CPU_DRAMRST#

CD9

DDRA_DQ12
DDRA_DQ13

10U_0603_6.3V6M

DDRA_DQ26
DDRA_DQ27

CD8

DDRA_DQ24
DDRA_DQ25

DDRA_DQ18
DDRA_DQ19

DDRA_DQ6
DDRA_DQ7

DDRA_DQS#2
DDRA_DQS2

DDRA_DQ16
DDRA_DQ17

DDRA_DQ10
DDRA_DQ11

DDRA_DQS#0
DDRA_DQS0

DDRA_DQS#1
DDRA_DQS1

DDRA_DQ4
DDRA_DQ5

RD8
24.9_0402_1%

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

on
fid

2
1

DDRA_DQ8
DDRA_DQ9

VSS_2
DQ4
DQ5
VSS_4
DQS0#
DQS0
VSS_6
DQ6
DQ7
VSS_8
DQ12
DQ13
VSS_10
DM1
RESET#
VSS_12
DQ14
DQ15
VSS_14
DQ20
DQ21
VSS_16
DM2
VSS_18
DQ22
DQ23
VSS_20
DQ28
DQ29
VSS_22
DQS3#
DQS3
VSS_24
DQ30
DQ31
VSS_26

DDRA_DQ2
DDRA_DQ3

VREF_DQ
VSS_1
DQ0
DQ1
VSS_3
DM0
VSS_5
DQ2
DQ3
VSS_7
DQ8
DQ9
VSS_9
DQS1#
DQS1
VSS_11
DQ10
DQ11
VSS_13
DQ16
DQ17
VSS_15
DQS2#
DQS2
VSS_17
DQ18
DQ19
VSS_19
DQ24
DQ25
VSS_21
DM3
VSS_23
DQ26
DQ27
VSS_25

CD7
33P_0402_50V8J

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

CD6
33P_0402_50V8J

DDRA_DQ0
DDRA_DQ1

CD5
33P_0402_50V8J

CD@

CD2

.1U_0402_10V6-K

CD4

2.2U_0603_6.3V6K

JDDR1
+VREF_DQ_DIMMA
RD7
1.82K_0402_1%

CD3
0.022U_0402_16V7-K

1
2
2_0402_5%

DDRA_MA[0..15]

For RF

tia

RD6

en

RD5
1.82K_0402_1%

1
CD@
2

DDRA_DQ62
DDRA_DQ63
SMB_DATA_S3
SMB_CLK_S3

SMB_DATA_S3
SMB_CLK_S3
+0.675VS

0.65A@0.75V
CD68
33P_0402_50V8J
@

For RF

PDF created with pdfFactory Pro trial version www.pdffactory.com

7,15,40
7,15,40

Issued Date

Title

LC Future Center Secret Data

Security Classification
2013/08/08

2013/08/05

Deciphered Date

DDRIII SO-DIMM A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Thursday, December 26, 2013
Date:

Rev
1.0

ACLUA

Sheet

14

of

59

DDR_SB_VREFDQ

DDR3 SO-DIMM B

+1.35V

Swap Table
Pin
Number

+1.35V

+1.35V

3A@1.5V

DDRB_DQ8
DDRB_DQ10
DDRB_DQS#1
DDRB_DQS1
DDRB_DQ14
DDRB_DQ15
DDRB_DQ27
DDRB_DQ26

10U_0603_6.3V6M

1U_0402_6.3V6K

CD63

1U_0402_6.3V6K

CD62

1
CD@
2

CD43

1
CD@
2

2 0_0402_5%

+VREF_CA

14

CD49
2.2U_0603_6.3V6K
CD@

DDRB_DQ45
DDRB_DQ41

Layout Note:
Place near DIMM

DDRB_DQS#5
DDRB_DQS5

(10U_0603_6.3V)*2
(.1U_0402_10V)*4

DDRB_DQ46
DDRB_DQ47

+0.675VS

DDRB_DQ49
DDRB_DQ53

DDRB_DQ54
DDRB_DQ55
DDRB_DQ56
DDRB_DQ61
DDRB_DQS#7
DDRB_DQS7

1
CD@
2

1
CD@
2

1
CD@
2

DDRB_DQ58
DDRB_DQ60

Pin Name

Net Name

5
7
15
17
4
6
16
18
10
12

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS#0
DQS0

DDRB_DQ17
DDRB_DQ23
DDRB_DQ18
DDRB_DQ21
DDRB_DQ16
DDRB_DQ22
DDRB_DQ19
DDRB_DQ20
DDRB_DQS#2
DDRB_DQS2

21
23
33
35
22
24
34
36
27
29

DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS#1
DQS1

DDRB_DQ3
DDRB_DQ5
DDRB_DQ6
DDRB_DQ1
DDRB_DQ2
DDRB_DQ4
DDRB_DQ0
DDRB_DQ7
DDRB_DQS#0
DDRB_DQS0

39
41
51
53
40
42
50
52
45
47

DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS#2
DQS2

DDRB_DQ8
DDRB_DQ10
DDRB_DQ14
DDRB_DQ15
DDRB_DQ13
DDRB_DQ12
DDRB_DQ9
DDRB_DQ11
DDRB_DQS#1
DDRB_DQS1

57
59
67
69
56
58
68
70
62
64

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS#3
DQS3

DDRB_DQ27
DDRB_DQ26
DDRB_DQ28
DDRB_DQ24
DDRB_DQ31
DDRB_DQ30
DDRB_DQ29
DDRB_DQ25
DDRB_DQS#3
DDRB_DQS3

129
131
141
143
130
132
140
142
135
137

DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS#4
DQS4

DDRB_DQ33
DDRB_DQ36
DDRB_DQ39
DDRB_DQ38
DDRB_DQ37
DDRB_DQ32
DDRB_DQ35
DDRB_DQ34
DDRB_DQS#4
DDRB_DQS4

147
149
157
159
146
148
158
160
152
154

DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS#5
DQS5

DDRB_DQ40
DDRB_DQ43
DDRB_DQ42
DDRB_DQ44
DDRB_DQ45
DDRB_DQ41
DDRB_DQ46
DDRB_DQ47
DDRB_DQS#5
DDRB_DQS5

163
165
175
177
164
166
174
176
169
171

DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS#6
DQS6

DDRB_DQ52
DDRB_DQ51
DDRB_DQ50
DDRB_DQ48
DDRB_DQ49
DDRB_DQ53
DDRB_DQ54
DDRB_DQ55
DDRB_DQS#6
DDRB_DQS6

181
183
191
193
180
182
192
194
186
188

DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQS#7
DQS7

DDRB_DQ62
DDRB_DQ57
DDRB_DQ59
DDRB_DQ63
DDRB_DQ56
DDRB_DQ61
DDRB_DQ58
DDRB_DQ60
DDRB_DQS#7
DDRB_DQS7

SMB_DATA_S3
SMB_CLK_S3

SMB_DATA_S3
SMB_CLK_S3
+0.675VS

7,14,40
7,14,40

0.65A@0.75V

206

CD69
33P_0402_50V8J
@

For RF
5

RD19 1

10U_0603_6.3V6M

G2

CD67

G1

LCN_DAN06-K4406-0102
ME@

1
CD@
2

10U_0603_6.3V6M

1
CD@
2

CD42

DDRB_DQ35
DDRB_DQ34

1U_0402_6.3V6K

CD48

10U_0603_6.3V6M

205
CD55
.1U_0402_10V6-K

+VREF_CB

DDRB_DQ37
DDRB_DQ32

CD66

.1U_0402_10V6-K

1
CD54
2.2U_0603_6.3V6K

6
5

DDRB_ODT1

CD53

+3VS

DDRB_CS0#
DDRB_ODT0

.1U_0402_10V6-K

2 @
0_0402_5%
1
2
RD21 10K_0402_5%

DDRB_ODT1

CD52

RD20 1

DDRB_CS0#
DDRB_ODT0

.1U_0402_10V6-K

DDRB_DQ59
DDRB_DQ63
A

6
6

CD51

DDRB_DQ62
DDRB_DQ57

DDRB_BS1#
DDRB_RAS#

.1U_0402_10V6-K

DDRB_DQ50
DDRB_DQ48

CD50

DDRB_DQS#6
DDRB_DQS6

DDRB_CLK1
DDRB_CLK1#

CD61

DDRB_DQ52
DDRB_DQ51

DDRB_MA2
DDRB_MA0

10U_0603_6.3V6M

DDRB_DQ42
DDRB_DQ44

DDRB_MA6
DDRB_MA4

DDRB_BS1#
DDRB_RAS#

CD41

DDRB_DQ40
DDRB_DQ43

DDRB_MA11
DDRB_MA7

DDRB_CLK1
DDRB_CLK1#

1U_0402_6.3V6K

DDRB_DQ39
DDRB_DQ38

1
CD@

CD60

DDRB_DQS#4
DDRB_DQS4

DDRB_CKE1

DDRB_MA15
DDRB_MA14

.1U_0402_10V6-K

DDRB_DQ33
DDRB_DQ36

DDRB_CKE1

1
CD@

CD40

DDRB_DQ29
DDRB_DQ25

CD47

DDRB_CS1#

DDRB_MA13
DDRB_CS1#

+1.35V

DDRB_DQS#3
DDRB_DQS3

10U_0603_6.3V6M

DDRB_WE#
DDRB_CAS#

DDRB_DQ31
DDRB_DQ30

CD39

DDRB_WE#
DDRB_CAS#

DDRB_DQ9
DDRB_DQ11

.1U_0402_10V6-K

DDRB_BS0#

6
6

(10uF_0603_6.3V)*8
(1U_0402_6.3V)*8
(.1U_0402_10V6-K)*4

Layout Note:
Place near DIMM

DDRB_DQ13
DDRB_DQ12

.1U_0402_10V6-K

DDRB_MA10
DDRB_BS0#

6
6

5,14

CD46

DDRB_CLK0
DDRB_CLK0#

CPU_DRAMRST#

DDRB_DQ0
DDRB_DQ7

.1U_0402_10V6-K

DDRB_CLK0
DDRB_CLK0#

6
6

CPU_DRAMRST#

CD45

DDRB_MA3
DDRB_MA1

DDRB_DQ2
DDRB_DQ4

.1U_0402_10V6-K

DDRB_MA8
DDRB_MA5

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

CD44

DDRB_MA12
DDRB_MA9

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

10U_0603_6.3V6M

DDRB_BS2#

10U_0603_6.3V6M

DDRB_BS2#

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

CD38

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

DDRB_DQ19
DDRB_DQ20

CD37

DDRB_CKE0

10U_0603_6.3V6M

DDRB_CKE0

DDRB_DQS#2
DDRB_DQS2

CD36

DDRB_DQS[0..7]

DDRB_MA[0..15]

10U_0603_6.3V6M

DDRB_DQ28
DDRB_DQ24
C

DDRB_DQ6
DDRB_DQ1

DDRB_DQ16
DDRB_DQ22

tia

DDRB_DQS#0
DDRB_DQS0

DDRB_DQ[0..63]

DDRB_DQS#[0..7]

on
fid

1
2

RD18
24.9_0402_1%

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

DDRB_DQ3
DDRB_DQ5

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

CD35
33P_0402_50V8J

DDRB_DQ18
DDRB_DQ21

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

CD34
33P_0402_50V8J

DDRB_DQ17
DDRB_DQ23

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

CD33
33P_0402_50V8J

.1U_0402_10V6-K

CD31

CD@

2.2U_0603_6.3V6K

CD30

For RF

JDDR2
+VREF_DQ_DIMMB
RD17
1.82K_0402_1%

CD32
0.022U_0402_16V7-K

RD16

1
2
2_0402_5%

en

RD15
1.82K_0402_1%

PDF created with pdfFactory Pro trial version www.pdffactory.com

Issued Date

Title

LC Future Center Secret Data

Security Classification
2013/08/08

2013/08/05

Deciphered Date

DDRIII SO-DIMM B

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Thursday, December 26, 2013
Date:

Rev
1.0

ACLUA

Sheet

15

of

59

en

tia

on
fid

Title

LC Future Center Secret Data

Security Classification
Issued Date

2013/08/08

PDF created with pdfFactory Pro trial version www.pdffactory.com

Blank

2013/08/05

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Size
Document Number
Custom
Date:

Rev
1.0

ACLUA

Thursday, December 26, 2013

1

Sheet

16

of

59

en

tia

on
fid

Title

LC Future Center Secret Data

Security Classification
Issued Date

2013/08/08

PDF created with pdfFactory Pro trial version www.pdffactory.com

Blank

2013/08/05

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Size
Document Number
Custom
Date:

Rev
1.0

ACLUA

Thursday, December 26, 2013

1

Sheet

17

of

59

N15x GPIO
I/O

GPIO0

OUT

GPIO1

OUT

Performance Mode P0 TDP at Tj = 102 C* (DDR3)

Function Description

N/A

OUT

N/A

GPIO3

OUT

N/A

GPIO4

OUT

N/A

GPIO5

OUT

N/A

GPU power sequencing---3V3_MAIN_EN

GPIO6

IN

GPU wake signal for GC6 2.0

GPIO7

OUT

N/A

GPIO8

I/O

System side PCIe reset Monitor

GPIO9

I/O

N/A

2.2K Pull-up

GPIO10

OUT

N/A

GPIO11

OUT

GPU Core VDD PWM control signal

GPIO12

IN

GPIO13

OUT

Phase Shedding

IN

N/A

IN
IN

N/A

GPIO19

IN

N/A

GPIO20

(A)

(W)

(A)

(W)

(mA)

(W)

(mA)

(W)

(mA)

(W)

N14X
128bit
2GB
DDR3

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

ROM_SI
ROM_SO

N/A

GPIO18

(W)

FBVDD
(1.35V)

NVVDD

Logical
Strapping Bit3

Logical
Strapping Bit2

Logical
Strapping Bit1

Logical
Strapping Bit0

+3VGS

SOR3_EXPOSED

SOR2_EXPOSED

SOR1_EXPOSED

SOR0_EXPOSED

+3VGS

RAM_CFG[3]

RAM_CFG[2]

RAM_CFG[1]

RAM_CFG[0]

DEVID_SEL

PCIE_CFG

SMB_ALT_ADDR

VGA_DEVICE

Power Rail

+3VGS

N/A

STRAP0

+3VGS

STRAP1

+3VGS

STRAP2

+3VGS

STRAP3

+3VGS

STRAP4

+3VGS

Other
(3.3V)

Reserved(keep pull-up and pull-down footprint and stuff 50Kohm pull-up)

Reserved(keep pull-up and pull-down footprint and not stuff by default)

SMBUS_ALT_ADDR

on
fid

GPIO17

(A)

Physical
Strapping pin
ROM_SCLK

N/A

GPIO16

I/O and
PLLVDD
(1.05V)

(V)

en

GPIO15

FBVDDQ
PCI Express
(GPU+Mem) (1.05V)
(1.35V)
(6)

(MHz)

(10K pull High)

N/A

NVCLK
/MCLK

(W)

N15x Multi-level Straps

AC Power Detect Input

IN

Mem
(1,5)

(W)

GPIO2

GPIO14

GPU
(4)
Products

FB Enable for GC6 2.0

ACTIVE

tia

GPIO

GPIO21

OUT

GPU PCIe self-reset control

OVERT

OUT

Active Low Thermal Catastrophic Over Temperature

N15V-GM Power Sequence

B

+3VG_AON

Other Power rail

+VGA_CORE
+3VG_AON
tNVVDD >0

+1.35VGS

tPEX_VDD >0

1.all GPU power rails should be turned off within 10ms

2. Optimus system VDD33 avoids drop down earlier than NVDD and FBVDDQ

1. all power rail ramp up time should be larger than 40us

0x9C (Multi-GPU usage)

Physical
Strapping pin
ROM_SCLK

+1.05VS_VGA

0x9E (Default)

N15x Binary Straps

Tpower-off <10ms
tFBVDDQ >0

Power Rail

Strap Mapping

+3VGS

SMB_ALT_ADDR

ROM_SI

+3VGS

SUB_VENDOR

ROM_SO

+3VGS

VGA_DEVICE

STRAP0

+3VGS

RAM_CFG[0]

STRAP1

+3VGS

RAM_CFG[1]

STRAP2

+3VGS

RAM_CFG[2]

STRAP3

+3VGS

RAM_CFG[3]

STRAP4

+3VGS

PCIE_MAX_SPEED

N15S-GT Power Sequence

+3VG_AON
+VGA_CORE
A

tNVVDD >0

+1.05VS_VGA
+1.35VGS
tPEX_VDD >0

Issued Date

Title

LC Future Center Secret Data

Security Classification
1. all power rail ramp up time should be larger than 40us

2013/08/08

Deciphered Date

2013/08/05

VGA Notes List

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Date:
5

PDF created with pdfFactory Pro trial version www.pdffactory.com

Document Number

Rev
1.0

ACLUA
Thursday, December 26, 2013
1

Sheet

18

of

59

GPIO52

GPIO53

RV1

1 GC6@

2 0_0402_5%

FB_GC6_EN_R

RV2

1 GC6@

2 0_0402_5%

GPU_EVENT#

PCIE_CRX_GTX_N[0..3]
PCIE_CRX_GTX_P[0..3]

PCIE_CTX_C_GRX_P[0..3]

UV1A
+3VGS

1 RV175
@

Part 1 of 6

VCC

GND

SYS_PEX_RST_MON#

74LVC1G08GW_SOT353-1-5
OPT@
2
1
RV14
10K_0402_5%
OPT@

+3VG_AON

8
8

1
2 RV39
N15VGM@ 0_0402_5%

change to BAT54A for cost down

2
2 RV48
0_0402_5%

CV24
@

FB_GC6_EN_R

1
2

B7
A7

VGA_CRT_CLK
VGA_CRT_DATA

I2CB_SCL
I2CB_SDA

C9
C8

I2CB_SCL
I2CB_SDA

A9
B9

I2CC_SCL
I2CC_SDA

I2CC_SCL
I2CC_SDA

D9
D8

VGA_SMB_CK2
VGA_SMB_DA2

VID_PLLVDD

N6

PEX_RST_N
PEX_TERMP

XTAL_IN
XTAL_OUT

XTAL_SSIN
XTAL_OUTBUFF

C11
B10

.1U_0402_10V6-K

3
1
3

+3VG_AON

44

QV23
2N7002KW_SOT323-3
@

RV13
10K_0402_5%
GC6@

GPU_EVENT#_R

CV12
GC6@

GPU_EVENT#

QV4
2N7002KW_SOT323-3
GC6@

Connect to CPU GPIO

---colin

2 RV15
0_0402_5%

+3VG_AON

+PLLVDD

2 RV24
0_0402_5%

VGA_CRT_DATA

RV17 1

VGA_CRT_CLK

RV19 1

I2CB_SCL

RV22 1

I2CB_SDA

RV25 1

I2CC_SCL

RV28 1

I2CC_SDA

RV30 1

XTALOUT

RV33 1

+SP_PLLVDD

XTAL_IN
XTAL_OUT

A10 XTALSSIN
C10 XTALOUT

+3VG_AON

WRST#

PEX_REFCLK
PEX_REFCLK_N
PEX_CLKREQ_N
PEX_TSTCLK
PEX_TSTCLK_N

CV2
@

+3VG_AON

Internal Thermal Sensor

45mA

CV218
@

I2C,if not use, can be soft grounded

and delete pull up resistor

L6
M6

45mA

1
QV3
2N7002KW_SOT323-3
@

CV3

6
CV221
0.01U_0402_25V7K
@

2
OPT@ 2.2K_0402_5%
2
OPT@ 2.2K_0402_5%
2
OPT@ 2.2K_0402_5%
2
OPT@ 2.2K_0402_5%
2
OPT@ 2.2K_0402_5%
2
OPT@ 2.2K_0402_5%
2
@ 10K_0402_5%

3VGS_PWR_EN

RV18 2

OVERT#

RV20 1

VGA_ALERT#

RV23 1

1
OPT@ 10K_0402_5%
2
OPT@ 10K_0402_5%
2
OPT@ 10K_0402_5%
RV26 1
2
VGA_AC_DET_R
OPT@ 100K_0402_5%
RV29 1
2
PSI_VGA
OPT@ 10K_0402_5%
2
GPU_PEX_RST_HOLD# RV31 1
OPT@ 10K_0402_5%

1 OPT@
1 OPT@

2 RV34 10K_0402_5%
2 RV36 10K_0402_5%

Under GPU(below 150mils)

180ohms (ESR=0.2) Bead

1

+SP_PLLVDD

150mA

CV15

2
OPT@

CV16

2
OPT@

CV17

2
OPT@

2 LV1

+1.05VGS

PBY160808T-181Y-N_2P
CV18

OPT@

2
OPT@

2 RV38
OPT@ 10M_0402_5%

YV1
XTAL_IN

1
2

CV19
OPT@

OSC1

GND2

GND1

OSC2

Under GPU

Near GPU

30ohms (ESR=0.05) Bead

1

+PLLVDD

27MHZ_10PF_7V27000050
OPT@

2 LV2

+1.05VGS

XTAL_OUT

1
1

CV20
OPT@

CV21
0.1U_0402_10V7K
2
OPT@

PBY160808T-300Y-N_2P
OPT@

CV22
22U_0805_6.3V6M
OPT@

RV45
10K_0402_5%
@

QV6
2N7002KW_SOT323-3
@

2
RV46
10K_0402_5%
@

.1U_0402_10V6-K

GPIO

I2CA_SCL
I2CA_SDA

W5
AE2
AF2

2
G

+3VG_AON

CLK_REQ_GPU#

FB_GC6_EN

RV47
10K_0402_5%
GC6@

Connect to CPU GPIO

QV5
2N7002KW_SOT323-3
OPT@

1
2
D

GPU_CLKREQ#

RV44
10K_0402_5%
OPT@

OVERT#

60mA

RV41
10K_0402_5%
@

.1U_0402_10V6-K

2 1K_0402_5%

10P_0402_50V8J

+3VG_AON

1
@

AE3
AE4

10P_0402_50V8J

RV40
10K_0402_5%
OPT@

AG3
AF4
AF3

+3VG_AON

+3VG_AON

CV23
OPT@

AC7
AF25

OVERT#

N15S-GT-S-A2_FCBGA595
N15SGT@

PLT_RST_VGA#

BAT54AWT1G_SOT323-3
GC6@

PLT_RST_VGA#
1
2 RV35
PEX_TERMP
OPT@ 2.49K_0402_1%

2 0_0402_5%

AF22
AE22

1 RV8
@

GPU_PEX_RST_HOLD#

A6
AB6

NC102
NC103
NC104

CORE_PLLVDD
SP_PLLVDD

SYS_PEX_RST_MON#

GPU_PEX_RST_HOLD#

DV6

RV37
10K_0402_5%
@

NC100
NC101

I2CS_SCL
I2CS_SDA

RV180
2.2K_0402_5%
GC6@

2 RV32
PEX_TSTCLK_OUT
200_0402_1% PEX_TSTCLK_OUT#

AE8
AD8
AC6

Differential signal

CLK_PCIE_GPU
CLK_PCIE_GPU#
CLK_REQ_GPU#

CLK_PCIE_GPU
CLK_PCIE_GPU#

58
PLT_RST_VGA#

+3VGS

.1U_0402_10V6-K

PSI_VGA

RV174

on
fid

2 RV16
0_0402_5%

2 RV6
PSI_VGA
0_0402_5%

.1U_0402_10V6-K

CV11
.1U_0402_10V6-K
OPT@

1
N15SGT@

QV2A
2N7002KDWH_SOT363-6
@

22U_0805_6.3V6M

PXS_RST#

44

PLT_RST#
4

VGA_AC_DET

2
G

OVERT#

1
RB751V-40_SOD323-2

8,37,40,44

DV1

1
UV2

PLT_RST#

PEX_TX0
PEX_TX0_N
PEX_TX1
PEX_TX1_N
PEX_TX2
PEX_TX2_N
PEX_TX3
PEX_TX3_N
NC89
NC90
NC91
NC92
NC93
NC94
NC95
NC96
NC17
NC18
NC19
NC20
NC21
NC22
NC23
NC24
NC25
NC26
NC27
NC28
NC29
NC30
NC31
NC32

58
2
@

H_THRMTRIP#

QV2B
2N7002KDWH_SOT363-6
@

+3VG_AON

2 0_0402_5%
@

AC9
AB9
AB10
AC10
AD11
AC11
AC12
AB12
AB13
AC13
AD14
AC14
AC15
AB15
AB16
AC16
AD17
AC17
AC18
AB18
AB19
AC19
AD20
AC20
AC21
AB21
AD23
AE23
AF24
AE24
AG24
AG25

NVVDD_PWM_VID

CV1
@

5
G

4.7U_0402_6.3V6M

RV12 1

PCIE_CRX_C_GTX_P0
PCIE_CRX_C_GTX_N0
PCIE_CRX_C_GTX_P1
PCIE_CRX_C_GTX_N1
PCIE_CRX_C_GTX_P2
PCIE_CRX_C_GTX_N2
PCIE_CRX_C_GTX_P3
PCIE_CRX_C_GTX_N3

NVVDD_PWM_VID
VGA_AC_DET_R
PSI_VGA_R

0.1U_0402_10V7K

0_0402_5%

.1U_0402_10V6-K
.1U_0402_10V6-K
.1U_0402_10V6-K
.1U_0402_10V6-K
.1U_0402_10V6-K
.1U_0402_10V6-K
.1U_0402_10V6-K
.1U_0402_10V6-K

21,58

A6 Symbol update to OVER

0.1U_0402_10V7K

2
2
2
2
2
2
2
2

SYS_PEX_RST_MON#
VGA_ALERT#

PLT_RST_VGA#

NC97
NC98
NC99

2 0_0402_5%

RV4
10K_0402_5%
@

RV10
@

1
1
1
1
1
1
1
1

CV10
CV13
CV8
CV9
CV6
CV7
CV4
CV5

3VGS_PWR_EN

GPU_EVENT#_R

+3VGARST

PCIE_CRX_GTX_P0
PCIE_CRX_GTX_N0
PCIE_CRX_GTX_P1
PCIE_CRX_GTX_N1
PCIE_CRX_GTX_P2
PCIE_CRX_GTX_N2
PCIE_CRX_GTX_P3
PCIE_CRX_GTX_N3

3VGS_PWR_EN

+3VS

23

PU AT EC SIDE, +3VS AND 4.7K

OVERT
NC33

FB_GC6_EN

RV9

QV1A
2N7002KDWH_SOT363-6
OPT@
2
@
1 0_0402_5%

7,39,44

FB_GC6_EN

tia

EC_SMB_DA2

C6
B2
D6
C7
F9
A3
A4
B6
E9
F8
C5
E7
D7
B4
B3
C3
D5
D4
C2
F7
E6
C4

en

DACs

2
G

VGA_SMB_DA2

7,39,44

CLK

EC_SMB_CK2

QV1B
2N7002KDWH_SOT363-6
OPT@
RV7
2
@
1 0_0402_5%

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21

VGA_SMB_CK2

PEX_RX0
PEX_RX0_N
PEX_RX1
PEX_RX1_N
PEX_RX2
PEX_RX2_N
PEX_RX3
PEX_RX3_N
NC81
NC82
NC83
NC84
NC85
NC86
NC87
NC88
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16

PCI EXPRESS

RV5
2.2K_0402_5%
OPT@

RV3
2.2K_0402_5%
OPT@

AG6
AG7
AF7
AE7
AE9
AF9
AG9
AG10
AF10
AE10
AE12
AF12
AG12
AG13
AF13
AE13
AE15
AF15
AG15
AG16
AF16
AE16
AE18
AF18
AG18
AG19
AF19
AE19
AE21
AF21
AG21
AG22

I2C

PCIE_CTX_C_GRX_P0
PCIE_CTX_C_GRX_N0
PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_N1
PCIE_CTX_C_GRX_P2
PCIE_CTX_C_GRX_N2
PCIE_CTX_C_GRX_P3
PCIE_CTX_C_GRX_N3

+3VG_AON

+3VG_AON

2 RV49
GC6@ 0_0402_5%

Issued Date

Title

LC Future Center Secret Data

Security Classification

.1U_0402_10V6-K

PCIE_CTX_C_GRX_N[0..3]

.1U_0402_10V6-K

9
9

2013/08/08

Deciphered Date

2013/08/05

N15X_PCIE/ DAC/ GPIO

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Tuesday, December 31, 2013
Date:

Rev
1.0

ACLUA

PDF created with pdfFactory Pro trial version www.pdffactory.com

Sheet

19

of

59

UV1C

NC115
NC116
NC117
NC118
NC119
NC120
NC121
NC122
NC123
NC124
NC125
NC126
NC127
NC128
NC129
NC130
NC131
NC132

N1
M1
M2
M3
K2
K3
K1
J1
M4
M5
L3
L4
K4
K5
J4

J5
N4
N5
P3
P4

J2
J3
H3
H4

NC133
NC134
NC135
NC136
NC137
NC138
NC139
NC140

NC71
NC72
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
NC73

MULTI_STRAP_REF0_GND
MULTI_STRAP_REF1_GNDMLS_REF1
MULTI_STRAP_REF2_GND

NC34
NC35
NC36
NC37
NC38
NC39
NC40
NC41

THERMDP
THERMDN

NC42
NC43
NC44
NC45
NC46

D11

2
@

1 RV50
10K_0402_5%

D10
E10
F10

Symbol update to GPIO8

D1
D2
E4
E3
D3
C1
F6
F4
F5

STRAP0
STRAP1
STRAP2
STRAP3
STRAP4

STRAP0
STRAP1
STRAP2
STRAP3
STRAP4

1
N15SGT@

28
28
28
28
28

2 RV51
40.2K_0402_1%

F12
E12

on
fid

V3
V4
U3
U4
T4
T5
R4
R5

PGOOD

GENERAL

LVDS/TMDS

BUFRST_N
T2
T3
T1
R1
R2
R3
N2
N3

B19 Symbol update to FBA_CMD32

V5
V6
G1
G2
G3
G4
G5
G6
G7
V1
V2
W1
W2
W3
W4

FERMI_RSVD1
FERMI_RSVD2
NC56
NC57
NC58
NC59
NC60
NC61
NC62
NC63
NC64
NC65
NC66
NC67
NC68

F11
AD10
AD7

tia

AB5
AB4
AB3
AB2
AD3
AD2
AE1
AD1
AD4
AD5

NC105
NC106
NC107
NC108
NC109
NC110
NC111
NC112
NC113
NC114

NC

AC3
AC4
Y4
Y3
AA3
AA2
AB1
AA1
AA4
AA5

NC50
NC51
NC52

en

Part 3 of 6

VDD_SENSE

F2

VCCSENSE_VGA

VCCSENSE_VGA

58

trace width: 16mils

differential voltage sensing.
differential signal routing.

NC47
NC48

GND_SENSE

NC49
NC141
NC142

TEST

NC143
NC144
NC145
NC146

TESTMODE
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N

NC147
NC148

SERIAL

VSSSENSE_VGA

AD9
AE5
AE6
AF6
AD6
AG4

TESTMODE
@
@
@
@

VSSSENSE_VGA

1 OPT@

1
1
1
1

TV1
TV2
TV3
1TV4

OPT@

D12
B12
A12
C12

@ 1
ROM_SI
ROM_SO
ROM_SCLK

ROM_CS_N
ROM_SI
ROM_SO
ROM_SCLK

F1

58

2 RV52
10K_0402_5%

2 RV53
10K_0402_5%

TV5

ROM_SI
ROM_SO
ROM_SCLK

28
28

28

N15S-GT-S-A2_FCBGA595
N15SGT@

Issued Date

Title

LC Future Center Secret Data

Security Classification
2013/08/08

Deciphered Date

2013/08/05

N15X_LVDS/ HDMI/ THERM

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Date:
5

PDF created with pdfFactory Pro trial version www.pdffactory.com

Document Number

Rev
1.0

ACLUA
Thursday, December 26, 2013
1

Sheet

20

of

59

UV1D

+3VS

+3VG_AON

+5VALW

B25

PEX_PLL_HVDD_1
PEX_PLL_HVDD_2

OPT@

2 RV56
42.2_0402_1%

OPT@

2 RV57
51.1_0402_1%

AB8

120mA

PEX_PLLVDD_1
PEX_PLLVDD_2

AA14
AA15

2
OPT@

2
OPT@

CV215

40.2Ohm

FB_CAL_x_PU_GND

42.2Ohm

FB_CAL_xTERM_GND

51.1Ohm

CV49

4.7U_0603_6.3V6K

1U_0402_6.3V6K

CV48

CV52

CV51

+3VG_AON

2
OPT@

120ohm (ESR=0.18) Bead

1

2
OPT@

2
OPT@

+1.05VGS

2
1 LV3
@
HCB1608KF-121T30_0603
1

2 RV62
0_0603_5%

2
OPT@

AON6414AL_DFN8-5

1
2
3

QV14

CV67
1

OPT@

CV68

CV69

CV70

RV67
470_0603_5%
@

+20VSB

CV66
1

+5VALW

1
OPT@2 RV68
100K_0402_5%

FBVDDQ_PW R_EN#

QV15
2N7002KW _SOT323-3
@

1
FBVDDQ_PW R_EN#

2
G

QV17
2N7002KW _SOT323-3
OPT@

3
1

FBVDDQ_PW R_EN

1
CV71
0.01U_0402_25V7K
OPT@

RV70
120K_0402_5%
OPT@

2
G

QV18
2N7002KW _SOT323-3
OPT@

3
RV72
470_0603_5%
@

2
G

1
2

1
CV73
0.01U_0402_25V7K
GC6@

+1.35VGS

CV74
10U_0603_6.3V6M
GC6@

QV20
DGPU_PW R_EN#

CV75
.1U_0402_10V6-K
GC6@

2
G

S 2N7002KW _SOT323-3

Issued Date

N15SGT@

Title

LC Future Center Secret Data

Security Classification

S 2N7002KW _SOT323-3

2013/08/08

Deciphered Date

2013/08/05

N15X_Power

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Date:
5

33P_0402_50V8J

N15VGM@CV42

N15VGM@CV41

10U_0603_6.3V6M

N15VGM@CV40

10U_0603_6.3V6M

CV39

10U_0603_6.3V6M

N15VGM@CV38

10U_0603_6.3V6M

CV37

CV47

CV50

CV53

DDR3

FB_CAL_x_PD_VDDQ

S 2N7002KW _SOT323-3

23

1
2
1

CALIBRATION PIN

2
3

Change RV9 to 0ohm jump

2
OPT@

.1U_0402_16V7K
OPT@

CV65
1

RV69

@
RV74
100K_0402_5%

2
OPT@

2
3VGS_PW R_EN

2
OPT@

10U_0603_6.3V6M
@

1
GC6@

LP2301ALT1G_SOT23-3

GC6@

19,58

2
4.7K_0402_5%
GC6@

2
OPT@

2 0_0402_5%
@

+1.35V

+1.35V TO +1.35VGS

47K_0402_5%
OPT@

QV19

2
G

CV63
10U_0603_6.3V6M
OPT@

1
RV73

DGPU_PW R_EN#

10U_0603_6.3V6M
OPT@

22uF

Place near balls

N15VGM@

@
CV72
.1U_0402_10V6-K

220U_B2_2.5VM_R15M
@

RV64
470_0603_5%
@

+5VALW

10uF

+PEX_PLLVDD

3
QV16

2 RV55
40.2_0402_1%

AA8
AA9

+3.3VS TO +3VGS

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

N15VGM@CV46

22U_0805_6.3V6M

N15VGM@CV45

N15VGM@CV44

22U_0805_6.3V6M

.1U_0402_10V6-K

1U_0402_6.3V6K

N15VGM@CV36

1U_0402_6.3V6K

N15VGM@CV35

N15VGM@CV34

CV33

1U_0402_6.3V6K

OPT@

4.7U_0603_6.3V6K

C24

+3VGS

+3VG_AON

GC6@

Place near GPU

1U_0402_6.3V6K

.1U_0402_10V6-K

D22

RV71
47K_0402_5%

4.7uF

QV13

RV171 1
0_0603_5%

N15S-GT

1.0uF

RV54 1
+1.35VGS

RV66 OPT@
100K_0402_5%

N15V-GM

CV62
0.01U_0402_25V7K
@

PXS_PW REN#

S 2N7002KW _SOT323-3

2
OPT@

+VDD33

10U_0603_6.3V6M
OPT@

OPT@
CV64
.1U_0402_10V6-K

2
@

+3VGS

G8
G9

10U_0603_6.3V6M
OPT@

OPT@

LP2301ALT1G_SOT23-3

2
G

PXS_PW REN

4,58

2 RV65
10K_0402_5%
OPT@

2
OPT@

Under GPU(below 150mils)

NC76
NC77
NC78
NC79
NC80

PXS_PW REN#

@
CV61
.1U_0402_10V6-K

OPT@

OPT@

QV11

RV63
47K_0402_5%

QV12

3
B

2
OPT@

Place near balls(Under GPU)

N15S-GT-S-A2_FCBGA595
N15SGT@

+3.3VS TO +3VG_AON

For RF
1

Place near balls

PEX_SVDD_3V3
J7
K7
K6
H6
J6

CV60

3
3

FB_CAL_TERM

S
2N7002KW _SOT323-3

CV59

QV10
2N7002KW _SOT323-3
@

+3VG_AON

Near

4.7U_0805_25V6-K

2
G

1.05VGS_EN#

NC158
NC159
NC160
NC161

Under

CV58

T7
R7
U6
R6

1U_0603_25V6M

S
2N7002KW _SOT323-3

QV9
@

3V3_MAIN_1
3V3_MAIN_2

G10
G12

on
fid

RV61
120K_0402_5%
@

PEX_IOVVDD/Q Decouling

CV54
0.1U_0402_16V4Z
@

1.05VGS_EN

QV8

47K_0402_5%
@

57

2
G

1.05VGS_EN#

RV60

MLCC

.1U_0402_10V6-K

1
1

RV59
470_0603_5%
@

NC154
NC155
NC156
NC157

1
OPT@

+3VG_AON

3V3_AON_1
3V3_AON_2

FB_CAL_GND
M7
N7
T6
P6

+1.05VGS

Symbol update to 3V3_AON

FB_CAL_VDDQ

.1U_0402_10V6-K

CV220
QV7
0.1U_0402_16V4Z
@

1
2 RV58
@
100K_0402_5%

2
OPT@

2
OPT@

CV57

NC150
NC151
NC152
NC153

AA22
AB23
AC24
AD25
AE26
AE27

en

+20VSB
+5VALW

W7
AA6
W6
Y6

1
2
3

Under GPU(below 150mils)

4.7U_0603_6.3V6K

NC149

CV56

V7

4.7U_0603_6.3V6K

+1.05VGS
AON6414AL_DFN8-5

2
OPT@

tia

+1.05VS

FBVDDQ_AON_1
FBVDDQ_AON_2
FBVDDQ_AON_3
FBVDDQ_AON_4

PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4
PEX_IOVDD_5
PEX_IOVDD_6

CV55

H24
H26
J21
K21

Reserve for GPU +1.05V

+1.05VGS

.1U_0402_10V6-K

Symbol update to FBVDDQ_AON

H24/H26/J21/K21

AA10
AA12
AA13
AA16
AA18
AA19
AA20
AA21
AB22
AC23
AD24
AE25
AF26
AF27

22U_0805_6.3V6M

PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8
PEX_IOVDDQ_9
PEX_IOVDDQ_10
PEX_IOVDDQ_11
PEX_IOVDDQ_12
PEX_IOVDDQ_13
PEX_IOVDDQ_14

1U_0402_6.3V6K

2
OPT@

Near GPU

2000mA

FBVDDQ_01
FBVDDQ_02
FBVDDQ_03
FBVDDQ_04
FBVDDQ_05
FBVDDQ_06
FBVDDQ_07
FBVDDQ_08
FBVDDQ_09
FBVDDQ_10
FBVDDQ_11
FBVDDQ_12
FBVDDQ_13
FBVDDQ_14
FBVDDQ_19
FBVDDQ_20
FBVDDQ_21
FBVDDQ_22
FBVDDQ_23
FBVDDQ_24
FBVDDQ_25
FBVDDQ_26
FBVDDQ_27

CV43

2
OPT@

CV32

Part 4 of 6

B26
C25
E23
E26
F14
F21
G13
G14
G15
G16
G18
G19
G20
G21
L22
L24
L26
M21
N21
R21
T21
V21
W21

POWER

2
OPT@

CV31

CV30

0.1U_0402_10V7K

2
OPT@

3.5A
0.1U_0402_10V7K

CV29

CV28

2
OPT@

1U_0603_25V6M

2
OPT@

1U_0603_25V6M

1
OPT@

CV27

4.7U_0603_6.3V6K

2
OPT@

Under GPU(below 150mils)

CV26

CV25

10U_0603_6.3V6M

22U_0805_6.3V6M

Near GPU

4.7U_0603_6.3V6K

+1.35VGS

22U_0805_6.3V6M

PDF created with pdfFactory Pro trial version www.pdffactory.com

Document Number

Rev
1.0

ACLUA
Thursday, December 26, 2013
1

Sheet

21

of

59

UV1E
UV1F

OPT@

OPT@

CV88

CV87

4.7U_0603_6.3V6K

CV86

OPT@

4.7U_0603_6.3V6K

CV85

2
@

tia

OPT@

4.7U_0603_6.3V6K

CV84

4.7U_0603_6.3V6K

CV83

4.7U_0603_6.3V6K

CV82

4.7U_0603_6.3V6K

OPT@

CV101

4.7U_0603_6.3V6K

CV100

4.7U_0603_6.3V6K

CV99

4.7U_0603_6.3V6K

N15S-GT-S-A2_FCBGA595
N15SGT@

CV102

CV81
CV98

4.7U_0603_6.3V6K

2
@

1 2

+3VGS

RV176
10K_0402_5%
@
DV5

+3VG_AON
57

+1.05VGS_PW RGD

VGA_PW RGD

9,44

+5VALW
RV179

RV178

2
47K_0402_5%
@

QV22

10K_0402_5%

BAT54AW T1G_SOT323-3
@

2
G

QV25
2N7002KW _SOT323-3
@

+1.35VGS

S
2N7002KW _SOT323-3

RV177

2
B
1

2
@

.1U_0402_10V6-K

1
2
@
2.2K_0402_5%

CV219

S
2N7002KW _SOT323-3

QV24
MMBT3904W H_SOT323-3
E

OPT@

@
A

Issued Date

Title

LC Future Center Secret Data

Security Classification
2013/08/08

Deciphered Date

2013/08/05

N15X_+VGA CORE, GND

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Date:
5

VDD_041
VDD_040
VDD_039
VDD_038
VDD_037
VDD_036
VDD_035
VDD_034
VDD_033
VDD_032
VDD_031
VDD_030
VDD_029
VDD_028
VDD_027
VDD_026
VDD_025
VDD_024
VDD_023
VDD_022
VDD_021

D
QV21

4.7U_0603_6.3V6K

CV80
CV97

For RF

2
G

G
@

1
2

RV173
470_0603_5%
@

RV172
47K_0402_5%
@

OPT@

2
@

+VGA_CORE

EN_VGA

CV213

OPT@

VDD_001
VDD_002
VDD_003
VDD_004
VDD_005
VDD_006
VDD_007
VDD_008
VDD_009
VDD_010
VDD_011
VDD_012
VDD_013
VDD_014
VDD_015
VDD_016
VDD_017
VDD_018
VDD_019
VDD_020

V18
V16
V14
V12
V10
U17
U15
U13
U11
T18
T16
T14
T12
T10
R17
R15
R13
R11
P18
P16
P14

Near GPU

AA7
AB7

+5VALW

57,58

For RF

33P_0402_50V8J

2
OPT@

OPT@

4.7U_0603_6.3V6K

CV96

4.7U_0603_6.3V6K

CV79

2
OPT@

4.7U_0603_6.3V6K

CV78

4.7U_0603_6.3V6K

OPT@

CV92

en

1U_0402_6.3V6K

CV91

2
OPT@

OPT@

CV214

CV95

2
OPT@

4.7U_0603_6.3V6K

CV105

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

CV77

1U_0402_6.3V6K

CV90
CV94

OPT@

22U_0805_6.3V6M

2
OPT@

33P_0402_50V8J

2
OPT@

OPT@

4.7U_0603_6.3V6K

1U_0402_6.3V6K

2
OPT@

2
OPT@

4.7U_0603_6.3V6K

CV89

CV93

1U_0402_6.3V6K

OPT@

CV104

22U_0805_6.3V6M

CV76

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

Under GPU

K10
K12
K14
K16
K18
L11
L13
L15
L17
M10
M12
M14
M16
M18
N11
N13
N15
N17
P10
P12

POWER

+VGA_CORE

N15S-GT-S-A2_FCBGA595
N15SGT@

+VGA_CORE
Part 6 of 6

on
fid

GND_113
GND_114

+VGA_CORE

K11
K13
K15
K17
L10
L12
L14
L16
L18
L2
L23
L25
L5
M11
M13
M15
M17
N10
N12
N14
N16
N18
P11
P13
P15
P17
P2
P23
P26
P5
R10
R12
R14
R16
R18
T11
T13
T15
T17
U10
U12
U14
U16
U18
U2
U23
U26
U5
V11
V13
V15
V17
Y2
Y23
Y26
Y5

4.7U_0603_6.3V6K

GND_057
GND_058
GND_059
GND_060
GND_061
GND_062
GND_063
GND_064
GND_065
GND_066
GND_067
GND_068
GND_069
GND_070
GND_071
GND_072
GND_073
GND_074
GND_075
GND_076
GND_077
GND_078
GND_079
GND_080
GND_081
GND_082
GND_083
GND_084
GND_085
GND_086
GND_087
GND_088
GND_089
GND_090
GND_091
GND_092
GND_093
GND_094
GND_095
GND_096
GND_097
GND_098
GND_099
GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112

CV103

Part 5 of 6

22U_0805_6.3V6M

GND_001
GND_002
GND_003
GND_004
GND_005
GND_006
GND_007
GND_008
GND_009
GND_010
GND_011
GND_012
GND_013
GND_014
GND_015
GND_016
GND_017
GND_018
GND_019
GND_020
GND_021
GND_022
GND_023
GND_024
GND_025
GND_026
GND_027
GND_028
GND_029
GND_030
GND_031
GND_032
GND_033
GND_034
GND_035
GND_036
GND_037
GND_038
GND_039
GND_040
GND_041
GND_042
GND_043
GND_044
GND_045
GND_046
GND_047
GND_048
GND_049
GND_050
GND_051
GND_052
GND_053
GND_054
GND_055
GND_056

GND

A2
A26
AB11
AB14
AB17
AB20
AB24
AC2
AC22
AC26
AC5
AC8
AD12
AD13
AD15
AD16
AD18
AD19
AD21
AD22
AE11
AE14
AE17
AE20
AF1
AF11
AF14
AF17
AF20
AF23
AF5
AF8
AG2
AG26
B1
B11
B14
B17
B20
B23
B27
B5
B8
E11
E14
E17
E2
E20
E22
E25
E5
E8
H2
H23
H25
H5

PDF created with pdfFactory Pro trial version www.pdffactory.com

Document Number

Rev
1.0

ACLUA
Thursday, December 26, 2013
1

Sheet

22

of

59

24,25,26,27
24,25,26,27
24,25,26,27
24,25,26,27

FBA_D[0..63]

FBA_D[0..63]
FBA_DQM[7..0]
FBA_DQS[7..0]
FBA_DQS#[7..0]

24,25,26,27

FBA_CMD[30..0]

UV1B
D

Part 2 of 6

Place close to BGA

2
OPT@

2
OPT@

CV113

CV112

0.1U_0402_10V7K

CV111

22U_0805_6.3V6M

+FB_PLLAVDD

Place close to ball

1U_0402_6.3V6K

Place close to BGA

2
OPT@

F16
P22

FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7

FB_PLLAVDD_1
FB_PLLAVDD_2

D23
+FB_PLLAVDD

FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7

1
2
OPT@
2
RV119 1
@
RV120 1 OPT@

FB_GC6_EN

H22
CV115
0.1U_0402_10V7K
FB_CLAMP F3
0_0402_5%
2 10K_0402_5%

FBA_CLK0
FBA_CLK0_N
FBA_CLK1
FBA_CLK1_N

FB_VREF

Place close to ball

FBA_WCK01
FBA_WCK01_N
FBA_WCK23
FBA_WCK23_N
FBA_WCK45
FBA_WCK45_N
FBA_WCK67
FBA_WCK67_N

FB_DLLAVDD
FB_CLAMP

FBA_DQS#0
FBA_DQS#1
FBA_DQS#2
FBA_DQS#3
FBA_DQS#4
FBA_DQS#5
FBA_DQS#6
FBA_DQS#7

E19
C15
B16
B22
R25
W23
AB26
T26

FBA_DQS0
FBA_DQS1
FBA_DQS2
FBA_DQS3
FBA_DQS4
FBA_DQS5
FBA_DQS6
FBA_DQS7

D24
D25

FBA_CLK0
FBA_CLK0#

N22
M22

FBA_CLK1
FBA_CLK1#

24,25,26,27
25,27
27
25
25,27
24,25,26,27

RV81 1
RV82 1

2 100_0402_5%
2 100_0402_5%

FBA_CMD8

RV83 1
RV84 1

2 100_0402_5%
2 100_0402_5%

FBA_CMD9

RV85 1
RV86 1

2 100_0402_5%
2 100_0402_5%

1 60.4_0402_1%
1 60.4_0402_1%

FBA_CLK0
FBA_CLK0#

24,26
24,26

FBA_CLK1
FBA_CLK1#

25,27
25,27

D18
C18
D17
D16
T24
U24
V24
V25

FBA_CMD10

RV87 1
RV88 1

2 100_0402_5%
2 100_0402_5%

FBA_RAS#

RV89 1
RV90 1

2 100_0402_5%
2 100_0402_5%

FBA_CMD12

RV91 1
RV92 1

2 100_0402_5%
2 100_0402_5%

FBA_CMD13

RV93 1
RV94 1

2 100_0402_5%
2 100_0402_5%

FBA_CMD14

RV95 1
RV96 1

2 100_0402_5%
2 100_0402_5%

FBA_CAS#

RV97 1
RV98 1

2 100_0402_5%
2 100_0402_5%

FBA_CMD21

RV99 1
RV100 1

2 100_0402_5%
2 100_0402_5%

FBA_CMD22

RV101 1
RV102 1

2 100_0402_5%
2 100_0402_5%

FBA_CMD23

RV103 1
RV104 1

2 100_0402_5%
2 100_0402_5%

FBA_CMD24

RV105 1
RV106 1

2 100_0402_5%
2 100_0402_5%

FBA_CMD25

RV107 1
RV108 1

2 100_0402_5%
2 100_0402_5%

FBA_CMD26

RV109 1
RV110 1

2 100_0402_5%
2 100_0402_5%

FBA_CMD27

RV111 1
RV112 1

2 100_0402_5%
2 100_0402_5%

FBA_CMD28

RV113 1
RV114 1

2 100_0402_5%
2 100_0402_5%

FBA_CMD29

RV115 1
RV116 1

2 100_0402_5%
2 100_0402_5%

RV117 1
RV118 1

2 100_0402_5%
2 100_0402_5%

FBA_CMD30

CV106

FBA_CMD7

FBx_CMD0

ODT_L

FBx_CMD1

Rank1

32..63

0..31

32..63

ODT_L
CS1#_L

FBx_CMD2

CS0#_L

FBx_CMD3

CKE_L

CKE_L

FBx_CMD4

A9

A9

A11

A11

FBx_CMD5

A6

A6

A7

A7

FBx_CMD6

A3

A3

BA1

BA1

FBx_CMD7

A0

A0

A12

A12

FBx_CMD8

A8

A8

A8

A8

FBx_CMD9

A12

A12

A0

A0

FBx_CMD10

A1

A1

A2

A2

FBx_CMD11

RAS#

RAS#

RAS#

RAS#

FBx_CMD12

A13

A13

A14

A14

FBx_CMD13

BA1

BA1

A3

A3

FBx_CMD14

A14

A14

A13

A13

FBx_CMD15

CAS#

CAS#

CAS#

CAS#

CV108

FBA_CAS#
FBA_ODT_H
FBA_CS1#_H
FBA_CS0#_H
FBA_CKE_H
FBA_RST#

0.1U_0402_10V7K

2 100_0402_5%
2 100_0402_5%

0..31

CV107

RV79 1
RV80 1

Rank0
Address

FBA_CMD6

0.1U_0402_10V7K

24,25,26,27

0.1U_0402_10V7K

2 100_0402_5%
2 100_0402_5%

CV109

FBA_RAS#

@
FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7

F19
C14
A16
A22
P25
W22
AB27
T27

RV77 1
RV78 1

tia

FBA_CMD5

FBx_CMD16

FBx_CMD17

FBx_CMD18

ODT_H

ODT_H
CS1#_H

CS0#_H

FBx_CMD19

CKE_H

CKE_H

FBx_CMD20

RST

RST

RST

RST

FBx_CMD21

A7

A7

A6

A6

FBx_CMD22

A4

A4

A5

A5

FBx_CMD23

A11

A11

A9

A9

FBx_CMD24

A2

A2

A1

A1

FBx_CMD25

A10

A10

WE#

WE#

FBx_CMD26

A5

A5

A4

A4

FBx_CMD27

BA2

BA2

FBx_CMD28

WE#

WE#

A10

A10

FBx_CMD29

BA0

BA0

BA0

BA0

FBx_CMD30

BA2

BA2

N15S-GT-S-A2_FCBGA595
N15SGT@

2
2

2 100_0402_5%
2 100_0402_5%

0.1U_0402_10V7K

OPT@

CMD mapping mod Mode E

RV75 1
RV76 1

FBA_CMD4

CV110

2 LV4
HCB1608KF-300T60_2P

+1.35VGS

24,26
26
24
24,26

Symbol update to +1.35VGS

FBA_CMD34/35

F22 RV121
J22 RV122
D19
D14
C17
C22
P24
W24
AA25
U25

FBA_ODT_L
FBA_CS1#_L
FBA_CS0#_L
FBA_CKE_L

0.1U_0402_10V7K

200mA
1

FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7

FBA_ODT_L
FBA_CS1#_L
FBA_CS0#_L
FBA_CKE_L
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_RAS#
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CAS#
FBA_ODT_H
FBA_CS1#_H
FBA_CS0#_H
FBA_CKE_H
FBA_RST#
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30

CV114

+FB_PLLAVDD

FBA_CMD34
FBA_CMD35

C27
C26
E24
F24
D27
D26
F25
F26
F23
G22
G23
G24
F27
G25
G27
G26
M24
M23
K24
K23
M27
M26
M25
K26
K22
J23
J25
J24
K27
K25
J27
J26
B19

0.1U_0402_10V7K

+1.05VGS

FBA_CMD00
FBA_CMD01
FBA_CMD02
FBA_CMD03
FBA_CMD04
FBA_CMD05
FBA_CMD06
FBA_CMD07
FBA_CMD08
FBA_CMD09
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31
FBA_CMD32

en

30ohms (ESR=0.01) Bead

FBA_D00
FBA_D01
FBA_D02
FBA_D03
FBA_D04
FBA_D05
FBA_D06
FBA_D07
FBA_D08
FBA_D09
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63

on
fid

E18
F18
E16
F17
D20
D21
F20
E21
E15
D15
F15
F13
C13
B13
E13
D13
B15
C16
A13
A15
B18
A18
A19
C19
B24
C23
A25
A24
A21
B21
C20
C21
R22
R24
T22
R23
N25
N26
N23
N24
V23
V22
T23
U22
Y24
AA24
Y22
AA23
AD27
AB25
AD26
AC25
AA27
AA26
W26
Y25
R26
T25
N27
R27
V26
V27
W27
W25

MEMORY
INTERFACE A

FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63

RV123

FB_GC6_EN

FB_GC6_EN

DV4 GC6@

2 0_0402_5%

GC6_EN 2

+3VGS

57,58

DGPU_PW ROK

RV124

2
10K_0402_5%
OPT@

FBVDDQ_PW R_EN

BAV70W -7-F_SOT323-3

21

2 RV126
0_0402_5%
N15VGM@

RV125
200K_0402_5%
GC6@

19

Issued Date

Title

LC Future Center Secret Data

Security Classification
2013/08/08

Deciphered Date

N15X_MEM Interface

2013/08/05

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Date:
5

PDF created with pdfFactory Pro trial version www.pdffactory.com

Document Number

Rev
1.0

ACLUA
Thursday, December 26, 2013
1

Sheet

23

of

59

at least 16 mils width(optimal)

20 mils spacing to other signals /planes

FBA_D[0..63]

23,25,26,27

+1.35VGS
FBA_CMD[30..0]

23,25,26,27D

FBA_D31
FBA_D25
FBA_D30
FBA_D24
FBA_D29
FBA_D27
FBA_D28
FBA_D26

Group3

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

23,26
23,26
23,26

FBA_CLK0
FBA_CLK0#
FBA_CKE_L

FBA_CLK0
FBA_CLK0#
FBA_CKE_L

J7
K7
K9

CK
CK
CKE

B2
D9
G7
K2
K8
N1
N9
R1
R9

FBA_CLK0
FBA_CLK0#
FBA_CKE_L

FBA_DQS0
FBA_DQS3

F3
C7

FBA_DQM0
FBA_DQM3

RV129
162_0402_1%
RANKA@

E7
D3

FBA_DQS#0 G3
FBA_DQS#3 B7
FBA_CLK0#

FBA_RST#

RV131
10K_0402_5%
RANKA@

FBA_ODT_L

2 RV130
L8
243_0402_1%
RANKA@
J1
L1
J9
L9
M7

1
RANKA@

RANKA@

RANKA@

RESET
ZQ
NC1
NC2
NC3
NC4
NC5

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

K1
L2
J3
K3
L3

FBA_DQS1
FBA_DQS2

F3
C7
E7
D3

FBA_DQM1
FBA_DQM2

FBA_DQS#1 G3
FBA_DQS#2 B7

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9

T2

FBA_RST#

B1
B9
D1
D8
E2
E8
F9
G1
G9

L8
J1
L1
J9
L9
M7

RV132
243_0402_1%
RANKA@

RANKA@

RANKA@

For RF
RANKA@

+1.35VGS

FBA_DQS[7..0]

23,25,26,27

FBA_DQS#[7..0]

23,25,26,27

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

CK
CK
CKE

ODT
CS
RAS
CAS
WE

DQSL
DQSU
DML
DMU

DQSL
DQSU

RESET
ZQ
NC1
NC2
NC3
NC4
NC5

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9

CMD mapping mod Mode E

Rank0
Address

D7
C3
C8
C2
A7
A2
B8
A3

FBA_D17
FBA_D22
FBA_D16
FBA_D23
FBA_D19
FBA_D21
FBA_D18
FBA_D20

0..31

FBx_CMD0

Rank1

32..63

ODT_L

B2
D9
G7
K2
K8
N1
N9
R1
R9

32..63

ODT_L

FBx_CMD1
Group2

0..31
CS1#_L

FBx_CMD2

CS0#_L

FBx_CMD3

CKE_L

FBx_CMD4

A9

A9

A11

A11

FBx_CMD5

A6

A6

A7

A7

FBx_CMD6

A3

A3

BA1

BA1

FBx_CMD7

A0

A0

A12

A12

FBx_CMD8

A8

A8

A8

A8

FBx_CMD9

A12

A12

A0

A0

FBx_CMD10

A1

A1

A2

A2

FBx_CMD11

RAS#

RAS#

RAS#

RAS#

FBx_CMD12

A13

A13

A14

A14

FBx_CMD13

BA1

BA1

A3

A3

FBx_CMD14

A14

A14

A13

A13

FBx_CMD15

CAS#

CAS#

CAS#

CAS#

CKE_L

A1
A8
C1
C9
D2
E9
F1
H2
H9

FBx_CMD16

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

ODT_H

ODT_H

FBx_CMD17

CS1#_H

FBx_CMD18

CS0#_H

FBx_CMD19

B1
B9
D1
D8
E2
E8
F9
G1
G9

CKE_H

CKE_H

FBx_CMD20

RST

RST

RST

RST

FBx_CMD21

A7

A7

A6

A6

FBx_CMD22

A4

A4

A5

A5

FBx_CMD23

A11

A11

A9

A9

FBx_CMD24

A2

A2

A1

A1

FBx_CMD25

A10

A10

WE#

WE#

FBx_CMD26

A5

A5

A4

A4

FBx_CMD27

BA2

BA2

FBx_CMD28

WE#

WE#

A10

A10

FBx_CMD29

BA0

BA0

BA0

BA0

BA2

BA2

FBx_CMD30

+1.35VGS

UV5 SIDE
For RF

CV129

CV122

Group1

96-BALL
SDRAM DDR3
K4W 4G1646B-HC11_FBGA96
@

0.1U_0402_10V7K

CV121

+1.35VGS

0.1U_0402_10V7K

CV120

1U_0603_25V6M

CV119

1U_0603_25V6M

CV118

1U_0603_25V6M

UV6 SIDE
0.1U_0402_10V7K

CV117

0.1U_0402_10V7K

+1.35VGS

DQSL
DQSU

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12

FBA_ODT_L
FBA_CS0#_L
FBA_RAS#
FBA_CAS#
FBA_CMD28

96-BALL
SDRAM DDR3
K4W 4G1646B-HC11_FBGA96
@

1U_0603_25V6M

RV134
10K_0402_5%
RANKA@

RV133
10K_0402_5%
RANKA@

DML
DMU

A1
A8
C1
C9
D2
E9
F1
H2
H9

CV127

FBA_CKE_L

DQSL
DQSU

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9

33P_0402_50V8J

23,25,26,27

T2

FBA_RST#

ODT
CS
RAS
CAS
WE

J7
K7
K9

BA0
BA1
BA2

en

K1
L2
J3
K3
L3

FBA_CLK0

FBA_ODT_L
FBA_CS0#_L
FBA_RAS#
FBA_CAS#
FBA_CMD28

FBA_ODT_L
FBA_CS0#_L
FBA_RAS#
FBA_CAS#

M2
N8
M3

FBA_CMD29
FBA_CMD13
FBA_CMD27

on
fid

23,26
23
23,25,26,27
23,25,26,27

FBA_D11
FBA_D13
FBA_D8
FBA_D15
FBA_D10
FBA_D14
FBA_D9
FBA_D12

tia

CV216
.01U_0402_16V7-K
RANKA@

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

RANKA@

RANKA@

RANKA@

CV132

BA0
BA1
BA2

1U_0603_25V6M

26

M2
N8
M3

CV131

+FBA_VREFDQ0

FBA_CMD29
FBA_CMD13
FBA_CMD27

E3
F7
F2
F8
H3
H8
G2
H7

+1.35VGS

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7

FBA_CMD7
FBA_CMD10
FBA_CMD24
FBA_CMD6
FBA_CMD22
FBA_CMD26
FBA_CMD5
FBA_CMD21
FBA_CMD8
FBA_CMD4
FBA_CMD25
FBA_CMD23
FBA_CMD9
FBA_CMD12
FBA_CMD14

Group0

VREFCA
VREFDQ

1U_0603_25V6M

D7
C3
C8
C2
A7
A2
B8
A3

M8
H1

+FBA_VREFCA0
+FBA_VREFDQ0

1U_0603_25V6M

+FBA_VREFDQ0

RANKA@
RV168
1.33K_0402_1%

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

FBA_D5
FBA_D1
FBA_D7
FBA_D0
FBA_D4
FBA_D3
FBA_D6
FBA_D2

+1.35VGS

RANKA@
RV167
1.33K_0402_1%

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14

23,25,26,27

RANKA@

RANKA@

RANKA@

CV139

+1.35VGS

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7

E3
F7
F2
F8
H3
H8
G2
H7

33P_0402_50V8J

FBA_CMD7
FBA_CMD10
FBA_CMD24
FBA_CMD6
FBA_CMD22
FBA_CMD26
FBA_CMD5
FBA_CMD21
FBA_CMD8
FBA_CMD4
FBA_CMD25
FBA_CMD23
FBA_CMD9
FBA_CMD12
FBA_CMD14

CV116
.01U_0402_16V7-K
RANKA@

FBA_DQM[7..0]
UV5

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

VREFCA
VREFDQ

CV130

RANKA@
RV127
1.33K_0402_1%

M8
H1

CV134

+FBA_VREFCA0
+FBA_VREFDQ0

26

+FBA_VREFCA0

1U_0603_25V6M

UV6

+FBA_VREFCA0

CV133

RANKA@
RV128
1.33K_0402_1%

Issued Date

Title

LC Future Center Secret Data

Security Classification
2013/08/08

Deciphered Date

DDR3 VRAM Rank0_L

2013/08/05

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Date:
5

PDF created with pdfFactory Pro trial version www.pdffactory.com

Document Number

Rev
1.0

ACLUA
Thursday, December 26, 2013
1

Sheet

24

of

59

at least 16 mils width(optimal)

20 mils spacing to other signals /planes

+1.35VGS

FBA_D[0..63]

RANKA@
RV135
1.33K_0402_1%

D7
C3
C8
C2
A7
A2
B8
A3

FBA_D34
FBA_D38
FBA_D35
FBA_D39
FBA_D32
FBA_D36
FBA_D33
FBA_D37
FBA_D59
FBA_D62
FBA_D58
FBA_D63
FBA_D57
FBA_D60
FBA_D56
FBA_D61

M8
H1

+FBA_VREFCA1
+FBA_VREFDQ1

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7

FBA_CMD7
FBA_CMD10
FBA_CMD24
FBA_CMD6
FBA_CMD22
FBA_CMD26
FBA_CMD5
FBA_CMD21
FBA_CMD8
FBA_CMD4
FBA_CMD25
FBA_CMD23
FBA_CMD9
FBA_CMD12
FBA_CMD14

Group4

Group7

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

FBA_CLK1
FBA_CLK1#
FBA_CKE_H

23,27
23
23,24,26,27
23,24,26,27

FBA_ODT_H
FBA_CS0#_H
FBA_RAS#
FBA_CAS#

FBA_ODT_H
FBA_CS0#_H
FBA_RAS#
FBA_CAS#
FBA_CMD28

K1
L2
J3
K3
L3

FBA_DQS4
FBA_DQS7

F3
C7

FBA_CLK1

RV137
162_0402_1%

FBA_DQM4
FBA_DQM7

RANKA@

E7
D3

CK
CK
CKE
ODT
CS
RAS
CAS
WE
DQSL
DQSU
DML
DMU

FBA_CLK1#
FBA_DQS#4 G3
FBA_DQS#7 B7

23,24,26,27

FBA_RST#

FBA_RST#

T2
L8

FBA_CKE_H

J1
L1
J9
L9
M7

RV140
243_0402_1%
RANKA@

FBA_ODT_H

RV138
RV139
10K_0402_5% 10K_0402_5%
RANKA@
RANKA@

DQSL
DQSU

RESET
ZQ
NC1
NC2
NC3
NC4
NC5

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9

J7
FBA_CLK1
FBA_CLK1# K7
FBA_CKE_H K9

A1
A8
C1
C9
D2
E9
F1
H2
H9

K1
L2
J3
K3
L3

FBA_ODT_H
FBA_CS0#_H
FBA_RAS#
FBA_CAS#
FBA_CMD28

F3
C7

FBA_DQS5
FBA_DQS6

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

E7
D3

FBA_DQM5
FBA_DQM6

FBA_DQS#5 G3
FBA_DQS#6 B7

B1
B9
D1
D8
E2
E8
F9
G1
G9

T2

FBA_RST#

L8
J1
L1
J9
L9
M7

RV141
243_0402_1%
RANKA@

RANKA@

2
RANKA@

CV154

+1.35VGS

CV152

C
CV147

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

CK
CK
CKE

ODT
CS
RAS
CAS
WE

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9

DQSL
DQSU
DML
DMU

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12

DQSL
DQSU

RESET
ZQ
NC1
NC2
NC3
NC4
NC5

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9

FBA_DQM[7..0]

23,24,26,27

FBA_DQS[7..0]

23,24,26,27

FBA_DQS#[7..0]

23,24,26,27

Rank0
Address

0..31

FBx_CMD0

B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9

0..31

RANKA@

RANKA@

32..63

ODT_L
CS1#_L

FBx_CMD1
FBx_CMD2

CS0#_L

FBx_CMD3

CKE_L

FBx_CMD4

A9

A9

A11

A11

FBx_CMD5

A6

A6

A7

A7

FBx_CMD6

A3

A3

BA1

BA1

FBx_CMD7

A0

A0

A12

A12

FBx_CMD8

A8

A8

A8

A8

FBx_CMD9

A12

A12

A0

A0

FBx_CMD10

A1

A1

A2

A2

FBx_CMD11

RAS#

RAS#

RAS#

RAS#

FBx_CMD12

A13

A13

A14

A14

FBx_CMD13

BA1

BA1

A3

A3

FBx_CMD14

A14

A14

A13

A13

FBx_CMD15

CAS#

CAS#

CAS#

CAS#

CKE_L

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

ODT_H

ODT_H

FBx_CMD16

CS1#_H

FBx_CMD17

B1
B9
D1
D8
E2
E8
F9
G1
G9

FBx_CMD18

CS0#_H

FBx_CMD19

CKE_H

CKE_H

FBx_CMD20

RST

RST

RST

RST

FBx_CMD21

A7

A7

A6

A6

FBx_CMD22

A4

A4

A5

A5

FBx_CMD23

A11

A11

A9

A9

FBx_CMD24

A2

A2

A1

A1

FBx_CMD25

A10

A10

WE#

WE#

FBx_CMD26

A5

A5

A4

A4

FBx_CMD27

BA2

BA2

FBx_CMD28

WE#

WE#

A10

A10

FBx_CMD29

BA0

BA0

BA0

BA0

BA2

BA2

+1.35VGS

UV7 SIDE
1

Rank1

32..63

ODT_L

FBx_CMD30

0.1U_0402_10V7K

CV146

CV145

RANKA@

1U_0603_25V6M

BA0
BA1
BA2

23,24,26,27

CMD mapping mod Mode E

Group6

96-BALL
SDRAM DDR3
K4W 4G1646B-HC11_FBGA96
@

0.1U_0402_10V7K

RANKA@

1U_0603_25V6M

CV144

CV143

RANKA@

1U_0603_25V6M

+1.35VGS

For RF

33P_0402_50V8J

RANKA@

1U_0603_25V6M

CV142

UV8 SIDE
0.1U_0402_10V7K

0.1U_0402_10V7K

+1.35VGS

FBA_D52
FBA_D50
FBA_D55
FBA_D51
FBA_D53
FBA_D48
FBA_D54
FBA_D49

M2
N8
M3

FBA_CMD29
FBA_CMD13
FBA_CMD27

96-BALL
SDRAM DDR3
K4W 4G1646B-HC11_FBGA96
@

D7
C3
C8
C2
A7
A2
B8
A3

Group5

tia

23,27
23,27
23,27

B2
D9
G7
K2
K8
N1
N9
R1
R9

CV156

J7
K7
K9

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

CV155

FBA_CLK1
FBA_CLK1#
FBA_CKE_H

BA0
BA1
BA2

1U_0603_25V6M

M2
N8
M3

en

FBA_CMD29
FBA_CMD13
FBA_CMD27

FBA_D44
FBA_D43
FBA_D45
FBA_D40
FBA_D47
FBA_D42
FBA_D46
FBA_D41

+1.35VGS

27

CV217
.01U_0402_16V7-K
RANKA@

E3
F7
F2
F8
H3
H8
G2
H7

23,24,26,27

FBA_CMD[30..0]

RANKA@

RANKA@

RANKA@

For RF
1

2
RANKA@

CV164

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E3
F7
F2
F8
H3
H8
G2
H7

+FBA_VREFDQ1

1
2

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

+1.35VGS

+FBA_VREFDQ1

RANKA@
RV170
1.33K_0402_1%

VREFCA
VREFDQ

33P_0402_50V8J

RANKA@
RV169
1.33K_0402_1%

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7

CV159

+1.35VGS

M8
H1

CV158

FBA_CMD7
FBA_CMD10
FBA_CMD24
FBA_CMD6
FBA_CMD22
FBA_CMD26
FBA_CMD5
FBA_CMD21
FBA_CMD8
FBA_CMD4
FBA_CMD25
FBA_CMD23
FBA_CMD9
FBA_CMD12
FBA_CMD14

1U_0603_25V6M

+FBA_VREFCA1
+FBA_VREFDQ1

CV157

27

CV141
.01U_0402_16V7-K
RANKA@

1U_0603_25V6M

+FBA_VREFCA1

1
2

1U_0603_25V6M

+FBA_VREFCA1

RANKA@
RV136
1.33K_0402_1%

UV7

on
fid

UV8

Issued Date

Title

LC Future Center Secret Data

Security Classification
2013/08/08

Deciphered Date

DDR3 VRAM Rank0_H

2013/08/05

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Date:
5

PDF created with pdfFactory Pro trial version www.pdffactory.com

Document Number

Rev
1.0

ACLUA
Thursday, December 26, 2013
1

Sheet

25

of

59

FBA_D[0..63]

UV9

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E3
F7
F2
F8
H3
H8
G2
H7

FBA_D1
FBA_D5
FBA_D0
FBA_D7
FBA_D2
FBA_D6
FBA_D3
FBA_D4

D7
C3
C8
C2
A7
A2
B8
A3

FBA_D25
FBA_D31
FBA_D24
FBA_D30
FBA_D26
FBA_D28
FBA_D27
FBA_D29

M8
H1

+FBA_VREFCA0
+FBA_VREFDQ0

Group0

Group3

FBA_CMD9
FBA_CMD24
FBA_CMD10
FBA_CMD13
FBA_CMD26
FBA_CMD22
FBA_CMD21
FBA_CMD5
FBA_CMD8
FBA_CMD23
FBA_CMD28
FBA_CMD4
FBA_CMD7
FBA_CMD14
FBA_CMD12

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7

FBA_CMD29
FBA_CMD6
FBA_CMD30

M2
N8
M3

VREFCA
VREFDQ

K1
L2
J3
K3
L3

FBA_DQS0
FBA_DQS3

F3
C7

FBA_DQM0
FBA_DQM3

E7
D3

FBA_DQS#0 G3
FBA_DQS#3 B7

23,24,25,27

FBA_RST#

FBA_RST#

T2

2 RV142
L8
243_0402_1%
RANKB@
J1
L1
J9
L9
M7

ODT
CS
RAS
CAS
WE
DQSL
DQSU
DML
DMU
DQSL
DQSU

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12

RESET
ZQ

NC1
NC2
NC3
NC4
NC5

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9

J7
K7
K9

FBA_CLK0
FBA_CLK0#
FBA_CKE_L

A1
A8
C1
C9
D2
E9
F1
H2
H9

K1
L2
J3
K3
L3

FBA_ODT_L
FBA_CS1#_L
FBA_RAS#
FBA_CAS#
FBA_CMD25

FBA_DQS1
FBA_DQS2

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

FBA_DQM1
FBA_DQM2

F3
C7
E7
D3

FBA_DQS#1 G3
FBA_DQS#2 B7

FBA_RST#

B1
B9
D1
D8
E2
E8
F9
G1
G9

T2
L8
J1
L1
J9
L9
M7

RV143
243_0402_1%
RANKB@

96-BALL
SDRAM DDR3
K4W 4G1646B-HC11_FBGA96
@

RANKB@

RANKB@

RANKB@

RANKB@

RANKB@

RANKB@

Group1

D7
C3
C8
C2
A7
A2
B8
A3

FBA_D22
FBA_D17
FBA_D23
FBA_D16
FBA_D20
FBA_D18
FBA_D21
FBA_D19

Group2

23,24,25,27

CMD mapping mod Mode E

BA0
BA1
BA2

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

B2
D9
G7
K2
K8
N1
N9
R1
R9

CK
CK
CKE

ODT
CS
RAS
CAS
WE

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9

DQSL
DQSU
DML
DMU

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12

DQSL
DQSU

RESET
ZQ
NC1
NC2
NC3
NC4
NC5

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9

Rank0
Address

0..31

FBx_CMD0

ODT_L

Rank1

32..63

A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

CS1#_L
CS0#_L

FBx_CMD3

CKE_L

FBx_CMD4

A9

A9

A11

A11

FBx_CMD5

A6

A6

A7

A7

FBx_CMD6

A3

A3

BA1

BA1

FBx_CMD7

A0

A0

A12

A12

FBx_CMD8

A8

A8

A8

A8

FBx_CMD9

A12

A12

A0

A0

FBx_CMD10

A1

A1

A2

A2

FBx_CMD11

RAS#

RAS#

RAS#

RAS#

FBx_CMD12

A13

A13

A14

A14

FBx_CMD13

BA1

BA1

A3

A3

FBx_CMD14

A14

A14

A13

A13

FBx_CMD15

CAS#

CAS#

CAS#

CAS#

CKE_L

ODT_H

RANKB@

RANKB@

CV180

CV179

ODT_H

FBx_CMD17

CS1#_H

FBx_CMD18

CS0#_H

FBx_CMD19

CKE_H

CKE_H

FBx_CMD20

RST

RST

RST

RST

FBx_CMD21

A7

A7

A6

A6

FBx_CMD22

A4

A4

A5

A5

FBx_CMD23

A11

A11

A9

A9

FBx_CMD24

A2

A2

A1

A1

FBx_CMD25

A10

A10

WE#

WE#

FBx_CMD26

A5

A5

A4

A4

FBx_CMD27

BA2

BA2

FBx_CMD28

WE#

WE#

A10

A10

FBx_CMD29

BA0

BA0

BA0

BA0

BA2

BA2

+1.35VGS
1U_0603_25V6M

1U_0603_25V6M

32..63

FBx_CMD2

FBx_CMD16

B1
B9
D1
D8
E2
E8
F9
G1
G9

0..31
ODT_L

FBx_CMD1

UV3 SIDE
0.1U_0402_10V7K

CV178

+1.35VGS

CV176

CV171

FBA_D13
FBA_D11
FBA_D15
FBA_D8
FBA_D12
FBA_D9
FBA_D14
FBA_D10

96-BALL
SDRAM DDR3
K4W 4G1646B-HC11_FBGA96
@

0.1U_0402_10V7K

+1.35VGS

For RF
1

23,24,25,27

FBx_CMD30

33P_0402_50V8J

CV170

1U_0603_25V6M

CV169

1U_0603_25V6M

CV168

1U_0603_25V6M

CV167

1U_0603_25V6M

CV166

UV4 SIDE
0.1U_0402_10V7K

0.1U_0402_10V7K

+1.35VGS

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E3
F7
F2
F8
H3
H8
G2
H7

tia

FBA_ODT_L
FBA_CS1#_L
FBA_RAS#
FBA_CAS#
FBA_CMD25

CK
CK
CKE

en

FBA_ODT_L
FBA_CS1#_L
FBA_RAS#
FBA_CAS#

J7
K7
K9

23,24
23
23,24,25,27
23,24,25,27

FBA_CLK0
FBA_CLK0#
FBA_CKE_L

FBA_CLK0
FBA_CLK0#
FBA_CKE_L

FBA_DQS[7..0]
FBA_DQS#[7..0]

+1.35VGS

B2
D9
G7
K2
K8
N1
N9
R1
R9

on
fid

23,24
23,24
23,24

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14

+1.35VGS

BA0
BA1
BA2

23,24,25,27

RANKB@

RANKB@

RANKB@

For RF
1

RANKB@

CV188

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

33P_0402_50V8J

M2
N8
M3

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14

CV183

FBA_CMD29
FBA_CMD6
FBA_CMD30

VREFCA
VREFDQ

CV182

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7

1U_0603_25V6M

M8
H1

FBA_CMD9
FBA_CMD24
FBA_CMD10
FBA_CMD13
FBA_CMD26
FBA_CMD22
FBA_CMD21
FBA_CMD5
FBA_CMD8
FBA_CMD23
FBA_CMD28
FBA_CMD4
FBA_CMD7
FBA_CMD14
FBA_CMD12

1U_0603_25V6M

+FBA_VREFCA0
+FBA_VREFDQ0

+FBA_VREFCA0
+FBA_VREFDQ0

23,24,25,27

FBA_DQM[7..0]

UV10

CV181

24
24

at least 16 mils width(optimal)

20 mils spacing to other signals /planes

23,24,25,27

FBA_CMD[30..0]

Issued Date

Title

LC Future Center Secret Data

Security Classification
2013/08/08

Deciphered Date

DDR3 VRAM Rank1_L

2013/08/05

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Date:
5

PDF created with pdfFactory Pro trial version www.pdffactory.com

Document Number

Rev
1.0

ACLUA
Thursday, December 26, 2013
1

Sheet

26

of

59

FBA_D[0..63]

23,24,25,26

FBA_CMD[30..0]

23,24,25,26

FBA_DQM[7..0]

23,24,25,26

FBA_DQS[7..0]

23,24,25,26

FBA_DQS#[7..0]

23,24,25,26

UV11

at least 16 mils width(optimal)

20 mils spacing to other signals /planes

25
25

M8
H1

+FBA_VREFCA1
+FBA_VREFDQ1

+FBA_VREFCA1
+FBA_VREFDQ1

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7

FBA_CMD9
FBA_CMD24
FBA_CMD10
FBA_CMD13
FBA_CMD26
FBA_CMD22
FBA_CMD21
FBA_CMD5
FBA_CMD8
FBA_CMD23
FBA_CMD28
FBA_CMD4
FBA_CMD7
FBA_CMD14
FBA_CMD12

UV12

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3

FBA_D38
FBA_D34
FBA_D39
FBA_D35
FBA_D37
FBA_D33
FBA_D36
FBA_D32
FBA_D62
FBA_D59
FBA_D63
FBA_D58
FBA_D61
FBA_D56
FBA_D60
FBA_D57

+FBA_VREFCA1
+FBA_VREFDQ1
FBA_CMD9
FBA_CMD24
FBA_CMD10
FBA_CMD13
FBA_CMD26
FBA_CMD22
FBA_CMD21
FBA_CMD5
FBA_CMD8
FBA_CMD23
FBA_CMD28
FBA_CMD4
FBA_CMD7
FBA_CMD14
FBA_CMD12

Group4

Group7

M8
H1
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E3
F7
F2
F8
H3
H8
G2
H7

FBA_D43
FBA_D44
FBA_D40
FBA_D45
FBA_D41
FBA_D46
FBA_D42
FBA_D47

D7
C3
C8
C2
A7
A2
B8
A3

FBA_D50
FBA_D52
FBA_D51
FBA_D55
FBA_D49
FBA_D54
FBA_D48
FBA_D53

K1
L2
J3
K3
L3

FBA_DQS4
FBA_DQS7

F3
C7
E7
D3

FBA_DQM4
FBA_DQM7

FBA_DQS#4 G3
FBA_DQS#7 B7

23,24,25,26

T2

FBA_RST#

FBA_RST#

L8

J1
L1
J9
L9
M7

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9

DQSL
DQSU
DML
DMU

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12

DQSL
DQSU

RESET
ZQ
NC1
NC2
NC3
NC4
NC5

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9

RV144
243_0402_1%
RANKB@

ODT
CS
RAS
CAS
WE

J7
FBA_CLK1
FBA_CLK1# K7
FBA_CKE_H K9

A1
A8
C1
C9
D2
E9
F1
H2
H9

FBA_ODT_H
FBA_CS1#_H
FBA_RAS#
FBA_CAS#
FBA_CMD25
FBA_DQS5
FBA_DQS6

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

FBA_DQM5
FBA_DQM6

K1
L2
J3
K3
L3

F3
C7
E7
D3

FBA_DQS#5 G3
FBA_DQS#6 B7

FBA_RST#

B1
B9
D1
D8
E2
E8
F9
G1
G9

T2
L8

RV145
243_0402_1%
RANKB@

96-BALL
SDRAM DDR3
K4W 4G1646B-HC11_FBGA96
@

BA0
BA1
BA2

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

CK
CK
CKE

ODT
CS
RAS
CAS
WE

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9

J1
L1
J9
L9
M7

DQSL
DQSU
DML
DMU

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12

DQSL
DQSU

RESET
ZQ
NC1
NC2
NC3
NC4
NC5

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9

Address

0..31

FBx_CMD0

ODT_L

Rank1

32..63

0..31

FBx_CMD1

A1
A8
C1
C9
D2
E9
F1
H2
H9

32..63

ODT_L
CS1#_L

FBx_CMD2

CS0#_L

FBx_CMD3

CKE_L

FBx_CMD4

A9

A9

A11

A11

FBx_CMD5

A6

A6

A7

A7

FBx_CMD6

A3

A3

BA1

BA1

FBx_CMD7

A0

A0

A12

A12

FBx_CMD8

A8

A8

A8

A8

FBx_CMD9

A12

A12

A0

A0

FBx_CMD10

A1

A1

A2

A2

FBx_CMD11

RAS#

RAS#

RAS#

RAS#

FBx_CMD12

A13

A13

A14

A14

FBx_CMD13

BA1

BA1

A3

A3

FBx_CMD14

A14

A14

A13

A13

FBx_CMD15

CAS#

CAS#

CAS#

CAS#

CKE_L

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

FBx_CMD16

ODT_H

ODT_H

FBx_CMD17

B1
B9
D1
D8
E2
E8
F9
G1
G9

CS1#_H

FBx_CMD18

CS0#_H

FBx_CMD19

96-BALL
SDRAM DDR3
K4W 4G1646B-HC11_FBGA96
@

CKE_H

CKE_H

FBx_CMD20

RST

RST

RST

RST

FBx_CMD21

A7

A7

A6

A6

FBx_CMD22

A4

A4

A5

A5

FBx_CMD23

A11

A11

A9

A9

FBx_CMD24

A2

A2

A1

A1

FBx_CMD25

A10

A10

WE#

WE#

FBx_CMD26

A5

A5

A4

A4

FBx_CMD27

BA2

BA2

FBx_CMD28

WE#

WE#

A10

A10

FBx_CMD29

BA0

BA0

BA0

BA0

BA2

BA2

FBx_CMD30

Rank0

B2
D9
G7
K2
K8
N1
N9
R1
R9

tia

FBA_ODT_H
FBA_CS1#_H
FBA_RAS#
FBA_CAS#
FBA_CMD25

CK
CK
CKE

M2
N8
M3

en

FBA_ODT_H
FBA_CS1#_H
FBA_RAS#
FBA_CAS#

J7
K7
K9

FBA_CMD29
FBA_CMD6
FBA_CMD30

23,25
23
23,24,25,26
23,24,25,26

FBA_CLK1
FBA_CLK1#
FBA_CKE_H

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

B2
D9
G7
K2
K8
N1
N9
R1
R9

FBA_CLK1
FBA_CLK1#
FBA_CKE_H

BA0
BA1
BA2

CMD mapping mod Mode E

+1.35VGS

on
fid

23,25
23,25
23,25

M2
N8
M3

Group6

+1.35VGS
FBA_CMD29
FBA_CMD6
FBA_CMD30

Group5

+1.35VGS

UV6 SIDE

+1.35VGS

+1.35VGS

UV5 SIDE

RANKB@

RANKB@

RANKB@

RANKB@

RANKB@

RANKB@

RANKB@

CV207

CV206

33P_0402_50V8J

CV205

1U_0603_25V6M

CV204

1U_0603_25V6M

CV203

1U_0603_25V6M

CV202

1U_0603_25V6M

CV200

CV195

33P_0402_50V8J

CV194

CV193

RANKB@

1U_0603_25V6M

0.1U_0402_10V7K

RANKB@

1U_0603_25V6M

CV192

CV191

RANKB@

1U_0603_25V6M

For RF
0.1U_0402_10V7K

RANKB@

1U_0603_25V6M

CV190

0.1U_0402_10V7K

0.1U_0402_10V7K

For RF

CV212

+1.35VGS

RANKB@

Issued Date

Title

LC Future Center Secret Data

Security Classification
2013/08/08

Deciphered Date

DDR3 VRAM Rank1_H

2013/08/05

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Date:
5

PDF created with pdfFactory Pro trial version www.pdffactory.com

Document Number

Rev
1.0

ACLUA
Thursday, December 26, 2013
1

Sheet

27

of

59

Physical
Strapping pin
ROM_SCLK

+3VG_AON

2
RV150
45.3K_0402_1%
@

STRAP0
STRAP1
STRAP2
STRAP3
STRAP4

Logical
Strapping Bit3

Logical
Strapping Bit2

Logical
Strapping Bit1

Logical
Strapping Bit0

+3VGS

SOR3_EXPOSED

SOR2_EXPOSED

SOR1_EXPOSED

SOR0_EXPOSED

ROM_SI

+3VGS

RAM_CFG[3]

RAM_CFG[2]

RAM_CFG[1]

RAM_CFG[0]

ROM_SO

+3VGS

DEVID_SEL

PCIE_CFG

SMB_ALT_ADDR

VGA_DEVICE

STRAP0

+3VGS

STRAP1

+3VGS

Power Rail

Reserved(keep pull-up and pull-down footprint and stuff 50Kohm pull-up)

STRAP2

+3VGS

STRAP3

+3VGS

STRAP4

+3VGS

Pull-down to Gnd

1000

0000

10K

1001

0001

15K

1010

0010

20K

1011

24.9K

1100

30.1K

1101

34.8K

1110

45.3K

1111

Physical
Strapping pin
ROM_SCLK

RV158
4.99K_0402_1%
@

ROM_SI
ROM_SO

ROM_SI
ROM_SO
ROM_SCLK

STRAP0
STRAP2
RV161
4.99K_0402_1%
N15SGT@

STRAP4

X76
FB Memory (DDR3)

GPU
B

Hynix
900MHz
Micron
900MHz
Samsung
900MHz

H5TC4G63AFR-11C

0x3

256M x 16

PD 20K

MT41J256M16HA-093G:E

0x4

256M x 16

PD 24.9K

K4W4G1646D-BC1A

0x5

256M x 16

PD 30.1K

ROM_SO

PD 4.99K

ROM_SCLK

PD 4.99K

STRAP0

PU 49.9K

STRAP1

Un-stuff

STRAP2

Un-stuff

GPU

FB Memory (DDR3)

STRAP3

STRAP2

STRAP1

STRAP0

PD 10K

PU 10K

PD 10K

PD 10K

PU 10K

PU 10K

PD 10K

PU 10K

0011
0100

STRAP3

Un-stuff

PCIE_CFG
0

0101
0110

(Default)

0111

SMBUS_ALT_ADDR
0

0x9E (Default)

0x9C (Multi-GPU usage)

Strap Mapping

+3VGS

SMB_ALT_ADDR

+3VGS

SUB_VENDOR

+3VGS

VGA_DEVICE

VGA_DEVICE

+3VGS

RAM_CFG[0]

3D Device (Class Code 302h)

+3VGS

RAM_CFG[1]

VGA Device (Default)

+3VGS

RAM_CFG[2]

+3VGS

RAM_CFG[3]

+3VGS

PCIE_MAX_SPEED

STRAP4
VRAM

X76
X76409JVL01

VRAM P/N
SA00005SH10

Samsung
X76409JVL51 (1G 32Mx16)

Un-stuff

X76409JVL02

Micron

SA00005M100

X76409JVL02 (2G 64Mx32)

N15S-GT

ROM_SI

STRAP3

Power Rail

on
fid

RV160
4.99K_0402_1%
N15SGT@

RV159
20K_0402_1%
@

X76

STRAP1
2

ROM_SI
ROM_SO
ROM_SCLK

(Default)

en

2
1

RV157
4.99K_0402_1%
@

tia

+3VGS

RV156
4.99K_0402_1%
@

DEVID_SEL

Pull-up to
+3VGS

4.99K

Resistor Values

RV155
45.3K_0402_1%
@

RV154
4.99K_0402_1%
@

RV153
15K_0402_1%
@

2
1

RV152
4.99K_0402_1%
@

20
20

Reserved(keep pull-up and pull-down footprint and not stuff by default)

RV151
45.3K_0402_1%
@

20

RV149
4.99K_0402_1%
@

RV148
24.9K_0402_1%
@

RV147
4.99K_0402_1%
@

1
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4

20
20
20
20
20

RV146
49.9K_0402_1%
N15SGT@

Hynix

STRAP4

ROM_SI

ROM_SO

ROM_SCLK

PD 10K

PD 10K

PD 10K

PD 10K

H5TC4G63AFR-11C
Hynix
900MHz
A

Micron
900MHz

N15V-GM

256M x 16

0x4

MT41J256M16HA-093G:E
256M x 16

0xD

Issued Date

Title

LC Future Center Secret Data

Security Classification
2013/08/08

Deciphered Date

N15X_MISC

2013/08/05

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Date:
5

PDF created with pdfFactory Pro trial version www.pdffactory.com

Document Number

Rev
1.0

ACLUA
Thursday, December 26, 2013
1

Sheet

28

of

59

en

tia

on
fid

Issued Date

Title

LC Future Center Secret Data

Security Classification
2013/08/08

Blank

2013/08/05

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Size
Document Number
Custom
Date:

PDF created with pdfFactory Pro trial version www.pdffactory.com

Rev
1.0

ACLUA

Thursday, December 26, 2013

1

Sheet

29

of

59

en

tia

on
fid

Title

LC Future Center Secret Data

Security Classification
Issued Date

2013/08/08

PDF created with pdfFactory Pro trial version www.pdffactory.com

Blank

2013/08/05

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Size
Document Number
Custom
Date:

Rev
1.0

ACLUA

Thursday, December 26, 2013

1

Sheet

30

of

59

en

tia

on
fid

Title

LC Future Center Secret Data

Security Classification
Issued Date

2013/08/08

PDF created with pdfFactory Pro trial version www.pdffactory.com

Blank

2013/08/05

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Size
Document Number
Custom
Date:

Rev
1.0

ACLUA

Thursday, December 26, 2013

1

Sheet

31

of

59

en

tia

on
fid

Title

LC Future Center Secret Data

Security Classification
Issued Date

2013/08/08

PDF created with pdfFactory Pro trial version www.pdffactory.com

Blank

2013/08/05

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Size
Document Number
Custom
Date:

Rev
1.0

ACLUA

Thursday, December 26, 2013

1

Sheet

32

of

59

LCD POWER CIRCUIT

CMOS Camera

+3VS

+5VALW

Need short

+3VS

W=60mils

J1

R2
100K_0402_5%

2 0_0402_5%

4.7U_0603_6.3V6K
C7

2
G

2N7002KDW H_SOT363-6

1
CD@

C6

@2

R3 1

W=40mils

2
0_0603_5%

C3
.1U_0402_10V6-K
CD@

C4
10U_0603_6.3V6M
@

2
R5 1
@
100K_0402_5%

CMOS_ON#
C9
0.01U_0402_25V7K
@

R7
100K_0402_5%

33P_0402_50V8J
@
C43

G
D

R6

PCH_ENVDD

C5
.1U_0402_10V6-K
@

W=60mils

1
2
FCM2012CF-800T06_2P

+LCDVDD_CON

+LCDVDD
L1

C2
.1U_0402_10V6-K
Q8A

Q7 3

LP2301ALT1G_SOT23-3

@
.01U_0402_16V7-K

2N7002KDW H_SOT363-6

+3VS_CMOS
LP2301ALT1G_SOT23-3

W=40 mils

R4
1
2
220K_0402_5%

5
G

Q8B

+3VS_CMOS_R

JUMP_43X39

Q9

C1
4.7U_0603_6.3V6K
CD@

.1U_0402_10V6-K
C8

R1
130_0603_1%

+LCDVDD

For EMI
Close to R5

C10
.1U_0402_10V6-K
@

+3VS

R16
100K_0402_5%

AO3401A_SOT23-3

Q33

1 @

C14
1
CD@

LEDVDD_EN#

2 0_0402_5%

INVT_PW M

Q34

PCH_ENVDD

2
R181 1
@
0_0402_5%

R22

.1U_0402_10V6-K
2 TS@
C23 1

1 TS@
2
100K_0402_5%

+3VS_TS_R

+3VS_TS

LP2301ALT1G_SOT23-3

S
2N7002KW _SOT323-3

1
TS@

+3VS

C25
.1U_0402_10V6-K
@

+3VS_TS_R

1 TS@

2 0_0402_5%

2 0_0402_5%

+3VS_TS

R26

9
9

USB20_N4
USB20_P4

R28

R23
R24

1 TS@
1 TS@

+3VS_TS

1 10K_0402_5% TS_RS
2 0_0402_5%
2 0_0402_5%

USB20_N4_CONN
USB20_P4_CONN

1
2
3
4
5
6

1
2
3
4
5
6

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

C19
C16

1
1

2 .1U_0402_10V6-K
2 .1U_0402_10V6-K

EDP_TX0+
EDP_TX0-

CPU_EDP_TX1+
CPU_EDP_TX1-

C17
C18

1
1

2 .1U_0402_10V6-K
2 .1U_0402_10V6-K

EDP_TX1+
EDP_TX1-

CPU_EDP_AUX
C20
CPU_EDP_AUX# C21

1
1

2 .1U_0402_10V6-K
2 .1U_0402_10V6-K

EDP_AUX
EDP_AUX#

INVT_PW M

INVT_PW M

CPU_EDP_HPD

W=60mils

+LCDVDD_CON
+3VS

43
43

DMIC_DATA
DMIC_CLK

9
9

C13

470P_0402_50V7K

C12

CPU_EDP_TX0+
CPU_EDP_TX0-

USB20_P5
USB20_N5

R182 1
@
R183 1
+3VS_CMOS@

2 0_0402_5% USB20_P5_R
2 0_0402_5% USB20_N5_R
2

C24
0.047U_0402_16V7K

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

G1
G2
G3
G4
G5

31
32
33
34
35

ACES_50406-03071-001
ME@

W=40mils
CD@

EMI request

GND1
GND2

7
8

For EMI

ACES_87213-00601-P01
ME@

USB20_N4_CONN

+3VALW

R21

470P_0402_50V7K

l
C11

DISPOFF#

2
@

JEDP1

4
42
1
@
0_0402_5%

JTS1

USB20_P4_CONN

2 0_0402_5%

+3VS

Touch Screen
3

R25

CPU_EDP_AUX
CPU_EDP_AUX#

C22
680P_0402_50V7K
@

3
Q11

CPU_EDP_TX1+
CPU_EDP_TX1-

+LEDVDD

EC_TS_ON#

INVT_PW M

C132
.1U_0402_10V6-K
@

44

CPU_EDP_TX0+
CPU_EDP_TX0-

4
4

4
4

Reserve for power consumption test

Touch Screen

R20
100K_0402_5%

4
4

on
fid

R19

PCH_EDP_PW M

1 2

R180
100K_0402_5%
@

R18
1K_0402_5%
@

R15
100K_0402_1%

DISPOFF#

EMI Request

2
R179 1
@
100K_0402_5%

B+

DMIC_CLK

.1U_0402_10V6-K

R13
100K_0402_1%
C15
0.1U_0402_25V6

+3VS

+1.35V

100P_0402_50V8J

2A 80 mil

2
R17 1
0_0805_5%

44

2A 80 mil
ENBKL

ENBKL

EMI request
+3VS

C138
1
2

+LEDVDD

2 0_0402_5%

B+

DISPOFF#

en

R14

PCH_ENBKL

R9
100K_0402_1%

EDP_AUX
EDP_AUX#

2 0_0402_5%
@

4.7U_0805_25V6-K

R12

BKOFF#

44

R8
100K_0402_1%

tia

1
2
@
0_0402_5%

R11

PCH_ENBKL

R10
4.7K_0402_5%
@

+3VS

For RF

USB20_P5

USB20_N5

L12

USB20_P5_R

USB20_N5_R

CMM21T-900M-N_4P
R27

D2

For EMI

USB20_N4

USB20_P4_CONN

USB20_N4_CONN

D1
AZC199-02S.R7G_SOT23-3
@

L13
USB20_P4

For EMI

CMM21T-900M-N_4P

AZ5215-01F_DFN1006P2E2

Issued Date

Title

LC Future Center Secret Data

Security Classification
2013/08/08

2013/08/05

Deciphered Date

eDP/ CMOS/Touch screen

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Thursday, December 26, 2013
Date:

Rev
1.0

ACLUA

PDF created with pdfFactory Pro trial version www.pdffactory.com

Sheet

33

of

59

L2

HDMI_CLK-_C

HDMI_CLK-_CON

2
3.3P_0402_50V8-C

C26
@

HDMI_CLK+_C

HDMI_CLK+_CON

2
3.3P_0402_50V8-C

C27

HDMI2012F2SF-900T04_4P
D

+3VS

L3

HDMI_TX0-_C

1
HDMI_TX0-_CON
C28

2
3.3P_0402_50V8-C
@

1
HDMI_TX0+_CON
C29

2
3.3P_0402_50V8-C

G
HDMI_DET

D3
1 1

10 9

HDMI_DET

HDMIDAT_R

2 2

9 8

HDMIDAT_R

HDMICLK_R

4 4

7 7

HDMICLK_R

+5VS_HDMI

5 5

6 6

+5VS_HDMI

Q1B
L4

HDMI_TX1-_CON

2
3.3P_0402_50V8-C

C30

L5

3 3

2
3.3P_0402_50V8-C

C32

DDPB_DATA

HDMIDAT_R

2N7002KDWH_SOT363-6

2
3.3P_0402_50V8-C

For EMC

2 470_0402_5%

2 470_0402_5%

HDMI_TX0-_C

R31

2 470_0402_5%

HDMI_TX0+_C

R32

2 470_0402_5%

HDMI_TX1-_C

R33

2 470_0402_5%

HDMI_TX1+_C

R34

2 470_0402_5%

HDMI_TX2-_C

R37

2 470_0402_5%

HDMI_TX2+_C

R38

2 470_0402_5%

+3VS

100K_0402_5%

F1

3
RB491D_SOT23-3

BAT54S-7-F_SOT23-3

0.5A_8V_KMC3S050RY

LP2301ALT1G_SOT23-3

Q22

R39
2.2K_0402_5%

SUSP

46

R41
20K_0402_5%

JHDMI1

HDMIDAT_R
HDMICLK_R

HDMI_CLK-

HDMI_CLK-

C35

1 .1U_0402_10V6-K

HDMI_CLK-_C

R43 2

1 0_0402_5%

HDMI_CLK-_CON

4
4

HDMI_CLK+
HDMI_TX0-

HDMI_CLK+
HDMI_TX0-

C36
C37

2
2

1 .1U_0402_10V6-K
1 .1U_0402_10V6-K

HDMI_CLK+_C R44 2
HDMI_TX0-_C R45 2

@
@

1 0_0402_5%
1 0_0402_5%

HDMI_CLK+_CON
HDMI_TX0-_CON

4
4

HDMI_TX0+
HDMI_TX1-

HDMI_TX0+
HDMI_TX1-

C38
C39

2
2

1 .1U_0402_10V6-K
1 .1U_0402_10V6-K

HDMI_TX0+_C R46 2
HDMI_TX1-_C R47 2

@
@

1 0_0402_5%
1 0_0402_5%

HDMI_TX0+_CON
HDMI_TX1-_CON

4
4

HDMI_TX1+
HDMI_TX2-

HDMI_TX1+
HDMI_TX2-

C40
C41

2
2

1 .1U_0402_10V6-K
1 .1U_0402_10V6-K

HDMI_TX1+_C R48 2
HDMI_TX2-_C R49 2

@
@

1 0_0402_5%
1 0_0402_5%

HDMI_TX1+_CON
HDMI_TX2-_CON

HDMI_TX2+

HDMI_TX2+

C42

1 .1U_0402_10V6-K

HDMI_TX2+_C R50 2

1 0_0402_5%

HDMI_TX2+_CON

19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

C34
.1U_0402_10V6-K

R40
2.2K_0402_5%

HDMI_DET

3
R42

+5VS_HDMI

2N7002KW_SOT323-3

2N7002KW_SOT323-3

D4

on
fid

Q13

+5VS_HDMI_F
D5

2
G

Q12

HDMI_HPD

R35
1M_0402_5%

+5VS

D4

+3VS

+5VS

R30

For EMC

R29

HDMI_CLK+_C

en

HDMI_CLK-_C

AZ1045-04F_DFN2510P10E-10-9
@

3 HDMI_TX2+_CON
1
4
3
C33
HDMI2012F2SF-900T04_4P

HDMI_TX2-_CON

2
G

Q1A

tia

HDMI_TX2+_C

2N7002KDWH_SOT363-6

2
3.3P_0402_50V8-C

HDMI_TX2-_C

HDMICLK_R

1
3
HDMI_TX1+_CON
4
3
C31
HDMI2012F2SF-900T04_4P

DDPB_CLK

HDMI_TX1+_C

3
D

HDMI_TX1-_C

HDMI2012F2SF-900T04_4P

HDMI_TX0+_C

HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
20
CKGND1 21
CK_shield
GND2
CK+
22
D0GND3 23
D0_shield
GND4
D0+
D1D1_shield
D1+
D2D2_shield
D2+
FOX_QJ111A1-RC0AH1-8H
ME@

Close to JHDMI1

HDMI_CLK+_CON

D6
1 1

10 9

HDMI_CLK+_CON

HDMI_TX1-_CON

D7
1 1

10 9

HDMI_TX1-_CON

HDMI_CLK-_CON

2 2

9 8

HDMI_CLK-_CON

HDMI_TX1+_CON

2 2

9 8

HDMI_TX1+_CON

HDMI_TX0+_CON

4 4

7 7

HDMI_TX0+_CON

HDMI_TX2-_CON

4 4

7 7

HDMI_TX2-_CON

HDMI_TX0-_CON

5 5

6 6

HDMI_TX0-_CON

HDMI_TX2+_CON

5 5

6 6

HDMI_TX2+_CON

3 3

3 3

AZ1045-04F_DFN2510P10E-10-9
@

For EMC

AZ1045-04F_DFN2510P10E-10-9
@

Issued Date

Title

LC Future Center Secret Data

Security Classification
2013/08/08

2013/08/05

Deciphered Date

HDMI_CONN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Thursday, December 26, 2013
Date:

Rev
1.0

ACLUA

PDF created with pdfFactory Pro trial version www.pdffactory.com

Sheet

34

of

59

Need open

+1.35V
+3VS

+3VS_DVGA

+3VS_DVGA

+3VS_DVGA

2 0_0603_5%

LVG1

1
2
PBY160808T-331Y-N

VDD33

CVG1
.47U_0402_6.3V6K

LVG2

CVG2
1U_0402_6.3V6K

1
2
PBY160808T-331Y-N

CVG3
.47U_0402_6.3V6K

VDDA33

LVG3

CVG4
1U_0402_6.3V6K

1
2
PBY160808T-331Y-N

VDD33VGA

CVG5
.47U_0402_6.3V6K

CVG51
CVG6
4.7U_0603_6.3V6K

@2

4.7U_0603_6.3V6K

RVG1

+1.35VS

JVG1 @

1
@

JUMP_43X39

8
7
6
5

RVG36

5VS_GATE

1
2
3

46

QVG1

CVG46
4.7U_0603_6.3V6K
@

CVG47
.1U_0402_10V6-K
@

AP4800BGM-HF_SO-8

10K_0402_5%

+5VALW

CVG48
.1U_0402_10V6-K
@

2
1
+1.2VS

CVG7
1U_0402_10V6K

+1.2VS

+1.35VS_DVGA

l
2

1
2
PBY160808T-331Y-N

VDDRX

CVG13
1U_0402_6.3V6K

+3VS_DVGA

1
CD@

CVG31
1U_0402_6.3V6K

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

VGA_SDA
RVGA
REXT
VDDA33
VDD33
GND1
VDD12_1
XTLO
XTLI
AUXN
AUXP
DP_HPD
VDDRX
DRX0p
DRX0n
GND2
DRX1p
DRX1n
RST#
PD#

RVG7

2 4.7K_0402_5%

CSCL

RVG8

2 4.7K_0402_5%

VDD12
XTLO
XTLI
AUXN
AUXP
DP_HPD
VDDRX
DRX0P
DRX0N

DRX1P
DRX1N
RST#
PD#

41

VGA_SCL
RED
GNDVGA3
GREEN
GNDVGA2
VDD33VGA
BLUE
GNDVGA1
VGA_HS
VGA_VS
GPIO1
TESTMODE
CSDA
CSCL
GPIO3/TSCK_O
VDD12_2
GPIO0
GND3
GPIO2/INTRQ
CFG

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

GND2

GND1

OSC2

2 4.7K_0402_5%

+3VS_DVGA

GREEN

VDD33VGA
BLUE

CVG21

VGA_HS
VGA_VS
GPIO1

2 .1U_0402_10V6-K

VGA_HS
VGA_VS
GPIO1

CSDA
CSCL
GPIO3/TSCK_O
VDD12
1
GPIO0
GPIO2/INTRQ
CFG

RVG14
4.7K_0402_5%
@

36
36
36
GPIO3/TSCK_O

TVG1 PAD @

1
TVG2 PAD @

EPAD

2 1M_0402_5%

RVG9

VGA_SCL
RED

PS8613TQFN40GTR2-A1_TQFN40_5X5

OSC1

CFG

Initial code loading selection, internal pull down ~80k :

L: Loading initial code from internal MTP ROM
H: No initial code loading, external I2C control is expected

VGA_SDA
RVGA
REXT
VDDA33
VDD33

CSDA

2 RVG12
2 RVG10

CVG12
.47U_0402_6.3V6K

PD#

RED

RVG17

2 10_0402_5%

GREEN

RVG18

2 10_0402_5%

BLUE

RVG20

2 10_0402_5%

VGA_SCL

RVG23

2 0_0402_5%

VGA_SDA

RVG24

2 0_0402_5%

CRT_R

RVG15
4.7K_0402_5%
@

1
CD@

I2C address, 3-state inputs:

L: 0x50h ~ 0x6Fh
M: 0x90h ~ 0xAFh
H: 0x30h ~ 0x4Fh

36

CRT_G

36

CRT_B

36

CRT_DDC_CLK

36

CRT_DDC_DAT

36

4
3

27MHZ_10PF_7V27000050

LVG5

CVG11
1U_0402_6.3V6K

1
1

YVG1

.1U_0402_10V6-K
CVG29

2
RST#

.01U_0402_16V7-K
CVG28

UVG2
6.65K_0402_1%
4.99K_0402_1%

DP_HPD

RVG13
10K_0402_5%

XTLI

VDD12

en

2 1K_0402_5%

RVG16

1
2
PBY160808T-331Y-N

DRX0N
DRX0P
DRX1N
DRX1P
AUXN
AUXP

+3VS_DVGA

CVG30
.1U_0402_10V6-K

CVG10
.47U_0402_6.3V6K

LVG4

+3VS_DVGA

.1U_0402_10V6-K
.1U_0402_10V6-K
.1U_0402_10V6-K
.1U_0402_10V6-K
.1U_0402_10V6-K
.1U_0402_10V6-K

2 0_0603_5%

on
fid

RVG111

+1.35VS

RVG5
20K_0402_1%

.01U_0402_16V7-K
CVG27

VGA_HPD

RVG35

+1.35VS_DVGA
CVG8
10U_0603_6.3V6M

+3VS

.1U_0402_10V6-K
CVG26

FB

APL5930KAI-TRG_SO8

.01U_0402_16V7-K
CVG25

VGA_TX0VGA_TX0+
VGA_TX1VGA_TX1+
VGA_AUX#
VGA_AUX

2
2
2
2
2
2

.1U_0402_10V6-K
CVG22

4
4
4
4
4
4

CVG151
CVG161
CVG171
CVG181
CVG191
CVG201

RVG3
10K_0402_1%

RVG6
100K_0402_5%
@

FB

3
4

2 0_0603_5%

CVG14
.1U_0402_10V6-K

VFB=0.8V
Vo=VFB*(1+RVG3/RVG5)
OCP:Min 4A

RVG4

1
2
10K_0402_5%

SUSP#

EN
POK

.1U_0402_10V6-K
CVG24

44,46,55,56,57

8
7

EN
POK

VOUT1
VOUT2

tia

CVG9
4.7U_0603_6.3V6K

VCNTL
VIN1
VIN2

RVG34

2 0_0603_5%
+1.5VS_VIN
1

.1U_0402_10V6-K
CVG23

GND

6
5
9

@
RVG2

UVG1

+1.5VS

XTLO
A

CVG32
15P_0402_50V8J

CVG33
12P_0402_50V8-J

Issued Date

Title

LC Future Center Secret Data

Security Classification
2013/08/08

2013/08/05

Deciphered Date

DP to CRT Converter(PS8613)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Thursday, December 26, 2013
Date:

Rev
1.0

ACLUA

PDF created with pdfFactory Pro trial version www.pdffactory.com

Sheet

35

of

59

CRT Connector
+CRT_VCC_CON

+5VS_HDMI

+5VS

+CRT_VCC

RVG39

2 0_0603_5%

DVG1

FVG1

2 @

+CRT_VCC_CON

0.5A_8V_KMC3S050RY

W=40mils

1
3
PMEG2010ET_SOT23-3

CVG34
.1U_0402_10V6-K
CD@

DVG2
AZ5425-01F_DFN1006P2E2

JCRT1

VSYNC_CON

35

CVG41
100P_0402_50V8J
@

+3VS_DVGA

6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

For EMC

G
G

16
17

SUYIN_070546HR015M25KZR
ME@

RVG28
4.7K_0402_5%

CRT_HSYNC

RVG44

UVG3
74AHCT1G125GW_SOT353-5
@

LVG9
CRT_HSYNC_R

1
HSYNC_CON

33_0402_5%

2
RVG30
2.2K_0402_5%

1
2
BLM18BA100SN1D

RVG31
2.2K_0402_5%

CRT_DDC_CLK

CVG42
15P_0402_50V8J

CRT_DDC_DAT

CVG43
100P_0402_50V8J
@

CVG44
68P_0402_50V8J
@

RVG46
0_0402_5%
@

2 0_0402_5%

A
3

4
CRT_VSYNC RVG48
Y
UVG4
74AHCT1G125GW_SOT353-5
@

2 0_0402_5%

CRT_B_CON

DVG3
1 1

10 9

CRT_B_CON

VSYNC_CON

DVG4
1 1

10 9

VSYNC_CON

CRT_G_CON

2 2

9 8

CRT_G_CON

HSYNC_CON

2 2

9 8

HSYNC_CON

CRT_R_CON

4 4

7 7

CRT_R_CON

CRT_DDC_CLK

4 4

7 7

CRT_DDC_CLK

CRT_DET#

5 5

6 6

CRT_DET#

CRT_DDC_DAT

5 5

6 6

CRT_DDC_DAT

3 3

3 3

AZ1045-04F_DFN2510P10E-10-9
@

RVG33

33_0402_5%

CRT_VSYNC_R

LVG10

1
2
BLM18BA100SN1D

VSYNC_CON

OE#

P
RVG45

VGA_VS

RVG38
1
2
@
1K_0402_5%

2
VGA_VS

.1U_0402_10V6-K

+5VS

RVG47
0_0402_5%
@

RVG32

+5VS

CVG50
1
2 @

2 0_0402_5%

RVG42
0_0402_5%
@

2 0_0402_5%

on
fid

OE#

P
RVG43

VGA_HS

VGA_HS

RVG41
0_0402_5%
@

1
@
2
0_0402_5%

RVG37
1
@
2
1K_0402_5%

.1U_0402_10V6-K

CVG49
1
2 @

RVG40
0_0402_5%
@

+5VS

GPIO1

RVG29

en

35

35

CRT_DDC_CLK

CRT_DDC_CLK

CLOSE TO UVG1
C

35

CRT_DDC_DAT
CRT_G_CON

CRT_DDC_DAT

HSYNC_CON
CRT_B_CON
CVG40
3.3P_0402_50V8-C

1
2
BLM18BA100SN1D
CVG39
3.3P_0402_50V8-C

LVG8

35

CVG38
3.3P_0402_50V8-C

1
2
BLM18BA100SN1D

CVG37
5P_0402_50V8-C

RVG27
75_0402_1%

CVG36
5P_0402_50V8-C

RVG26
75_0402_1%

CVG35
5P_0402_50V8-C

RVG25
75_0402_1%

1
2
BLM18BA100SN1D

LVG7

CRT_DET#
CRT_R_CON

CRT_B

LVG6

TVG3

tia

35

CRT_G

CRT_R

35

35

@ PAD

CVG45
15P_0402_50V8J

AZ1045-04F_DFN2510P10E-10-9
@

For EMC
Issued Date

Title

LC Future Center Secret Data

Security Classification
2013/08/08

2013/08/05

Deciphered Date

CRT

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Thursday, December 26, 2013
Date:

Rev
1.0

ACLUA

PDF created with pdfFactory Pro trial version www.pdffactory.com

Sheet

36

of

59

+3VALW TO +3VALW_LAN
+3VALW

Need short
1

JL1

+3VALW_LAN rising time (10%~90%):

0.5msspec100ms

+3VALW_LAN

+3VALW_LAN

+LAN_VDDREG

width : 40 mils

2 @

@
RL1 1

2
0_0603_5%

JUMP_43X79

2
@

2
@

CL4
@

CL5
@

Close to Pin11

Close to Pin32

CL6

CL7

Close to Pin11

.1U_0402_10V6-K

.1U_0402_10V6-K

CL9

.01U_0402_16V7-K

1 @

CL1
4.7U_0603_6.3V6K

CL2
.1U_0402_10V6-K
CD@

Close to Pin32
+3VALW_LAN

2 0_0402_5%
2 0_0402_5%

PCIE_WAKE#_R

RL8

1
2
2.49K_0402_1%

+3VS

+3VALW_LAN
RSET
+LAN_VDD10
LAN_XTALO
LAN_XTALI

TL3 @ 1

LAN_PWR_ON#

2
RL121
@
0_0402_5%

LAN_DISABLE#
TL4 @ 1

RL9
1K_0402_1%

RL10 1

8,19,40,44
PLT_RST#
9
PCIE_PRX_DTX_N3
9
PCIE_PRX_DTX_P3

LAN_PWR_ON#

CL10 1
CL11 1

2 .1U_0402_10V6-K
2 .1U_0402_10V6-K

CL10 close to Pin18

CL11 close to Pin17

0_0402_5%

RL11
15K_0402_5%
@

GND
AVDD33_2
RSET
AVDD10
CKXTAL2
CKXTAL1
LED0
LED1/GPIO
LED2
REGOUT
VDDREG
DVDD10
LANWAKEB
ISOLATEB
PERSTB
HSON
HSOP

on
fid

ISOLATE#

+LAN_REGOUT
+LAN_VDDREG
+LAN_VDD10
PCIE_WAKE#_R
ISOLATE#
PLT_RST#
PCIE_PRX_C_DTX_N3
PCIE_PRX_C_DTX_P3

33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

REFCLK_N
REFCLK_P
HSIN
HSIP
CLKREQB
AVDD33_1
MDIN3
MDIP3
AVDD10_2
MDIN2
MDIP2
MDIN1
MDIP1
AVDD10_1
MDIN0
MDIP0

en

RL7 1
RL6 1

PCIE_WAKE#
LAN_WAKE#

16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

2
QL1

tia

UL1

RL4
10K_0402_5%
@

LAN_CLKREQ#_R

RL5
10K_0402_5%
@

8,9,40,44
40,44

+3VS

+3VALW_LAN

LAN_CLKREQ#

.1U_0402_10V6-K

1
2

CL8

1
2
@
47K_0402_5%

Q14
1

RL3

LAN_PWR_ON#

RL2
100K_0402_5%
@

44

LP2301ALT1G_SOT23-3

4.7U_0603_6.3V6K

+3VALW

4.7U_0603_6.3V6K

2N7002KW_SOT323-3
0_0402_5%

CLK_PCIE_LAN#
CLK_PCIE_LAN
PCIE_PTX_C_DRX_N3
PCIE_PTX_C_DRX_P3
LAN_CLKREQ#_R
+3VALW_LAN
LAN_MDI3LAN_MDI3+
+LAN_VDD10
LAN_MDI2LAN_MDI2+
LAN_MDI1LAN_MDI1+
+LAN_VDD10
LAN_MDI0LAN_MDI0+

CLK_PCIE_LAN#
8
CLK_PCIE_LAN
8
PCIE_PTX_C_DRX_N3
PCIE_PTX_C_DRX_P3
LAN_MDI3LAN_MDI3+

38
38

LAN_MDI2LAN_MDI2+
LAN_MDI1LAN_MDI1+

38
38
38
38

LAN_MDI0LAN_MDI0+

38
38

1 RL18
@

9
9

RTL8111GUL-CG_QFN32_4X4
GIGA@

LAN_XTALI
YL1

CL12
10P_0402_50V8J

OSC1

GND2

GND1

OSC2

1
25MHZ_10PF_7V25000014

For RTL8111GUL/ RTL8106EUL (SWR mode)

+LAN_REGOUT

LAN_XTALO

+LAN_VDD10

1
2
LL1
2.2UH_NLC252018T-2R2J-N_5%

CL13
10P_0402_50V8J

CL15
4.7U_0603_6.3V6K

1
CL16
.1U_0402_10V6-K
CD@

1
CL17
.1U_0402_10V6-K

1
CL18
.1U_0402_10V6-K

1
CL19
.1U_0402_10V6-K

1
CL20
.1U_0402_10V6-K

Close to Pin3, 8, 22, 30

1
CL21
1U_0402_6.3V6K
@

CL22
.1U_0402_10V6-K
@

Close to Pin22(Reserved)

Layout Note: LL1 must be

within 200mil to Pin36,
CL15,CL16 must be within
200mil to LL1
+LAN_REGOUT: Width =60mil

Issued Date

Title

LC Future Center Secret Data

Security Classification
2013/08/08

2013/08/05

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

LAN_RTL8111GUL/RTL8106EUL
Size
Document Number
Custom
Date:

PDF created with pdfFactory Pro trial version www.pdffactory.com

Rev
1.0

ACLUA

Thursday, December 26, 2013

1

Sheet

37

of

59

DL1/DL2
1'S PN:SC300003M00

6
LAN_MDI2-

NC3

NC4

I/O3

I/O1

11
8
1

6
LAN_MDI1-

GND

NC3

NC4

I/O3

I/O1

LAN_MDI0+

10
11
8
1

CL24

NC5
NC2
VDD

LAN_MDI1-

37

LAN_MDI1+

37

LAN_MDI2+

37

LAN_MDI2-

37

LAN_MDI3+

37

LAN_MDI3-

20

LAN_MDI1+

19

LAN_MDI2+

17

LAN_MDI2-

16

LAN_MDI3+
LAN_MDI3-

LAN_MDI0-

@
2 0_0603_5%
@
RL15 1

TCT2

MX2+

TD2+

MX2-

TD2-

MCT3

TCT3

MX3+

TD3+

MX3-

TD3-

MCT4

TCT4

LAN_MDO0+

MCT

LAN_MDO1-

LAN_MDO1+

MCT

LAN_MDO2+

LAN_MDO2-

10

MCT

RL17
20_0603_5%

MX4+

TD4+

MX4-

TD4-

11

LAN_MDO3+

13

12

CL32
0.022U_0603_50V7K

LAN_MDO3-

2 0_0603_5%
@

CHASSIS1_GND

Reserve for EMI go rural solution

CL25
1000P_1206_2KV7-K
@

CHASSIS1_GND

JRJ1

ME@
GND_4
GND_3

LAN_MDO0+

LAN_MDO0-

LAN_MDO1+

LAN_MDO2+

LAN_MDO2-

LAN_MDO1-

LAN_MDO3+

LAN_MDO3-

2 0_0603_5%

DL3
BS4200N-C-LV_SMB-F2

on
fid

Place Close to TL2

RL14 1

14

TD1-

MCT2

GST5009 LF

AZ3033-04F_DFN2525P10E10

RL16 1

LAN_MDI1-

15

@
I/O2

37

MX1-

LAN_MDO0-

en

+3VALW_LAN

4
5

I/O4
NC1

22

LAN_MDI3-

68P_0402_50V8J

9
2

LAN_MDI0+

18

Place Close to TL1

LAN_MDI1+

LAN_MDI0+

21

AZ3033-04F_DFN2525P10E10

DL2

37

MCT

GND

LAN_MDI3+

10

NC2
VDD

TD1+

I/O2
NC5

TCT1

MX1+

4
5

I/O4
NC1

23

+3VALW_LAN

9
2

LAN_MDI0-

LAN_MDI2+

LAN_MDI0-

tia

DL1

37

GIGA@

MCT1

TL1
24
D

GND_2
PR1+
GND_1

12
11
10
9

PR1PR2+

CHASSIS1_GND

PR3+
PR3PR2PR4+
PR4SANTA_130460-3

Issued Date

Title

LC Future Center Secret Data

Security Classification
2013/08/08

Deciphered Date

LAN_Transformer

2013/08/05

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize
B
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Date:
5

PDF created with pdfFactory Pro trial version www.pdffactory.com

Document Number

Rev
1.0

ACLUA
Friday, December 27, 2013

Sheet
1

38

of

59

SMSC thermal sensor

placed near DIMM
+3VS

REMOTE-_R

U1

1
1
C47
.1U_0402_10V6-K
CD@

+3VS

R51

REMOTE+_R

REMOTE-_R

2
1
@
10K_0402_5%

SCL

D+

SDA

D-

ALERT#

T_CRIT#

GND

EC_SMB_CK2

EC_SMB_DA2

R176 1 UMA@ 2 0_0402_5%

REMOTE+_R

REMOTE2-

R177 1 UMA@ 2 0_0402_5%

REMOTE-_R

REMOTE1-

R178 1

EC_SMB_DA2

7,19,44

Near CPU core

REMOTE2+

C46
100P_0402_50V8J
@

tia

REMOTE2+

7,19,44

Q15
MMBT3904WH_SOT323-3
OPT@

2 0_0402_5%

2 0_0402_5%

2
B
2

REMOTE2-

C
Q16
MMBT3904WH_SOT323-3
UMA@

en

Address 1001_100xb
R175 1

EC_SMB_CK2

2
B
2

REMOTE1-

VDD

NCT7718W_MSOP8

REMOTE1+

C45
100P_0402_50V8J
@

C44
2200P_0402_50V7K

Near GPU&VRAM

REMOTE1+

REMOTE+_R

Close to U1

on
fid

REMOTE+/-_R, REMOTE1+/-, REMOTE2+/-:

Trace width/space:10/10 mil
Trace length:<8"

FAN Conn

+5VS

R52 1

C49
10U_0805_10V6K

2 0_0603_5%

C50
.1U_0402_10V6-K
@

JFAN1

1
2
3
4
5
6

+5VS_FAN

44
44

EC_FAN_SPEED
EC_FAN_PWM

1
2
3
4
GND1
GND2
ACES_85205-04001
ME@

Title

LC Future Center Secret Data

Security Classification
Issued Date

2013/08/08

Deciphered Date

2013/08/05

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Thermal sensor/FAN CONN

Size
Document Number
Custom
Date:

PDF created with pdfFactory Pro trial version www.pdffactory.com

Rev
1.0

ACLUA

Thursday, December 26, 2013

Sheet
1

39

of

59

Mini-Express Card(WLAN/WiMAX)
+3VS_W LAN

JW LAN1

9
9

JUMP_43X79
+3VALW

1 AOAC@

C52
@

C51
.1U_0402_10V6-K
@

R54 1 AOAC@ 2

100K_0402_5%

.01U_0402_16V7-K

Q17

AOAC_ON#

GND1
USB_D+
USB_DGND2
9
NC
11
NC
13
NC
15
NC
17
19 MLDIR_SENSE
21 DP_ML3N
23 DP_ML3P
GND3
25
27 DP_ML2N
29 DP_ML2P
31 GND4
33 DP_HPD
35 GND5
37 PETP0
39 PETN0
41 GND6
43 PERP0
45 PERN0
47 GND7
49 REFCLKP0
51 REFCLKN0
53 GND8
55 CLKREQ0#
57 PEWAKE0#
59 GND9
61 PETP1
63 PETN1
65 GND10
67 PERP1
69 PERN1
71 GND11
73 REFCLKP1
75 REFCLKN1
GND12
76
PEG1

LP2301ALT1G_SOT23-3

44

1
3
5
7

USB20_P6
USB20_N6

C53
.1U_0402_10V6-K
AOAC@

C54
.1U_0402_10V6-K
AOAC@

9
9

PCIE_PTX_C_DRX_P4
PCIE_PTX_C_DRX_N4
9
9

PCIE_PRX_DTX_P4
PCIE_PRX_DTX_N4

8
8

CLK_PCIE_W LAN
CLK_PCIE_W LAN#
W LAN_CLKREQ_Q#

8,9,37,44
37,44

PCIE_W AKE#
R57

LAN_W AKE#

2 0_0402_5%

+3VS

+3VS_W LAN

T2

T3

R62
R63

1
1

@
@

2 0_0402_5%
2 0_0402_5%

SUSCLK_R
R55
PLT_RST#
BT_OFF#
R53
W LAN_OFF#
R56
SMB_DATA_S3_R R58
SMB_CLK_S3_R
R59
1
@ T4
EC_TX_R

2 0_0402_5%

1
1
1
1

@
@
@

2 1K_0402_5%
2 0_0402_5%
2 0_0402_5%
2 0_0402_5%

+3VS_W LAN

EC_TX_R
BT_OFF#

SUSCLK
8
PLT_RST#
8,19,37,44
PCH_BT_OFF#
9
PCH_W LAN_OFF#
9
SMB_DATA_S3
7,14,15
SMB_CLK_S3
7,14,15

77

W LAN_CLKREQ_Q#

EC_TX_R

R184

2 100_0402_1%

BT_OFF#

R185

2 100_0402_1%

EC_TX

44

EC_RX

44

R186
100K_0402_5%

en

EC_TX_RSVD
EC_RX_RSVD

2N7002KW _SOT323-3

R61

AOAC@ 3

W LAN_CLKREQ#

PEG2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74

JAE_SM3ZS067U410BAR1000
ME@

R60
10K_0402_5%
AOAC@

Q18

3.3VAUX1
3.3VAUX2
LED#1
NC
NC
NC
NC
LED#2
GND16
DP_AUXN
DP_AUXP
GND13
DP_ML1N
DP_ML1P
GND14
DP_ML0N
DP_ML0P
GND15
RESERVED1
RESERVED2
RESERVED3
COEX3
COEX2
COEX1
SUSCLK
PERST0#
RESERVED/W_DISABLE#2
W_DISABLE#1
I2C_DATA
I2C_CLK
I2C_ALERT#
RESERVED4
PERST1#
CLKREQ1#
PEWAKE1#
3.3VAUX4
3.3VAUX5

J2

Need short

+3VS

+3VS_W LAN

tia

2 0_0402_5%

on
fid

If support AOAC, NC R61;

if not support AOAC, stuff R61.

Issued Date

Title

LC Future Center Secret Data

Security Classification
2013/08/08

2013/08/05

Deciphered Date

NGFF WLAN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Thursday, December 26, 2013
Date:

Rev
1.0

ACLUA

PDF created with pdfFactory Pro trial version www.pdffactory.com

Sheet

40

of

59

U2

+5VALW

1
1

2
2.2U_0603_10V6-K
1
2
C58
44,45

3
USB_ON#

USB_ON#

GND

VOUT3

VIN1

VOUT2

VIN2

VOUT1

EN/EN

FLAG

C55

+USB_VCCA

+USB_VCCA

LEFT SIDE USB3.0 PORT X2

C56
@

C57
@

2
220U_6.3V_M
2
1U_0603_25V6M

8
7

2
470P_0402_50V7K

6
JUSB1

USB_OC1#

AP2820CMMTR-G1_MSOP8

Low Active 2A

USB_OC1#

9
9
9

C61
1000P_0402_50V7K
@

USB20_N2
USB20_P2

USB20_N2
USB20_P2

R65
R64

1
1

@
@

2 0_0402_5%
2 0_0402_5%

1
2
3
4

USB20_N2_R
USB20_P2_R

VBUS
DD+
GND

ME@

GND1
GND2
GND3
GND4

5
6
7
8

C-K_20267-5K11-02

tia

USB20_P2_R

+USB_VCCA

1
1

D11

AZ5425-01F_DFN1006P2E2

D10

AZ5425-01F_DFN1006P2E2

en

D9

AZ5425-01F_DFN1006P2E2

USB20_N2_R

USB20_P1_R

CMM21T-900M-N_4P

USB30_TX_R_N1 7

4 USB30_TX_R_N1

USB30_TX_R_P1 6

5 USB30_TX_R_P1

AZ1045-04F_DFN2510P10E-10-9

L9
USB30_RX_N1

USB30_RX_P1

1 USB30_RX_R_P1

USB30_TX_C_P1 2

USB30_TX_R_N1

USB30_TX_R_P1

L10

DLW21SN900HQ2L_4P

L11
USB20_N1

USB20_P1

USB20_N1_R

USB20_P1_R

D14

For EMC

4 USB30_RX_R_N1

DLW21SN900HQ2L_4P

USB30_TX_C_N1 3

D13

USB20_N2_R

USB20_N1_R

2 USB30_RX_R_P1

on
fid

USB30_RX_R_P1 8

@
1 1USB30_RX_R_N1

AZ5425-01F_DFN1006P2E2

D12
USB30_RX_R_N1 9 10

USB20_P2_R

USB20_N2

AZ5425-01F_DFN1006P2E2

L8
USB20_P2

9
9
9

CMM21T-900M-N_4P

+USB_VCCA
C62
@

2
1U_0603_25V6M

C63
@

2
470P_0402_50V7K

JUSB2
USB30_TX_P1
USB30_TX_N1
USB20_P1

USB20_N1
USB30_RX_P1

USB30_RX_N1

USB30_TX_P1 C64

2 .1U_0402_10V6-K

USB30_TX_C_P1 R68

2 0_0402_5%

USB30_TX_R_P1

USB30_TX_N1 C65
USB20_P1

2 .1U_0402_10V6-K

USB30_TX_C_N1 R69
R70

1
1

@
@

2 0_0402_5%
2 0_0402_5%

USB30_TX_R_N1
USB20_P1_R

USB20_N1
USB30_RX_P1

R71
R72

1
1

@
@

2 0_0402_5%
2 0_0402_5%

USB20_N1_R
USB30_RX_R_P1

USB30_RX_N1

R73

2 0_0402_5%

USB30_RX_R_N1

9
1
8
3
7
2
6
4
5

ME@

StdA_SSTX+
VBUS
StdA_SSTXD+
GND_DRAIN
DStdA_SSRX+
GND_5
StdA_SSRX-

GND_1
GND_2
GND_3
GND_4

10
11
12
13

SUYIN_020053GR009M2736L
4

For EMC

Issued Date

Title

LC Future Center Secret Data

Security Classification
2013/08/08

Deciphered Date

USB2.0/USB3.0 PORT (LEFT)

2013/08/05

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Size
Document Number
Custom
Date:

PDF created with pdfFactory Pro trial version www.pdffactory.com

Rev
1.0

ACLUA

Thursday, December 26, 2013

Sheet
E

41

of

59

SATA HDD Conn.

JHDD1

SATA_PRX_DTX_N0
SATA_PRX_DTX_P0

C66
C67

1
1

2 .01U_0402_16V7-K
2 .01U_0402_16V7-K

SATA_PTX_C_DRX_P0
SATA_PTX_C_DRX_N0

SATA_PRX_DTX_N0
SATA_PRX_DTX_P0

C68
C69

1
1

2 .01U_0402_16V7-K
2 .01U_0402_16V7-K

SATA_PRX_C_DTX_N0
SATA_PRX_C_DTX_P0

+5VS

J3

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

+5VS_HDD

Need short
1

1
2
3
4
5
6
7

JUMP_43X79

+5VS_HDD

C74
1000P_0402_50V7K
CD@

C75
.1U_0402_10V6-K

C76
1U_0402_10V6K
CD@

C77
10U_0805_10V6K

C78
10U_0805_10V6K
@

SATA ODD Conn.

GND_1
A+
AGND_2
BB+
GND_3

JODD1
7
7

V33_1
V33_2
V33_3
GND_4
GND_5
GND_6
V5_1
V5_2
V5_3
GND_7
DAS/DSS
GND_8
V12_1
V12_2
V12_3

7
7

SATA_PTX_DRX_P1
SATA_PTX_DRX_N1
SATA_PRX_DTX_N1
SATA_PRX_DTX_P1

SUYIN_127043HR022M32QZR

en
2

JUMP_43X79
+5VALW

+5VS

SATA_PTX_C_DRX_P1_14
SATA_PTX_C_DRX_N1_14

2 .01U_0402_16V7-K
2 .01U_0402_16V7-K

SATA_PRX_C_DTX_N1_14
SATA_PRX_C_DTX_P1_14

GND_1
RX+
RXGND_2
TXTX+
GND_3

8
9
10
11
12
13

DP
+5V_1
+5V_2
MD
GND_4
GND_5

GND1
GND2

14
15

FOR 15"

SATA ODD FFC Conn

15@ C79
15@ C80

1
1

2 .01U_0402_16V7-K
2 .01U_0402_16V7-K

SATA_PTX_C_DRX_P1_15
SATA_PTX_C_DRX_N1_15

SATA_PRX_DTX_N1
SATA_PRX_DTX_P1

15@ C81
15@ C82

1
1

2 .01U_0402_16V7-K
2 .01U_0402_16V7-K

SATA_PRX_C_DTX_N1_15
SATA_PRX_C_DTX_P1_15

R74

ODD_DETECT#

2 0_0402_5%

ODD_DETECT#_R

@
+5V_ODD
ODD_DA#_R

R92
0_0402_5%
@

1
2
3
4
5
6
7
8
9
10

11
12

1
2
3
4
5
6
7
8
9
10
GND_1
GND_2
ACES_51524-01001-003
ME@

+5V_ODD

+3VS

R77
10K_0402_5%
@

R79
470_0603_5%
@

C87
.01U_0402_16V7-K
@

C86

.1U_0402_10V6-K

C84

C83

10U_0805_10V6K

9
44

2
G

ODD_EN#

ODD_DA#
ODD_DA_EC#

R80

2 0_0402_5%

R86

2 0_0402_5%

ODD_DA#_R

Q21
2N7002KW_SOT323-3
@
S

@2

C139

R81
100K_0402_5%
@

CD@

100P_0402_50V8J

Q20
2N7002KW_SOT323-3
@

@2

ODD_EN

@2

2
1

2
G
2

@
1
2 R78
100K_0402_5%

.1U_0402_10V6-K

1
2

ODD_EN#

R76
10K_0402_5%
@

1 Q19
@

C85

.01U_0402_16V7-K

LP2301ALT1G_SOT23-3

R75
10K_0402_5%
@

JODD2
SATA_PTX_DRX_P1
SATA_PTX_DRX_N1

on
fid

2 .01U_0402_16V7-K
2 .01U_0402_16V7-K

1
1

1
2
3
4
5
6
7

SUYIN_127382FB013S255ZL
ME@

J4

1
1

14@ C72
14@ C73

+5V_ODD
ODD_DA#_R

For EMC

14@ C70
14@ C71

SATA_PRX_DTX_N1
SATA_PRX_DTX_P1

ODD_DETECT#_R

Need open

SATA_PTX_DRX_P1
SATA_PTX_DRX_N1

7
7

SATA_PTX_DRX_P0
SATA_PTX_DRX_N0

SATA_PTX_DRX_P0
SATA_PTX_DRX_N0

tia

7
7

FOR 14"

ME@

Issued Date

Title

LC Future Center Secret Data

Security Classification
2013/08/08

2013/08/05

Deciphered Date

HDD/ODD CONN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Thursday, December 26, 2013
Date:

Rev
1.0

ACLUA

PDF created with pdfFactory Pro trial version www.pdffactory.com

Sheet

42
H

of

59

+3VS

2 0_0603_5%

+3.3VD

RA8

+3VS

+5VA

2 0_0402_5%

RA3

2 0_0603_5%

RA5

2 0_0603_5%

RA43

+3VALW

2 0_0402_5%

DVDD_IO

@
RA7

2 0_0603_5%

+5VA

2 0_0603_5%

+5VD

CA1

@
RA10 1

.1U_0402_10V6-K

RA11
+5VS

AVDD_HP

+3VL

2 0_0603_5%

AVDD_HP

.1U_0402_10V6-K
CA12

+1.5VS
@
RA2

.1U_0402_10V6-K
CA11

+3VS

Close to Pin28 Close to Pin24

Close to Pin3

Close to Pin7

.1U_0402_10V6-K
1
2
CA13

JSENSE
+5VD

11

19
20

2 2.2U_0603_6.3V6K

21

+5VD

PORTB_R_LINE
PORTB_L_LINE

CLASS-D_REF

PORTD_A_MIC
PORTD_B_MIC

LPWR_5.0
RPWR_5.0

HGNDA
HGNDB

FLY_P
FLY_N

AVDD_HP

AVEE

PORTA_R
PORTA_L

GND

PORTD_A_MIC
PORTD_B_MIC

25
26

RING2_CONN
RING3_CONN

24

AVDD_HP

23
22

HPOUT_R
HPOUT_L

RB751V-40_SOD323-2
2 @
DA4 1

2 0_0402_5%

2 0_0402_5%

RA9

2 0_0402_5%

RA12

2 0_0402_5%

RA13

2 0_0402_5%

CA9
.1U_0402_10V6-K

LINE_B_L

2.2U_0603_6.3V6K
CA6
1U_0402_6.3V6K
CA10

CA5
.1U_0402_10V6-K

1U_0402_6.3V6K
CA8
CA35
4.7U_0603_10V6-K

CA36
4.7U_0603_10V6-K
RA20 1
RA21 1

2 82.5_0402_1%
2 82.5_0402_1%

HP_OUTR
HP_OUTL

45
45

RA22
PORTD_A_MIC
PORTD_B_MIC

1
1

2 100_0402_5%
2 100_0402_5%

CA20 1
CA21 1

2 2.2U_0603_6.3V6K
2 2.2U_0603_6.3V6K

RING3_CONN
RING2_CONN

45
45

RA23

JSPK1
15_0402_5%
15_0402_5%
15_0402_5%
15_0402_5%

HDA_SYNC_AUDIO

CD@
CD@
CD@
CD@

2
2
2
2

RA25
RA29
RA32
RA33

SPK_R+
SPK_RSPK_L+
SPK_L-

RA26
RA31
RA30
RA34

1
1
1
1

2
2
2
2

BLM18PG221SN1D_2P
BLM18PG221SN1D_2P
BLM18PG221SN1D_2P
BLM18PG221SN1D_2P

1
2
3
4

SPK_R+_CONN
SPK_R-_CONN
SPK_L+_CONN
SPK_L-_CONN

1
2
3
4

HDA_BITCLK_AUDIO

CA26

5
6

GND1
GND2
ACES_88231-04001
ME@

CD@ CD@ CD@ CD@

2
@

1
1
1
1

HDA_SDOUT_AUDIO

33P_0402_50V8J

CA25

CA24

2
@

CA23

33P_0402_50V8J

22P_0402_50V8-J

CA38

2
@

100P_0402_50V8J

100P_0402_50V8J

CA37

DMIC_DATA

CA22
22P_0402_50V8-J

68P_0402_50V8J

DMIC_CLK

RA40
100_0402_5%

HDA_RST_AUDIO#

HDA_SDIN0

GNDA

RA27 1
@
2
27_0402_5%

Use 250mils wide trace bridging

AGND and DGND at codec

2
RA35 1
0_0402_5%

470P_0402_50V7K

EC_MUTE#

470P_0402_50V7K
CA34

EC_MUTE#

RA6

GND

RA28
47K_0402_5%
@
SPKR_MUTE#

44

RA4

470P_0402_50V7K
CA33

RB751V-40_SOD323-2
2 @
DA3 1

2 0_0402_5%

220P_0402_50V7K
CA30

HDA_RST_AUDIO#

2
RA24 1
@
0_0402_5%

Close to Pin11,13,16

+3.3VD

Close to Pin29

RA39
100_0402_5%

Reserve DA2 to prevent

cross-talk between
HPOUT_R/L, if stuff DA2,
RA37/RA38 need change to
3K.

220P_0402_50V7K
CA29

CD@

RA1

220P_0402_50V7K
CA28

220P_0402_50V7K
CA27

CA19
.1U_0402_10V6-K

CA18
.1U_0402_10V6-K

CA16
4.7U_0603_10V6-K

CA15
4.7U_0603_10V6-K

CD@

LINE_B_R
LINE_B_L

RA41
0_0402_5%
@

LINE_B_R

33
32

30
31

CX20752-21Z_QFN40_5X5

RA42
0_0402_5%
@

MICBIASB

on
fid

41

35
34

RA38
3K_0402_1%

CA17 1

2 1U_0402_6.3V6K

SPK_R+
SPK_R-

RA37

CA14 1

MICBIASC
MICBIASB

17
15

DA2
BAT54AWT1G_SOT323-3

3K_0402_1%

13
16

1
2
20K_0402_1%

RA36

MUSIC_REQ/GPIO0/PORTC_L_MIC
DMIC_CLK/MUSIC_REQ/GPIO0
DMIC_DAT/GPIO1

SPK_L+
SPK_L-

36
40
1

DMIC_CLK_R
DMIC_DATA_R

RIGHT+
RIGHT-

12
14

CA31

1
2
39.2K_0402_1%

RA17

PLUG_IN

2
33_0402_5% 1 RA18
RA19
1
@
2
0_0402_5%

LEFT+
LEFT-

470P_0402_50V7K
CA32

45

DMIC_CLK
DMIC_DATA

+3.3VD

MICBIASB

CX20751-11Z

JSENSE
GPIO1/PORTC_R_MIC

AVDD_3.3
VREF_1.65V
+5VA

33
33

PC_BEEP
SPKR_MUTE#

27
29
28

38
37

JSENSE

RA15
5.11K_0402_1%

SDATA_IN
SDATA_OUT

AVDD_3.3
VREF_1.65V
AVDD_5V

10
39

SYNC

6
4

SDATA_IN

BIT_CLK

PC_BEEP
SPKR_MUTE#

2
C

7
HDA_SDIN0
HDA_SDOUT_AUDIO

HDA_SYNC_AUDIO
RA16
1
33_0402_5%
HDA_SDOUT_AUDIO

HDA_BITCLK_AUDIO

HDA_SYNC_AUDIO

Close to Pin27

HDA_BITCLK_AUDIO

FILT_1.8V
VDD_IO
VDDO_3.3
DVDD_3.3

RESET#

FILT_1.8V
DVDD_IO

HDA_RST_AUDIO#

3
7
2
18

+3.3VD

UA1
HDA_RST_AUDIO#

CA16 close to Pin18

CA17 close to Pin2

CD@ CA7
.1U_0402_10V6-K

1
RA14
10K_0402_5%

BAT54CW_SOT323-3

tia

PCH_BEEP

PC_BEEP

en

PC_BEEP1

.1U_0402_10V6-K
1
2
CA2

.1U_0402_10V6-K
CA3

BEEP#

CA4
4.7U_0603_10V6-K

DA1
44

For EMI

Issued Date

For EMI

Title

LC Future Center Secret Data

Security Classification
2013/08/08

2013/08/05

Deciphered Date

Codec_CX20752

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Thursday, December 26, 2013
Date:

Rev
1.0

ACLUA

PDF created with pdfFactory Pro trial version www.pdffactory.com

Sheet

43

of

59

For EMI

2 0_0402_5%

2 0_0402_5%
@

CE6
CD@

CE7

HCB1608KF-181T20
+3VALW _R

CE8

CE9

CE10

1
1

CE11
LE2 1

2
HCB1608KF-181T20

CE4
.1U_0402_10V6-K

EC_AGND 2

CE5
1000P_0402_50V7K

LE1

RE5
10K_0402_5%

@
EC_AGND

45

1 PAD

KSO[0..17]

KSO[0..17]

+3VALW _R

1 RE16

2 2.2K_0402_5%

1 RE17

2 2.2K_0402_5% EC_SMB_DA1

EC_SMB_CK1
EC_SMB_DA1

EC_SMB_CK1

+3VS

PAD
PAD
PAD
PAD
PAD

KSI7
KSI6
W RST#

1 RE20
1 RE22

2 2.2K_0402_5%

2 2.2K_0402_5% EC_SMB_DA2

@
IT1
@
IT2
@
IT3
@
IT4
@
IT5

@
IT6
@
IT7
@
IT8

For factory EC flash

52,53
52,53
2 43_0402_5%

RE24 1

H_PECI

1
1
1

EC_SMB_CK2

45
54

+3VL

37
7,19,39
7,19,39

110
111
115
116
117
118
94
95

ON/OFF

ON/OFF
EC_ON
EC_SMB_CK1
EC_SMB_DA1

EC_SMB_CK1
EC_SMB_DA1
PECI_EC

LAN_PW R_ON#
EC_SMB_CK2
EC_SMB_DA2

EC_SMB_CK2
EC_SMB_DA2

RE27
59

2 10K_0402_5% ON/OFF

RE36 1

2 10K_0402_5% BKOFF#

33
35
93

CK32KE/GPJ7
CK32K/GPJ6

74

GPIO

GPJ1
SSCE0#/GPG2
SSCE1#/GPG0
DSR0#/GPG6
DTR1#/SBUSY/GPG1/ID7
CRX0/GPC0
CTX0/TMA0/GPB2
RI1#/GPD0
RI2#/GPD1
TACH2/GPJ0
TACH1A/TMA1/GPD7
TACH0A/GPD6
L80HLAT/BAO/GPE0
L80LLAT/GPE7

GPIO

ENBKL

TP_CLK
TP_DATA

8
52
RE14

33

VGA_GATE#

77
100
106
104
107
119
123
18
21
76
48
47
19
20

2 0_0402_5%

PROCHOT#

LID_SW #

+5VALW

55
53
0_0402_5% 2

RE25 2

RE26

EC_ADAPTER

SUSP#

RE18 1

SUSP#

RE19 1

2 100K_0402_5%

SYSON

RE21 1

2 100K_0402_5%

SUS_VCCP

RE23 1

EC_ADAPTER_R

RE28 1

1 0_0402_5%

NUM_LED#

51
8
7

SYSON

RE29 1

2 0_0402_5%

AOAC_ON#

40

EMC Request

PCIE_W AKE#

8,9,37,40

39
RE30 1

2 0_0402_5% VGA_AC_DET

VGA_AC_DET

19

ODD_DA_EC#

42

RE34

VR_HOT#

2 0_0402_5%

H_PROCHOT#

@
D

2
G

2N7002KW _SOT323-3

5,51,52

+5VS +3VS

CE14
47P_0402_50V8J
@

1 10K_0402_5%

SPI_CS0#

RE47 2

EC_SPI_SO

RE48 2

1 0_0402_5%

SPI_SI

1 0_0402_5%

SPI_SO

SPI_SI

SPI_SO

EC_SPI_CLK

RE49 2

@2

1 0_0402_5%

SPI_CLK

SPI_CLK

BATT_TEMP @ CE16

2 100P_0402_50V8J

ACIN#

2 100P_0402_50V8J

@ CE17
@ CE18

2 1U_0402_6.3V6K

+3VS

Issued Date

ACIN#

ACIN#

PDF created with pdfFactory Pro trial version www.pdffactory.com

1
2
3
4
5
6

1
2
3
4
GND1
GND2
ACES_85205-04001
ME@

2013/08/08

ACIN

53

2N7002KW _SOT323-3 S

Deciphered Date

Title

EC ITE8586LQFP

2013/08/05

Date:
4

J80P1

2 0_0402_5%

QE2

CE19
.1U_0402_10V6-K

LC Future Center Secret Data

Security Classification

8,53

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5

2 0_0402_5%

RE42
10K_0402_5%

@
EC_SPI_SI

2
2 47P_0402_50V8J

7
C48

SPI_CS0#

RE39 1

RE41
100K_0402_5%
@

1
1

@ CE15

.01U_0402_16V7-K

RE46 2

when mirror, GPG2 pull high

when no mirror, GPG2 pull low

1 0_0402_5%

RE37 1

EC_TX
EC_RX
+3VL

ON/OFF
RE45 2

CE13
.1U_0402_10V6-K

Reserve for VGA_AC_DET

NOVO#

@
EC_SPI_CS0#

1
@

45

QE1

1 10K_0402_5%
1 10K_0402_5%

2 100K_0402_5%

2 100K_0402_5%
@

PM_SLP_S5#
ME_FLASH

55
33

PM_SLP_S3#
8
PM_SLP_S4#
8
NOVO#
45
EC_TS_ON#
33
EC_FAN_SPEED

H_PROCHOT#_EC

+3VALW _R

RE44 2

2 100K_0402_5%

Change RE30 to 0ohm jump

59

+3VL

RE43 2

Clock

PECI_EC

GPG2

2 100K_0402_5%

+3VALW _R

2 10K_0402_5% BKOFF#

GPG2

RE15 1

46,52
8,10

for EC version update to EX, manual modify PN to FX

GPG2

1 4.7K_0402_5%

43

SYSON
BKOFF#

EC_FAN_SPEED

1 4.7K_0402_5%

RE13 2

52

45

EC_MUTE#

SYSON
BKOFF#

RE12 2

TP_DATA

45

VGA_GATE#
4
VDDQ_PGOOD
ADAPTER_ID_ON#

GPG2
EC_ADAPTER_R

RE51
0_0402_5%

TP_CLK

USB_ON#

EC_AGND

2 100K_0402_5%

RE52
0_0402_5%
@

EC_SPI_CS0#
EC_SPI_SI
EC_SPI_SO
EC_SPI_CLK

82
83
84

2 10K_0402_5%

Change RE14 to 0ohm jump

CAPS_LED#
PCH_PW R_EN
ACOFF
53
PCH_PW ROK

ACIN#
LID_SW #

2 10K_0402_5%

+5VS +3VS

VGA_PW RGD
9,22
PBTN_OUT#
8
PM_SLP_SUS#
8
SUSACK#
8
TP_CLK
45
TP_DATA
45

108
109

35,46,55,56,57

SUSW ARN#
MAINPW ON

H_PROCHOT#_EC

101
102
103
105

26
50
92
114
121
127
VSTBY1
VSTBY2
VSTBY3
VSTBY4
VSTBY5
VSTBY(PLL)

AVCC

96
97
98
99

RE9

NTC_V
52
TURBO_V
52
BATT_TEMP
52,53
VR_IMVP_IMON
59
VR_CPU_PW ROK
10,59
ADP_I
52,53
ADAPTER_ID
51,53

BATT_TEMP

78
79
80
81
85
86
87
88
89
90

SUSP#

RE7

ENBKL

RE40 1

EGAD/GPE1
EGCS#/GPE2
EGCLK/GPE3

Bus

2 10K_0402_5% LID_SW #

AC_IN#
LID_SW#

UART

IT8586E-AX_LQFP128_14X14

RE38 1

GPH3/ID3
GPH4/ID4
GPH5/ID5
GPH6/ID6
NC1
NC2
NC3
NC4

SPI Flash ROM

WAKE UP

GINT/CTS0#/GPD5
RTS1#/GPE5
CLKRUN#/GPH0/ID0

2
128

EC_LID_OUT#
AC_PRESENT

EXTERNAL SERIAL FLASH

VSS1

RE35 1

VSTBY0
GPE4

DAC2/TACH0B/GPJ2
DAC3/TACH1B/GPJ3
DAC4/DCD0#/GPJ4
DAC5/RIG0#/GPJ5

PS2CLK0/TMB0/CEC/GPF0
PS2DAT0/TMB1/GPF1
GPF2
PS2
GPF3
PS2CLK2/GPF4
PS2DAT2/GPF5

+3VL

112
125

USB_ON#

41,45
USB_ON#
8
DPW ROK_EC
8
EC_RSMRST#
9
8

2 0_0402_5%

EC_VR_ON

DAC

PWRSW#
SM
XLP_OUT
SMCLK1/GPC1
SMDAT1/GPC2
SMCLK2/PECI/GPF6
SMDAT2/PECIRQT#/GPF7
CRX1/SIN1/SMCLK3/GPH1/ID1
CTX1/SOUT1/GPH2/SMDAT3/ID2

@
B

11

12

KSI0/STB#
KSI1/AFD#
KSI2/INIT#
KSI3/SLIN#
KSI4
KSI5
KSI6
KSI7
KSO0/PD0
Int. K/B
KSO1/PD1
Matrix
KSO2/PD2
KSO3/PD3
KSO4/PD4
KSO5/PD5
KSO6/PD6
KSO7/PD7
KSO8/ACK#
KSO9/BUSY
KSO10/PE
KSO11/ERR#
KSO12/SLCT
KSO13
KSO14
KSO15
KSO16/SMOSI/GPC3
KSO17/SMISO/GPC5

66
67
68
69
70
71
72
73

RE11 1

LPC_FRAME#

PAD
PAD
PAD

1
1
1
1
1

ADC

IT8586E/AX
LQFP-128L

58
59
60
61
62
63
64
65
36
37
38
39
40
41
42
43
44
45
46
51
52
53
54
55
56
57

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

ADC0/GPI0
ADC1/GPI1
ADC2/GPI2
ADC3/GPI3
ADC4/GPI4
ADC5/DCD1#/GPI5
ADC6/DSR1#/GPI6
ADC7/CTS1#/GPI7

SUS_VCCP
LAN_W AKE#
SUSP#

EC_FAN_PW M

10K_0402_5%

EC_RX
EC_TX
PLT_RST#

KSI[0..7]

KSI[0..7]
45

EC_SMI#
EC_RX
EC_TX
PLT_RST#
EC_SCI#
@
IT9

EC_FAN_PW M

9
40
40
CE12
1U_0402_6.3V6K8,19,37,40
9
2

LPC

PW R_LED#
45
BATT_CHG_LED#
45
BATT_LOW _LED#
45
BATT_LEN#
52
SYS_PW ROK
8
EC_FAN_PW M
39
BEEP#
43
SUS_VCCP
57

RE10 1

2 100K_0402_5%

PWM

24
25
28
29
30
31
32
34
120
124

tia

PWM0/GPA0
PWM1/GPA1
PWM2/GPA2
PWM3/GPA3
PWM4/GPA4
PWM5/GPA5
PWM6/SSCK/GPA6
PWM7/RIG1#/GPA7
TMRI0/GPC4
TMRI1/GPC6

RE8

CLK_PCI_EC
W RST#

KBRST#/GPB6
SERIRQ/GPM6
LFRAME#/GPM5
LAD3/GPM3
LAD2/GPM2
LAD1/GPM1
LAD0/GPM0
LPCCLK/GPM4
WRST#
ECSMI#/GPD4
PWUREQ#/BBO/SMCLK2ALT/GPC7
LPCPD#/GPE6
LPCRST#/GPD2
ECSCI#/GPD3
GA20/GPB5

RB751V-40_SOD323-2

4
5
6
7
8
9
10
13
14
15
16
17
22
23
126

LPC_FRAME#

en

KBRST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
CLK_PCI_EC

on
fid

7
7
7
7
7
8

VSS2
VSS3
VSS4
VSS5
VSS6

27
49
91
113
122

DE1

37,40

+3VS
EC_FAN_SPEED

AVSS

9
9

+3VALW _R

LAN_W AKE#

minimum trace width 12 mil

75

W RST#

VCC

VBAT
19

VCORE

UE1

LAN_W AKE#

Change RE6 to 0ohm jump

RE4 1
RE6

All capacitors close to EC

+3VALW _R

+3VALW _EC

+3VS
VCCRTC

+3VALW _EC

+3VALW _R

VCOREVCC

.1U_0402_10V6-K

+3VALW
+3VALW _R

CE3
1

2 0_0603_5%

.1U_0402_10V6-K

CE2
10P_0402_50V8J
@

RE3 1

.1U_0402_10V6-K

CE1
220P_0402_50V7K

+3VL

Close EC

2 10_0402_5%

.1U_0402_10V6-K

RE2

.1U_0402_10V6-K

CLK_PCI_EC

.1U_0402_10V6-K

PLT_RST#

2 0_0603_5%

.1U_0402_10V6-K

For ESD

RE1

Document Number

Rev
1.0

ACLUA
Tuesday, December 31, 2013
1

Sheet

44

of

59

ON/OFF switch
+3VL

K/B Connector

+3VALW

14"

+3VS

15"

KSO[0..17]

D15
44

PWR_CAPS_LED C133

2 @

100P_0402_50V8J

PWR_NUM_LED

C134

2 @

100P_0402_50V8J

KSO16

C91

2 @

100P_0402_50V8J

JKB2

NOVO#

NOVO#

44

CAPS_LED# C117
1
R85

2 0_0402_5%

100P_0402_50V8J

44

NOVO_BTN#

@
ON/OFF

2 @

NUM_LED#

C118

2 @

100P_0402_50V8J

KSO17

C88

2 @

100P_0402_50V8J

KSO2

C89

2 @

100P_0402_50V8J

KSO1

C90

2 @

100P_0402_50V8J

CAPS_LED#
PWR_CAPS_LED
KSO15
KSO10
KSO11
KSO14
KSO13
KSO12
KSO3
KSO6
KSO8
KSO7
KSO4
KSO2
KSI0
KSO1
KSO5
KSI3
KSI2
KSO0
KSI5
KSI4
KSO9
KSI6
KSI7
KSI1

CAPS_LED#

BAT54CW_SOT323-3

+3VL

+3VALW

@
R119 1

ON/OFFBTN#
J5 1

R114
100K_0402_5%
1

R111
100K_0402_5%
@
2 0_0402_5%

ON/OFF

ON/OFF

44

KSO15

C92

2 @

100P_0402_50V8J

KSO7

C93

2 @

100P_0402_50V8J

KSO6

C94

2 @

100P_0402_50V8J

KSI2

C95

2 @

100P_0402_50V8J

KSO8

C96

2 @

100P_0402_50V8J

KSO5

C97

2 @

100P_0402_50V8J

KSO13

C98

2 @

100P_0402_50V8J

KSI3

C99

2 @

100P_0402_50V8J

KSO12

C100

2 @

100P_0402_50V8J

KSO14

C101

2 @

100P_0402_50V8J

KSO11

C102

2 @

100P_0402_50V8J

KSI7

C103

2 @

100P_0402_50V8J

KSO10

C104

2 @

100P_0402_50V8J

KSI6

C105

2 @

100P_0402_50V8J

KSO3

C106

2 @

100P_0402_50V8J

KSI5

C107

2 @

100P_0402_50V8J

2
KSO4

C108

2 @

100P_0402_50V8J

KSI4

C109

2 @

100P_0402_50V8J

KSI0

C110

2 @

100P_0402_50V8J

KSO9

C111

2 @

100P_0402_50V8J

SHORT PADS
J6 1

2
KSO0

C112

2 @

100P_0402_50V8J

KSI1

C113

2 @

26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

100P_0402_50V8J

SHORT PADS

PWR/B Connector

TP_P5
TP_P6

LED1

+5VALW

R143 1

2 470_0402_5%

+3VALW

2 14@

LTST-C193KFKT-LC

LED5

D19

LED3

2 14@

LTW-C193TS5

BATT_CHG_LED#

AZ5425-01F_DFN1006P2E2

2 15@

LTST-C193KFKT-LC

2 1.5K_0402_5%

+5VALW

NUM_LED#

30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

NUM_LED#
PWR_NUM_LED
CAPS_LED#
PWR_CAPS_LED
KSO17
KSO16
KSO15
KSO10
KSO11
KSO14
KSO13
KSO12
KSO3
KSO6
KSO8
KSO7
KSO4
KSO2
KSI0
KSO1
KSO5
KSI3
KSI2
KSO0
KSI5
KSI4
KSO9
KSI6
KSI7
KSI1

30 GND1
29 GND2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

31
32

KSO1_15

KB_6 KSI5_14

KSI0_15

KB_7 KSO0_14

KSO2_15

KB_8 KSI2_14

KSO4_15

KB_9 KSI3_14

KSO7_15

KB_10 KSO5_14

KSO8_15

KB_11 KSO1_14

KSO6_15

KB_12 KSI0_14

KSO3_15

KB_13 KSO2_14

KSO12_15

KB_14 KSO4_14

KSO13_15

KB_15 KSO7_14

KSO14_15

KB_16 KSO8_14

KSO11_14

KB_17 KSO6_14

KSO10_15

KB_18 KSO3_14

KSO15_15

KB_19 KSO12_14

KSO16_15

KB_20 KSO13_14

KSO17_15

KB_21 KSO14_14

KB_LED_PWR_15

KB_22 KSO11_14

CAPS_LED#_15

KB_23 KSO10_14

VDD_15

KB_24 KSO15_14

NUM_LED#_15

LID_SW#

DT5

2
3

en

1
1
2
2

AZ5215-01F_DFN1006P2E2

1
1
2

2.2U_0603_10V6-K
1
2
C119

GND1
GND2

7
8

41,44

USB_ON#

USB_ON#

+USB_VCCB

U3

+USB_VCCB

GND
VIN1

VOUT2

VIN2

VOUT1

EN/EN

VOUT3

JUSB3

+3VS
7
@
6
5

FLAG

9
9

USB_OC2#
1

AP2820CMMTR-G1_MSOP8

Low Active 2A

USB_OC2#

R67
R66

USB20_P0
USB20_N0
9
9

43
43

2 0_0402_5% USB20_P0_CONN
2 0_0402_5% USB20_N0_CONN
@

C120
1000P_0402_50V7K
@

1
1

USB20_P3
USB20_N3

HP_OUTR
HP_OUTL

44

43

RING2_CONN

43
43

RING3_CONN
PLUG_IN

USB20_P3
USB20_N3

HP_OUTR
HP_OUTL
RING2_CONN
RING3_CONN
PLUG_IN

18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

18 G2
17 G1
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

20
19

ACES_50505-0184N-P01
ME@

L14
USB20_P0

USB20_N0

USB20_P0_CONN

USB20_N0_CONN

CMM21T-900M-N_4P

2 15@

Title

LC Future Center Secret Data

Security Classification

LTW-C193TS5

Issued Date

2013/08/08

Deciphered Date

2013/08/05

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

KBD/PWR/IO/LED/TP Conn.
Size Document Number
Custom
Date:

KSO5_15

KB_5 KSI4_14

USB I/O Connector

TP_P6

1
2
3
4
5
6

ACES_50503-0060N-001
ME@

LED6

R144 1

For EMC

EVQPLHA15_4P

2 15@

LED2

5
EVQPLHA15_4P

1
A

A1

GND1
GND2

B1

1
2 1.5K_0402_5%

1
2
D18

BATT_CHG_LED#

R142 1

LTW-C193TS5

BATT_LOW_LED#

AZ5425-01F_DFN1006P2E2

44

2 14@

LTW-C193TS5

LED4
@

BATT_LOW_LED#

For 15"

1
2
3
4
5
6

on
fid

PWR_LED#
D16

44

44

PWR_LED#

AZ5425-01F_DFN1006P2E2

44

For 14"

LED

A1

1
1

15@
@

GND1

1
1
2
2

A1

GND1
GND2

B1

EVQPLHA15_4P

A1

GND1

A
3

14@

SW4
DT4

GND2

TP-R

DT3

TP_RIGHT Button

B1

TP-R

15@

TP_P5
D17

DT2

TP-L

SW2

TP_P6

GND2

TP-L

B1

SW3

EVQPLHA15_4P

GND

DAT

GND

+5VALW

NOVO_BTN#
ON/OFFBTN#
LID_SW#

TP_LEFT Button

AZ5215-01F_DFN1006P2E2

+3VL

AZC199-02S.R7G_SOT23-3

JPWRB1

TP_P5

TP_RIGHT Button

AZ5215-01F_DFN1006P2E2

DAT

CLK

CLK

1
A
3

14@

VDD

For 15"

VDD

AZ5215-01F_DFN1006P2E2

AZ5215-01F_DFN1006P2E2

For 14"

KSI3_15

KB_4 KSO9_14

Right Side USB2.0 Port X 1 (USB/B)

7
8

For EMC

TP_LEFT Button

SW1

GND1
GND2

ACES_50503-0060N-001
ME@

C116

@1

100P_0402_50V8J

C115

100P_0402_50V8J

TP_P4
@1

1
2
3
4
5
6

DT1

TP_CLK
TP_DATA

TP_CLK
TP_DATA

C114

.1U_0402_10V6-K

44
44
1

KSI2_15

KB_3 KSI6_14

TP_CLK
TP_DATA
JTP1
1
2
3
4
5
6

tia

TP_PWR

KSO0_15

KB_2 KSI7_14

JKB1

For EMC

2
R160 1
@
0_0402_5%
2
R141 1
0_0402_5%

R90
300_0402_5%

ACES_50504-3041-001
ME@

+5VS
+3VS

R84
300_0402_5%
27
28

GND1
GND2
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

15"

ACES_88514-02601-071
ME@

TP/B Connector

KSO[0..17]

14"

44

KSI[0..7]

R83
100K_0402_5%

KB_1 KSI1_14
KSI[0..7]

R82
100K_0402_5%

PDF created with pdfFactory Pro trial version www.pdffactory.com

Rev
1.0

ACLUA

Thursday, December 26, 2013

Sheet

45

of

59

+5VALW to +5VS
AP4800BGM
VGS=10V, ID=9A, Rds=18m ohm
VGS=+-25V

+5VALW

AP4800BGM
VGS=10V, ID=9A, Rds=18m ohm
VGS=+-25V

+3VALW

+5VS

+3VS

R148

Q26
SUSP

3VS_GATE_R
D

1 R150
2
0_0402_5%

2
G

1
S 2N7002KW_SOT323-3

C128
0.01U_0402_25V7K

2 R147
1
0_0402_5%

5VS_GATE

2 R151
1
0_0402_5%
@

3VS_GATE
D

5VS_GATE

2
R152 1
@ 470K_0402_5%

35
+20VSB

Q27

Q28

R154
820K_0402_5%
@

SUSP

G
S

R146
470_0603_5%

2N7002KW_SOT323-3
@

S 2N7002KW_SOT323-3

tia

C126
1U_0603_25V6M
2 CD@

2
G

2N7002KW_SOT323-3

1
S

D Q25

R153
820K_0402_5%
@

C127
0.01U_0402_25V7K

AP4800BGM-HF_SO-8

C123
10U_0603_6.3V6M
2 CD@

+20VSB

2 R149
1
150K_0402_5%

5VS_GATE

1
1

1
2
82K_0402_1%

5VS_GATE_R

1
2
3

R145
470_0603_5%

C125
10U_0805_25V6K
@

C122
1U_0603_25V6M
2 CD@

AP4800BGM-HF_SO-8

8
7
6
5

1
C121
10U_0805_10V6K
CD@

1
2
3

8
7
6
5

C124
10U_0805_25V6K
@

Q24

Q23

+3VALW to +3VS

+3VALW_PCH

Q29

Id=3.2A

C130
0.01U_0402_25V7K
@

34

+0.675VS

R159
47_0603_5%

Q6B

SUSP#

5
G

2N7002KDWH_SOT363-6

SUSP

G
S

S 2N7002KDWH_SOT363-6

C131
.1U_0402_10V6-K
@

1
Q6A

35,44,55,56,57

PCH_PWR_EN#_R

R157
100K_0402_5%
@

SUSP

SUSP

on
fid

R162
100K_0402_5%

C129
.1U_0402_10V6-K
@

S 2N7002KW_SOT323-3

PCH_PWR_EN

44,52

LP2301ALT1G_SOT23-3
Q30

PCH_PWR_EN

R156
100K_0402_5%

JUMP_43X79

PCH_PWR_EN#

2 100K_0402_5%

+5VALW

R158 1

+5VLP

PCH_PWR_EN#_R

en

R155
100K_0402_5%
@

J7

Need short

+3VALW
2

+5VALW

Issued Date

Title

LC Future Center Secret Data

Security Classification
2013/08/08

2013/08/05

Deciphered Date

DC V TO VS INTERFACE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Thursday, December 26, 2013
Date:

Rev
1.0

ACLUA

PDF created with pdfFactory Pro trial version www.pdffactory.com

Sheet

46

of

59

3
DPWROK_EC

B1
PCH_RSMRST#

A3

B4

PM_SLP_S3#
PM_SLP_S4#
PM_SLP_S5#
PM_SLP_SUS#
12

PCH_PWROK

13

NOVO

VR_REDY

SYSON

on
fid

11

SYS_PWROK

ON/OFF

PCH

en

B3

14
PM_DRAM_PWRGD

NVDD_PWR_EN
Vb

(DIS)

Q31
+5VS
Q32
+3VS

+VGA_CORE
PU801

+1.5VS_VGA
PU601

+1.05VSP_VGA
PU702

PU602
+1.5VS

Va (DIS)

+3VS_VGA
Q27

VGA

PU502
+0.675V

PU701
+1.05VS

SUS_VCCP

16

CPU

DGPU_PWROK

SUSP#,SUSP

15

DGPU_PWR_EN

VR_ON

CPU_PLTRST#

+1.35V
PU501

10

PU901
+CPU_CORE

H_CPUPWRGD

tia

EC_ON

PBTN_OUT#

EC

+3V_PCH

+3VALW

BATT

B5

V V

PU904

A4
B+

Q25,+3V_PCH

V V

BATT
MODE

A2

PU301

V V

VIN

PCH_PWR_EN#

A1

AC
MODE

A2
+3VLP

V V V

B2
D

Issued Date

Title

LC Future Center Secret Data

Security Classification
2013/08/08

2013/08/05

Deciphered Date

Power sequence Block

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Thursday, December 26, 2013
Date:

Rev
1.0

ACLUA

PDF created with pdfFactory Pro trial version www.pdffactory.com

Sheet

47

of

59

LAN chip
UL1

Transformer
100M@

TL1

RTL8106EUL-CG

100M@

ZZZ2

TST1284A LF

SA000060Q00

X76 BOM
H4GX8T@

ZZZ3 M4GX8T@

Hynix

SP050008C00

ZZZ4 H2GX4T@

Micron

X7603212001

X7603212002

Hynix

X7603212003

ZZZ5 H2GX4M@

ZZZ6 M2GX4M@

Hynix

ZZZ7 M2GX4T@

Micron

X7603212051

ZZZ8 S4GX8T@

Micron

X7603212052

Samsung

X7603212004

ZZZ9 S2GX4T@

ZZZ10

Samsung

X7603212054

14@

ZZZ11

PCB PN

X7603212053

15@

PCB PN

DAZ0TY00100

DAZ0TZ00100

PCB_MB

UV1

N15VGM@

RV155

NV N15V-GM GPU

UV6

UV7

H4T@

UV8

H4T@

RC100

H5TC4G63AFR-11C

H5TC4G63AFR-11C

H5TC4G63AFR-11C

SA00005YL00

SA00005YL00

SA00005YL00

SD02810028J

UV9

UV10

UV11

UV12

RV159

H5TC4G63AFR-11C

SA00005YL00

H4T@

H5TC4G63AFR-11C
SA00005YL00

H4T@

H5TC4G63AFR-11C

SA00005YL00

H2M@

H4T@

X7603212002

UV5

M4T@

UV6

UV6

H5TC4G63AFR-11C

H5TC4G63AFR-11C

20K_0402_1%

SA00005YL00

M4T@

UV8

SD03420028J

M4T@

RC100

H5TC4G63AFR-11C

SA00005YL00

RV151

RV152

10K_0402_1%

MT41J256M16HA-093G:E

MT41J256M16HA-093G:E

10K_0402_5%

SA000060I10

SA000060I10

SA000060I10

SD02810028J

UV9

UV10

UV11

UV12

RV159

10K_0402_1%
SD03410028J

M2M@

M4T@

M4T@

M4T@

RV146

MT41J256M16HA-093G:E

MT41J256M16HA-093G:E

SA000060I10

SA000060I10

MT41J256M16HA-093G:E

MT41J256M16HA-093G:E

SA000060I10

24.9K_0402_1%

SA000060I10

SD03424928J

M2M@

10K_0402_1%

UV5

H2T@

H5TC4G63AFR-11C

SA00005YL00

UV6

on
fid

SD03410028J

Hynix 2G---256X16 *4 pcs

X7603212003
H2T@

H5TC4G63AFR-11C
SA00005YL00

UV7

H2T@

UV8

H5TC4G63AFR-11C

SA00005YL00

H2T@

RC107

H5TC4G63AFR-11C

H2T@

10K_0402_5%

SA00005YL00

SD02810028J
RV159

H2T@

20K_0402_1%
SD03420028J

K4W4G1646D-BC1A

S4T@

K4W4G1646D-BC1A

UV7

S4T@

K4W4G1646D-BC1A

UV8

S4T@

SA000063F10

SA000063F10

SA000063F10

UV9

UV10

UV11

UV12

K4W4G1646D-BC1A

S4T@

K4W4G1646D-BC1A

SA000063F10

SA000063F10

S4T@

K4W4G1646D-BC1A

SA000063F10

RC100

K4W4G1646D-BC1A

SA000063F10

S4T@

RC107

H5TC4G63AFR-11C

S2T@

UV6

S2T@

UV7

S2T@

UV7

MT41J256M16HA-093G:E
SA000060I10

RV148

M2M@

10K_0402_1%
SD03410028J

M2M@

MT41J256M16HA-093G:E

SA000060I10

RV149

M2M@

RV152

10K_0402_1%

MT41J256M16HA-093G:E
SA000060I10

UV7

UV8

M2M@

RC107

MT41J256M16HA-093G:E

M2M@

10K_0402_5%

SA000060I10

SD02810028J

M2M@

10K_0402_1%

SD03410028J

M2T@

UV6

SD03410028J

SD03410028J

M2T@

UV8

MT41J256M16HA-093G:E

SA000060I10

M2T@

MT41J256M16HA-093G:E
SA000060I10

RC107

M2T@

10K_0402_5%
SD02810028J
RV159

M2T@

S4T@

24.9K_0402_1%
SD03424928J

10K_0402_5%
SD02810028J

S4T@

RV159

K4W4G1646D-BC1A

S4T@

PR9440

PR9434

PR9436

27K_0402_1%
N15VGM@

7.5K_0402_1%
N15VGM@

0_0402_5%
N15VGM@

30.1K_0402_1%

SA000063F10

UV8

10K_0402_5%
SD02810028J

10K_0402_1%

SD03430128J

Samsung 2G---256X16 *4 pcs X7603212053

UV5

H2M@

H2M@

UV6

M2M@

X7603212004

MT41J256M16HA-093G:E

S4T@

H2M@

SA00005YL00
RV154

SD03410028J

UV5

M2T@

H2M@

10K_0402_1%

Micron 2G---256X16 *4 pcs

SA000060I10

Samsung 4G---256X16 *8 pcs X7603212054

UV5

SD03410028J

X7603212052

UV6

MT41J256M16HA-093G:E
SA000060I10

M4T@

H2M@

en

MT41J256M16HA-093G:E

UV8

H5TC4G63AFR-11C

SA00005YL00

H2M@

M4T@

SA000060I10

M4T@

H2M@

RV148

UV5

MT41J256M16HA-093G:E

UV7

SA00005YL00

Micron 2G---256X16 *4 pcs

UV7

10K_0402_1%

X7603212051
H2M@

M4T@

SD03410028J

N15VGM@

H4T@

SD03410028J

Micron 4G---256X16 *8 pcs

10K_0402_1%

SD03410028J

RV161

10K_0402_5%

SA00005YL00

H4T@

N15VGM@

H4T@
UV5

H5TC4G63AFR-11C

10K_0402_1%

SD03410028J

Hynix 2G---256X16 *4 pcs

X7603212001
H4T@

RV160

H4T@

N15VGM@

tia

UV5

RV159

10K_0402_1%

SA000064R00

Hynix 4G---256X16 *8 pcs

N15VGM@

S2T@

RC107

PR9437

PR9431

PC1277

6.2K_0402_1%
N15VGM@

1.74K_0402_1%
N15VGM@

5600P_0402_25V7-K
N15VGM@

S2T@

K4W4G1646D-BC1A

K4W4G1646D-BC1A

SA000063F10

SA000063F10

K4W4G1646D-BC1A

SA000063F10

K4W4G1646D-BC1A

10K_0402_5%

SA000063F10

SD02810028J
RV159

S2T@

Issued Date
30.1K_0402_1%

Title

LC Future Center Secret Data

Security Classification
2013/08/08

Deciphered Date

Virtual symbol

2013/08/05

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

SD03430128J

Date:
5

PDF created with pdfFactory Pro trial version www.pdffactory.com

Document Number

Rev
1.0

ACLUA
Tuesday, December 31, 2013
1

Sheet

48

of

59

NH3
HOLEA

PCB Fedical Mark PAD

NH4
HOLEA

FD2

FD5

FD6

Pad_ct8p0b9p0d2p8

pad_shapet8p8x8p0cb9p0d2p8

pad_shapet8p8x8p0cb9p0d2p8

PAD_CT6P5B5P0D4P0

PAD_CT6P5B5P0D4P0

PAD_CT6P5B5P0D4P0

H12
HOLEA

PAD_CT6P5B5P0D4P0

H11
HOLEA

H10
HOLEA

H9
HOLEA

H8
HOLEA

H7
HOLEA

pad_ct6p0d4p3

Pad_ct6p0b8p0d4p6

tia

Pad_ct8p0b9p0d2p8

H6
HOLEA

H5
HOLEA

H4
HOLEA

PAD_SHAPET5P0X6P0B7P0D2P3

H3
HOLEA

pad_SHT7P0X7P05BR10P65X10P3D2P8

FD4

pad_o2p3x2p8d2p3x2p8n

H2
HOLEA

H1
HOLEA

pad_o2p3x2p8d2p3x2p8n

pad_c2p3d2p3n

pad_c2p3d2p3n

FD3

FD1
D

NH2
HOLEA

NH1
HOLEA

PAD_ShapeT5P0X6P0-D

GP12
PAD_RT2P45X2P5
@

GP11
PAD_RT2P45X2P5
@
1

GP10
PAD_RT2P21X2P99
@
1

GP9
PAD_RT2P21X2P99
@

H21
HOLEA

H23
HOLEA

H22
HOLEA

H20
HOLEA

CHASSIS1_GND
pad_ct5p5b6p0d3p3

GP8
PAD_RT2P65X2P2
@

GP7
PAD_RT2P65X2P2
@

GP6
PAD_RT2P65X2P2
@

GP5
PAD_RT2P65X2P2
@

GP4
PAD_RT2P65X2P2
@

GP3
PAD_RT2P65X2P2
@

GP2
PAD_RT2P65X2P2
@

GP1
PAD_RT2P65X2P2
@

PAD_shapeT5P0X6P0-U

on
fid

pad_ct6p0b7p0d2p3 pad_shapet6p8x8p0cb8p0d2p5

en

H19
HOLEA

H18
HOLEA

PAD_CT6P0shapeb10p04x10p0d2p8

H17
HOLEA

pad_ct6p0shapeb8p0x6p75d2p3

H16
HOLEA

pad_cb8p0d7p0

H15
HOLEA

H14
HOLEA

H13
HOLEA

pad_ct3p8b6p0d3p3 pad_ct5p5b6p0d3p3
pad_ct5p5b8p0d2p5

+VGA_CORE

+5VALW

+3VS

+3VALW

C137
1

C135
.1U_0402_10V6-K
@
2

1
@

2 .1U_0402_10V6-K

C136
.1U_0402_10V6-K
@

FFC CONN GROUND PAD

For EMC

Issued Date

Title

LC Future Center Secret Data

Security Classification
2013/08/08

Deciphered Date

Hole

2013/08/05

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize
B
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Date:
5

PDF created with pdfFactory Pro trial version www.pdffactory.com

Document Number

Rev
1.0

ACLUA
Thursday, December 26, 2013

Sheet
1

49

of

59

B+

Silergy
SY8208CQNC
Converter
FOR SYSTEM

Adaptor
EC_ON

EN

Silergy
SY8868QMC
QFN10_2X2
Switch Mode

+5VALW/5A
PGOOD

ALW_PWRGD

PGOOD

ALW_PWRGD

FOR VDDR

S3

FOR DDR

+1.35V/12A

Silergy
SY8032ABC
SOT23-6
Switch Mode

+0.675VS/2A

PGOOD

+1.05VSP_VGA/2A

FOR VDDR

VR_ON

EN

Onsemi
NCP81101MNTXG
QFN28_4X4
Switch Mode
FOR CPU Core PGOOD

Battery
Li-ion
4S1P/41WH
VIDs
EN

PGOOD_NB

VGATE

Onsemi
NCP81172MNTWG
QFN24_4X4
Switch Mode
FOR GPU VDDC

PGOOD

+VGA_CORE/31A
VGA_PWRGD

NVDD_PWR_EN

CPU Core/14A/32A

PGOOD

on
fid

PGOOD

EN

PAGE 46

SMBus

TI
TPS51716RUKR
WQFN20_3X3
Switch Mode

EN

+1.5VSP/1A

tia

S5

SUSP#

PGOOD

en

SYSON

EN

ANPEC
APL5930KAI-TRG_SO8
LDO

+3VALW/4A

SUSP#

TI
BQ24737RGRR
Battery Charger
Switch Mode

+1.05VS/5A

+3VLP/ 100mA

PAGE 39

FOR VDDR
SUSP#

Silergy
SY8206BQNC
Converter
FOR SYSTEM

EN

+5VLP/ 100mA

PAGE 39

EC_ON

Issued Date

Title

LC Future Center Secret Data

Security Classification
2013/08/08

Deciphered Date

2013/08/05

Power Diagram

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OFSize
R&D Document Number
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Thursday, December 26, 2013
Date:

Rev
1.0

ACLUA

PDF created with pdfFactory Pro trial version www.pdffactory.com

Sheet

50

of

59

+3VL
VCCRTC

VIN

PD703
RB751V-40_SOD323-2

PL708
HCB2012KF-121T50_0805
1
2

For EMI request

PC104
1000P_0402_50V7K

44,53

PC102
2
1

7A_24VDC_429007.WRML
ADAPTER_ID

APDIN1

PC103
2
1

470P_0402_50V7K

PC101
1000P_0402_50V7K

APDIN

RTC_VCC

PL707
HCB2012KF-121T50_0805
1
2

PF101

1
1 2
2 3
3 4
4 5
5
ACES_50299-00501-003
ME@

470P_0402_50V7K

JDCIN1

JRTC1

PR9400

PD704

BAT_D

1K_0603_5%

change to 1K

FDK_ML1220-TT28

RB751V-40_SOD323-2

SD01310018J

tia

53

+1.05VS

PC1257
2
1

+1.05VS

3
PC1260
2
1

2
1

EN

RESET

OVSET

UVSET
TMER

PR9410 +3VALW
1
2

6
5

375K for
124K for

15uS
5uS

15K_0402_1% @

PR9411
10K_0402_1%

PR368

H_PROCHOT#

0_0402_5%

PR9409

RT9553AGQW_WDFN10_3X3
PR9407
124K_0402_1%
@
@

PQ204 @ D
G
2N7002KW_SOT323-3

@ PR9412
10K_0402_5%

+3VALW
@

PR9404
10K_0402_1%

PR9417
30K_0402_1%

ILIM

H_PROCHOT#

1
0_0402_5%

@
@
+3VALW

10K_0402_1%
PR9413
10K_0402_1%
@

set OVP

0.1U_0402_25V6

VCC

2
PR369

on
fid

CSP

11

35.7K_0402_1%

+3VALW

CSN PROCHOT#

PR9406
10K_0402_5%
@

UVP 12V

5,44,52

en

10

GND

PR9403

PC1259@
0.1U_0402_25V6

EC_ADAPTER

PR9405
10K_0402_5%
@

PU1208
0.1U_0402_25V6
PR367
0_0402_5%

44

PC1256
0.1U_0402_25V6

PC1258 @
2
1

0.1U_0402_25V6

+5VALW

737_ACN

737_ACP

53

45W current limit 2.8A

65W current limit 3.6A

New solution need verify in SDV

This solution will reverse in next phase

Issued Date

Title

LC Future Center Secret Data

Security Classification
2013/08/08

2013/08/05

Deciphered Date

DCIN / RTC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Thursday, December 26, 2013
Date:

Rev
1.0

ACLUA

PDF created with pdfFactory Pro trial version www.pdffactory.com

Sheet

51

of

59

VMB2
VMB

JBATT1

PF201
8A_24V_F1206HI8000V024T
1
2

PH201 under CPU botten side :

CPU thermal protection at 92+-3 degree C
Recovery at 56 +-3 degree C

BATT+

For KB9012 (Red square) --> Remove PU201 circuit, but keep PR206
PH201, PR205,PR211,PQ201,PR208,PR212

1
PC201
1000P_0402_50V7K

PC202
0.01U_0402_25V7K

PR202
100_0402_1%

+5VLP
+3VL

@
MAINPW ON

Turbo_V

PR215

PROCHOT#

+3VALW

VMB2
+5VALW

PR106 @
2

O2

-_2

PQ101A @

AS393MTR-G1_SO8

on
fid

PR116
430K_0402_1%
2
1

PU202B

+_2

VIN

4
2

+20VSB

2
1

PJ201
JUMP_43X39
2
1
2

PC205
0.1U_0603_25V7-M

VSBP_3

1
2

22K_0402_1%

@
54

ALW _PW RGD

44,46

PCH_PW R_EN

PR219
0_0402_5%
2

PQ203

3
PR220
1
2
1K_0402_1%

S 2N7002KW _SOT323-3

PC206
1U_0402_6.3V6K
@

Title

LC Future Center Secret Data

Security Classification
Issued Date

2
G

VSBP_1

PR217
1
VSBP_2

+VSBP

PQ202
TP0610K-T1-E3_SOT23-3

B+

2N7002KDWH_SOT363-6

BATT_LEN#

44

PR229
PQ996A
10K_0402_1%
D
1
2 2
G

+3VL

PR230
100K_0402_1%

PR227
100K_0402_1%
1
2

PR225
100K_0402_1%
1
2

PR366
1
2
0_0603_5%
@

+3VALW

53

AS393MTR-G1_SO8

PQ205
2N7002KW _SOT323-3
S

0.22U_0603_25V7K

PQ996B
2N7002KDW H_SOT363-6

PC204
2
1

-_1

PR216
100K_0402_1%
2
1

2
5

1
3

O1

PR224
49.9K_0402_1%

+_1

PC108
0.1U_0402_25V6

BATT_OUT

@
PU202A

8
2

100K_0402_1%
PR223

PR228
10M_0402_5%
1
2

PR226
280K_0402_1%
PR222
10K_0402_1%
1
2

+3VALW

PR221
100K_0402_1%
1
2

PC207
0.01U_0402_25V7K

+3VALW

VMB2

PR353
1M_0402_5%

+5VALW

PQ101B @
2N7002KDW H_SOT363-6

PC1268
220P_0402_50V7K
2
1

PR114
180K_0402_1%
2
1

PC107 @
0.1U_0402_25V6

20K_0402_1%

1 PR9416 2@

12.5V

AZ5215-01F_DFN1006P2E2
@

H_PROCHOT#

1.78M_0402_1%

PD306

PR109 @
0_0402_5%
2
1

PR110 @
430K_0402_1%

en

PR103
499K_0402_1%
2
1

Reverse PD305 For EMI request

@

SUYIN_200082GR007G232ZR
ME@

VMB2

PR108 @
221K_0402_1%

PR105 @
10K_0402_1%

PR352
1M_0402_5%

EC_SMCA
EC_SMDA
BATT_TEMP_IN

PD305
AZC199-02S.R7G_SOT23-3
@

1
2
3
4
5
6
7
8
9

1
2
3
4
5
6
7
GND1
GND2

+5VALW

JBATT2
C

+3VALW

tia

0_0402_5% @

2N7002KDWH_SOT363-6

44

44

0_0402_5%

44

100K_0402_1%_TSM0B104F4251RZ
PR213
0_0402_5%

@ PR214
1

PH201

PR210
57.6K_0402_1%
@

ADP_OCP_2 1

NTC_V

PR209
10K_0402_1%

UVP_1

2
Turbo_V_1

44,53

OTP_N_003

A/D

BATT_TEMP

BATT_TEMP_IN

2ADP_OCP_1
G

OTP_N_002

G718TM1U_SOT23-8

PQ201
2N7002KW _SOT323-3

PR204
1
2
10K_0402_5%

OT2 RHYST2

NTC_V_1

OT1 TMSNS2

+3VALW

GND RHYST1

44

H_PROCHOT#

PR208
100K_0402_1%
@

VCC TMSNS1

PR212
10K_0402_1%

2
5,44,51

PR203
1
2
100K_0402_1%

PR207
21.5K_0402_1%
@

1
44,53

PR206
13.7K_0402_1%

PU201

44,53

EC_SMB_DA1

PR205
4.42K_0402_1%
@

+3VS
EC_SMB_CK1

ADP_I

PC203
0.1U_0603_25V7-M
@

44,53

ME@

2
PR211
0_0402_5%

SUYIN_200082GR007G232ZR
D

PL201
C8BBPH403025-1TAPING_2P
1
2

EC_SMCA
EC_SMDA

1
2
3
4
5
6
7
8
9

PR201
100_0402_1%
2
1

1
2
3
4
5
6
7
GND1
GND2

For KB930 --> Keep PU1 circuit

(Vth = 0.825V)

2013/08/08

2013/08/05

Deciphered Date

BATTERY CONN/OTP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Thursday, December 26, 2013
Date:

Rev
1.0

ACLUA

PDF created with pdfFactory Pro trial version www.pdffactory.com

Sheet

52

of

59

B+

PC111
0.1U_0402_25V6

PC110
1000P_0402_50V7K
2
1

PC106
0.1U_0402_25V6
2
1

PQ303
AO4407AL_SO8

BQ24737_VDD

1SS355_SOD323-2

PD302

PACIN_P

737_ACDET

GND
BTST

17

BST_CHG 1

2
2.2_0603_5%

PC317
2
1

REGN

16

3
2
1

ACOK

PACIN

en

2
G

S
PQ308A
2N7002KDW H_SOT363-6

PQ309

PR312

0.047U_0603_16V7K
ACPRN

5
6
7
8

AO4466L_SO8

14

ACDET

CMPOUT

1
2
59K_0402_1%
PC316
1
2

ACN

PR311

ACP

1
S

20

PR310
390K_0402_1%

VCC

PQ307B
2N7002KDW H_SOT363-6

PD303
RB751V-40_SOD323-2
2
1

2
D

PC313
0.1U_0603_25V7-M

PC315
1U_0603_25V6M
2

0.1U_0603_25V7-M
737_VCC

1SS355_SOD323-2

PC312
2
1

VIN

5
PACIN_G

47K_0402_1%
C

PR308
2
1
52 10_1206_5%
PC314
1U_0603_25V6M
2
1

PR347
1M_0402_5%

BATT_OUT

1
2

5PACIN_N

0.1U_0603_25V7-M

tia

PQ990A
2
G

P2-2
PR309

PQ308B
2N7002KDW H_SOT363-6

S 2N7002KDW H_SOT363-6

PR306
200K_0402_1%

PR307
68K_0402_1%

PACIN

PD301

1
PC311
1

0.1U_0603_25V7-M

6
1

PR305
10K_0402_1%

PC310
2
1

P2

2N7002KDWH_SOT363-6

PQ307A D

2
G

VIN

47K_0402_1%

PR356
20K_0402_1%

P2_G1

PQ305
LTC015EUBFS8TL_UMT3F-3

PR304
1

737_ACN

P2-1

BATT+
8
7
6
5

DISCHG_G

2ACOFF-1

For EMI request

PC307
2200P_0402_50V7K

For EMI request

1
DISCHG_G-1

51

PC303
10U_0805_25V6K
@

PC306
4.7U_0805_25V6-K
1
2

PC302
10U_0805_25V6K
@

PC305
4.7U_0805_25V6-K
1
2

PR303
200K_0402_1%

737_ACP

1
2

100P_0402_50V8J

51

1
2
3

2
1

1P2_G2

PC308
0.1U_0603_25V7-M
2
1

LTA044EUBFS8TL_UMT3F-3

PC301
1
2

PQ304

PR302
200K_0402_5%

PL710
HCB2012KF-121T50_0805
1
2
PC109
0.1U_0603_25V7-M
1
2

VIN

1
2
3

8
7
6
5

PL709 @
HCB2012KF-121T50_0805
1
2
PR301
0.01_1206_1%

PC105
1000P_0402_50V7K
2
1

P3
PQ302
SI4483ADY-T1-GE3_SO8
1
8
2
7
3
6
5

P2
PQ301
AO4407AL_SO8

Charge Option() bit[8]=1

PC304
4.7U_0805_25V6-K
1
2

DH_CHG

SDA

PHASE

19

ILIM

BM#

5
6
7
8

15

+3VALW

4.7UH_PCMB063T-4R7MS_5.5A_20% 2

DL_CHG

BATT+

PR317
4.7_1206_5%

AO4466L_SO8

SRP_1 13

2 CHG

PC321
680P_0402_50V7K
@

1
2

PC322
1
2

PC324
0.1U_0603_25V7-M
@

737_SRP

0.1U_0603_25V7-M

737_SRN

PC323
0.1U_0603_25V7-M

BATT_TEMP

PQ311

21

on
fid

PR324

316K_0402_1%
2

1
B

44,52

PAD

PR320
10_0603_5%

737_ILIM

100K_0402_1%

2N7002KDW H_SOT363-6 S

SRN_1 12

PR319
6.8_0603_5%
1

PR321

PR345
0_0402_5%
@

10

10K_0402_5%
1
2

+3VS

PQ990B D

5
G

BM#

11
3

PR318 @
BATT_OUT

LODRV
SRP

IOUT

PC318
100P_0402_50V8J

SRN

ADP_I

CMPIN

ADP_I

2N7002KDW H_SOT363-6

44,52

PR349
1M_0402_5%

PR316
0.01_1206_1%
PL302

LX_CHG

PC320
10U_0805_25V6K
2
1

18

BQ24737RGRR_VQFN20_3P5X3P5

PC319
10U_0805_25V6K
2
1

EC_SMB_DA1

HIDRV

44,52

SCL

PR315 0_0402_5%
2
737_SDA

0_0402_5%

PU301
737_SCL

EC_SMB_CK1

16251_SN

0.1U_0402_25V6 PR313 0_0402_5%

1
2

44,52

ACOFF

3
2
1

44

PQ998A
2
G

2ACOFF-1

PR314

BQ24737_VDD

PR325
47K_0402_1%

PR326
10K_0402_1%

PR327
2

ACIN

44

10K_0402_1%
PACIN

44,51

ADAPTER_ID

2N7002KDW H_SOT363-6 S

ADAPTER_ID_ON#

44

PQ995B @
2N7002KDW H_SOT363-6

G
S

5
PR328 @
1M_0402_5%
PD304
AZ5425-01F_DFN1006P2E2

ACPRN

S 2N7002KDW H_SOT363-6

1
@

ADAPTER_ID_ON#_G

PC1266
0.1U_0402_25V6
2
1

PC1267
680P_0402_50V7K
2
1

@
2

PR333
12K_0402_1%

D PQ995A

PR336
0_0402_5%

PQ998B

PR323 @
1M_0402_5%

PR322
750_0603_1%

VIN

+3VALW

ACPRN

PR334
0_0402_5%
1
2
@

ACIN#

8,44

Title

LC Future Center Secret Data

Security Classification
Issued Date

ACIN#

2013/08/08

Deciphered Date

2013/08/05

CHARGER

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Date:
5

PDF created with pdfFactory Pro trial version www.pdffactory.com

Document Number

Rev
1.0

ACLUA
Thursday, December 26, 2013
1

Sheet

53

of

59

B+

PU904

PC1057

1
1

change 470P to 10nf for soft start time 2ms

PJ304

PR341
2

1K_0402_1%

+3VL

+3VLP

JUMPER

0.01U_0402_25V7K

3V_GND

tia

3V_GND

PJ1

3V_GND
3V_GND

JUMP_43X79

PC1106
1000P_0402_50V9-J
@

PTP1
PAD

4A

PJ303

+3VALW _P

PR338
4.7_1206_5%
@

100mA +3VLP

PL303
1
2
2.2UH_PCMB063T-2R2MS_8A_20%

+3VALW _P

+3VALW

PC1048
2

PC1052
22U_0805_6.3V6M

LDO

FB

+3VLX

PR339
1M_0402_5%

@ PC1054
0.1U_0402_25V6

LX
OUT

10

+3VALW _FB

0.1U_0603_25V7-M

PC1051
22U_0805_6.3V6M
2
1

0_0402_5%

+3VBS

PC1050
22U_0805_6.3V6M
2
1

EN1

+3V_PW RGD

2
6

PC1049
22U_0805_6.3V6M
2
1

+3VALW _EN

BS

GND

3V_GND

EC_ON

PG

1 2

IN

EN2

PC1055
4.7U_0603_6.3V6K

PR337

1
44

+3V_VIN
PR335
1M_0402_5%

PC1047
10U_0805_25V6K

1
2
@

1.5A

PC1046
0.1U_0402_25V6

JUMP_43X79

SY8206BQNC_QFN10_3X3

PJ302

en

JUMP_43X39

+3VALW

on
fid

PR342
100K_0402_5%

B+

52

4
7

0.1U_0603_25V7-M
+5VLX
PR351
0_0402_5%
1
2+5VALW _P

+5VALW

PL304

3.3UH_PCMB063T-3R3MS_6.5A_20%

5A

PJ306

PR340
4.7_1206_5%
@

100mA +5VLP

0_0402_5%

+5VALW _P
PC1091
22U_0805_6.3V6M

LDO

10

PC1061
1
2

PC1090
22U_0805_6.3V6M
2
1

FB

LX

OUT

+5VBS

PC1080
22U_0805_6.3V6M
2
1

EN

+5V_PW RGD

PR348
1M_0402_5%
2
1

+5VFB

@ PC1069
0.1U_0402_25V6

ALW _PW RGD

PC1063
22U_0805_6.3V6M
2
1

0_0402_5%

VCC

BS

1U_0603_25V6M
+5VALW _EN
5V_GND

PG

GND

1 2

PC1062
1
2+5VVCC

IN

PC1070
4.7U_0603_6.3V6K

SY8208CQNC_QFN10_3X3

PC1059
10U_0805_25V6K

PR346
EC_ON
B

+5V_VIN

2
@

PC1060
10U_0805_25V6K

JUMP_43X79

PR344

2.5A
PC1058
0.1U_0402_25V6

0_0402_5% @

PU905
PJ305

PR343

+3V_PW RGD

JUMP_43X79
B

PC1107
1000P_0402_50V9-J
@

5V_GND

5V_GND

5V_GND

PJ2

JUMPER

PC1072
1
2
6800P_0402_25V7-K

PR350
2

1K_0402_1%

6800pf soft start 2ms

47nf soft start 7ms

@
5V_GND

Issued Date

Title

LC Future Center Secret Data

Security Classification
2013/08/08

Deciphered Date

2013/08/05

PWR_3VALW/5VALW

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Date:
5

PDF created with pdfFactory Pro trial version www.pdffactory.com

Document Number

Rev
1.0

ACLUA
Thursday, December 26, 2013
1

Sheet

54

of

59

PC1102 @
0.1U_0402_10V7K

LG_1.35V

JUMPER
@

PC856
10U_0805_25V6K

10U_0805_25V6K
2
1

1
2

1
+

+1.35V

JUMP_43X118

PC1105
330U_2.5V_M

3
2
1

REFIN

on
fid

PJ4

14A

PC1103
1000P_0402_50V9-J
@

1
2

PR379

+1.35VP
Vout=1.367V
Iocp min=27A

1.35V_GND

1.35V_GND

93.1K_0402_1%

1
2

PC1263
0.01U_0402_25V7K

PR378
4.7_1206_5%

1.35V_GND

10

6
2

1.35V_GND

PQ43

JUMP_43X118
PJ316

PC1104
1U_0603_25V6M

DDR_VREF
30K_0402_1%
1
2
PR374

PC1265
0.1U_0402_25V6

+5VALW

1
2

PGND

REFIN

11

GND

VREF

DRVL

12

PJ317

2
@

PL307

LX_1.35V

B+

JUMP_43X79 @

PC1053
22U_0805_6.3V6M

13

0.1U_0402_25V6
PC857
2
1

16

PC1064
2
1

PR381 0_0402_5%
1 UG_1.35V

3
2
1

tia

PR380
PC1081
0_0603_5% 0.1U_0603_25V7-M
1
2 2
1
BST_1.35V

PQ997
AON6414AL_DFN8-5

S5_1.35V

17
S3

63.4K_0402_1%
S3_1.35V

S5
SW
V5IN

VTTREF

JUMP_43X79

1.35V_GND

TRIP

TPS51716RUKR_WQFN20_3X3

VDDQSNS

1.35V_SN

DRVH

14

PJ309

0.47UH_PCMC063T-R47MN_17.5A_20%

1.35V_GND
+0.675VS

44

15

5 2A
1.35V_B+

SYSON

PC1101 0.1U_0402_10V7K
@

VBST

VTTGND

PJ315

PR9415

VTT

PC1264
1U_0402_6.3V6K

CPU_DRAMPG_CNTL

PR376 0_0402_5%
1

35,44,46,56,57

en

+VTT_REFP

+0.675VSP

VLDOIN

+1.35V

SUSP#

PR377 0_0402_5%
2
1

VTTSNS

PR9350 0_0402_5%
1
2

AON6554_DFN

PC1099
22U_0805_6.3V6M
2
1

2A

+0.675VSP

2A

PC1100
22U_0805_6.3V6M
2
1

18

20

PAD

PGOOD

PU1207

19

PR9414
1K_0402_1%

VDDQ_PGOOD

21

1.35V_GND

MODE

PR375
1
2
10K_0402_1%

1.35V_GND

44

1k for 500K
12k for 670K

+3VALW

Issued Date

Title

LC Future Center Secret Data

Security Classification
2013/08/08

Deciphered Date

2013/08/05

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

1.35VS/+0.675VS
Size
Document Number
Custom
Date:

PDF created with pdfFactory Pro trial version www.pdffactory.com

Rev
1.0

ACLUA

Thursday, December 26, 2013

D

Sheet

55

of

59

PU602

PC618
.1U_0402_10V6-K

PR616
100K_0402_5%
@

PC728
220P_0402_50V7K

PC617 @
10U_0603_6.3V6M

PR615
24K_0402_1%

+3VS

JUMP_43X39

PR613
21.5K_0402_1%

VFB=0.8V

APL5930KAI-TRG_SO8

on
fid

FB

PJ603

VOUT1
VOUT2

+1.5VS
500mA

EN
POK

3
4

8
7

0_0402_5%

2EN_1_5VSP
1

VCNTL
VIN1
VIN2

+1.5VSP

SUSP#

PR614
35,44,46,55,57

JUMP_43X39

PC616
4.7U_0603_6.3V6K

en

6
5
9

PJ604

500mA

GND

PC615
1U_0603_25V6M

+3VALW

tia

+5VALW

Issued Date

Title

LC Future Center Secret Data

Security Classification
2013/08/08

Deciphered Date

2013/08/05

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

+1.35VS_VGA/+1.5VS
Size
Document Number
Custom
Date:

PDF created with pdfFactory Pro trial version www.pdffactory.com

Rev
1.0

ACLUA

Thursday, December 26, 2013

D

Sheet

56

of

59

+3VS

PR701
10K_0402_5%

PC706
22U_0805_6.3V6M

1
2

1
2

PC707
330U_D2_2V_Y
@

PC710
680P_0402_50V7K
@

PR706
2
1
75K_0402_1%

1_05VS_FB

SY8868QMC_QFN10_2X2
PC711
0.01U_0402_25V7K

1
D

PC705
22U_0805_6.3V6M

GND

+1.05VS

tia

10

FB

JUMP_43X79
PR703
4.7_1206_5%
@

PC709
.1U_0402_10V6-K

0_0402_5%

SS

PC704
22U_0805_6.3V6M

PJ702

0.68UH_PCMC063T-R68MN_15.5A_20%

OUT

1_05VS_LX

PC703
22U_0805_6.3V6M

EN

PG

LX3

2
2

SUS_VCCP

LX2

8
PR705

44

LX1

1_05VS_EN

PR994

VIN

@ PR704
1
2
0_0402_5%

SUSP#

47K_0402_5%

35,44,46,55,56

5A
PL701

1SNB_1_05VS 2

PU701

1_05VS_PVIN

JUMP_43X79
@

PC701
22U_0805_6.3V6M

PC1066
2
1

+5VALW
D

0.1U_0402_25V6

PJ704

PC702
22U_0805_6.3V6M

1_05VS_PG1

PR707
100K_0402_1%

1 PC712
22P_0402_50V8-J

VFB=0.6V
Vo=VFB*(1+PR706/PR705)

en

on
fid

+3VS

PR708
10K_0402_5%
OPT@

+1.05VSP_VGA

PR715

1
0_0402_5%
N15SGT@

PC717
22U_0805_6.3V6M

+1.05VGS

@
PC716
22U_0805_6.3V6M

1
2

OPT@

OPT@

PR714
100K_0402_1%
OPT@

PC719
0.22U_0402_10V6K
N15VGM@

EN_VGA

PR713
1M_0402_5%

22,58

PC718
680P_0402_50V7K
@

JUMP_43X79

1.05VMP_FB

1.05VGS_EN

4.7K_0402_5%
N15VGM@

EN

PC715
68P_0402_50V8J
1

FB

PJ709

OPT@

PD701
2 @

DGPU_PWROK

GND

PL702
1
2
1UH_PH041H-1R0MS_3.8A_20%
OPT@

1.05VMP_LX

SY8032ABC_SOT23-6
OPT@ FB=0.6Volt

PR172

23,58

PG

OPT@

LX

OPT@
PR711
75K_0402_1%
2
1

IN

1
2

PR710
4.7_1206_5%

1.05VMP_VIN

PC714
22U_0805_6.3V6M

JUMP_43X79

PC713
22U_0805_6.3V6M
2
1

PJ703
+3VALW

2.5A

PU702

OPT@

+1.05VGS_PW RGD

22

OPT@

1.05VGS_EN

1.05VGS_EN

21

Issued Date

Title

LC Future Center Secret Data

Security Classification
2013/08/08

Deciphered Date

2013/08/05

+1.05VS/+1.05VS_VGA

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Date:
5

PDF created with pdfFactory Pro trial version www.pdffactory.com

Document Number

Rev
1.0

ACLUA
Thursday, December 26, 2013
1

Sheet

57

of

59

PR9443
100K_0402_5%
@

EN_VGA

EN_VGA

22,57

PC1303
.1U_0402_10V6-K
OPT@

PR9444
10K_0402_1%
OPT@

+VGA_B+
PJ710

2
PSI_VGA

B+

22
21

PVCC_VGA

20

PC1298
10U_0805_25V6K

PC1295
10U_0805_25V6K

OPT@ PC1297
330U_D2_2V_Y

1SNUB1_VGA 2

OPT@ PC1293
330U_D2_2V_Y

OPT@

OPT@

OPT@
PL706
0.24UH_PCME063T-R24MS1R145_35A_20%
1
2
OPT@

PHASE2_VGA

PC1282
680P_0402_50V7K
@

Issued Date

Deciphered Date

OPT@

OPT@

OPT@

OPT@

Title

LC Future Center Secret Data

2013/08/08

PC1292
22U_0805_6.3V6M

+3VS

PC1281
330U_D2_2V_Y
OPT@

PC1291
22U_0805_6.3V6M
2
1

OPT@

PR9433 OPT@
10K_0402_5%

Security Classification

PC1280
330U_D2_2V_Y
@

PR9428
4.7_1206_5%
@

PC1290
22U_0805_6.3V6M
2
1

LGATE2_VGA

PR9432
0_0402_5% @
2
1

PC1279
1U_0402_10V6K
OPT@

+VGA_CORE

PQ994

PC1288
22U_0805_6.3V6M

PR9424
PC1278
0_0603_5%
0.22U_0603_16V7K
2
1OPT@ BOOT2_2_VGA 1
2
OPT@

PC1287
22U_0805_6.3V6M

+5VS
2
1
PR9427
OPT@
2.2_0402_5%

UGATE2_2_VGA

PC1255
0.1U_0603_25V7K

PR9423
0_0402_5%
1
2

BST2

18

HG2

17

VCC

16

15

VCC_VGA

+VGA_B+

OPT@

BOOT2_VGA

+5VS

NCP81172MNTWG_QFN24_4X4

UGATE2_VGA

14

TSNS

GND

13

25

OPT@

PR9426
1
VREFOPT@ 2
5.9K_0402_1%

PR9418
0_0402_5%

19

DGPU_PWROK
PR9425
10K_0402_5%
+3VS
2
1

2OPT@

AON6554_DFN

PH903
100K_0402_1%_TSM0B104F4251RZ
2
1

PC1299

.1U_0402_10V6-K
OPT@

PC1301
4.7U_0603_6.3V6K

23

PC1276
10U_0805_25V6K

PH2

PC1296
680P_0402_50V7K
@

1SNUB2_VGA 2

LG2

24

FB

reserve for future tune

PVCC

1
+

PC1275
10U_0805_25V6K

FBRTN

OPT@

PC1273
0.1U_0603_25V7K

PGND

+VGA_CORE

OPT@

FS

COMP

PHASE1_VGA

EN_VGA

BST1

PSI_VGA

2
HG1

VID

EN

LG1

on
fid

11
PC1270
FB_VGA
PC1269
47P_0402_50V8J
PR9419
PC1271
1
2FB1_VGA1
2
1
2
COMP_VGA 12
1000P_0402_50V7K
PR9420
51_0402_1%
OPT@
10P_0402_50V8J
OPT@
PR9421
PC1272
0_0402_5%
OPT@
OPT@
1 VCC_SEN
1
2
1
2FB2_VGA1 PR9422 2
VCCSENSE_VGA OPT@ 2
OPT@
10K_0402_1%
100P_0402_50V8J
82K_0402_1% OPT@
OPT@
PR9448
100_0402_5%
1
2
OPT@

PH1

VREF

PL705
0.24UH_PCME063T-R24MS1R145_35A_20%
1
2

10

VSS_SEN

REFIN

OPT@

PR9435
4.7_1206_5%
@

OPT@ PQ993
AON6414AL_DFN8-5

PQ991
AON6414AL_DFN8-5

5
8

FS

PR9438
5.1K_0402_1%
@

en

7
VREF

TALERT#

2N15SGT@

2700P_0402_50V7-K
PR9439
2
1OPT@
39K_0402_1%

VIDBUF

1
PC1277

PU909

VSSSENSE_VGA

PC1294
0.01U_0603_50V7K
2
OPT@ 1
PR9449
0_0402_5%
1
OPT@ 2

PR9437
18K_0402_1%
2
1N15SGT@

PR9431
0_0402_5%
1
N15SGT@ 2

PR9436
2K_0402_1%
N15SGT@

OPT@

PQ992

LGATE1_VGA

UGATE1_VGA

OPT@

OPT@

1
GPU_VID

reserve follow
NV suggestion
PR9434
PR9440
20K_0402_1% 20K_0402_1%
2
1
2
1VIDBUF
VREF
N15SGT@
N15SGT@

PR9447
100_0402_5%
2
1
OPT@

+VGA_CORE

PSI

PC1261
10P_0402_50V8J
2
1

@
PC1262
2700P_0402_50V7-K
1
2

27
7.5
0
6.2
1.74
5.6

UGATE1_2_VGA

AON6554_DFN

20
20
2
18
0
2.7

PR9440
PR9434
PR9436
PR9437
PR9431
PC1277

reserve

PGOOD

B
D
N15S-GT N15V-GM

BOOT1_VGA

PR9430
0_0402_5%

R1
R2
R3
R4
R5
C(nF)

3
2
1

4
PR9429
PC1300
0_0603_5%
0.22U_0603_16V7K
2
1BOOT1_2_VGA 1
2
PR9441
OPT@
OPT@
0_0402_5%
2
1

N15S-GT use config-B

N15V-GM use config-D

3
2
1

DGPU_PWROK

VCCSENSE_VGA

DGPU_PWROK

3
2
1

VCCSENSE_VGA

20

JUMP_43X79

3
2
1

VSSSENSE_VGA

tia

VSSSENSE_VGA

PSI_VGA

20

23,57

NVVDD_PWM_VID

NVVDD_PWM_VID
19

NVVDD_PWM_VID

19

PD705
RB751V-40_SOD323-2
OPT@
2

1
1

3VGS_PWR_EN

19,21

2
PR9445
0_0402_5%
N15SGT@

PR9442
10K_0402_5%
@

PC1289
22U_0805_6.3V6M
2
1

2
PR9446
0_0402_5%
N15VGM@

PXS_PWREN

+3VGS

4,21

2013/08/05

PWR-VGA_CORE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Friday, December 27, 2013
Date:

Rev
1.0

ACLUA

PDF created with pdfFactory Pro trial version www.pdffactory.com

Sheet

58

of

59

CPU_PH

PC989

PJ708
JUMP_43X79

68U_25V_M

1
PR9335

3A

2
1
0_0402_5%
@

+5VALW

B+

1 PR9337 2
165K_0402_1%
PC1158
68P_0402_50V8J
1
2

PR9346

PC1159
330P_0402_50V7K
1
2

VR_IMVP_IMON

PH901
220K_0402_5%_TSM0B224J4702RE
2
1

470P_0402_50V7K

PC1157
2
1

PR9334
27.4K_0402_1%
44

CORE_GND

CORE_GND

PR9338
75K_0402_1%

PR9347
2
1
0_0402_5%
@

PR9348
2
1
0_0402_5%
@

PC988

68U_25V_M

1
2

1
2

1
2

PC1170
22U_0805_6.3V6M
@

PC1089
22U_0805_6.3V6M
2
1
@

PC1148
22U_0805_6.3V6M

PC1088
22U_0805_6.3V6M
2
1

PC1073
22U_0805_6.3V6M
2
1

1
2

3
2
1

0.1U_0402_25V6

AON6414AL_DFN8-5

PC1116
22U_0805_6.3V6M

PC1160
22U_0805_6.3V6M
2
1

1
2

1
2

PC1139
22U_0805_6.3V6M

PC1180
22U_0805_6.3V6M

PC1173
22U_0805_6.3V6M

PC1174
22U_0805_6.3V6M
2
1

PC1163
22U_0805_6.3V6M

1
2

PC1165
22U_0805_6.3V6M
PC1178
22U_0805_6.3V6M

1
2
1
2

PC1162
22U_0805_6.3V6M
PC1176
22U_0805_6.3V6M

1
2

PC1177
22U_0805_6.3V6M

1
2

PC1149
22U_0805_6.3V6M

1
2

1
2

PC626 @
10U_0603_6.3V6M

PC1164
22U_0805_6.3V6M

2
1

10,44

PR9342
0_0402_5%
2
1

1
2

54.9_0402_1%

@
PR9149
2
1
0_0402_5%

130_0402_1%

75_0402_1%

PC622
.1U_0402_10V6-K

CORE_GND
PR31

PR60

PR9148
2
1
0_0402_5%

PC621
680P_0402_50V7K

PH902
100K_0402_1%_TSM0B104F4251RZ

VR_CPU_PW ROK

CPU_SVID_CLK

PR617
4.7_1206_5%

VR_HOT#
CPU_SVID_DAT
CPU_SVID_ALERT#

+1.05VSR

PR47
10K_0402_5%

PR9098
+1.05VS

PC1167
22U_0805_6.3V6M
2
1

CORE_GND

TSENSE

10

PL9

0.22UH_SPS-06CZ-R22M-V1_23A_20%

For EMI request

+3VS

CORE_GND

1
44
10

CPU_B+

PC1155
0.01U_0402_25V7K

PR9265
499_0402_1%

10

32A

+1.05VSR

PC620
.1U_0402_10V6-K
@

PR9339

CPU_VR_ON

1K_0402_1%

59K_0402_1%

10

PR9331

CORE_GND

EC_VR_ON

PU908
NCP81101MNTXG_QFN28_4X4

PC242
CORE_GND
1U_0603_25V6M

44

CPU_CORE

en

2.2_0603_5%

1
PR9343 2
@
0_0402_5%
PR9146
2
1
0_0402_5%

PC113

on
fid

560P_0402_50V7-K

+5VALW

1
2
3
4
5
6
7

PC1254 @
1
2

CPU_CSREF
2
2
1

21
20
19
18
17
16
15

GND

CPU_LG

PQ39

PC98

tia

29

PR9145

CPU_PH
CPU_HG_R
PC97
1 PR80
2 1
2
2_0603_5%
0.22U_0603_25V7K

CPU_PH

CORE_GND

PC1154
1000P_0402_50V7K

CPU_VCC_SENSE

10

0_0402_5%
C

0_0603_5%

PC1156
0.01U_0402_25V7K
2
TSENSE 1
CORE_GND
CPU_LG

14
13
12
11
10
9
8

VBOOT
TSENSE
LG
PGND
SW
HG
BST

2
2

CPU_VSS_SENSE

ROSC
COMP
FB
DIFFOUT
VSN
VSP
VCC

2CPU_HG

3
2
1

PR9402
12

CPU_HG_R 1

+5VALW

AON6554_DFN

22
23
24
25
26
27
28

PR365

PR9332
69.8K_0402_1%
1
2

ENABLE
VR_HOT#
SDIO
ALERT#
SCLK
VR_RDY
VRMP

PR362
0_0402_5%
1
2

PQ40

CORE_GND

0_0402_5%

ILIM
IOUT
CSCOMP
CSSUM
CSREF
IMAX
PVCC

PR1
16.2K_0402_1%

1 CSCOMP
2
1
PC1152 @
PR2
2200P_0402_50V7K 4.02K_0402_1%
1
2
1
2

PR9330
1K_0402_1%
1
2

PC1172
2.2U_0603_6.3V6K
PR9341
1
2

PC99

10U_0805_25V6K

CORE_GND

PC1171
1000P_0402_50V7K

PC100

10U_0805_25V6K

PC1181
10P_0402_50V8J
1
2

PR9340
102K_0402_1%

PC1065

10U_0805_25V6K

PC1153
330P_0402_50V7K
1
2

CORE_GND

10U_0805_25V6K

PR3
49.9_0402_1%
1
2

CORE_GND

CPU_B+
CPU_CSREF

PR9333
16.5K_0402_1%

PR9345
2
1
@
0_0402_5%

CSCOMP
CSSUM
2 PR9401 1CPU_CORE
1
10_0402_1%

140K_0603_1%

1
+

PC708
220U_D2_2.5VY_R6M

2 3
B

PJ3

JUMPER
@

CORE_GND

Issued Date

Title

LC Future Center Secret Data

Security Classification
2013/08/08

Deciphered Date

2013/08/05

PWR_CPU Core

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

Date:
5

PDF created with pdfFactory Pro trial version www.pdffactory.com

Document Number

Rev
1.0

ACLUA
Thursday, December 26, 2013
1

Sheet

59

of

59