Lenovo B460 Wistron LB46E

5
/%(%ORFN'LDJUDP
D
THERMAL EMC2102
Mobile CPU
CLK GEN.
Project code: 91.4HK01.A01

PCB P/N
:
REVISION
: 10307-sc
PCB STACKUP
27
Penryn 479
TOP
VCC
4, 5
HOST BUS
DDR3 DIMM1
800/1066 MHz
800/1066MHz
LVDS, CRT I/F
X4 DMI
400MHz
C-Link0
PCIE x 16
DCBATOUT
BOTTOM
3D3V_S5
CRT
19
nVIDIA
6,7,8,9,10,11
OUTPUTS
5V_S5
18
INTEGRATED GRAHPICS
800/1066MHz
INPUTS
DIS
37
TPS51125
GND
LCD
DDR Memory I/F
17
UMA
AGTL+ CPU I/F
DDR3 DIMM2
SYSTEM DC/DC
19
Cantiga
16
800/1066 MHz
CRT
667/800/1067MHz@1.05V
SYSTEM DC/DC
TPS51218/RT9025 39
LCD
N11M-OP1
INPUTS
18
46~51
OUTPUTS
1D05V_S0
DCBATOUT
Line Out
(NO SPDIF)
1D8V_S0
ICH9M
TPS51116
6 PCIe ports
PCI/PCI BRIDGE
25
MIC In
Codec
25
4X128MB
GDDRIII52,53
4 SATA
1D5V_S3
ETHERNET (10/100/1000MbE)
Internal MIC
High Definition Audio
25
LAN
PCIex1
LPC I/F
TXFM
RTL8111E 23
Serial Peripheral I/F

B
1D5V_S3
TPS51116
12 USB 2.0/1.1 ports
CX20671
25
DCBATOUT
ACPI 2.0
AZALIA
38
RJ45
38
0D75V_S0
CPU DC/DC
24
ISL6266A
36
B
Matrix Storage Technology(DO)
INPUTS
Active Managemnet Technology(DO)
PCIex1
VCC_CORE_S0
DCBATOUT
Mini Card
Kedron
OUTPUTS
0.35~1.5V
a/b/g/n
26
25
CHARGER
LPC BUS
BQ24745
12,13,14,15
INT.SPKR
INPUTS
Camera
(USB)
HDD SATA
KBC
28
20
USB
3 Port
SATA
21
LPC
Winbond
W25X16
16M Bits
KBC773L
SATA
ODD SATA
USB
18
BIOS
29
OUTPUTS
BT+
DEBUG
CONN.34
USB
22
41
DCBATOUT
DCBATOUT
<Core Design>
Touch
Pad 30
Wistron Corporation
INT.
KB 30
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Taipei Hsien 221, Taiwan, R.O.C.
Title
1_BLOCK DIAGRAM
Size
A3
Power Board
31
Date:
Document Number
Rev
SA
LB46E
Monday, December 27, 2010
Sheet
of
http://mycomp.su - . , , .
5
53
ICH9M Functional Strap Definitions

ICH9 EDS 642879 Rev.1.5
ICH9M Integrated Pull-up

and Pull-down Resistors
page 92
Signal
Usage/When Sampled
HDA_SDOUT
XOR Chain Entrance/

PCIE Port Config1 bit1,
Rising Edge of PWROK
Allows entrance to XOR Chain testing when TP3

pulled low.When TP3 not pulled low at rising edge
of PWROK,sets bit1 of RPC.PC(Config Registers:
offset 224h). This signal has weak internal pull-down
CL_CLK[1:0]
PULL-UP 20K
CL_DATA[1:0]
PULL-UP 20K
HDA_SYNC
PCIE config1 bit0,

Rising Edge of PWROK.
This signal has a weak internal pull-down.

Sets bit0 of RPC.PC(Config Registers:Offset 224h)
CL_RST0#
PULL-UP 20K
GNT2#/
GPIO53
PCIE config2 bit2,

DPRSLPVR/GPIO16
PULL-DOWN 20K
ENERGY_DETECT
PULL-UP 20K
GPIO20
Reserved
This signal has a weak internal pull-up.

Sets bit2 of RPC.PC2(Config Registers:Offset 0224h)
This signal should not be pulled high.
HDA_BIT_CLK
PULL-DOWN 20K
GNT1#/
GPIO51
ESI Strap (Server Only)

HDA_DOCK_EN#/GPIO33
PULL-UP 20K
HDA_RST#
PULL-DOWN 20K
HDA_SDIN[3:0]
PULL-DOWN 20K
HDA_SDOUT
PULL-DOWN 20K
GNT3#/
GPIO55
GNT0#:
SPI_CS1#/
GPIO58
SPI_MOSI
3
GPIO49
SATALED#
SPKR
TP3
GPIO33/
HDA_DOCK
_EN#
Top-Block
Swap Override.
Comment
ICH9 EDS 642879
SIGNAL
ESI compatible mode is for server platforms only.

This signal should not be pulled low for desttop
and mobile.
Sampled low:Top-Block Swap mode(inverts A16 for
all cycles targeting FWH BIOS space).
Note: Software will not be able to clear the
Top-Swap bit until the system is rebooted
without GNT3# being pulled down.
The pull-up or pull-down active when configured for native

GLAN_DOCK# functionality and determined by LAN controller
Boot BIOS Destination

Selection 0:1.
Controllable via Boot BIOS Destination bit

(Config Registers:Offset 3410h:bit 11:10).
GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC.
GNT[3:0]#/GPIO[55,53,51]
PULL-UP 20K
GPIO[20]
PULL-DOWN 20K
Integrated TPM Enable,

Rising Edge of CLPWROK
Sample low: the Integrated TPM will be disabled.

Sample high: the MCH TPM enable strap is sampled
low and the TPM Disable bit is clear, the
Integrated TPM will be enable.
GPIO[49]
PULL-UP 20K
LDA[3:0]#/FHW[3:0]#
PULL-UP 20K
LAN_RXD[2:0]
PULL-UP 20K
LDRQ[0]
PULL-UP 20K
LDRQ[1]/GPIO23
PULL-UP 20K
PME#
PULL-UP 20K
PWRBTN#
PULL-UP 20K
PCI Express Lane

Reversal. Rising Edge
of PWROK.
Signal has weak internal pull-up. Sets bit 27

of MPC.LR(Device 28:Function 0:Offset D8)
SATALED#
PULL-UP 15K
No Reboot.
If sampled high, the system is strapped to the

"No Reboot" mode(ICH9 will disable the TCO Timer
system reboot feature). The status is readable
via the NO REBOOT bit.
SPI_CS1#/GPIO58/CLGPIO6
PULL-UP 20K
SPI_MOSI
PULL-DOWN 20K
SPI_MISO
PULL-UP 20K
This signal should not be pull low unless using

XOR Chain testing.
SPKR
PULL-DOWN 20K
TACH_[3:0]
PULL-UP 20K
TP[3]
PULL-UP 20K
USB[11:0][P,N]
PULL-DOWN 15K
XOR Chain Entrance.

Flash Descriptor
Security Override Strap
Sampled low:the Flash Descriptor Security will be

overridden. If high,the security measures will be
in effect.This should only be enabled in manufacturing
environments using an external pull-up resister.
page 218
Pin Name
CFG[2:0]
CFG[4:3]
CFG8
CFG[15:14]
CFG[18:17]
Strap Description
0.5
Configuration
FSB Frequency
Select
000 = FSB1067
011 = FSB667
010 = FSB800
others = Reserved
Reserved
CFG5
DMI x2 Select
CFG6
iTPM Host
Interface
0 = DMI x2
1 = DMI x4 (Default)
0= The iTPM Host Interface is enabled(Note2)
1=The iTPM Host Interface is disalbed(default)
0 = Transport Layer Security (TLS) cipher
suite with no confidentiality
1 = TLS cipher suite with
confidentiality (default)
CFG7
Intel Management
engine Crypto strap
CFG9
PCIE Graphics Lane
0 = Reverse Lanes,15->0,14->1 ect..

1= Normal operation(Default):Lane
Numbered in order
CFG10
PCIE Loopback enable
0 = Enable (Note 3)
1= Disabled (default)
PULL-DOWN 20K
GLAN_DOCK#
DMI Termination Voltage, The signal is required to be low for desktop

applications and required to be high for
mobile applications.
Montevina Platform Design guide 22339

Rev.1.5
Resistor Type/Value
HDA_SYNC
Cantiga chipset and ICH9M I/O controller

Hub strapping configuration
CFG[13:12]
CFG16
CFG19
00
10
01
11
XOR/ALL
=
=
=
=
Reserve
XOR mode Enabled
ALLZ mode Enabled (Note 3)
Disabled (default)
FSB Dynamic ODT
0 = Dynamic ODT Disabled

1 = Dynamic ODT Enabled (Default)
DMI Lane Reversal
0 = Normal operation(Default):
Lane Numbered in Order
1 = Reverse Lanes
DMI x4 mode[MCH -> ICH]:(3->0,2->1,1->2and0->3)
DMI x2 mode[MCH -> ICH]:(3->0,2->1)
CFG20
Digital Display Port

(SDVO/DP/iHDMI)
Concurrent with PCIe
0 = Only Digital Display Port

or PCIE is operational (Default)
1 =Digital display Port and PCIe are
operting simulataneously via the PEG port
0 =No SDVO Card Present (Default)
SDVO_CTRLDATA
SDVO Present
1 = SDVO Card Present
0 = LFP Disabled (Default)
L_DDC_DATA
Local Flat Panel

(LFP) Present
1= LFP Card Present; PCIE disabled
NOTE:
1. All strap signals are sampled with respect to the leading edge of
the (G)MCH Power OK (PWROK) signal.
2. iTPM can be disabled by a 'Soft-Strap' option in the
Flash-decriptor section of the Firmware. This 'Soft-Strap' is
activated only after enabling iTPM via CFG6.
Only one of the CFG10/CFG/12/CFG13 straps can be enabled at any time.
SMBus
EMC2102
Thermal
USB Table
KBC
USB
PCIE Routing
LANE1
RTL8111E
LANE2
MiniCard WLAN
LANE3
NC
LANE4
NC
LANE5
NC
LANE6
NC
Pair
BAT_SCL
BATTERY
Device
USB1
USB3
NC
MINIC1
WEBCAM
NC
<Core Design>
ICH9M
NC
NC
Wistron Corporation
NC

USB2
10
NC
11
NC
Title
SMBC_ICH
9LPRS365BKLFT
DDR
http://mycomp.su - . , ,
.
Reference
Size
A3
Date:
Document Number
Rev
SB
LB46E
Monday, October 25, 2010
Sheet
of
53
1D05V_S0
3D3V_S0
3D3V_S0
1
2
3D3V_CLKGEN_S0
C205
DY
2
DY
1
2
C152
SCD1U16V2ZY-2GP
R87 2
1
0R0402-PAD
C155
SCD1U16V2ZY-2GP
C224
SCD1U16V2ZY-2GP
C226
SCD1U16V2ZY-2GP
DY
C179
SCD1U16V2ZY-2GP
DY
C204
SC4D7U10V5ZY-3GP
C173
SCD1U16V2ZY-2GP
DY
1 R80
2
0R2J-2-GP
SCD1U16V2ZY-2GP
C196
SCD1U16V2ZY-2GP
4
3
2
1
C156
SCD1U16V2ZY-2GP
5
6
7
8
C176
SCD1U16V2ZY-2GP
C149
SC4D7U10V5ZY-3GP
DY
SRN10KJ-6-GP
RN61
C165
3D3V_CLKGEN_S0
DY
3D3V_CLKPLL_S0
SCD1U16V2ZY-2GP
SC1U16V3ZY-GP
SC4D7U6D3V3KX-GP
DY
3D3V_S0
C227
C221
3D3V_48MPW R_S0
R95 2
1
0R0402-PAD
R302 2
1
0R0402-PAD
3D3V_S0
RN62
GEN_XTAL_OUT
78.27034.1FL
19
27
43
52
33
56
X1
X2
GEN_XTAL_OUT_R
1
13
C230
SC27P50V2JN-2-GP
CLK48 17
CLK48_ICH
4,7
22R2J-2-GP
2
1
CPU_SEL0
R88
PCLKCLK4
24
25
SRCT1
27MHZ_NONSS 27MHZ_SS
SRCC1
20
2K2R2J-2-GP
45
44
15,16,17 SMBC_ICH
15,16,17 SMBD_ICH
7
6
13 CLK_PW RGD
1
10KR2J-3-GP
63
CK_PWRGD/PD#
8
10
11
12
13
14
PCI0/CR#_A
PCI1/CR#_B
PCI2/TME
PCI3
PCI4/27_SELECT
PCI_F5/ITP_EN
64
5
FSLB/TEST_MODE
REF0/FSLC/TEST_SEL
PCI_STOP#
CPU_STOP#
DOTT_96
3D3V_S0
CPU_SEL2
8
7
6
5
SRCT0
SRCC0
3D3V_S0
Pull high PCLKCLK4

For VGA Clock-0415
RN28
2
R89
DY
SRN10KJ-6-GP
PCLKCLK0
PCLKCLK1
PCLKCLK2
1
2
3
4
RN23
PCLKCLK2
13
CPU_SEL2_R
PCLKCLK5
3D3V_S0
1
2
3
4
CLK_ICH14
28
13
PCLK_KBC
PCLK_ICH
4,7
CPU_SEL1
8
7
6
5
CPU_SEL2_R
PCLKCLK4
PCLKCLK5
SCLK
SDATA
SRN33J-7-GP
NC#55
PCLKCLK4
UMA
10KR2J-L-GP
ICS9LPRS365BKLFT-GP-U
ICS9LPRS365BKLFT setting table

PIN NAME
DESCRIPTION
71.09365.A03
2nd = 71.08513.003
PCI0/CR#_A
PCI1/CR#_B
Byte 5, bit 5
0 = PCI1 enabled (default)
1= CR#_B enabled. Byte 5, bit 6 controls whether CR#_B controls SRC1 or SRC4 pair
Byte 5, bit 4
0 = CR#_B controls SRC1 pair (default)
1= CR#_B controls SRC4 pair
PCI2/TME
0 = Overclocking of CPU and SRC Allowed

1 = Overclocking of CPU and SRC NOT allowed
PCI3
3.3V PCI clock output
PCI4/27M_SEL
0 = Pin24 as SRC-1, Pin25 as SRC-1#, Pin20 as DOT96, Pin21 as DOT96#

1 = Pin24 as 27MHz, Pin25 as 27MHz_SS, Pin20 as SRC-0, Pin21 as SRC-0#
PCI_F5/ITP_EN
0 =SRC8/SRC8#
1 = ITP/ITP#
SRCT3/CR#_C
Byte 5, bit 3
0 = SRC3 enabled (default)
1= CR#_C enabled. Byte 5, bit 2 controls whether CR#_C controls SRC0 or SRC2 pair
Byte 5, bit 2
0 = CR#_C controls SRC0 pair (default),
1= CR#_C controls SRC2 pair
58
57
CLK_MCH_BCLK 6
CLK_MCH_BCLK# 6
NB
CPUT2_ITP/SRCT8
CPUC2_ITP/SRCC8
54
53
CLK_PCIE_LAN 23
CLK_PCIE_LAN# 23
LAN
1
EC33
1
2
CPU
CPUT1_F
CPUC1_F
DY
SRCT7/CR#_F
SRCC7/CR#_E
51
50
SRCT6
SRCC6
48
47
SRCT10
SRCC10
41
42
SRCT11/CR#_H
SRCC11/CR#_G
40
39
SRCT9
SRCC9
PCIE_REQ_LAN#_R
3
SB DMI
CLK_PCIE_ICH 13
CLK_PCIE_ICH# 13
CLK_PCIE_PEG 46
CLK_PCIE_PEG# 46
(100 MHz)
37
38
CLK_PCIE_MINI1 26
CLK_PCIE_MINI1# 26
MINI1
SRCT4
SRCC4
34
35
CLK_MCH_3GPLL 7
CLK_MCH_3GPLL# 7
NB CLK
SRCT3/CR#_C
SRCC3/CR#_D
31
32
SRCT2/SATAT
SRCC2/SATAC
28
29
CLK_PCIE_SATA 12
CLK_PCIE_SATA# 12
SB SATA
PCIE_REQ_MINI#_R
27MHZ_NONSS/SRCT1/SE1
27MHZ_SS/SRCC1/SE2
SRCT0/DOTT_96
SRCC0/DOTC_96
20
21
1
2
4
3
VGA_XIN1 50
XTAL_SSIN1 50
(27 MHz)
SRN0J-6-GP
DIS
RN76
DREFSSCLK#_R
DREFSSCLK_R
DREFCLK#_R
DREFCLK_R
1
2
3
4
8
7
6
5
DREFSSCLK# 7
DREFSSCLK 7
DREFCLK# 7
DREFCLK 7
SRN0J-7-GP
UMA
SEL2 SEL1 SEL0

FSC FSB FSA
PIN NAME
DESCRIPTION
SRCC3/CR#_D
Byte 5, bit 1
1= CR#_D enabled. Byte 5, bit 0 controls whether CR#_D controls SRC1 or SRC4 pair
Byte 5, bit 0
0 = CR#_D controls SRC1 pair (default)
1= CR#_D controls SRC4 pair
SRCC7/CR#_E
Byte 6, bit 7
0 = SRC7# enabled (default)
1= CR#_F controls SRC6
SRCT7/CR#_F
Byte 6, bit 6
1= CR#_F controls SRC8
SRCC11/CR#_G
Byte 6, bit 5
0 = SRC11# enabled (default)
1= CR#_G controls SRC9
SRCT11/CR#_H
Byte 6, bit 4
1= CR#_H controls SRC10
1
0
0
0
0
0
0
1
1
0
FSB
100M
133M
166M
200M
266M
X
533M
667M
800M
1066M
1
Wistron Corporation
Title
1
1
1
0
0
CPU
<Core Design>
Size
Clock Generator
Document Number
Rev
LB46E
A
CLK_CPU_BCLK 4
CLK_CPU_BCLK# 4
3rd = 71.00875.C03
Byte 5, bit 7
0 = PCI0 enabled (default)
1= CR#_A enabled. Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair
Byte 5, bit 6
0 = CR#_A controls SRC0 pair (default),
1= CR#_A controls SRC2 pair
DY
61
60
24
25
GND
55
R600
EC66
RN99
65
DIS 10KR2J-L-GP
CPU_SEL2_R
GND
GNDSRC
GNDSRC
GNDSRC
GNDCPU
GND
PCLKCLK4
GND48
GNDPCI
GNDREF
22
30
36
49
59
26
R599
18
15
1
4,7
DY
USB_48MHZ/FSLA
13 PM_STPPCI#
13 PM_STPCPU#
21
DOTT_96
EC62
CPUT0
CPUC0
R597
3
2
VDD96_IO
VDDPLL3_IO
VDDSRC_IO
VDDSRC_IO
VDDSRC_IO
VDDCPU_IO
4
16
9
46
62
23
VDDREF
VDD48
VDDPCI
VDDSRC
VDDCPU
VDDPLL3
R91 2
1
0R0402-PAD
82.30005.891
DY
CLK48_ICH
SC5P50V2CN-2GP
X4
X-14D31818M-35GP
PCLK_ICH
SC5P50V2CN-2GP
78.27034.1FL
SC5P50V2CN-2GP
U14
SC27P50V2JN-2-GP
C229
GEN_XTAL_IN
1
2
EC31
3D3V_CLKPLL_S0
SRN470J-3-GP
CL=20pF
0.2pF
PCLK_KBC
CLK_ICH14
3D3V_48MPW R_S0
SC5P50V2CN-2GP
8 PCIE_REQ_LAN#_R
7 PCLKCLK0
6 PCIE_REQ_MINI#_R
5 PCLKCLK1
1
2
3
4
23 PCIE_REQ_LAN#
13 SATACLKREQ#
26 PCIE_REQ_MINI#
7
CLK_MCH_OE#
Date:
D
SB
Sheet
E
of
53
H_A#[35..3]
H_A#[35..3]
H_DINV#[3..0]
CPU1A
1 OF 4
H_DINV#[3..0]
H_DSTBN#[3..0]
1
TP11 TPAD14-GP
RSVD_CPU_11
B1
H_D#[63..0]
G6
E4
BPM0#
BPM1#
BPM2#
BPM3#
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
DBR#
AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20
H_TRDY#
H_HIT#
H_HITM#
6
6
DY
H_THERMDC
XDP_BPM#5
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
XDP_DBRESET#
AFTP112
6
6
6
R63
68R2-GP
H_DSTBN#0
H_DSTBP#0
H_DINV#0
D21 CPU_PROCHOT#
A24
B25
H_THERMDA 27
H_THERMDC 27
C7
PM_THRMTRIP-A# 7,12,34
A22
A21
1
R62
DY
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
CPU_PROCHOT#_R
36
0R2J-2-GP
CLK_CPU_BCLK 3
CLK_CPU_BCLK# 3
1D05V_S0
PM_THRMTRIP#
should connect to
ICH9 and MCH
without T-ing
( No stub)
6
6
6
R179
1KR2F-3-GP
Layout Note:
"CPU_GTLREF0"
0.5" max length.
H_DSTBN#1
H_DSTBP#1
H_DINV#1
CPU_GTLREF0
BCLK0
BCLK1
C438
SC2200P50V2KX-2GP
1D05V_S0
AFTE14P-GP
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_THERMDA
THERMTRIP#
CPU1B
6
R181
2KR2F-3-GP
DY C352
TPAD14-GP
KEY_NC
3ND=62.10053.581,
62.10053.341,
62.10040.491,
62.10079.021,
62.10040.221
1D05V_S0
62.10079.001
2nd = 62.10053.581
TPAD14-GP
TPAD14-GP
3,7
3,7
3,7
TP18
TP44
TP60
CPU_SEL0
CPU_SEL1
CPU_SEL2
2 OF 4
E22
F24
E26
G22
F23
G25
E25
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25
D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
D13#
D14#
D15#
DSTBN0#
DSTBP0#
DINV0#
N22
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
DSTBN1#
DSTBP1#
DINV1#
AD26
TEST1
C23
TEST2
D25
1RSVD_CPU_12 C24
TEST4
AF26
1RSVD_CPU_13 AF1
1RSVD_CPU_14 A26
B22
B23
C21
GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
DATA GRP2
HIT#
HITM#
H_RS#0
H_RS#1
H_RS#2
DATA GRP3
C1
F3
F4
G3
G2
12
RESET#
RS0#
RS1#
RS2#
TRDY#
H_INIT#
H_LOCK# 6
H_CPURST# 6,43
H_RS#[2..0]
H4
H_BREQ#0 6
H_IERR#
BGA479-SKT6-GPU7
MISC
BSEL0
BSEL1
BSEL2
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
DSTBN2#
DSTBP2#
DINV2#
Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
DSTBN3#
DSTBP3#
DINV3#
AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
COMP0
COMP1
COMP2
COMP3
R26
U26
AA1
Y1
COMP0
COMP1
COMP2
COMP3
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#
E5
B5
D24
D6
D7
AE6
H_DSTBN#2 6
H_DSTBP#2 6
H_DINV#2 6
H_DSTBN#3 6
H_DSTBP#3 6
H_DINV#3 6
R53
R51
R45
R44
2 54D9R2F-L1-GP
XDP_TDI
R48
2 54D9R2F-L1-GP
XDP_BPM#5
R43
2 54D9R2F-L1-GP
H_CPURST#
XDP_TCK
1
1
R41
XDP_TRST#
R42
1
1
DY
1
1
1
1
2
2
2
2
27D4R2F-L1-GP
54D9R2F-L1-GP
27D4R2F-L1-GP
54D9R2F-L1-GP
H_DPRSTP# 7,12,36
H_DPSLP# 12
H_DPW R# 6
H_PW RGD 12,34
H_CPUSLP# 6
PSI#
36
BGA479-SKT6-GPU7
62.10079.001
2nd = 62.10053.581
Layout Note:
Comp0, 2 connect with Zo=27.4 ohm, make
trace length shorter than 0.5" .
Comp1, 3 connect with Zo=55 ohm, make
trace length shorter than 0.5" .
Follow Demo Circuit

R50
1
LOCK#
HCLK
XDP_TMS
CONTROL
D20
B3
TP20
F1
SC1KP50V2KX-1GP
TPAD14-GP
BR0#
IERR#
INIT#
PROCHOT#
THRMDA
THRMDC
RSVD#M4
RSVD#N5
RSVD#T2
RSVD#V3
RSVD#B2
RSVD#C3
RSVD#D2
RSVD#D22
RSVD#D3
RSVD#F6
H_DSTBP#[3..0]
Place testpoint on
H_IERR# with a GND
0.1" away
R64
56R2J-4-GP
DEFER#
DRDY#
DBSY#
THERMAL
ICH
M4
N5
T2
V3
B2
C3
D2
D22
D3
F6
H_D#[63..0]
STPCLK#
LINT0
LINT1
SMI#
H_DEFER# 6
H_DRDY# 6
H_DBSY# 6
H_DSTBP#[3..0]
1D05V_S0
H_STPCLK#
H_INTR
H_NMI
H_SMI#
D5
C6
B4
A3
H5
F21
E1
6
6
6
A20M#
FERR#
IGNNE#
H_ADS#
H_BNR#
H_BPRI#
DATA GRP1
H_A20M#
H_FERR#
H_IGNNE#
A6
A5
C4
H1
E2
G5
DATA GRP0
H_ADSTB#1
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#
A32#
A33#
A34#
A35#
ADSTB1#
ADDR GROUP 1
12
12
12
12
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
Y2
U5
R3
W6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
U2
V4
W3
AA4
AB2
AA3
V1
Side Band
Non GTL
12
12
12
K3
H2
K2
J3
L1
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
ADS#
BNR#
BPRI#
XDP/ITP SIGNALS
H_ADSTB#0
H_REQ#[4..0]
A3#
A4#
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
ADSTB0#
RESERVED
6
6
J4
L5
L4
K5
M3
N2
J1
N3
P5
P2
L2
P4
P1
R1
M1
ADDR GROUP 0
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_DSTBN#[3..0]
R213
2
51R2F-2-GP
1
R65
DY
2 TEST1
1KR2J-1-GP
1
R215
DY
2
C343
2 54D9R2F-L1-GP
Net "TEST4" as short as possible,

make sure "TEST4" routing is
reference to GND and away other
noisy signals
TEST2
1KR2J-1-GP
TEST4
1
SCD1U10V2KX-4GP
DY
2 54D9R2F-L1-GP
<Core Design>
3D3V_S0
All place within 2" to CPU

R60
XDP_DBRESET#
DY
Wistron Corporation
2
1KR2J-1-GP

1D05V_S0
Title
XDP_TDO
R47
DY
2 54D9R2F-L1-GP
CPU (1 of 2)
Size
Rev
SB
LB46E
A
Document Number
Date:
D
Sheet
E
of
53
CPU1D
VCC_CORE
VCC_CORE
DY
C62
1
2
1
2
1
2
1
2
1
2
1
2
1
2
DY
C48
SC10U6D3V5MX-3GP
DY
C381
SC10U6D3V5MX-3GP
DY
1D05V_S0
VCC_CORE
R38
100R2F-L1-GP-U
PBY160808T-121Y-GP
68.00206.021
2nd = 68.00230.041
36
36
36
36
36
36
36
H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
H_VID6
L10
C429
1
1D5V_S0
1D5V_VCCA_S0
H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
H_VID6
C66
C78
C69
C81
C82
C83
C65
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
layout note: "1D5V_VCCA_S0"

as short as possible
C84
SC4D7U6D3V3KX-GP
AE7
C384
SC10U6D3V5MX-3GP
VSSSENSE
C382
SC10U6D3V5MX-3GP
AF7
C383
SC10U6D3V5MX-3GP
VCCSENSE
C61
SC10U6D3V5MX-3GP
VID0
VID1
VID2
VID3
VID4
VID5
VID6
C90
SC10U6D3V5MX-3GP
B26
C26
AD6
AF5
AE5
AF4
AE3
AF3
AE2
C70
1D05V_S0
G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
VCCA
VCCA
C92
SC10U6D3V5MX-3GP
VCC_CORE
SC10U6D3V5MX-3GP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
TPAD14-GP
SC10U6D3V5MX-3GP
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
SCD1U10V2KX-4GP
VCC_SENSE 36
VSS_SENSE 36
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
SC10U6D3V5MX-3GP
A7
A9
A10
A12
A13
A15
A17
A18
A20
B7
B9
B10
B12
B14
B15
B17
B18
B20
C9
C10
C12
C13
C15
C17
C18
D9
D10
D12
D14
D15
D17
D18
E7
E9
E10
E12
E13
E15
E17
E18
E20
F7
F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AB9
AC10
AB10
AB12
AB14
AB15
AB17
AB18
3 OF 4
CPU1C
VCCSENSE and VSSSENSE lines

should be of equal length.
2nd = 62.10053.581
Layout Note:
R39
100R2F-L1-GP-U
BGA479-SKT6-GPU7
62.10079.001
Layout Note:
Provide a test point (with
no stub) to connect a
differential probe
between VCCSENSE and
VSSSENSE at the location
where the two 54.9ohm
resistors terminate the
55 ohm transmission line.
TP46
A4
A8
A11
A14
A16
A19
A23
AF2
B6
B8
B11
B13
B16
B19
B21
B24
C5
C8
C11
C14
C16
C19
C2
C22
C25
D1
D4
D8
D11
D13
D16
D19
D23
D26
E3
E6
E8
E11
E14
E16
E19
E21
E24
F5
F8
F11
F13
F16
F19
F2
F22
F25
G4
G1
G23
G26
H3
H6
H21
H24
J2
J5
J22
J25
K1
K4
K23
K26
L3
L6
L21
L24
M2
M5
M22
M25
N1
N4
N23
N26
P3
4 OF 4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25
TPAD14-GP
TP45
1
1
TPAD14-GP
TPAD14-GP
TP48
TP21
1
1
TPAD14-GP
TPAD14-GP
TP61
TP43
BGA479-SKT6-GPU7
62.10079.001
2nd = 62.10053.581
Wistron Corporation
Title
CPU (2 of 2)
Size
Rev
SB
LB46E
A
Document Number
Date:
D
Sheet
E
of
53
1 OF 10
NB1A
H_A#[35..3]
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
1D05V_S0
H_SWING routing Trace width and

Spacing use 10 / 20 mil
H_D#[63..0]
R239
221R2F-2-GP
H_SWING Resistors and

Capacitors close MCH
500 mil ( MAX )
1
H_SW ING
R238
100R2F-L1-GP-U
C478
SCD1U10V2KX-4GP
H_RCOMP routing Trace width and

Spacing use 10 / 20 mil
1
R226
2
24D9R2F-L-GP
H_RCOMP
Place them near to the chip ( < 0.5")
F2
G8
F8
E6
G2
H6
H2
F6
D4
H3
M9
M11
J1
J2
N12
J6
P2
L2
R2
N9
L6
M5
J3
N2
R1
N5
N6
P13
N8
L7
N10
M3
Y3
AD14
Y6
Y10
Y12
Y14
Y7
W2
AA8
Y9
AA13
AA9
AA11
AD11
AD10
AD13
AE12
AE9
AA2
AD8
AA3
AD3
AD7
AE14
AF3
AC1
AE3
AC3
AE11
AE8
AG2
AD6
H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63
HOST
H_D#[63..0]
H_SW ING
H_RCOMP
4,43 H_CPURST#
4
H_CPUSLP#
H_AVREF
A11
B11
1
R240
2KR2F-3-GP
C12
E11
C479
SCD1U16V2ZY-2GP
H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
H12
B16
G17
A9
F11
G12
E9
B10
AH7
AH6
J11
F9
H9
E12
H11
C9
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
J8
L3
Y13
Y1
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
L10
M7
AA5
AE6
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
L9
M8
AA6
AE5
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
B15
K13
F13
B13
B14
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_SWING
H_RCOMP
H_CPURST#
H_CPUSLP#
H_RS#_0
H_RS#_1
H_RS#_2
B6
F12
C8
H_RS#0
H_RS#1
H_RS#2
H_AVREF
H_DVREF
H_ADS# 4
H_ADSTB#0 4
H_ADSTB#1 4
H_BNR# 4
H_BPRI# 4
H_BREQ#0 4
H_DEFER# 4
H_DBSY# 4
CLK_MCH_BCLK 3
CLK_MCH_BCLK# 3
H_DPW R# 4
H_DRDY# 4
H_HIT# 4
H_HITM# 4
H_LOCK# 4
H_TRDY# 4
H_DSTBN#[3..0]
H_DSTBP#[3..0]
H_REQ#[4..0]
H_RS#[2..0]
H_DINV#[3..0]
H_DSTBN#[3..0]
H_DSTBP#[3..0]
H_REQ#[4..0]
H_RS#[2..0]
CANTIGA-GM-GP-U-NF
R241
1KR2F-3-GP
C5
E3
A14
C15
F16
H13
C18
M16
J13
P16
R16
N17
M13
E17
P17
F17
G20
B19
J16
E20
H16
J20
L17
A17
B17
L16
C21
J17
H20
B18
K17
B20
F21
K21
L20
H_DINV#[3..0]
1D05V_S0
H_A#[35..3]
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35
71.CNTIG.00U
<Core Design>
Wistron Corporation
Title
Size
Rev
SB
LB46E
5
Cantiga (1 of 6)_HOST
Document Number
Date:
2
Sheet
1
of
53
2 OF 10
NB1B
1D5V_S3
CLK
M_RCOMPP
PEG_CLK
PEG_CLK#
R98
DY
2 4K02R2F-GP
PM_SYNC#
H_DPRSTP#
13
PM_SYNC#
4,12,36 H_DPRSTP#
PWROK_GD
RSTIN#
PM_THRMTRIP-A#
PM_DPRSLPVR
2
100R2J-2-GP
DY
C147
SC100P50V2JN-3GP
DMI
DDR3_DRAMRST#
BG22
BH21
M_RCOMPP
M_RCOMPN
BF28
BH28
SM_RCOMP_VOH
SM_RCOMP_VOL
AV42
AR36
BF17
BC36
SM_PWROK
SM_REXT
2
499R2F-2-GP
DREFCLK
DREFCLK#
DREFSSCLK
DREFSSCLK#
B38
A38
E41
F41
16,17
F43
E43
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
AE40
AE38
AE48
AH40
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
AE35
AE43
AE46
AH42
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
AD35
AE44
AF46
AH43
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
H47
E46
G40
A40
18 GMCH_TXAOUT0+
18 GMCH_TXAOUT1+
18 GMCH_TXAOUT2+
H48
D45
F40
B40
DREFCLK 3
DREFCLK# 3
DREFSSCLK 3
DREFSSCLK# 3
C250
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2
LVDSA_DATA#_3
LVDSA_DATA_0
LVDSA_DATA_1
LVDSA_DATA_2
LVDSA_DATA_3
TVA_DAC
TVB_DAC
TVC_DAC
RN15
13
13
13
13
LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2
LVDSB_DATA#_3
B42
G38
F37
K37
UMA/DIS
8
7
6
5
1
2
3
4
LVDSB_DATA_0
LVDSB_DATA_1
LVDSB_DATA_2
LVDSB_DATA_3
F25
H25
K25
TVA_DAC
TVB_DAC
TVC_DAC
H24
SRN75J-1-GP
TV_RTN
C31
E32
TV_DCONSEL_0
TV_DCONSEL_1
DIS=66.R0036.A8L
DMI_TXP0 13
DMI_TXP1 13
DMI_TXP2 13
DMI_TXP3 13
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
L_VDD_EN
LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK
A41
H38
G37
J37
CLK_MCH_3GPLL 3
CLK_MCH_3GPLL# 3
AE41
AE37
AE47
AH39
18 GMCH_TXAOUT018 GMCH_TXAOUT118 GMCH_TXAOUT2-
DDR_VREF_S3
1R243
)RU'LVFKDQJH51WRRKP
GMCH_BLUE_1
19 GMCH_BLUE_1
13
13
13
13
E28
GMCH_RED_1
19 GMCH_RED_1
GMCH_DDCCLK
1
2
4
3
GMCH_DDCDATA
GMCH_HS
GMCH_VS
PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15
PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15
CRT_GREEN
J28
CRT_RED
G29
19 GMCH_DDCCLK
19 GMCH_DDCDATA
19 GMCH_HSYNC
19 GMCH_VSYNC
PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15
CRT_BLUE
GMCH_GREEN_1 G28
19 GMCH_GREEN_1
DMI_RXP0 13
DMI_RXP1 13
DMI_RXP2 13
DMI_RXP3 13
CRT_IRTN
H32
J32
J29
E29
L29
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_TVO_IREF
CRT_VSYNC
SRN33J-5-GP-U
GFX_VR_EN
2 CRT_IREF
1K02R2F-1-GP
1
R299
B33
B32
G33
F33
E33
UMA
PEG_CMP 2
1
49D9R2F-GP
Close to GMCH as 500 mils.

H44
J46
L44
L40
N41
P48
N44
T43
U43
Y43
Y48
Y36
AA43
AD37
AC47
AD39
PEG_RXN0 46
PEG_RXN1 46
PEG_RXN2 46
PEG_RXN3 46
PEG_RXN4 46
PEG_RXN5 46
PEG_RXN6 46
PEG_RXN7 46
PEG_RXN8 46
PEG_RXN9 46
PEG_RXN10 46
PEG_RXN11 46
PEG_RXN12 46
PEG_RXN13 46
PEG_RXN14 46
PEG_RXN15 46
H43
J44
L43
L41
N40
P47
N43
T42
U42
Y42
W47
Y37
AA42
AD36
AC48
AD40
PEG_RXP0 46
PEG_RXP1 46
PEG_RXP2 46
PEG_RXP3 46
PEG_RXP4 46
PEG_RXP5 46
PEG_RXP6 46
PEG_RXP7 46
PEG_RXP8 46
PEG_RXP9 46
PEG_RXP10 46
PEG_RXP11 46
PEG_RXP12 46
PEG_RXP13 46
PEG_RXP14 46
PEG_RXP15 46
J41
M46
M47
M40
M42
R48
N38
T40
U37
U40
Y40
AA46
AA37
AA40
AD43
AC46
GMCH_TXN0
GMCH_TXN1
GMCH_TXN2
GMCH_TXN3
GMCH_TXN4
GMCH_TXN5
GMCH_TXN6
GMCH_TXN7
GMCH_TXN8
GMCH_TXN9
GMCH_TXN10
GMCH_TXN11
GMCH_TXN12
GMCH_TXN13
GMCH_TXN14
GMCH_TXN15
C658
C620
C669
C654
C610
C667
C649
C603
C665
C646
C601
C663
C638
C599
C661
C628
1DIS
1DIS
1DIS
1DIS
1DIS
1DIS
1DIS
1DIS
1DIS
1DIS
1DIS
1DIS
1DIS
1DIS
1DIS
1DIS
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
PEG_TXN0 46
PEG_TXN1 46
PEG_TXN2 46
PEG_TXN3 46
PEG_TXN4 46
PEG_TXN5 46
PEG_TXN6 46
PEG_TXN7 46
PEG_TXN8 46
PEG_TXN9 46
PEG_TXN10 46
PEG_TXN11 46
PEG_TXN12 46
PEG_TXN13 46
PEG_TXN14 46
PEG_TXN15 46
J42
L46
M48
M39
M43
R47
N37
T39
U36
U39
Y39
Y46
AA36
AA39
AD42
AD46
GMCH_TXP0
GMCH_TXP1
GMCH_TXP2
GMCH_TXP3
GMCH_TXP4
GMCH_TXP5
GMCH_TXP6
GMCH_TXP7
GMCH_TXP8
GMCH_TXP9
GMCH_TXP10
GMCH_TXP11
GMCH_TXP12
GMCH_TXP13
GMCH_TXP14
GMCH_TXP15
C604
C657
C622
C668
C653
C609
C666
C651
C602
C664
C641
C600
C662
C633
C598
C659
1DIS
1DIS
1DIS
1DIS
1DIS
1DIS
1DIS
1DIS
1DIS
1DIS
1DIS
1DIS
1DIS
1DIS
1DIS
1DIS
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
PEG_TXP0 46
PEG_TXP1 46
PEG_TXP2 46
PEG_TXP3 46
PEG_TXP4 46
PEG_TXP5 46
PEG_TXP6 46
PEG_TXP7 46
PEG_TXP8 46
PEG_TXP9 46
PEG_TXP10 46
PEG_TXP11 46
PEG_TXP12 46
PEG_TXP13 46
PEG_TXP14 46
PEG_TXP15 46
CANTIGA-GM-GP-U-NF
71.CNTIG.00U
FOR Cantiga: 1.02k_1% ohm

Teenah: 1.3k ohm
CRT_IREF routing Trace

width use 20 mil
C34
1D05V_S0
CL_CLK
CL_DATA
CL_PWROK
CL_RST#
CL_VREF
AH37
AH36
AN36
AJ35
AH34
CL_CLK0 13
CL_DATA0 13
PWROK
13,34
CL_RST#0
13
CLPWROK_MCH 2 R111
1
0R0402-PAD
MCH_CLVREF
C231
NC
NC#BG48
NC#BF48
NC#BD48
NC#BC48
NC#BH47
NC#BG47
NC#BE47
NC#BH46
NC#BF46
NC#BG45
NC#BH44
NC#BH43
NC#BH6
NC#BH5
NC#BG4
NC#BH3
NC#BF3
NC#BH2
NC#BG2
NC#BE2
NC#BG1
NC#BF1
NC#BD1
NC#BC1
NC#F1
NC#A47
18 GMCH_TXACLKSRN0J-6-GP18 GMCH_TXACLK+
UMA
DDPC_CTRLCLK
DDPC_CTRLDATA
SDVO_CTRLCLK
SDVO_CTRLDATA
CLKREQ#
ICH_SYNC#
N28
M28
G36
E36
K36
H36
SCD1U10V2KX-4GP
4,12,34 PM_THRMTRIP-A#
13,36 PM_DPRSLPVR
B
BG48
BF48
BD48
BC48
BH47
BG47
BE47
BH46
BF46
BG45
BH44
BH43
BH6
BH5
BG4
BH3
BF3
BH2
BG2
BE2
BG1
BF1
BD1
BC1
F1
A47
16
16
17
17
TPAD14-GP
R93
1KR2F-3-GP
UMA/DIS
1
TPAD14-GP
TP34
CLK_MCH_OE# 3
MCH_ICH_SYNC# 13
R242
TSATN#
B12
MCH_TSATN# 2
1
2
GMCH_GREEN_1 3
GMCH_RED_1
4
R92
511R2F-2-GP
8
7
6
5
SRN150F-1-GP
B
DIS=66.R0036.A8L
)RU'LVFKDQJH51WRRKP
FOR Cantiga:500 ohm

Teenah: 392 ohm
1D05V_S0
RN74
56R2J-4-GP
HDA_BCLK
HDA_RST#
HDA_SDI
HDA_SDO
HDA_SYNC
RN16
GMCH_BLUE_1
2
R110
1
R211
M_ODT0
M_ODT1
M_ODT2
M_ODT3
TP76
4
3
UMA RN21
GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4
PLT_RST1#
PM_SYNC#
PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR
PM
13,34 PWROK
13,23,26,28,46
16 PM_EXTTS#0
17 PM_EXTTS#1
1
0R0402-PAD
R29
B7
N33
P32
AT40
AT11
T20
R32
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3
ME
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
BD17
AY17
BF15
AY13
RN98
1
2
T37
T36
2 4K02R2F-GP
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
GRAPHICS VID
DY
CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20
16
16
17
17
M29
C44
B43
E37
E38
C41
C40
B37
A37
PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15
VGA
R306 1
T25
R25
P25
P20
P24
C25
N24
M24
E21
C23
C24
N21
P21
T21
R20
M20
CFG16 L21
H21
P29
R28
CFG20 T28
CFG
3D3V_S0
CPU_SEL0
CPU_SEL1
CPU_SEL2
MISC
3,4
3,4
3,4
HDA
R246
80D6R2F-L-GP
M_CS#0
M_CS#1
M_CS#2
M_CS#3
GMCH_LCDVDD_ON
LIBG
1 L_LVBG
LVDS_VREFH
LVDS_VREFL
PEG_COMPI
PEG_COMPO
L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA
TV
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
M_RCOMPN
BA17
AY16
AV16
AR13
M33
K33
J33
R99
L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK
GRAPHICS
SM_VREF
SM_PWROK
SM_REXT
SM_DRAMRST#
DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
R247
80D6R2F-L-GP
2
SM_RCOMP_VOH
SM_RCOMP_VOL
16
16
17
17
SCD1U10V2KX-4GP
layout take note
SM_RCOMP
SM_RCOMP#
M_CKE0
M_CKE1
M_CKE2
M_CKE3
LCTLB_DATA
CLK_DDC_EDID
DAT_DDC_EDID
18 CLK_DDC_EDID
18 DAT_DDC_EDID
18 GMCH_LCDVDD_ON
BC28
AY28
AY36
BB36
L32
G32
M32
PCI-EXPRESS
RESERVED#BG23
RESERVED#BF23
RESERVED#BH18
RESERVED#BF18
16
16
17
17
BG23
BF23
BH18
BF18
SA_ODT_0
SA_ODT_1
SB_ODT_0
SB_ODT_1
M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3
RESERVED#AY21
AR24
AR21
AU24
AV20
L_BKLTCTL
GMCH_BL_ON
LCTLA_CLK
18 L_BKLTCTL
28 GMCH_BL_ON
AY21
C483
C484
SCD01U16V2KX-3GP SC2D2U6D3V3MX-1-GP
2
SM_RCOMP_VOL
R248
1KR2F-3-GP
SA_CS#_0
SA_CS#_1
SB_CS#_0
SB_CS#_1
16
16
17
17
RESERVED#B31
RESERVED#B2
RESERVED#M1
SA_CKE_0
SA_CKE_1
SB_CKE_0
SB_CKE_1
M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3
LVDS
B31
B2
M1
SA_CK#_0
SA_CK#_1
SB_CK#_0
SB_CK#_1
AP24
AT21
AV24
AU20
C487
SCD01U16V2KX-3GP SC2D2U6D3V3MX-1-GP
SA_CK_0
SA_CK_1
SB_CK_0
SB_CK_1
C489
RSVD
R250
3K01R2F-3-GP
SM_RCOMP_VOH
D
DDR CLK/ CONTROL/COMPENSATION
1
2
R251
1KR2F-3-GP
RESERVED#M36
RESERVED#N36
RESERVED#R33
RESERVED#T33
RESERVED#AH9
RESERVED#AH10
RESERVED#AH12
RESERVED#AH13
RESERVED#K12
RESERVED#AL34
RESERVED#AK34
RESERVED#AN35
RESERVED#AM35
RESERVED#T24
1D05V_S0
3 OF 10
NB1C
M36
N36
R33
T33
AH9
AH10
AH12
AH13
K12
AL34
AK34
AN35
AM35
T24
1D5V_S3
RN73
1
2
3
4
8LCTLA_CLK
7DAT_DDC_EDID
6 CLK_DDC_EDID
5 LCTLB_DATA
1
2
3
4
B28
B30
B29
C29
A28
8
7
6
5
GMCH_VS
GMCH_HS
GMCH_DDCDATA
GMCH_DDCCLK
SRN0J-7-GP
DIS
SRN0J-7-GP
DIS
3D3V_S0
UMA
CANTIGA-GM-GP-U-NF
1 R536
CRT_IREF
DIS 0R2J-L-GP
RN81
LCTLB_DATA
LCTLA_CLK
71.CNTIG.00U
1
2
4
3
RN75
DREFSSCLK
DREFSSCLK#
DREFCLK#
DREFCLK
1
2
3
4
SRN10KJ-5-GP
8
7
6
5
SRN0J-7-GP
3D3V_S0
DIS
RN32
Pin Name
Strap Description
Configuration
CLK_MCH_OE#
PM_EXTTS#0
PM_EXTTS#1
5
6
7
8
4
3
2
1
GMCH_BL_ON
GMCH_LCDVDD_ON
RN22
1
2
4
3
SRN100KJ-6-GP
SRN10KJ-6-GP
UMA
3D3V_S5
SCD1U16V2KX-3GP
C379
1
U18
CFG20
Digital DisplayPort
(SDVO/DP/HDMI)
Concurrent with Low = Only digital DisplayPort
PCIE
(SDVO/DP/HDMI) or
PCIE is operational (default)
38
13,28,38
S3_PWRGD
PM_SLP_S4#
B
VCC
A
Y
5
4
DY
UMA
SM_PWROK
GND
74LVC1G08GW-1-GP
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Title
Cantiga (2 of 6)_DMI/PM/CFG
Size
4
Wistron Corporation
73.01G08.L04
2nd = 73.7SZ08.AAH
3rd = 73.01G08.L03
High = Digital DisplayPort

(SDVO/DP/HDMI) and
PCIE are operating simultaneously via the PEG port
5
R103
1
2
2K37R2F-GP
LIBG
Document Number
Rev
LB46E
Date:
2
SB
Sheet
of
53
5 OF 10
NB1E
BB20
BD20
AY20
M_A_RAS# 16
M_A_CAS# 16
M_A_W E# 16
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
AM37
AT41
AY41
AU39
BB12
AY6
AT7
AJ5
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
AJ44
AT44
BA43
BC37
AW12
BC8
AU8
AM7
AJ43
AT43
BA44
BD37
AY12
BD8
AU9
AM8
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14
BA21
BC24
BG24
BH24
BG25
BA24
BD24
BG27
BF25
AW24
BC21
BG26
BH26
BH17
AY25
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_DQS[7..0]
M_A_DQS#[7..0]
M_A_A[14..0]
M_A_DM[7..0] 16
M_A_DQS[7..0] 16
M_A_DQS#[7..0] 16
M_A_A[14..0] 16
AK47
AH46
AP47
AP46
AJ46
AJ48
AM48
AP48
AU47
AU46
BA48
AY48
AT47
AR47
BA47
BC47
BC46
BC44
BG43
BF43
BE45
BC41
BF40
BF41
BG38
BF38
BH35
BG35
BH40
BG39
BG34
BH34
BH14
BG12
BH11
BG8
BH12
BF11
BF8
BG7
BC5
BC6
AY3
AY1
BF6
BF5
BA1
BD3
AV2
AU3
AR3
AN2
AY2
AV1
AP3
AR1
AL1
AL2
AJ1
AH1
AM2
AM3
AH3
AJ3
SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63
SB_BS_0
SB_BS_1
SB_BS_2
BC16
BB17
BB33
M_B_BS0 17
M_B_BS1 17
M_B_BS2 17
SB_RAS#
SB_CAS#
SB_WE#
AU17
BG16
BF14
M_B_RAS# 17
M_B_CAS# 17
M_B_W E# 17
SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7
AM47
AY47
BD40
BF35
BG11
BA3
AP1
AK2
M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7
AL47
AV48
BG41
BG37
BH9
BB2
AU1
AN6
AL46
AV47
BH41
BH37
BG9
BC2
AT2
AN5
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14
AV17
BA25
BC25
AU25
AW25
BB28
AU28
AW28
AT33
BD33
BB16
AW33
AY33
BH15
AU33
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_DM[7..0]
SA_RAS#
SA_CAS#
SA_WE#
M_B_DQ[63..0]
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
MEMORY
SA_BS_0
SA_BS_1
SA_BS_2
M_A_BS0 16
M_A_BS1 16
M_A_BS2 16
SYSTEM
17 M_B_DQ[63..0]
BD21
BG18
AT25
M_A_DM[7..0]
SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
MEMORY
AJ38
AJ41
AN38
AM38
AJ36
AJ40
AM44
AM42
AN43
AN44
AU40
AT38
AN41
AN39
AU44
AU42
AV39
AY44
BA40
BD43
AV41
AY43
BB41
BC40
AY37
BD38
AV37
AT36
AY38
BB38
AV36
AW36
BD13
AU11
BC11
BA12
AU13
AV13
BD12
BC12
BB9
BA9
AU10
AV9
BA11
BD9
AY8
BA6
AV5
AV7
AT9
AN8
AU5
AU6
AT5
AN10
AM11
AM5
AJ9
AJ8
AN12
AM13
AJ11
AJ12
SYSTEM
M_A_DQ[63..0]
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
DDR
16 M_A_DQ[63..0]
4 OF 10
NB1D
DDR
M_B_DM[7..0] 17
M_B_DQS[7..0]
M_B_DQS[7..0] 17
M_B_DQS#[7..0]
M_B_A[14..0]
M_B_DQS#[7..0] 17
M_B_A[14..0] 17
CANTIGA-GM-GP-U-NF
CANTIGA-GM-GP-U-NF
71.CNTIG.00U
71.CNTIG.00U
Wistron Corporation
Title
Size
Rev
SA
LB46E
5
8_Cantiga (3 of 6)_DDR
Document Number
Date:
2
Sheet
1
of
53
1D05V_S0_AXG
1D05V_S0_AXG
1D05V_S0
R591
NB1G
C193
UMA
C177
G9
Coupling CAP
VCC_GMCH_35
T32
VCC CORE
1
2
1
2
UMA
C175
UMA
C194
UMA
C164
1
2
1
2
1
2
1
2
POWER
VCC GFX NCTF
VCC
1D05V_S0
VCC NCTF
AV44 SM_LF1_GMCH
BA37 SM_LF2_GMCH
AM40 SM_LF3_GMCH
AV21 SM_LF4_GMCH
AY5 SM_LF5_GMCH
AM10 SM_LF6_GMCH
BB13 SM_LF7_GMCH
AM32
AL32
AK32
AJ32
AH32
AG32
AE32
AC32
AA32
Y32
W32
U32
AM30
AL30
AK30
AH30
AG30
AF30
AE30
AC30
AB30
AA30
Y30
W30
V30
U30
AL29
AK29
AJ29
AH29
AG29
AE29
AC29
AA29
Y29
W29
V29
AL28
AK28
AL26
AK26
AK25
AK24
AK23
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
CANTIGA-GM-GP-U-NF
1
2
C235
C253
C246
SCD47U16V3ZY-3GP
2
C172
C136
C140
C153
71.CNTIG.00U
SCD22U10V2KX-1GP
2
CANTIGA-GM-GP-U-NF
VCC SM LF
VCC SM
VCC GFX
SC22U6D3V5MX-2GP
1
2
DY
SCD1U10V2KX-4GP
UMA
SCD1U10V2KX-4GP
VCC_AXG_SENSE
VSS_AXG_SENSE
71.CNTIG.00U
UMA
C183
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
SC1U10V3KX-3GP
AJ14
AH14
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
SC1U10V3KX-3GP
1
1
AE33
AC33
AA33
Y33
W33
V33
U33
AH28
AF28
AC28
AA28
AJ26
AG26
AE26
AC26
AH25
AG25
AF25
AG24
AJ23
AH23
AF23
Ivcc_axg=8.7A
SCD22U10V2KX-1GP
TPAD14-GP
TPAD14-GP
C145
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
GAP-CLOSE-PWR
SCD1U10V2KX-4GP
TP33
TP32
C162
Place on the Edge
SCD1U10V2KX-4GP
C163
DY
SC1U10V3ZY-6GP
C144
1D05V_S0_AXG
SCD1U10V2KX-4GP
R516
0R2J-L-GP
DIS
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
C455
SC10U6D3V5MX-3GP
Y26
AE25
AB25
AA25
AE24
AC24
AA24
Y24
AE23
AC23
AB23
AA23
AJ21
AG21
AE21
AC21
AA21
Y21
AH20
AF20
AE20
AC20
AB20
AA20
T17
T16
AM15
AL15
AE15
AJ15
AH15
AG15
AF15
AB15
AA15
Y15
V15
U15
AN14
AM14
U14
T14
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
AG34
AC34
AB34
AA34
Y34
V34
U34
AM33
AK33
AJ33
AG33
AF33
UMA 0R5J-5-GP
DIS
SC10U6D3V5MX-3GP
1D05V_S0_AXG
6 OF 10
NB1F
1D05V_S0
2
SC10U6D3V5MX-3GP
BA36
BB24
BD16
BB21
AW16
AW13
AT13
R592
1
R518
0R2J-L-GP
SC10U6D3V5MX-3GP
SC22U6D3V5MX-2GP
C348
UMA 0R5J-5-GP
SCD1U10V2KX-4GP
C347
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
SCD1U10V2KX-4GP
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
W28
V28
W26
V26
W25
V25
W24
V24
W23
V23
AM21
AL21
AK21
W21
V21
U21
AM20
AK20
W20
U20
AM19
AL19
AK19
AJ19
AH19
AG19
AF19
AE19
AB19
AA19
Y19
W19
V19
U19
AM17
AK17
AH17
AG17
AF17
AE17
AC17
AB17
Y17
W17
V17
AM16
AL16
AK16
AJ16
AH16
AG16
AF16
AE16
AC16
AB16
AA16
Y16
W16
V16
U16
SC10U6D3V5MX-3GP
667MTS 2400mA
800MTS 3000mA
C294
SC1U6D3V2KX-GP
1
AP33
AN33
BH32
BG32
BF32
BD32
BC32
BB32
BA32
AY32
AW32
AV32
AU32
AT32
AR32
AP32
AN32
BH31
BG31
BF31
BG30
BH29
BG29
BF29
BD29
BC29
BB29
BA29
AY29
AW29
AV29
AU29
AT29
AR29
AP29
POWER
7 OF 10
1D5V_S3
place near Cantiga
Wistron Corporation
Title
Size
5
Cantiga (4 of 6)_POWER
Document Number
Rev
SB
LB46E
Date:
2
Friday, December 03, 2010
Sheet
1
of
53
3D3V_S0_DAC
1D05V_S0
1D05V_RUN_PEGPLL
Connect to VCC_CORE
VCCA_DPLLB
Connect to VCC_CORE
Imax = 300 mA
5V_S0
1D8V_S3_R
1
2
UMA
C306
VCCA_DPLLA
60.3mA
Connect to GND
UMA
1D8V_S0
VCC_AXG_NCTF
1
0R2J-L-GP
Connect to GND
M38
L37
VCCD_LVDS
VCCD_LVDS
R529
0R2J-L-GP
DIS
1
2
1
2
1
2
1
2
VTTLF
VTTLF
VTTLF
A8
L1
AB2
1
2
1
2
C251
SC10U6D3V5MX-3GP
UMA
C139
1
2
C198
C309
SC1U10V3KX-3GP
UMA
1
2
1
2
C133
C467
SCD47U6D3V2KX-GP
C218
C457
DY
DY
VTTLF1
VTTLF2
VTTLF3
CANTIGA-GM-GP-U-NF
71.CNTIG.00U
C222
C460
SC10U6D3V5MX-3GP
DY
SC10U6D3V5MX-3GP
VCC_AXG
C261
SCD1U10V2KX-4GP
SCD47U6D3V2KX-GP
Connect to GND
DG 0.7= GND
DG 2.0=1.5V
456mA
SCD47U6D3V2KX-GP
VCCA_DAC_BG
C134
SCD1U10V2KX-4GP
Connect to GND
VCCD_PEG_PLL
UMA
1D05V_S0
SCD1U10V2KX-4GP
VCCD_QDAC
Connect to 1.5-V or GND
VCCD_HPLL
C466
R528
SCD1U10V2KX-4GP
VCCA_TV_DAC
Connect to GND
VCCD_TVDAC
AA47
VCC_DMI
VCC_DMI
VCC_DMI
VCC_DMI
C308
SC1KP50V2KX-1GP
DIS
1782mA
DY
AH48
AF48
AH47
AG47
0R2J-L-GP
R535
0R2J-L-GP
1D05V_S0
157.2mA
106mA
1
AF1
VCCD_QDAC
VCC_PEG
VCC_PEG
VCC_PEG
VCC_PEG
VCC_PEG
1D8V_S0
R105
1
2
0R0603-PAD
119mA
C462
SC10U6D3V5MX-3GP
Connect to GND
L28
VCCD_TVDAC
1D8V_TXLVDS_S3
VCCA_LVDS
M25
V48
U48
V47
U47
U46
C159
SC10U6D3V5MX-3GP
1D5VRUN_QDAC
1D05V_S0
C35
B35
A35
1D5V_SUS_SM_CK_RC
SC22U6D3V5MX-2GP
Connect to GND
3D3V_HV_S0
K47
1R2F-GP
UMA
SC22U6D3V5MX-2GP
1D5V_S0_R_DAC
1 R533
2
DIS 0R2J-L-GP
R534
2
SC4D7U6D3V3KX-GP
VCC_TX_LVDS
VCC_HDA
0R2J-L-GP
UMA
BF21
BH20
BG20
BF20
UMA
A32
R82
1
C166
SCD1U10V2KX-4GP
Connect to GND
VCC_HV
VCC_HV
VCC_HV
1D5V_S3
R81
1
2
0R0603-PAD
124mA
VCCD_LVDS
50mA
35mA
C480
SC10U6D3V5MX-3GP
DY
B22
B21
A21
R532
2
PEG
C185
2
1
SCD1U10V2KX-4GP
VTTLF
Connect to GND
C481
1D8V_TXLVDS_S3_R
VCC_TX_LVDS
VCCA_TV_DAC
VCCA_TV_DAC
LVDS
VCCA_CRT_DAC
VCC_SM_CK
VCC_SM_CK
VCC_SM_CK
VCC_SM_CK
HV
B24
A24
VCC_AXF
VCC_AXF
VCC_AXF
DMI
DIS 0R2J-L-GP
1D5V_S0
TV
1 R531
Connect to GND
HDA
VCCSYNC_CRT
C514
SCD01U16V2KX-3GP
D TV/CRT
UMA
VCCA_SM_CK
VCCA_SM_CK
VCCA_SM_CK
VCCA_SM_CK
VCCA_SM_CK
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
3D3V_S0_DAC
Pin Name
R255
10R2F-L-GP
BAT54-5-GP
83.BAT54.D81
2nd = 83.BAT54.X81
1D05V_S0
AXF
1
2
1
2
1
2
Power
AP28
AN28
AP25
AN25
AN24
AM28
AM26
AM25
AL25
AM24
AL24
AM23
AL23
3D3V_HV_S0
R254
2
1
0R0402-PAD
C497
1D5V_SUS_SM_CK
C180
SCD1U10V2KX-4GP
DY
SC2D2U6D3V3MX-1-GP
SC10U6D3V5MX-3GP
DY
C184
1D05V_HV_S0 1
POWER
26mA
C178
Design Guide 0.7 connector GND;

but 2.0 connector to 1.5V supply
to power the thermal sensor----0421
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
3D3V_S0
3
322mA
SM CK
1D05V_S0
1
1
2
2nd = 68.00214.051
1D5VRUN_QDAC
C201
SCD1U10V2KX-4GP
AR20
AP20
AN20
AR17
AP17
AN17
AT16
AR16
AP16
VCCA_PEG_PLL
D18
1
SC1U10V3KX-3GP
68.00206.041
C160
SC1U10V3KX-3GP
L4
2
PBY160808T-181Y-GP
C157
SC1U10V3KX-3GP
DY
SC4D7U6D3V3KX-GP
C161
C169
SC10U6D3V5MX-3GP
1D05V_S0
A PEG
AA48
VCCA_PEG_BG
A CK
C256
SCD1U10V2KX-4GP
1D05V_RUN_PEGPLL
1D05V_S0
1D5V_S0
VSSA_LVDS
DY
A SM
AD48
UMA
720mA
180ohm 100MHz
VCCA_LVDS
C138
SCD1U10V2KX-4GP
DY
J47
1D5V_S0
0R2J-L-GP
C260
SCD1U10V2KX-4GP
J48
C135
1 R530
DIS 0R2J-L-GP
VCCA_MPLL
1D8V_TXLVDS_S3_R
R527
VCCA_HPLL
AE1
VCCA_DPLLB
M_VCCA_MPLL
VCCA_DPLLA
AD1
VTT
M_VCCA_HPLL
DIS
1D8V_TXLVDS_S3
F47
M_VCCA_DPLLB
L48
PLL
M_VCCA_DPLLA
SRN0J-6-GP
1 R525
2
DIS 0R2J-L-GP
VCCA_DAC_BG
VSSA_DAC_BG
A LVDS
C511
SCD1U10V2KX-4GP
50mA
A25
B25
CRT
1
2
1
2
2nd = 68.00084.A01
68.00331.011
1D05V_RUN_PEGPLL
1
68.00119.111
UMA
HFB1608VF-102-GP
C468
SCD1U10V2KX-4GP
SBK160808T-221Y-N-GP
M_VCCA_DAC_BG
RN96
1
4
2
3
UMA
2nd = 68.00217.521
220ohm 100MHz
5mA
C214
SCD1U10V2KX-4GP
L5
1
3D3V_S0_DAC
R271
1
M_VCCA_MPLL
1
1
2
2
1D05V_S0
SC10U6D3V5MX-3GP
68.00119.101 DY
C463
2nd = 68.00217.161
120ohm 100MHz
DY
139.2mA
D
R526
0R2J-L-GP
DIS
C213
SCD47U6D3V2KX-GP
L13
1
UMA
VCCA_CRT_DAC
VCCA_CRT_DAC
C220
SC4D7U6D3V3KX-GP
2nd = 68.00217.161
C469
SCD1U10V2KX-4GP
B27
A26
C209
SC2D2U6D3V3MX-1-GP
C464
68.00119.101
C494
U13
T13
U12
T12
U11
T11
U10
T10
U9
T9
U8
T8
U7
T7
U6
T6
U5
T5
V3
U3
V2
U2
T2
V1
U1
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
UMA
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
SC4D7U6D3V3KX-GP
M_VCCA_HPLL
852mA
8 OF 10
NB1H
SCD1U10V2KX-4GP
C492
SCD01U16V2KX-3GP
24mA
L12
3D3V_CRTDAC_S0
73mA
R256 2
1
0R0402-PAD
120ohm 100MHz
1D05V_S0
3D3V_S0_DAC
U44
VOUT
5
1
VIN
GND
EN
NC#4
UMA
1
2
3
RT9198-33GBR-GP
2
UMA
C490
SC22U6D3V5MX-2GP
UMA
74.09198.Q7F
2nd = 74.09091.J3F
EC78
SC4D7U10V3KX-GP
1D05V_S0
1
2
RN97
1
2
C284
SCD1U10V2KX-4GP
DY
4
3
M_VCCA_DPLLA
M_VCCA_DPLLB
SRN0J-6-GP
UMA
65mA
SC10U6D3V5MX-3GP
C300
SC10U6D3V5MX-3GP
UMA
65mA
C282
C297
SCD1U10V2KX-4GP
DY
UMA
Wistron Corporation
Title
Size
5
Cantiga (5 of 6)_POWER
Document Number
Rev
1M
LB46E
Date:
2
Friday, December 03, 2010
Sheet
1
10
of
53
10 OF 10
NB1J
VSS
AM36
AE36
P36
L36
J36
F36
B36
AH35
AA35
Y35
U35
T35
BF34
AM34
AJ34
AF34
AE34
W34
B34
A34
BG33
BC33
BA33
AV33
AR33
AL33
AH33
AB33
P33
L33
H33
N32
K32
F32
C32
A31
AN29
T29
N29
K29
H29
F29
A29
BG28
BD28
BA28
AV28
AT28
AR28
AJ28
AG28
AE28
AB28
Y28
P28
K28
H28
F28
C28
BF26
AH26
AF26
AB26
AA26
C26
B26
BH25
BD25
BB25
AV25
AR25
AJ25
AC25
Y25
N25
L25
J25
G25
E25
BF24
AD12
AY24
AT24
AJ24
AH24
AF24
AB24
R24
L24
K24
J24
G24
F24
E24
BH23
AG23
Y23
B23
A23
AJ6
BA16
VSS
AU16
AN16
N16
K16
G16
E16
BG15
AC15
W15
A15
BG14
AA14
C14
BG13
BC13
BA13
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AN13
AJ13
AE13
N13
L13
G13
E13
BF12
AV12
AT12
AM12
AA12
J12
A12
BD11
BB11
AY11
AN11
AH11
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Y11
N11
G11
C11
BG10
AV10
AT10
AJ10
AE10
AA10
M10
BF9
BC9
AN9
AM9
AD9
G9
B9
BH8
BB8
AV8
AT8
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AH8
Y8
L8
E8
B8
AY7
AU7
AN7
AJ7
AE7
AA7
N7
J7
BG6
BD6
AV6
AT6
AM6
M6
C6
BA5
AH5
AD5
Y5
L5
J5
H5
F5
BE4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
BC3
AV3
AL3
R3
P3
F3
BA2
AW2
AU2
AR2
AP2
AJ2
AH2
AF2
AE2
AD2
AC2
Y2
M2
K2
AM1
AA1
P1
H1
VSS
VSS
VSS
VSS
U24
U28
U25
U29
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
AF32
AB32
V32
AJ30
AM29
AF29
AB29
U26
U23
AL20
V20
AC19
AL17
AJ17
AA17
U17
NCTF_VSS_SCB#BH48
NCTF_VSS_SCB#BH1
NCTF_VSS_SCB#A48
NCTF_VSS_SCB#C1
NCTF_VSS_SCB#A3
BH48
BH1
A48
C1
A3
VSS NCTF
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NCTF TEST PIN:

A3,C1,A48,BH1,BH48
AU48
AR48
AL48
BB47
AW47
AN47
AJ47
AF47
AD47
AB47
Y47
T47
N47
L47
G47
BD46
BA46
AY46
AV46
AR46
AM46
V46
R46
P46
H46
F46
BF44
AH44
AD44
AA44
Y44
U44
T44
M44
F44
BC43
AV43
AU43
AM43
J43
C43
BG42
AY42
AT42
AN42
AJ42
AE42
N42
L42
BD41
AU41
AM41
AH41
AD41
AA41
Y41
U41
T41
M41
G41
B41
BG40
BB40
AV40
AN40
H40
E40
AT39
AM39
AJ39
AE39
N39
L39
B39
BH38
BC38
BA38
AU38
AH38
AD38
AA38
Y38
U38
T38
J38
F38
C38
BF37
BB37
AW37
AT37
AN37
AJ37
H37
C37
BG36
BD36
AK15
AU36
BG21
L12
AW21
AU21
AP21
AN21
AH21
AF21
AB21
R21
M21
J21
G21
BC20
BA20
AW20
AT20
AJ20
AG20
Y20
N20
K20
F20
C20
A20
BG19
A18
BG17
BC17
AW17
AT17
R17
M17
H17
C17
VSS SCB
9 OF 10
NB1I
NC#E1
NC#D2
NC#C3
NC#B4
NC#A5
NC#A6
NC#A43
NC#A44
NC#B45
NC#C46
NC#D47
NC#B47
NC#A46
NC#F48
NC#E48
NC#C48
NC#B48
1
1
1
1
1
TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP
TP71
TP67
TP74
TP65
TP66
E1
D2
C3
B4
A5
A6
A43
A44
B45
C46
D47
B47
A46
F48
E48
C48
B48
Wistron Corporation
Title
CANTIGA-GM-GP-U-NF
CANTIGA-GM-GP-U-NF
71.CNTIG.00U
71.CNTIG.00U
Cantiga (6 of 6)
Document Number
Date:
Friday, October 29, 2010
Rev
SB
LB46E
5
Size
Sheet
1
11
of
53
C76
RTC_X1
X2
X-32D768KHZ-34GPU
R193
2
1MR2J-1-GP
C396
SC1U16V3ZY-GP
RTC1
1
C281
SCD1U16V2ZY-2GP
C392
SC1U16V3ZY-GP
20.F1267.003
2nd = 20.F0984.003
RTC_RST#
SRTC_RST#
INTRUDER#
A25
F20
C22
RTCRST#
SRTCRST#
INTRUDER#
INTVRMEN
LAN100_SLP
B22
A22
INTVRMEN
LAN100_SLP
E25
GLAN_CLK
TPAD30
TP50
LAN_RSTYNCC13
G84
near DIMM door
GLAN_COMP place within 500 mil of ICH9M
RTCX1
RTCX2
F14
G13
D14
GAP-OPEN
1R207
B10
GLAN_DOCK#/GPIO56
B28
B27
GLAN_COMPI
GLAN_COMPO
ACZ_BIT_CLK_R
ACZ_SYNC_R
AF6
AH4
HDA_BIT_CLK
HDA_SYNC
ACZ_RST#_R
AE7
HDA_RST#
2 GLAN_COMP
24D9R2F-L-GP
25 ACZ_SDATAIN0
3D3V_S0
ACZ_SDATAOUT_R
TP62 TPAD14-GP
1
R228
HDA_DOCK_RST#
DY
HDA_DOCK_EN#
2
8K2R2J-3-GP
28,31 SATA_LED#
RTC_AUX_S5
HDD
20
20
20
20
SATA_RXN0
SATA_RXP0
SATA_TXN0
SATA_TXP0
C55
C56
C58
C57
ODD
21
21
21
21
SATA_RXN1
SATA_RXP1
SATA_TXN1
SATA_TXP1
C285
C286
C289
C288
1
1
1
1
1
1
1
1
LAN_RXD0
LAN_RXD1
LAN_RXD2
LAN_TXD0
LAN_TXD1
LAN_TXD2
GLAN_DOCK#
13 GLAN_DOCK#
FWH4/LFRAME#
K3
LDRQ0#
LDRQ1#/GPIO23
J3
J1
A20GATE
A20M#
AF4
AG4
AH3
AE5
HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3
AG5
HDA_SDOUT
AG7
AE8
HDA_DOCK_EN#/GPIO33
HDA_DOCK_RST#/GPIO34
AG8
SATALED#
2
2
2
2
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
SATA_RXN0_C
SATA_RXP0_C
SATA_TXN0_C
SATA_TXP0_C
AJ16
AH16
AF17
AG17
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
2
2
2
2
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
SATA_RXN1_C
SATA_RXP1_C
SATA_TXN1_C
SATA_TXP1_C
AH13
AJ13
AG14
AF14
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
RTC_AUX_S5
K5
K4
L6
K2
LAN_RSTSYNC
D13
D12
E13
1D5V_S0
FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
28
28
28
28
H_DPSLP#
LPC_LFRAME# 28
LDRQ0#
3D3V_LDRQ1_S0
N7
AJ27
1
1
TPAD14-GP
TPAD14-GP
TP58
TP12
KA20GATE 28
H_A20M# 4
DPRSTP#
DPSLP#
AJ25
AE23
H_DPRSTP#
FERR#
AJ26
H_FERR#_R
1
1224 modify RN54
H_DPRSTP# 4,7,36
H_DPSLP# 4
1D05V_S0
RN54
CPUPWRGD
AD22
H_PW RGD 4,34
IGNNE#
AF25
H_IGNNE#
INIT#
INTR
RCIN#
AE22
AG25
L3
H_INIT# 4
H_INTR 4
KBRCIN# 28
NMI
SMI#
AF23
AF24
H_NMI 4
H_SMI# 4
STPCLK#
AH27
THRMTRIP#
AG26
H_THERMTRIP_R
PECI
AG27
ICH_TP8
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
AH11
AJ11
AG12
AF12
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
AH9
AJ9
AE10
AF10
SATA_CLKN
SATA_CLKP
AH18
AJ18
SATARBIAS#
SATARBIAS
AJ7
AH7
PM_THRMTRIP-A#
H_THERMTRIP_R
4
2
54D9R2F-L1-GP
Layout note: R373 needs to placed

within 2" of ICH9, R379 must be
placed within 2" of R373 w/o stub
CLK_PCIE_SATA# 3
CLK_PCIE_SATA 3
SATARBIAS
2
1
R227
24D9R2F-L-GP
1D05V_S0
Place within 500 mils of

ICH9 ball
3D3V_S0
DY
RN55
SRN10KJ-5-GP
3
4
Low=Disable
H_INIT#_G
1D05V_S0
DY R229
TP25 TPAD14-GP
1
2
1
High=Enable
R222
200R2F-L-GP
1 DY
2
H_PW RGD
H_STPCLK# 4
ICH9M-GP-NF
INTVRMEN
H_FERR#_R
C
R199
330KR2F-L-GP
LAN100_SLP
8
7
6
5
SRN56J-5-GP
integrated VccSus1_05,VccSus1_5,VccCL1_5
INTVRMEN
1
2
3
4
H_FERR#
71.ICH9M.00U
R200
330KR2F-L-GP
R223
56R2J-4-GP
DY
2
3
4
RTC_X2
C23
C24
2
1
DY
2
1
1 OF 6
SB1A
2
SC15P50V2JN-2-GP
R121
RTC_BAT
1
2
1KR2J-1-GP
C77
1
RN51
SRN20KJ-GP-U
RTC
LPC
83.R0304.B81
LAN / GLAN
CPU
CH715FPT-GP
2nd = 83.R2004.C81
1D05V_S0
C391
SC1U16V3ZY-GP
3
2
RTC_BAT_R
ACES-CON3-4-GP-U
R57
20MR3-GP
82.30001.661
IHDA
RTC_AUX_S5
SATA
D16
3D3V_AUX_S5
SC15P50V2JN-2-GP
integrated VccLan1_05VccCL1_05
DY
LAN100_SLP
High=Enable
Low=Disable
R198
0R2J-2-GP
RN63
ACZ_RST#_R
ACZ_SDATAOUT_R
ACZ_SYNC_R
ACZ_BIT_CLK_R
DY
Q24
C
FW H_INIT# 1
TP70 TPAD14-GP
MMBT3904-3-GP
1
2
3
4
EC73
SC10P50V2JN-4GP
EC65
SC10P50V2JN-4GP
DY
DY
SRN47J-4-GP
8
7
6
5
25 ACZ_RST#_AUDIO
25 ACZ_SDATAOUT_AUDIO
25 ACZ_SYNC_AUDIO
25 ACZ_BITCLK_AUDIO
H_INIT#
DY
R197
0R2J-2-GP
<Core Design>
Wistron Corporation

Title
Size
ICH9-M (1 of 4)_SATA/HDA/RTC
Document Number
Rev
SB
LB46E
Date:
Sheet
5
12
of
53
3 OF 6
SB1C
2 OF 6
3D3V_S0
27,36 VGATE_PWRGD
R209 2
1
0R0402-PAD
TPAD14-GP
R225
10KR2J-3-GP
TP22 TPAD14-GP
1 R194
PLT_RST1# 7,23,26,28,46
PCLK_ICH 3
28
28
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5
INT_PIRQE#
INT_PIRQF#
INT_PIRQG#
INT_PIRQH#
GAP-OPEN
RP4
PCI_REQ#3
INT_PIRQF#
INT_PIRQG#
PCI_SERR#
3D3V_S0
1
2
3
4
5
10
9
8
7
6
TP68
INT_PIRQD#
PCI_IRDY#
PCI_TRDY#
ECSCI#_1
25
ACZ_SPKR
7 MCH_ICH_SYNC#
TP51
SRN8K2J-2-GP-U
10
9
8
7
6
TPAD14-GP
INT_SERIRQ
PCI_DEVSEL#
PCI_STOP#
PCI_FRAME#
PERN2
PERP2
PETN2
PETP2
J29
J28
K27
K26
PERN3
PERP3
PETN3
PETP3
G29
G28
H27
H26
SPI_CS#1
USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5
USB_OC#6
USB_OC#7
USB_OC#8
USB_OC#9
USB_OC#10
USB_OC#11
R73
PERN4
PERP4
PETN4
PETP4
E29
E28
F27
F26
PERN5
PERP5
PETN5
PETP5
C29
C28
D27
D26
PERN6/GLAN_RXN
PERP6/GLAN_RXP
PETN6/GLAN_TXN
PETP6/GLAN_TXP
D23
D24
F23
D25
E23
USB_OC#0
USB_OC#1
A20
SST
AG19
AH21
AG21
A21
C12
C21
AE18
K1
AF8
AJ22
A9
D19
L1
AE19
AG22
AF21
AH24
A8
TACH1/GPIO1
TACH2/GPIO6
TACH3/GPIO7
GPIO8
LAN_PHY_PW R_CTRL/GPIO12
ENERGY_DETECT/GPIO13
TACH0/GPIO17
GPIO18
GPIO20
SCLOCK/GPIO22
GPIO27
GPIO28
SATACLKREQ#/GPIO35
SLOAD/GPIO38
SDATAOUT0/GPIO39
SDATAOUT1/GPIO48
GPIO49
GPIO57/CLGPIO5
M7
AJ24
B21
AH20
AJ20
AJ21
SPKR
MCH_SYNC#
TP3
PW M0
PW M1
PW M2
N4
N5
N6
P6
M1
N2
M4
M3
N3
N1
P5
P3
USB_RBIAS_PN AG2
AG1
DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
V27
V26
U29
U28
DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0
7
7
7
7
DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP
Y27
Y26
W 29
W 28
DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1
7
7
7
7
DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP
AB27
AB26
AA29
AA28
DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2
7
7
7
7
DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP
AD27
AD26
AC29
AC28
DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3
7
7
7
7
DMI_CLKN
DMI_CLKP
DMI_ZCOMP
DMI_IRCOMP
USBP0N
USBP0P
USBP1N
USBP1P
SPI_CLK
USBP2N
SPI_CS0#
USBP2P
SPI_CS1#/GPIO58/CLGPIO6 USBP3N
USBP3P
SPI_MOSI
USBP4N
SPI_MISO
USBP4P
USBP5N
OC0#/GPIO59
USBP5P
OC1#/GPIO40
USBP6N
OC2#/GPIO41
USBP6P
OC3#/GPIO42
USBP7N
OC4#/GPIO43
USBP7P
OC5#/GPIO29
USBP8N
OC6#/GPIO30
USBP8P
OC7#/GPIO31
USBP9N
OC8#/GPIO44
USBP9P
OC9#/GPIO45
USBP10N
OC10#/GPIO46
USBP10P
OC11#/GPIO47
USBP11N
USBP11P
USBRBIAS
USBRBIAS#
USB
22D6R2F-L1-GP
B13
PM_BATLOW#_R
PWRBTN#_ICH
RSMRST#_SB
BAS16-6-GP
3
83.00016.K11
2
PW RBTN#
R3
LAN_RST#
D20
RSMRST#
D22
CK_PW RGD
R5
CLK_PWRGD 3
CLPW ROK
R6
PWROK
SATA
GPIO
SLP_M#
B16
CL_CLK0
CL_CLK1
F24
B19
CL_DATA0
CL_DATA1
F22
C19
CL_VREF0
CL_VREF1
C25
A19
CL_RST0#
CL_RST1#
F21
D18
GPIO24/MEM_LED
GPIO10/SUS_PW R_ACK
GPIO14/AC_PRESENT
GPIO9/W OL_EN
A16
C18
C11
C20
PM_SLP_M#
TP4
T26
T25
CLK_PCIE_ICH# 3
CLK_PCIE_ICH 3
AF29
AF28
DMI_IRCOMP_R
AC5
AC4
AD3
AD2
AC1
AC2
AA5
AA4
AB2
AB3
AA1
AA2
W5
W4
Y3
Y2
W1
W2
V2
V3
U5
U4
U1
U2
USBPN0 22
USBPP0 22
USBPN2
USBPP2
USBPN3
USBPP3
USBPN4
USBPP4
22
22
26
26
18
18
USBPN9 22
USBPP9 22
8
7
6
5
3D3V_S5
1
2
3
4
SMLINK0
SMLINK1
RSMRST#_SB
1
2
3
4
5
3D3V_S5
CL_DATA0 7
CL_VREF0_ICH
CL_VREF1_ICH
CL_RST#0
RP7
1D5V_S0
10
9
8
7
6
1
2
3
4
5
3D3V_S5
PWROK
TPAD14-GP
TP3
GPIO24 1
GPIO10
GPIO14
GPIO9
1
C390
R55
3K24R2F-GP
TPAD14-GP
TP54
10
9
8
7
6
USB_OC#5
SMB_LINK_ALERT#
GPIO10
SMB_ALERT#
10
9
8
7
6
USB_OC#4
DBRESET#
USB_OC#3
USB_OC#6
DY
R205
453R2F-1-GP
R56
453R2F-1-GP
DY
RP6
3D3V_S5
USB_OC#8
USB_OC#9
USB_OC#10
USB_OC#11
3D3V_S5
1
2
3
4
5
SRN10KJ-L3-GP
10
9
8
7
6
3D3V_S5
SB_GPIO13
GPIO14
B
GLAN_DOCK# 12
SRN10KJ-L3-GP
GPIO57
SRN10KJ-L3-GP
R224
24D9R2F-L-GP
R195
1
2
0R2J-2-GP
DY
USB
Pair
Device
USB1
USB3
NC
MINIC1
BOOT BIOS Strap
WEBCAM
PCI_GNT#0
NC
NC
NC
NC
D15
USB2
10
NC
11
NC
RSMRST#_SB
1
3
28 RSMRST#_KBC
0
1
1
BOOT BIOS Location
1
0
1
SPI
PCI
LPC(Default)
A16 swap override strap

PCI_GNT#3
BAT54-5-GP
83.BAT54.D81
2nd = 83.BAT54.X81
3rd = 83.00054.Z81
<Core Design>
low = A16 swap override enable

high = default
PCI_GNT#0
SPI_CS#1
PCI_GNT#3
GNT0 and SPI_CS#1
have a weak internal pull up
R196
100KR2J-1-GP
SPI_CS#1
1
R210
1
R212
1
R208
1KR2J-1-GP
2
DY
1KR2J-1-GP
2
DY
1KR2J-1-GP
2
DY
Wistron Corporation
Title
ICH9-M (2 of 4)_PCIE/USB/DMI
Size
Date:
Document Number
Rev
SB
LB46E
71.ICH9M.00U
4
3D3V_S5
3D3V_S5
RP2
1
2
3
4
5
R204
3K24R2F-GP
SRN10KJ-L3-GP
USB_OC#2
USB_OC#7
PM_RI#
PCIE_WAKE#
SRN10KJ-6-GP
SATA0GP
SATA1GP
GPIO36
GPIO37
3D3V_S0
7,34
TPAD14-GP
DY
USB_OC#1
PM_BATLOW#_R
ECSWI#
USB_OC#0
PM_PWRBTN# 28
CL_CLK0 7
C75
RP1
PM_DPRSLPVR 7,36
71.ICH9M.00U
RN5
ICH9M-GP-NF
BATLOW #
TXN2
TXP2
L29
L28
M27
M26
MINICARD1
22
22
VRMPW RGD
7,34
R216 1
DY 2
100KR2J-1-GP
D17
1
1
1
PERN1
PERP1
PETN1
PETP1
PCI-Express
C418 SCD1U10V2KX-5GP 2
N29
N28
P27
P26
Direct Media Interface
PCIE_RXN2
PCIE_RXP2
PCIE_TXN2
PCIE_TXP2
1
1
TXN1
TXP1
SPI
26
26
26
26
D21
No Reboot Strap
SPKR
LOW = Defaule
High=No Reboot
4 OF 6
SB1D
W AKE#
SERIRQ
THRM#
PWROK
PM_DPRSLPVR
M2
ICH9M-GP-NF
SRN8K2J-2-GP-U
PCIE_RXN1
PCIE_RXP1
PCIE_TXN1
PCIE_TXP1
1 ICH_TP3
GPIO49 should be pulled down to

GND only when using Teenah. When
using Cantiga, this ball should
be left as No Connect.
3D3V_S0
LAN
23
23
23
23
SDATAOUT1
1 GPIO49
GPIO57
TPAD14-GP
G20
INT_PIRQH#
PCI_REQ#0
INT_PIRQC#
INT_PIRQB#
3D3V_S0
PW ROK
DPRSLPVR/GPIO16
TP53 TPAD14-GP
SCD1U10V2KX-4GP
3D3V_S0
1
2
3
4
5
TP19
TP63
TP69
3 SATACLKREQ#
3D3V_S0
SRN8K2J-2-GP-U
RP3
PCI_REQ#2
PCI_REQ#1
SDATAOUT1
PM_CLKRUN#
1 GPIO12
SB_GPIO13
PSW_CLR#
1 GPIO18
1 GPIO20
1 GPIO22
CLKRUN#
S4_STATE#1
SCD1U10V2KX-4GP
3D3V_S0
10
9
8
7
6
SB_GPIO1
TP52
TPAD14-GP
TPAD14-GP
TPAD14-GP
ICH_TP7
G61
71.ICH9M.00U
1
2
3
4
5
TP64
EC_TMR
ECSCI#_1
ECSWI#
28
DY 0R2J-2-GP
C10
C405
SC100P50V2JN-3GP
S4_STATE#/GPIO26
TP57 TPAD14-GP
DY
E20
M5
AJ23
23 PCIE_WAKE#
28 INT_SERIRQ
27
THRM#
PIRQA#
PIRQB#
PIRQC#
PIRQD#
RP5
PCI_PERR#
INT_PIRQE#
PCI_LOCK#
INT_PIRQA#
L4
TPAD14-GP
H4
K6
F2
G2
STP_PCI#
STP_CPU#
28 PM_CLKRUN#
ICH_PME#
Interrupt I/F
SMBALERT#/GPIO11
A14
E19
PM_SLP_S3# 28,34,38,39,44
PM_SLP_S4# 7,28,38
PCI_DEVSEL#
PCI_PERR#
PCI_LOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PM_STPPCI#
PM_STPCPU#
SLPS5#
3
3
TP55 TPAD14-GP
C16
E16
G17
PCI_IRDY#
PCI_PAR
A17
PM_SUS_CLK 27
SUSCLK
SLP_S3#
SLP_S4#
SLP_S5#
PMSYNC#/GPIO0
C14 PLT_RST#_R
D4
R2
SMB_ALERT#
SUS_STAT#/LPCPD#
SYS_RESET#
CLK_ICH14 3
CLK48_ICH 3
PLTRST#
PCICLK
PME#
M6
H1
AF3
P1
D3
E3
R1
C6
E4
C2
J4
A4
F5
D7
TP59
PM_SYNC#
CLK14
CLK48
IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#
RI#
D8
B4
D6
A5
R4
G19
SATA0GP
SATA1GP
GPIO36
GPIO37
AH23
AF19
AE21
AD20
TPAD14-GP
C/BE0#
C/BE1#
C/BE2#
C/BE3#
F19
1 PM_SUS_STAT#
DBRESET#
SATA0GP/GPIO21
SATA1GP/GPIO19
SATA4GP/GPIO36
SATA5GP/GPIO37
PM_RI#
PCI_REQ#3
PCI_GNT#3
SMBCLK
SMBDATA
LINKALERT#/GPIO60/CLGPIO4
SMLINK0
SMLINK1
SMB
PCI_REQ#2
ICH9M-GP-NF
C
G16
A13
SMB_LINK_ALERT# E17
SMLINK0
C17
SMLINK1
B18
SMB_CLK
SMB_DATA
Clocks
15
15
PCI_REQ#0
PCI_GNT#0
PCI_REQ#1
SYS GPIO
Power MGT
F1
G4
B6
A7
F13
F12
E6
F6
J5
E1
J6
C4
REQ0#
GNT0#
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55
MISC
GPIO
Controller Link
INT_PIRQA#
INT_PIRQB#
INT_PIRQC#
INT_PIRQD#
PCI
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
D11
C8
D9
E12
E9
C9
E10
B7
C7
C5
G11
F8
F11
E7
A3
D2
F10
D5
D10
B3
F7
C3
F3
F4
C1
G7
H7
D1
G5
H6
G1
H3
SB1B
Sheet

1
13
of
53
1
2
1
2
VccLan1D05
2
1
C385
DY
SCD1U10V2KX-4GP
80mA
C397
SC4D7U6D3V3KX-GP
1D5V_S0
C421
SC10U6D3V5MX-3GP
DY
3D3V_S0
C408
SCD1U10V2KX-4GP
1mA
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
A10
A11
VCCLAN1_05
VCCLAN1_05
A12
B12
VCCLAN3_3
VCCLAN3_3
A27
VCCGLANPLL
D28
D29
E26
E27
VCCGLAN1_5
VCCGLAN1_5
VCCGLAN1_5
VCCGLAN1_5
A26
VCCGLAN3_3
SCD1U10V2KX-4GP
23mA
1D5V_S0
C73
1
2
1
1
68.1R220.10D
DY
C435
SC4D7U6D3V3MX-2GP
1
2
1D05V_S0
1D05V_S0
1
2
1
2
C419
SC4D7U6D3V3KX-GP
AD8
VCCSUS1_5
F18
VCCCL1_5
VCCCL3_3
VCCCL3_3
1
2
1
2
1
2
3D3V_S0
11mA
3D3V_S5
C470
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
3D3V_S5
C445
C432
C399
C401
SCD1U10V2KX-4GP
C394
DY
VCCSUS3_3=212mA
C437
SCD1U10V2KX-4GP
DY
G22 VccSus1_05[3]
G23 VccSus1_5[3] 1
TP56 TPAD14-GP
3D3V_S5
T1
T2
T3
T4
T5
T6
U6
U7
V6
V7
W6
W7
Y6
Y7
T7
1D5V_S5
AF1
C410
SCD1U10V2KX-4GP
A18
D16
D17
E22
1D5V_S5
VCCCL1_05
11mA
C475
SCD1U10V2KX-4GP
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
C412
DY
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
C471
SCD1U10V2KX-4GP
C417
DY
3D3V_S0
C436
2
1
2
1D5V_S0
2
IND-1D2UH-10-GP
2mA
C465
SCD1U10V2KX-4GP
DY
3D3V_S0
C411
SCD1U10V2KX-4GP
A24
B24
Wistron Corporation
Title
ICH9M-GP-NF
71.ICH9M.00U
C448
SC4D7U6D3V3KX-GP
5
C404
3D3V_S0
2
VCCPSUS
1
2
1
CORE
VCCUSBPLL
23mA
C442
GLAN POWER
SCD1U10V2KX-4GP
DY
2
C409
19mA in S0;78mA in S3/S4/S5
DY
AA7
AB6
AB7
AC6
AC7
VCC1_5_A
VCC1_5_A
VCC1_5_A
USB CORE
SCD1U10V2KX-4GP
3D3V_S0
C451
SCD1U10V2KX-4GP
VCC1_5_A
VCC1_5_A
C407
DY
AC12
AC13
AC14
VCCPUSB
2
1
2
1
2
VCC1_5_A
G10
G9
L11
C403
AC8 VccSus1_05
F17
VCCSUS1_5
C400
SCD1U10V2KX-4GP
VCC1_5_A
VCC1_5_A
AC21
AJ3
C402
SCD1U10V2KX-4GP
VCC1_5_A
AC18
AC19
AJ4
DY
SCD1U10V2KX-4GP
AC9
AJ5
C473
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCCSUS1_05
VCCSUS1_05
C406
SCD1U10V2KX-4GP
AC11
AD11
AE11
AF11
AG10
AG11
AH10
AJ10
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
C395
48mA
1 R221
2
0R0603-PAD
DY
3D3V_S0
VCCHDA
VCCSUSHDA
ATX
DY
DY
USBPLL=11mA
C454
SCD1U10V2KX-4GP
VCCSATAPLL
ARX
C472
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1D5V_S0
C413
SC1U16V3ZY-GP
SC1U16V3ZY-GP
C458
AC16
AD15
AD16
AE15
AF15
AG15
AH15
AJ15
1
C440
2
C452
SC4D7U6D3V3KX-GP
C117
SCD1U16V2ZY-2GP
C74
SCD1U10V2KX-4GP
B9
F9
G3
G6
J2
J7
K7
DY
VCC3_3=308mA
AJ19
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCCP_CORE
1
2
1.34A
AD19
AF20
AG24
AC20
1D5V_S0
PCI
1
2
1
2
1
A
K
R72
100R2J-2-GP
V5REF_S5
RB751V-40-3-GP
D7
83.R2004.C8F
AC10
VCC3_3
VCC3_3
VCC3_3
VCC3_3
C474
SCD1U10V2KX-4GP
C447
SCD1U10V2KX-4GP
2mA
VCC3_3
C444
SCD1U10V2KX-4GP
5V_S5
AJ6
SCD1U10V2KX-4GP
3D3V_S5
VCC3_3
C423
C431
SCD01U16V2KX-3GP
SCD1U10V2KX-4GP
Layout Note:
Place near ICH9
AG29
C441
1
2
1
2
1
2
1
2
1
2
1
1
A
K
1
2
C72
SCD1U16V2ZY-2GP
VCC3_3
C422
SCD1U10V2KX-4GP
C477
AB23
AC23
DY
1D5V_DMIPLL_ICH_S0
W23 1D05V_DMI_ICH_S0
Y23
V_CPU_IO
V_CPU_IO
C439
SCD1U10V2KX-4GP
C476
SC10U6D3V5MX-3GP
VCCDMI
VCCDMI
DY
SCD1U10V2KX-4GP
68.1R220.10D
R29
C434
SCD1U10V2KX-4GP
R54
100R2J-2-GP
VCCDMIPLL
1D05V_S0
SCD1U10V2KX-4GP
2
IND-1D2UH-10-GP
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
1.63A
Layout Note:Place near ICH9M
SC10U6D3V5MX-3GP
RB751V-40-3-GP
D6
83.R2004.C8F
1D5V_APLL_S0
L14
V5REF_SUS
A15
B15
C15
D15
E15
F15
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18
VCCA3GP
V5REF_S0
C
SC1U16V3ZY-GP
2mA
1D5V_S0
AA24
AA25
AB24
AB25
AC24
AC25
AD24
AD25
AE25
AE26
AE27
AE28
AE29
F25
G25
H24
H25
J24
J25
K24
K25
L23
L24
L25
M24
M25
N23
N24
N25
P24
P25
R24
R25
R26
R27
T24
T27
T28
T29
U24
U25
V24
V25
U23
W24
W25
K23
Y24
Y25
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
SCD1U10V2KX-4GP
47mA
5V_S0
V5REF
SCD1U10V2KX-4GP
C461
SCD1U10V2KX-4GP
*Within a given well, 5VREF needs to be up before the

corresponding 3.3V rail
3D3V_S0
AE1
VCCRTC
SCD1U10V2KX-4GP
DY
SCD1U10V2KX-4GP
C453
V5REF_S5
A6
SCD1U10V2KX-4GP
C388
A23
SCD1U10V2KX-4GP
C443
SCD1U10V2KX-4GP
C415
DY
SC4D7U6D3V3KX-GP
DY
SCD1U10V2KX-4GP
C459
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C414
V5REF_S0
6 OF 6
SCD1U10V2KX-4GP
646mA
6uA in G3
SCD1U10V2KX-4GP
1D5V_S0
SCD1U10V2KX-4GP
C389
SB1F
RTC_AUX_S5
Size
ICH9-M (3 of 4)_POWER
Document Number
Rev
SB
LB46E
Date: Friday, December 03, 2010
Sheet
1
14
of
53
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
H5
J23
J26
J27
AC22
K28
K29
L13
L15
L2
L26
L27
L5
L7
M12
M13
M14
M15
M16
M17
M23
M28
M29
N11
N12
N13
N14
N15
N16
N17
N18
N26
N27
P12
P13
P14
P15
P16
P17
P2
P23
P28
P29
P4
P7
R11
R12
R13
R14
R15
R16
R17
R18
R28
T12
T13
T14
T15
T16
T17
T23
B26
U12
U13
U14
U15
U16
U17
AD23
U26
U27
U3
V1
V13
V15
V23
V28
V29
V4
V5
W26
W27
W3
Y1
Y28
Y29
Y4
Y5
AG28
AH6
AF2
B25
NCTF_VSS#A1
NCTF_VSS#A2
NCTF_VSS#B1
NCTF_VSS#A29
NCTF_VSS#A28
NCTF_VSS#B29
NCTF_VSS#AJ1
NCTF_VSS#AJ2
NCTF_VSS#AH1
NCTF_VSS#AJ28
NCTF_VSS#AJ29
NCTF_VSS#AH29
A1
A2
B1
A29
A28
B29
AJ1
AJ2
AH1
AJ28
AJ29
AH29
3D3V_S5
3D3V_S0
8
7
6
5
RN50
SRN2K2J-2-GP
1
2
3
4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NCTF TEST PIN:

A1,A2,B1,A28,A29,B29
AH1,AJ1,AJ2,AH29,AJ28,AJ29
AA26
AA27
AA3
AA6
AB1
AA23
AB28
AB29
AB4
AB5
AC17
AC26
AC27
AC3
AD1
AD10
AD12
AD13
AD14
AD17
AD18
AD21
AD28
AD29
AD4
AD5
AD6
AD7
AD9
AE12
AE13
AE14
AE16
AE17
AE2
AE20
AE24
AE3
AE4
AE6
AE9
AF13
AF16
AF18
AF22
AH26
AF26
AF27
AF5
AF7
AF9
AG13
AG16
AG18
AG20
AG23
AG3
AG6
AG9
AH12
AH14
AH17
AH19
AH2
AH22
AH25
AH28
AH5
AH8
AJ12
AJ14
AJ17
AJ8
B11
B14
B17
B2
B20
B23
B5
B8
C26
C27
E11
E14
E18
E2
E21
E24
E5
E8
F16
F28
F29
G12
G14
G18
G21
G24
G26
G27
G8
H2
H23
H28
H29
5 OF 6
SB1E
5V_S0
Q7
13
SMB_CLK
SMBC_ICH 3,16,17
2
2N7002KDW -GP
13
SMB_DATA
84.2N702.A3F
SMBD_ICH 3,16,17
SMBUS
1
1
1
1
1
1
1
1
1
1
1
1
TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP
TP1
TP2
TP10
TP8
TP7
TP9
TP30
TP31
TP28
TP29
TP27
TP26
Wistron Corporation
Title
ICH9-M (4 of 4)
Size
ICH9M-GP-NF
71.ICH9M.00U
Rev
SB
LB46E
A
Document Number
Date:
D
Sheet
E
15
of
53
3D3V_S0
C428
SC1U6D3V2KX-GP
C426
SC1U6D3V2KX-GP
C424
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C292
8 M_A_DQS#[7..0]
8 M_A_DQS[7..0]
7
7
116
120
M_ODT0
M_ODT1
M_VREF_CA_DIMM0
M_VREF_DQ_DIMM0
126
1
30
7,17 DDR3_DRAMRST#
MA_VTT
203
204
DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
ODT0
ODT1
VREF_CA
VREF_DQ
RESET#
VTT1
VTT2
SA0_DIM0
SA1_DIM0
C427
SCD1U10V2KX-5GP
2
1
C290
SC2D2U6D3V3KX-GP
1D5V_S3
75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124
SODIMM A DECOUPLING
2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
205
206
1D5V_S3
C239
C237
C219
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
C195
C200
C174
C181
C191
C223
C234
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
C171
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
77
122
125
12
29
47
64
137
154
171
188
199
197
201
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
3,15,17
3,15,17
10
27
45
62
135
152
169
186
NC#1
NC#2
NC#/TEST
SMBD_ICH
SMBC_ICH
3D3V_S0
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
-1 0107
2 0R0402-PAD
2 0R0402-PAD
PM_EXTTS#0 7
SCD1U10V2KX-5GP
MA_VTT
R230 1
R220 1
2
SCD1U10V2KX-5GP
R253
0R0603-PAD
R234 1
0R0402-PAD
SCD1U10V2KX-5GP
0D75V_S0
TS#_DIMM0
C154
SC2D2U6D3V3KX-GP
SODIMM0_1_SMB_DATA_R
SODIMM0_1_SMB_CLK_R
198
C190
SCD1U10V2KX-5GP
200
202
M_VREF_DQ_DIMM0
SA0
SA1
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
C206
SC2D2U6D3V3KX-GP
VDDSPD
M_CLK_DDR1 7
M_CLK_DDR#1 7
M_A_DM[7..0] 8
11
28
46
63
136
153
170
187
2
1
R52 1
0R0603-PAD
DIMM0_VREF_CADQ
C217
SCD1U10V2KX-5GP
SDA
SCL
EVENT#
102
104
M_VREF_CA_DIMM0
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
R231
10KR2J-3-GP
R131 1
0R0603-PAD
DIMM0_VREF_CADQ
3
R236
10KR2J-3-GP
DY
M_CLK_DDR0 7
M_CLK_DDR#0 7
R132
1KR2F-3-GP
101
103
If SA0 DIM0 = 1, SA1_DIM0 = 0

SO-DIMMA SPD Address is 0xA2
SO-DIMMA TS Address is 0x32
SA1_DIM0
DIMM0_VREF_CADQ
DY
CK1
CK1#
BA0
BA1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
M_CKE0 7
M_CKE1 7
R165
0R0603-PAD
5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194
73
74
Note:
If SA0 DIM0 = 0, SA1_DIM0 = 0
SO-DIMMA SPD Address is 0xA0
SO-DIMMA TS Address is 0x30
SA0_DIM0
7
7
1
R127
1KR2F-3-GP
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
M_CS#0
M_CS#1
109
108
M_A_BS0
M_A_BS1
M_A_DQ[63..0]
DDR_VREF_S3
1D5V_S0
M_A_BS2
CK0
CK0#
114
121
8
8
8
CKE0
CKE1
DY 10KR2J-3-GP
M_A_RAS# 8
M_A_WE# 8
M_A_CAS# 8
CS0#
CS1#
R235
NP1
NP2
110
113
115
NP1
NP2
RAS#
WE#
CAS#
TP149
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16/BA2
98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78
79
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
DIM1
M_A_A[14..0]
Place these Caps near SO-DIMMA.
H = 4mm
DDR3-204P-52-GP
62.10017.P61
<Core Design>
Wistron Corporation
21F,88,Sec.1,Hsin Tai Wu Rd.,Hsichih,
Taipei Hsien 221, Taiwan, R.O.C
Title
16_DDR3-SODIMM1
A
Size
A2
Document Number
Date:
Rev
SA
LB46E
E
Sheet
16
of
53
2010/9/27 Changed
116
120
M_VREF_CA_DIMM1
M_VREF_DQ_DIMM1
R515
0R0603-PAD
30
7,16 DDR3_DRAMRST#
MB_VTT
MB_VTT
203
204
1
2
2
-1 0107
DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
ODT0
ODT1
VREF_CA
VREF_DQ
RESET#
VTT1
VTT2
1
2
2
3,15,16
3,15,16
199
197
201
77
122
125
SA0_DIM1
SA1_DIM1
C293
SCD1U10V2KX-5GP
C291
SC2D2U6D3V3KX-GP
1D5V_S3
75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124
SODIMM B DECOUPLING
2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
205
206
1
2
1D5V_S3
C655
C558
C544
C545
C546
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
C212
C187
C170
C188
C189
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
C168
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SMBD_ICH
SMBC_ICH
3D3V_S0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
2 0R0402-PAD
2 0R0402-PAD
PM_EXTTS#1 7
NC#1
NC#2
NC#/TEST
Place these caps

close to VTT1 and
VTT2.
126
1
R502 1
R509 1
R499 1
0R0402-PAD
12
29
47
64
137
154
171
188
M_ODT2
M_ODT3
7
7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
TS#_DIMM1
SCD1U10V2KX-5GP
0D75V_S0
10
27
45
62
135
152
169
186
SODIMM1_1_SMB_DATA_R
SODIMM1_1_SMB_CLK_R
198
SCD1U10V2KX-5GP
8 M_B_DQS[7..0]
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
SA0
SA1
200
202
SCD1U10V2KX-5GP
8 M_B_DQS#[7..0]
VDDSPD
M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7
R259
DY 10KR2J-3-GP
SDA
SCL
EVENT#
11
28
46
63
136
153
170
187
2
1
C167
SC2D2U6D3V3KX-GP
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
R260
10KR2J-3-GP
2
1
M_VREF_DQ_DIMM1
C215
SCD1U10V2KX-5GP
M_CLK_DDR3 7
M_CLK_DDR#3 7
M_B_DM[7..0] 8
R58 1
0R0603-PAD
DIMM1_VREF_CADQ
C606
SC2D2U6D3V3KX-GP
M_CLK_DDR2 7
M_CLK_DDR#2 7
102
104
M_VREF_CA_DIMM1
C647
SCD1U10V2KX-5GP
101
103
R459 1
0R0603-PAD
DIMM1_VREF_CADQ
CK1
CK1#
SA0_DIM1
-1 0107
CK0
CK0#
Note:
SO-DIMMB SPD Address is 0xA4
SO-DIMMB TS Address is 0x34
SA1_DIM1
DY
M_CKE2 7
M_CKE3 7
R466
1KR2F-3-GP
M_CS#2 7
M_CS#3 7
73
74
DIMM1_VREF_CADQ
DY
CS0#
CS1#
CKE0
CKE1
BA0
BA1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
R292
10KR2J-3-GP
M_B_RAS# 8
M_B_WE# 8
M_B_CAS# 8
114
121
R465
0R0603-PAD
5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194
NP1
NP2
110
113
115
1
R455
1KR2F-3-GP
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
NP1
NP2
RAS#
WE#
CAS#
M_B_BS0
M_B_BS1
M_B_DQ[63..0]
DDR_VREF_S3
1D5V_S0
109
108
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16/BA2
8
8
8
M_B_BS2
98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78
79
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
TP150
8
3D3V_S0
DIM2
M_B_A[14..0]
DDR3-204P-57-GP
C645
SC1U6D3V2KX-GP
C644
SC1U6D3V2KX-GP
C643
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C642
H =8mm
1
62.10017.Q41
SO-DIMMB is placed farther from

the Processor than SO-DIMMA
<Core Design>
Wistron Corporation
Title
A
17_DDR3-SODIMM2
LB46E
Size
A2
Document Number
Date:

E
Sheet
Rev
SA
17
of
53
LCD/CCD CONN
1
2
C186
TXAOUT1TXAOUT1+
TXAOUT2TXAOUT2+
SC4D7U10V5ZY-3GP
CLK_DDC_EDID_1
DAT_DDC_EDID_1
TXAOUT0TXAOUT0+
1
2
3
VOUT
VIN
GND
NC#3 EN/EN#
C542
SC4D7U10V5ZY-3GP
CAM_EN 28
RT9711-APBG-GP
74.09711.A7F
2nd = 74.05240.A7F
CLKCLK+
USBPP4_R
USBPN4_R
R84 1
R85 1
2 0R0402-PAD
2 0R0402-PAD
USBPP4
USBPN4
13
13
R126 UMA
2
1
0R2J-2-GP
BRIGHTNESS_CN
BLON_OUT_1
R133 2
BRIGHTNESS_CN
BLON_OUT
1 33R2J-2-GP
DCBATOUT
L_BKLTCTL 7
1 R521
2
DIS 0R2J-L-GP
BRIGHTNESS 28
BLON_OUT
BLON_OUT 28
F5
DCBATOUT_LCD1
EC24
3D3V_S0
C197
2
1
SCD1U50V3ZY-1-GP
20.F1020.040
EC93
SCD1U50V3ZY-1-GP
RN34
SRN2K2J-1-GP
3
4
JAE-CON40-GP
1
POLYSW -1D1A24V-GP-U
SC10U25V5KX-GP
48
CCD_PW R
47
3D3V_S0
U54
3D3V_S0
46
3D3V_CAM_S0
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
NP2
49
45
C504
SC10U10V5ZY-1GP
44
C501
SCD1U25V3ZY-1GP
43
41
NP1
1
LCD1
42
LCDVDD
RN90
49 GPU_TXACLK+
49 GPU_TXACLK49 GPU_TXAOUT2+
49 GPU_TXAOUT2-
1
2
3
4
8
7
6
5
CLK+
CLKTXAOUT2+
TXAOUT2-
RN80
CLK_DDC_EDID_1
DAT_DDC_EDID_1
R340 1
R339 1
2 0R0603-PAD
2 0R0603-PAD
CLK_DDC_EDID_R
DAT_DDC_EDID_R
DIS
1
2
4
3
SRN0J-7-GP
DIS
7 GMCH_TXAOUT27 GMCH_TXAOUT2+
7 GMCH_TXACLK7 GMCH_TXACLK+
8
7
6
5
7 GMCH_LCDVDD_ON
1 R523
2
0R2J-L-GP
UMA
1
2
Layout 40 mil
LCDVDD
3D3V_S0
LCDVDD_ON_1
SB
C303
RN95
GMCH_TXAOUT0GMCH_TXAOUT0+
GMCH_TXAOUT1GMCH_TXAOUT1+
1
2
3
4
8
7
6
5
EN
GND
VOUT
VIN#5
VIN#4
4
C307
RT9724GB-GP
SC4D7U6D3V3KX-GP
DIS
1
2
3
1 R522
DIS 0R2J-L-GP
50 NV_LCDVDD_ON
TXAOUT1+
TXAOUT1TXAOUT0+
TXAOUT0-
SC4D7U6D3V3KX-GP
8
7
6
5
SRN0J-7-GP
7
7
7
7
7
7
UMA
RN93
1
2
3
4
DAT_DDC_EDID
CLK_DDC_EDID
U30
UMA
GPU_TXAOUT1+
GPU_TXAOUT1GPU_TXAOUT0+
GPU_TXAOUT0-
4
3
SRN0J-6-GP
SRN0J-7-GP
49
49
49
49
50
50
RN79
RN94
1
2
3
4
NV_LCD_EDID_CLK
NV_LCD_EDID_DAT
SRN0J-6-GP
74.09724.09F
2nd = 74.05285.07F
DY
SRN0J-7-GP
UMA
<Core Design>
Wistron Corporation
Title
LCD CONN
Size
Document Number
Rev
SB
LB46E
Date:
Sheet
18
of
53
Hsync & Vsync level shift

RN85
1
2
3
4
48 CRT_RED_1
48 CRT_GREEN_1
48 CRT_BLUE_1
CRT_RED_R
CRT_GREEN_R
CRT_BLUE_R
8
7
6
5
SRN0J-7-GP
DIS
RN87
RN86
1
2
3
4
7 GMCH_BLUE_1
7 GMCH_GREEN_1
7 GMCH_RED_1
48 CRT_HSYNC
48 CRT_VSYNC
8
7
6
5
DIS
1
2
CRT_HSYNC1
4
3
SRN0J-6-GP
SRN0J-7-GP
RN84
UMA
7 GMCH_VSYNC
7 GMCH_HSYNC
CRT_VSYNC1
UMA
1
2
4
3
SRN0J-6-GP
DDC_CLK & DATA level shift
CRT I/F & CONNECTOR
3D3V_S0
R537
CRT_RED_R
2
2
3
4
5
6
7
8
9
10
CRT_GREEN
CRT_BLUE
1
0R2J-L-GP
2 R538
1
0R2J-L-GP
2 R539
1
0R2J-L-GP
CRT_GREEN_R
CRT_BLUE_R
F3
CRT_VSYNC1
CRT_HSYNC1
5V_CRT_S0
69.50007.691
2nd = 69.50007.771
AFTE14P-GP
AFTP214
2N7002KDW -GP
AFTP215
ACES-CON10-13-GP
C505
SCD01U16V2KX-3GP
RN89
20.F0772.010
50 CRT_DDCCLK
50 CRT_DDCDATA
2nd = 21.D0339.110
1
2
DIS
4
3
1
1
1
1
1
1
1
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTP207
AFTP208
AFTP209
AFTP210
AFTP211
AFTP212
AFTP213
1
2
CLK_DDC1_5
1
Q5
RN88
7 GMCH_DDCDATA
7 GMCH_DDCCLK
4
CLK_DDC1_5_1
SRN0J-6-GP
CRT_RED
CRT_GREEN
CRT_BLUE
CRT_VSYNC1
CRT_HSYNC1
CLK_DDC1_5
DAT_DDC1_5
RN37
3
4
1
AFTE14P-GP
5V_CRT_DDC
FUSE-1D1A6V-4GP-U
SRN4K7J-8-GP
RB551V-30-2GP
D4
83.5R003.08F
SRN4K7J-8-GP
12
1
RN38
CLK_DDC1_5
DAT_DDC1_5
CRT_RED
2
1
5V_CRT_S0
2
1
11
5V_S0
CRT1
3
4
Layout Note:
* Must be a ground return path between this ground and the ground on
the VGA connector.
Pi-filter & 150 Ohm pull-down resistors should be as close as to CRT
CONN. RGB will hit 75 Ohm first, pi-filter, then CRT CONN.
84.2N702.A3F
DAT_DDC1_5_1
4
3
DAT_DDC1_5
SRN0J-6-GP
UMA
<Core Design>
Wistron Corporation
Title
Size
Rev
SB
LB46E
A
CRT Connector
Document Number
Date:
D
Sheet
E
19
of
53
SATA Connector
HDD1
C
23
NP1
1
2
3
4
5
6
7
SATA_TXP0 12
SATA_TXN0 12
SATA_RXN0 12
SATA_RXP0 12
AFTE14P-GP
AFTP179
C182
TC14
AMP-CON22-4-GP-U2
20.F0796.022
AFTP178
AFTE14P-GP
SCD1U16V2ZY-2GP
5V_S0
SC10U10V5ZY-1GP
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
NP2
24
2nd = 20.F0839.022
SATA_TXP0
SATA_TXN0
1
1
AFTE14P-GP AFTP180
AFTE14P-GP AFTP181
SATA_RXN0
SATA_RXP0
1
1
AFTE14P-GP AFTP182
AFTE14P-GP AFTP183
<Core Design>
Wistron Corporation
Title
Size
HDD
Rev
LB46E
5
Document Number
Date:
2
SB
Sheet
1
20
of
53
SATA ODD Connector

D
ODD1
8
NP1
S1
S2
S3
S4
S5
S6
S7
12 SATA_TXP1
12 SATA_TXN1
12 SATA_RXN1
12 SATA_RXP1
C
5V_S0
1
ODD_DP
TPAD14-GP AFTP136
ODD_MD
1
1
TPAD14-GP AFTP184
TPAD14-GP AFTP140
TC15
SC10U10V5ZY-1GP
SCD1U16V2ZY-2GP
C274
TPAD14-GP AFTP185
P1
P2
P3
P4
P5
P6
NP2
9
SKT-SATA7P-6P-16-GP
62.10065.D01
2nd = 62.10065.D61
AFTP189 AFTE14P-GP
AFTP190 AFTE14P-GP
1
1
SATA_TXP1
SATA_TXN1
AFTP191 AFTE14P-GP
AFTP186 AFTE14P-GP
1
1
SATA_RXN1
SATA_RXP1
<Core Design>
A
Wistron Corporation
Title
ODD
Size
Document Number
Rev
LB46E
Date: Monday, December 27, 2010
5
SB
Sheet
1
21
of
53
5V_USB1_S0
USB2
USB2
8
6
1
AFTP158 AFTE14P-GP
1
1
1 R298
USBPN9
USBPP9
2
2
USB_9USB_9+
2
3
4
5
7
0R0402-PAD
5V_S5
AFTE14P-GP
TP192
1
1
USB_9USB_9+
C245
SC4D7U10V3KX-GP
SKT-USB8-3-GP-U
22.10321.B81
28 USB_PWR_EN#
GND
VIN
VIN
EN#
VOUT
VOUT
VOUT
FLG#
8
7
6
5
USB_OC#1 13
RT9715DGF-GP
AFTP156 AFTE14P-GP
AFTP157 AFTE14P-GP
5V_USB2_S0
U49
1
2
3
4
13
13
R301
0R0402-PAD
74.09715.079
EC44
SCD1U16V2ZY-2GP
DY
2nd = 74.00547.A79
5V_USB2_S0
8
6
1
1
13
13
0R0402-PAD
R336 2
1
1
2
0R0402-PAD
R310
USBPN0
USBPP0
USB_0USB_0+
1
1
USB_0USB_0+
AFTE14P-GP
AFTP194
2
EC96
1
2
78.10491.4FL
2
3
4
5
7
1
AFTP144 AFTE14P-GP
AFTP145 AFTE14P-GP
80.15715.12L
2nd = 77.C1571.09L
EC71
SC1000P50V3JN-GP-U
TC23
ST150U6D3VBM-2-GP
USB1
SCD1U16V2ZY-2GP
DY
USB1
5V_USB1_S0
AFTE14P-GP
AFTP193
100 mil
DY
C
SKT-USB8-3-GP-U
22.10321.B81
2ND = 22.10321.E01
5V_S5
C142
SC4D7U10V3KX-GP
>1A
USBPN2
USBPP2
0R0402-PAD
R337 2
1
1
2
0R0402-PAD
R338
1
USBPN2USBPP2+
28 USB_PWR_EN#
GND
VIN
VIN
EN#
VOUT
VOUT
VOUT
FLG#
8
7
6
5
USB_OC#0 13
RT9715DGF-GP
74.09715.079
EC32
SCD1U16V2ZY-2GP
DY
2
3
4
13
13
AFTP159 AFTE14P-GP
USB3
5V_USB1_S0
U12
1
2
3
4
5V_USB2_S0
Connect to USB BD
2nd = 74.00547.A79
AFTP160
AFTE14P-GP
AFTP161
AFTP162
AFTE14P-GP
AFTE14P-GP
1
1
USBPN2USBPP2+
ACES-CON4-17-GP-U
20.F1621.004
2ND = 20.F1561.004
5V_USB1_S0
EC69
EC74
1
2
DY
SC1000P50V3JN-GP-U
TC22
SCD1U16V2ZY-2GP
ST150U6D3VBM-1-GP
100 mil
DY
<Core Design>
A
Wistron Corporation
Title
USB
Size
Document Number
Rev
LB46E
Date:
5
SB
Sheet

1
22
of
53
3D3V_LAN_S5
1D05V_LAN_S5
3D3V_S0
main pwr if have no ASF
R3123
1 R3130
LAN_RSET
RTL_ISOLATE#
R3136
1KR2J-1-GP
GPO
LAN_XTAL0
LAN_XTAL1
LAN_XTAL1
XTAL-25MHZ-102-GP
82.30020.851
1MR3J-L-GP
2K49R2F-GP
R3119
15KR2J-1-GP
MDI0+
MDI0-
1D05V_LAN_S5
24
24
Pin-XTAL2 is External Clock Input

Pin.
24
R3121 is need when using external 24
clock source.
MDI1+
MDI1-
1D05V_LAN_S5
MDI2+
MDI2-
1D05V_LAN_S5
24
24
MDI3+
MDI3-
1
2
3
4
5
6
7
8
9
10
11
12
MDIP0
MDIN0
AVDD10
MDIP1
MDIN1
AVDD10
MDIP2
MDIN2
AVDD10
MDIP3
MDIN3
AVDD33
2
3D3V_LAN_VDDSREG
REGOUT
VDDREG
VDDREG
ENSWREG
EEDI/SDA
LED3/EEDO
EECS/SCL
DVDD10
LANWAKE#
DVDD33
ISOLATE#
PERST#
36
35
34
33
32
31
30
29
28
27
26
25
3D3V_LAN_S5
1D05V_LAN_REGOUT
High:Link up
Low:Link down
GPO
0R2J-2-GP
LAN_ENSW REG
LAN_EEDI
1 R3125
LAN_EECS
RTL_ISOLATE#
1D05V_LAN_S5
PCIE_W AKE# 13
DY
3D3V_LAN_S5
PLT_RST1#
DVDD10
SMBCLK
SMBDATA
CLKREQ#
HSIP
HSIN
REFCLK_P
REFCLK_N
EVDD10
HSOP
HSON
GND
3D3V_LAN_S5
GND
24
24
U11
49
2 3D3V_LAN_S5
R3102 0ohm PAD For Enable Switch Regulator.

R3103 0ohm Res For Disable Switch Regulator.
1 R3120
2 1KR2J-1-GP
R3122
LAN_EECS
10KR2J-3-GP
2
10KR2J-3-GP
2
10KR2J-3-GP
2
1
R3126
R3124
0R2J-2-GP
LAN_EEDI
1
R3128
SMB_LAN_DATA 1
7,13,26,28,46
C3148
SC12P50V2JN-3GP
AVDD33
AVDD33
RSET
AVDD10
CKXTAL2
CKXTAL1
AVDD33
DVDD10
LED0
DVDD33
GPO/SMBALERT
LED1/EESK
C3103
SC15P50V2JN-2-GP
48
47
46
45
44
43
42
41
40
39
38
37
1
2
1D05V_LAN_S5 3D3V_LAN_S5
LAN_XTAL0
X3
25MHz XTAL
The SM DATA with 10K ohm pull GND.
Make sure PCIE_Wake# & PCIE_CLK_LAN_RQ1#connected to 10K

resistor pull high close to PCH side
13
14
15
16
17
18
19
20
21
22
23
24
RTL8111E-VB-GR-GP
71.08111.I03
1D05V_LAN_S5
SMB_LAN_DATA
0R0402-PAD 1 R3121 2LAN_CLKREQ#
3 PCIE_REQ_LAN#
13 PCIE_TXP1
13 PCIE_TXN1
3 CLK_PCIE_LAN
3 CLK_PCIE_LAN#
1D05V_LAN_EVDD10
1
2 PCIE_RXP1_C
13
PCIE_RXP1
C3145
SCD1U10V2KX-4GP
1
2
1
2
LAN_PWR_ON_C2
Q3104
2N7002A-7-GP
Layout Note: Close to U3101

pin C3113&C3114
84.2N702.E31
28 LAN_PW R_ON
C3113 value modify to 1uF

capacitor
3D3V_LAN_S5
C3150
SCD1U16V2ZY-2GP
C3149
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C3128
C3139
SCD22U10V2KX-1GP
R3132
10KR2J-3-GP
1D05V_LAN_EVDD10
1
C3138
SCD1U16V2ZY-2GP
1
C3134
C3133
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C3132
SCD1U16V2ZY-2GP
C3131
1
2
C3130
SCD1U16V2ZY-2GP
1
2
20100720
C3129
SCD1U16V2ZY-2GP
C3146
SC4D7U6D3V3KX-GP
L19
IND-4D7UH-192-GP
C3153
LAN_PW R_ON_T
1 R3131 2
0R0402-PAD
SC1U10V2KX-1GP
1D05V_LAN_REGOUT
Layout Note: Close to U3101 pin C3106 ~ C3112

B
D
AO3419L-GP
1D05V_LAN_S5
S
Q3103
R3133
100KR2J-1-GP
C3152
2 PCIE_RXN1_C
SCD1U10V2KX-4GP
-1 0114
C3151
SC1U10V2KX-1GP
SCD1U10V2KX-4GP
1
C3147
PCIE_RXN1
DY
0R3J-0-U-GP
3D3V_S5
SC1U10V2KX-1GP
13
3D3V_LAN_S5
R3135
3D3V_LAN_VDDSREG
C3137
<Core Design>
SC4D7U6D3V3KX-GP
1
SCD1U25V3KX-GP
Layout Note: Close to U3101 pin C3115 ~ C3120
SCD1U16V2ZY-2GP
1
2
SCD1U16V2ZY-2GP
C3136
C3144
SCD1U16V2ZY-2GP
C3143
C3142
SCD1U16V2ZY-2GP
1
C3141
C3140
SCD1U16V2ZY-2GP
1
C3135
SCD1U16V2ZY-2GP
1 R3134 2
0R0603-PAD
Wistron Corporation
Title
RTL8111E
C3122 change to 4.7uF X5R

type capacitor
Size
A3
5
Date:
2
Document Number
Rev
SB
LB46E
Sheet
1
23
of
53
1.route on bottom as differential pairs.

2.Tx+/Tx- are pairs. Rx+/Rx- are pairs.
3.No vias, No 90 degree bends.
4.pairs must be equal lengths.
5.6mil trace width,12mil separation.
6.36mil between pairs and any other trace.
7.Must not cross ground moat,except
RJ-45 moat.
LAN Connector
XF1
XRF_TDC
1
2
23
MDI3-
MDI3-
23
MDI3+
MDI3+
23
MDI2-
MDI2-
23
MDI2+
MDI2+
23
MDI1-
MDI1-
7
8
23
MDI1+
MDI1+
23
MDI0-
MDI0-
9
10
11
23
MDI0+
MDI0+
12
3
4
5
1CT:1CT
1CT:1CT
24
23
MCT2
RJ45_8
22
21
20
RJ45_7
MCT1
RJ45_5
LAN1
1CT:1CT
1CT:1CT
19
RJ45_4
18
17
MCT4
RJ45_6
16
15
14
RJ45_3
MCT3
RJ45_2
13
RJ45_1
AFTP201
AFTE14P-GP
RJ45_1
AFTP195
AFTP196
AFTP197
AFTP198
AFTP199
AFTP203
AFTP205
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
1
1
1
1
1
1
1
RJ45_2
RJ45_3
RJ45_4
RJ45_5
RJ45_6
RJ45_7
RJ45_8
AFTP206
AFTE14P-GP
9
NP1
1
2
3
4
5
6
7
8
NP2
10
RJ45-8P-45-GP
62.10044.631
XFORM-24P-15-GP
MCT3
MCT4
MCT1
MCT2
8
7
6
5
68.05009.301
2ND = 68.IH601.301
SCD01U50V2KX-1GP
C8
MCT_R
C5
SC1KP2KV6KX-GP
1
2
3
4
RN1
SRN75J-1-GP
<Core Design>
Wistron Corporation
Title
Size
A3
A
Date:
D
LAN Connector
Document Number
Rev
SB
LB46E
Sheet
E
24
of
53
5V_S0
R116
AUD_3D3V
0R3J-0-U-GP
3D3V_S0
2
G
ACZ_SDATA_OUT
10KR2F-2-GP
NC#25
NC#24
PORTA_R
PORTA_L
DMIC_CLK
DMIC_1/2
AUD_C_BIAS
PORTC_R
PORTC_L
C616 1
C277 1
AUD_AVEE
AUD_FLY_N
AUD_FLY_P1
2
C279
SC1U10V2KX-1GP
41
GND
RIGHT+
1
C304
Only needed if speaker

connector is physically far from
audio codec. When in doubt, it's
always a good idea to have
population option.
AUD_SENSE_A
R96
10KR2F-2-GP
AUD_SENSE_PORT_A
EMIC1
AUD_SPK_R+_L
L34 FCM1608KF-1-GP
AUD_PORTC_R
AUD_PORTC_R_C
100R3J-4-GP
1
AUD_PORTC_L
AUD_PORTC_L_C
AUD_SENSE_PORT_C
R3137
AUD_SPK_R-_L
AUD_PORTC_R_C_1
AUD_SPK_L+_L
AUD_AGND
AUD_AGND
NP2
NP1
5
4
3
6
2
1
AUDIO-JK222-GP-U
EC515
DY
C87
AUD_AGND
C86
1AUD_SENSE_PORT_C
1AUD_PORTC_R_C_1
1AUD_PORTC_L_C_1
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTP104
AFTP356
AFTP367
C85
SC470P50V2KX-3GP
AUD_SPK_L-_L
1
AFTE14P-GP
AFTP78
100R3J-4-GP
SCD1U10V2KX-4GP
L35 FCM1608KF-1-GP
AUD_PORTC_L_C_1
2
R3138
SC470P50V2KX-3GP
Place EMI
close to audio codec.
AUD_SENSE_PORT_C
39K2R2F-L-GP
MIC CONN.
SC470P50V2KX-3GP
R94
C271
RIGHT-
16
14
LEFT13
11
R97
5K11R2F-L1-GP
AUD_PORTA_R
AUD_PORTA_L
L26
R219
AUD_SPK_R+
1
2 AUD_SPK_R+_1 1
PBY160808T-121Y-GP
0R2J-2-GP
EC67
SC1KP50V2KX-1GP
L21
R182
AUD_SPK_R-_1 1
1
2
PBY160808T-121Y-GP
0R2J-2-GP
EC49
SC1KP50V2KX-1GP
L20
R245
AUD_SPK_L-_1 1
1
2
PBY160808T-121Y-GP
0R2J-2-GP
EC64
SC1KP50V2KX-1GP
L18
R214
AUD_SPK_L+_1 1
1
2
PBY160808T-121Y-GP
0R2J-2-GP
EC61
components
SC1KP50V2KX-1GP
AUD_SPK_R-
AUD_SPK_L-
AUD_SPK_L+
71.20671.A03
2ND = 20.F1686.004
3D3V_S0
23
22
SC10U10V5ZY-1GP
CX20671-21Z-GP
25
24
21
20
19
MIC1
20.F1621.004
AUD_PORTC_R
AUD_PORTC_L
2 SC2D2U16V3KX-GP
2 SC2D2U16V3KX-GP
Place these EMI components

close to speaker connector.
SCD1U25V2ZY-1GP
LEFT+
AVEE
FLY_N
FLY_P
40
1
32
31
30
C506
SCD1U10V2KX-4GP
SB 1024 C422 connect to 3D3V_S0,

place close to connector
DMIC_CLK
DMIC_DATA
DMIC_CLK_R
DMIC_DATA_R
1
1
35
34
33
SPDIF
GPIO0/EAPD#
GPIO1/SPK_MUTE#
DY
AFTE14P-GP
AFTE14P-GP
C_BIAS
PORTC_R
PORTC_L
AFTP204
AFTP202
PC_BEEP
Microphone jack
Internal stereo speakers
Internal stereo digital mic
39
38
37
BLM18BB470SN1D-GP
Headphone jack
4
3
2
2 SBY100505T-601Y-N-GP DMIC_CLK_R
DMIC_DATA_R
2
AFTP200
AFTE14P-GP
1
PORTB_R
PORTB_L
B_BIAS
10
L37
R130
2
10KR2J-3-GP
L36
DMIC_CLK 1
DMIC_DATA 1
C708
SC33P50V2JN-3GP
2
1
36
1
6
AUD_PORTC_L
A:
B:
C:
G:
J:
3D3V_S0
ACES-CON4-17-GP-U
AFTP192
AFTE14P-GP
SC 1208
C706
SC33P50V2JN-3GP
2
1
1
SENSE_A
2
0R2J-2-GP
'0,&,1
R124
3K3R2F-2-GP
1
2
1
2
2
1
17
CLASS_D_REF
12
15
RPWR_5_0
28
AVDD_5V
LPWR_5_0
29
27
FILT_1_65
AVDD_3_3
VAUX_3_3
VDD_IO
DVDD_3_3
AVDD_HP
2
7
18
26
3
FILT_1_8
2 AUD_PC_BEEP
SCD1U10V2KX-4GP
1 R186
AUD_PORTC_R
Port
Port
Port
Port
Port
R257
R294
1
2
0R2J-2-GP
Port Configuration
R258
3K3R2F-2-GP
AUD_SENSE_A
28 AMP_SHUTDOWN#
C617
1
C259
1
C248
BAS40CWH-GP
2
1
1
1
2
1
2
1
2
1
2
KBC_BEEP
BIT_CLK
SYNC
SDATA_IN
SDATA_OUT
C247
SC22P50V2JN-4GP
3AUD_PC_BEEP_1
28
1
2
1
2
2
1
2
RESET#
AUD_CLASSDREF
C255
SC10U10V5ZY-1GP
D26
ACZ_SPKR
5
8
6
4
ACZ_SDATAIN0_R
33R2F-3-GP
DY
DY
Q19
2N7002A-7-GP
AUD_C_BIAS
SC10U10V5ZY-1GP
SC6D8P50V2DN-GP
C275
1
2
SC6D8P50V2DN-GP
2
Layout Note: Path from +5V to LPWR_5.0 and

RPWR_5.0 must be very low resistance ( <0.01 ohms).
Place bypass caps very close to device.
SCD1U25V2ZY-1GP
12 ACZ_SDATAIN0
ACZ_BITCLK_AUDIO
AUD_SYNC
ACZ_SDATAIN0
1 R218
ACZ_SDATA_OUT
U65
SCD1U25V2ZY-1GP
12 ACZ_BITCLK_AUDIO
C623
C252
SCD1U10V2KX-4GP
C305
SCD1U25V2ZY-1GP
C273
SC10U10V5ZY-1GP
C10U10V5ZY-1GP
DY
C242
1
R293
C302
AUD_FILT_1D8V
R125
10KR2F-2-GP
DY
DY
12 ACZ_SDATAOUT_AUDIO
AUD_5V_PWR
C276
SCD1U25V2ZY-1GP
DY
C264
SCD1U25V2ZY-1GP
D1R5F-2-GP
ACZ_RST#_AUDIO
12 ACZ_RST#_AUDIO
13
SC10U10V5ZY-1GP
C228S
AUD_SYNC
Q18
2N7002A-7-GP
0R2J-2-GP
AUD_3D3V
SCD1U25V2ZY-1GP
SC1U10V2ZY-GP
C311
C265
SC100P50V2JN-3GP
DY
D
12 ACZ_SYNC_AUDIO
1D5V_S0
DY
AUD_5V
R267
C569
0R2J-2-GP
C280
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SC10U10V5ZY-1GP
AUD_3D3V_1D5V
C270
R291
DY
SHIELDING
1
C570
C619
SC33P50V2JN-3GP
AUD_3D3V_1D5V
AUD_AGND
DY
AUD_3D3V_R_1
0R2J-2-GP
AUD_AGND
AUD_3D3V_R_2
R263
R122
33KR2F-GP
AUD_3D3V
C618
SCD1U25V2ZY-1GP
R123
33KR2F-GP
DY
3D3V_S0
C621
SC10U10V5ZY-1GP
AUD_3D3V
AUD_LDO_OUT_3D3V
C624
SCD1U25V2ZY-1GP
AUD_FILT_1D65V
C240
SC1U10V2ZY-GP
AUD_3D3V
AUD_5V
HEADPHONE CONN.
DY
EC525 AUD_AGND
SCD1U10V2KX-4GP
HP1
AUD_PORTA_R
2 AUD_PORTA_R_C
AUD_PORTA_L
AUD_PORTA_L_C
AUD_AGND
AUD_AGND
AUD_AGND
AUD_AGND
AUD_AGND
1
2
EC526
DY
AUD_AGND
EC527
SCD1U10V2KX-4GP
SPK1
EC9
SC47P50V2JN-3GP
EC8
SC47P50V2JN-3GP
EC7
SC47P50V2JN-3GP
SC47P50V2JN-3GP
EC6
DY
C40
C64
1
2
DY
C50
SCD1U10V2KX-4GP
AUD_SPK_R+_L
1
4
3
2
AUDIO-JK222-GP-U
R78
10KR2F-2-GP
DY
6
AUD_SPK_L-_L
AUD_SPK_L+_L
AUD_SPK_R-_L
1
AFTE14P-GP
AFTP66
SC470P50V2KX-3GP
R40
10KR2F-2-GP
ACES-CON4-17-GP-U
SC470P50V2KX-3GP
AUD_SPK_L-_L
AUD_SPK_L+_L
AUD_SPK_R-_L
AUD_SPK_R+_L
1
1
1
1
SC470P50V2KX-3GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AUD_PORTA_L_C_1
5D1R2F-GP
L33 FCM1608KF-1-GP
AFTP163
AFTP164
AFTP165
AFTP166
AUD_PORTA_R_C_1
NP2
NP1
5
4
3
6
2
1
SHIELDING
,QWHUQDO6SHDNHU
AUD_SENSE_PORT_A
1
2
5D1R2F-GP
R3139
1
2
R3140
L30 FCM1608KF-1-GP
20.F1621.004
R3141
2ND = 20.F1686.004
1
1
R3142
AFTP107
AFTP96
AFTP103
0R0805-PAD-2-GP
2
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
1
1
1
AUD_SENSE_PORT_A
AUD_PORTA_R_C_1
AUD_PORTA_L_C_1
<Variant Name>
Wistron Corporation

0R0805-PAD-2-GP
AUD_AGND
Title
AUDIO CODEC ALC20671
5
Size
A2
Document Number
Date:
Rev
-1
LB46E
1
Sheet
25
of
53
Mini Card Connector(WLAN)

4
1D5V_S0
3D3V_MINI
3D3V_MINI
W LAN1
3 PCIE_REQ_MINI#
3 CLK_PCIE_MINI1#
3 CLK_PCIE_MINI1
28
28
E51_RxD
E51_TxD
13 PCIE_RXN2
13 PCIE_RXP2
3
13 PCIE_TXN2
13 PCIE_TXP2
3D3V_MINI
5V_S5
3
5
7
9
11
13
15
4
6
8
10
12
14
16
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
NP2
54
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
PLT_RST1#_R
2
R37
300R2F-GP
1DY R168 2
10KR2J-3-GP
SC100P50V2JN-3GP
C47
DY
W IRELESS_EN 28
PLT_RST1# 7,13,23,28,46
1
1
1MINI_W AKE#
TPAD14-GP TP49
53
NP1
1
USBPN3 13
USBPP3 13
LED_W W AN#
TP42 TPAD14-GP
LED_W PAN#
W LAN_LED#_MC 28,33
TP41 TPAD14-GP
TCN-CONN52A-2-GP
20.F1665.052
1 R159
2
0R0603-PAD-2-GP
3D3V_S0
3D3V_MINI
2ND = 20.F1692.052
1 R158
2
0R2J-2-GP
3D3V_S5
DY
Place near MINIC1
DY
1
2
1
2
1
2
DY
C333
C330
SCD1U16V2ZY-2GP
SC1U6D3V2KX-GP
C326
SCD1U16V2ZY-2GP
C334
C360
SCD1U16V2ZY-2GP
1D5V_S0
SC1U6D3V2KX-GP
C332
SC1U6D3V2KX-GP
3D3V_MINI
C356
SCD1U16V2ZY-2GP
DY
<Core Design>
1
Wistron Corporation
Title
MINI CARD
Size
Rev
LB46E
A
Document Number
Date:
D
SB
Sheet
E
26
of
53
EMC2102_FAN_TACH 43
EMC2102_FAN_DRIVE
43
EMC2102_FAN_TACH
EMC2102_FAN_DRIVE
*Layout* 15 mil
RN64
D11
SS14-3-GP
C346
SC22U6D3V5MX-2GP
5V_S0
EMC2102_FAN_TACH 2
EMC2102_fan_mode 1
FAN1
3D3V_S0
83.1R004.M8M
3
4
2
3
4
R188
49D9R2F-GP
SMBC_Therm 28,50
SMBD_Therm 28,50
23
22
SMCLK
SMDATA
25
26
24
VDD_5Vb
FANb
FANa
27
28
GND
TACH
U42
VDD_5Va
29
SCD1U16V2KX-3GP
GND = Internal Oscillator Selected

+3.3V = External 32.768kHz Clock Selected
19
ALERT#
EMC2102_DN2
DN2
CLK_IN
18
CLK_32K
EMC2102_DP2
DP2
CLK_SEL
17
EMC2102_CLK_SEL
EMC2102_DN3
DN3
RESET#
16
EMC2102_DP3
DP3
NC#15
15
PIN10
GND = Fan is OFF
OPEN = Fan is at 60% full-scale
+3.3V = Fan is at 75% full-scale
R177
2
0R2J-2-GP
POWER_OK#
THERMTRIP#
DY
EC60
SCD1U50V3ZY-1-GP
3D3V_S0
14
13
EMC2102_PW ROK 34
THRM# 13
1
1
R178
C349
10KR2F-2-GP
SCD1U16V2ZY-2GP
VGATE_PW RGD
PURE_HW _SHUTDOW N#
V_DEGREE
TRIP_SET Pin Voltage

V_DEGREE
=(((Degree-75)/21)
T8 90 degree
Layout notice : Both EMC2102_DN3 and EMC2102_DP3 routing

10 mil trace width and 10 mil spacing
DY
DY
3.HW T8 sensor
74.02102.A73
EMC2102_fan_mode
C51
SC470P50V3JN-2GP
B
C
84.T3904.C11
2nd = 84.03904.L06
EMC2102-DZK-GP
PIN9
GND = Channel 1
OPEN = Channel 3
C373
SC470P50V2JN-GP +3.3V = Disabled
SYS_SHDN#
NC#8
Layout notice : Both EMC2102_DN2 and EMC2102_DP2 routing

2.System Sensor, Put between CPU and NB.
MMBT3904-4-GP
Q6
21
EMC2102
12
20
ALERT#
TRIP_SET
DY
GND
DP1
84.T3904.C11
2nd = 84.03904.L06
C377
SC470P50V2JN-GP
DN1
FAN_MODE
MMBT3904-4-GP
Q14
C272
SC470P50V2JN-GP
H_THERMDA
11
SB
CC272 must be near Q7

C377 must be near EMC2102
H_THERMDC
NC#21
10
1.For CPU Sensor
VDD_3V
SHDN_SEL
H_THERMDA
H_THERMDC
C376
SC470P50V2JN-GP
2nd = 20.D0196.104
C370
Layout notice :
Both H_THERMDA and THERMDC routing
4
ACES-CON4-GP-U1
20.F0714.004
EMC2102_VDD_3D3
DY
C361
C357
SC4D7U10V5ZY-3GP
SCD1U16V2ZY-2GP
3D3V_S0
SRN10KJ-5-GP
R180
3KR2F-GP
C355
SCD1U16V2ZY-2GP
C51 must be near Q8

C373 must be near EMC2102
RUN_POW ER_ON
3D3V_S0
RN40
PM_SUS_CLK
CLK_32K_R
4
3
2
1
PURE_HW _SHUTDOW N#
EMC2102_CLK_SEL
THRM#
CLK_32K
13
5
6
7
8
Q22
R170
240KR3-GP
SRN10KJ-6-GP
2N7002-12-GP
84.27002.Y31
32K suspend clock output
3D3V_AUX_S5
DY
PURE_HW _SHUTDOW N#
Q21
13,36 VGATE_PW RGD
D10
BAT54-5-GP
83.BAT54.D81
2nd = 83.BAT54.X81
3rd = 83.00054.Z81
RSMRST#
<Core Design>
Wistron Corporation
RSMRST# 28,34

C335 DY
SCD1U16V2ZY-2GP
Title
(dummy, KBC already delay)

2N7002-12-GP
84.27002.Y31
Size
Thermal/Fan Controllor
Document Number
Rev
SB
LB46E
Date:
Sheet
27
of
53
3D3V_AUX_S5
AVCC
SHBM
S5_ENABLE 2
2K2R2J-2-GP
VREF
A/D
GPI90/AD0
GPI91/AD1
GPI92/AD2
GPI93/AD3
GPIO05
GPIO04
LPC
GPI94
GPI95
GPI96
GPI97
D/A
1KBC_XO_R 2
104
97
98
99
100
108
96
AD_IA
41
NOVO_BTN# 31
WIRELESS_BTN#
31
GPIO74/SDA2
GPIO73/SCL2
GPIO22/SDA1
GPIO17/SCL1
1
R192
GPIO77
GPIO76/SHBM
GPIO75
GPIO81
111
113
112
S5_ENABLE_KBC
VCORF
44
SP
GPIO66/G_PWM
84
83
82
91
114
14
15
DC_BATFULL
SMB
SPI
GPIO
GPO83/SOUT_CR/BADDR1
GPIO87/SIN_CR
GPO84/BADDR0
GPIO16
GPIO34
GPIO36
SER/IR
GPIO01/TB2
GPIO03
GPIO06
GPIO07
GPIO23
GPIO24
GPIO30
GPIO31
GPIO32/D_PWM
GPIO33/H_PWM
GPIO40/F_PWM
GPIO42/TCK
GPIO43/TMS
GPIO44/TDI
GPIO45/E_PWM
GPIO46/TRST#
GPIO47
GPIO50/TDO
GPIO51
GPIO52/RDY#
GPIO53
GPIO70
GPIO71
GPIO72
GPO82/TRIS#
101
105
106
107
KBC_THERMALTRIP#
64
95
93
94
119
6
109
120
65
66
16
17
20
21
22
23
24
25
26
27
28
73
74
75
110
PLATFORM_ID
TP_LED
5
18
45
78
89
116
DY
R46
2
20MR3-GP
KBC_XI
Pin 120: MODEL_ID_0
AD_OFF
RSMRST#_KBC
63
117
31
32
118
62
29
29
29
13
12
11
10
71
72
TPDATA
TPCLK
TPDATA
TPCLK
86
87
90
92
SPIDI
SPIDO
SPICS#
SPICLK
29
3D3V_AUX_S5
77
KBC_XO 79
30
AD_DETECT
PM_PWRBTN#
CHG_ON#
KBC_BEEP
EC_TMR
BRIGHTNESS
30
30
2 OF 2
U9B
82.30001.661
R49
33
PWR_LED 33
STOP_CHG# 41
INDICATE_LED 31
AD_OFF
40
RSMRST#_KBC 13
PM_SLP_S4# 7,13,38
CHARGE_LED 33
32KX1/32KCLKIN
KBSOUT0/JENK#
KBSOUT1/TCK
KBSOUT2/TMS
KBSOUT3/TDI
KBSOUT4/JEN0#
KBSOUT5/TDO
KBSOUT6/RDY#
KBSOUT7
KBSOUT8
KBSOUT9
KBSOUT10
KBSOUT11
KBSOUT12/GPIO64
KBSOUT13/GPIO63
KBSOUT14/GPIO62
KBSOUT15/GPIO61/XOR_OUT
GPIO60/KBSOUT16
GPIO57/KBSOUT17
32KX2
GPIO55/CLKOUT
GPIO14/TB1
GPIO20/TA2
GPIO56/TA1
GPIO15/A_PWM
GPIO21/B_PWM
GPIO13/C_PWM
GPIO12/PSDAT3
GPIO25/PSCLK3
GPIO27/PSDAT2
GPIO26/PSCLK2
GPIO35/PSDAT1
GPIO37/PSCLK1
F_SDI
F_SDO
F_CS0#
F_SCK
KBC
KBSIN0
KBSIN1
KBSIN2
KBSIN3
KBSIN4
KBSIN5
KBSIN6
KBSIN7
PS/2
FIU
VCC_POR#
Pin 24: MODEL_ID_1

SPI_WP# 29
LAN_PWR_ON 23 R185DIS
BLON_OUT
10KR2J-3-GP
BLON_OUT 18
UMA_DISCRETE# Pin 28:UMA=NC; DIS=PL
1
2
B46E_ID
USB_PWR_EN#
KCOL0
KCOL1
KCOL2
KCOL3
KCOL4
KCOL5
KCOL6
KCOL7
KCOL8
KCOL9
KCOL10
KCOL11
KCOL12
KCOL13
KCOL14
KCOL15
KCOL16
KCOL17
54
55
56
57
58
59
60
61
KROW0
KROW1
KROW2
KROW3
KROW4
KROW5
KROW6
KROW7
85
ECRST#
RN46
3D3V_AUX_S5
KA20GATE
KBRCIN#
E51_TxD
SHBM
WPCE773LA0DG-GP
53
52
51
50
49
48
47
43
42
41
40
39
38
37
36
35
34
33
WPCE773LA0DG-GP
R190
10KR2J-3-GP
1
2
22
1 10KR2J-3-GP
1
X1
PM_SLP_S3# 13,34,38,39,44
KBC_PWRBTN# 31
AC_IN#
41
LID_CLOSE# 32
KBC_PWRBTN#
GND
GND
GND
GND
GND
GND
AGND
2 R201
4
40
13
41
25
13
18
34
VCORF
103
8
7
6
5
3D3V_S0
5
6
7
8
4
3
2
1
ECRST#
LID_CLOSE#
KBC_THERMALTRIP#
SRN10KJ-6-GP
1
2
3
4
27,34
Q23
B
RSMRST#
MMBT3906-3-GP
84.03906.R11
2ND = 84.03906.F11
3RD = 84.03906.P11
SRN10KJ-6-GP
C378
SC1U10V3KX-3GP
C67
3
25 AMP_SHUTDOWN#
KBC_THERMALTRIP#
PCB_VER0
PCB_VER1
RN45
C387
SCD1U16V2ZY-2GP
X-32D768KHZ-34GPU
1
2
SCD1U16V2ZY-2GP
SC10U10V5ZY-1GP
2
1
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
2
1
SCD1U16V2ZY-2GP
2
1
1
2
SCD1U16V2ZY-2GP
2
1
1
19
46
76
88
115
U9A
VCC
VCC
VCC
VCC
VCC
102
AVCC
80
VDD
C60
S5_ENABLE
E51_TxD
E51_RxD
E51_TxD
E51_RxD
CAM_EN
18
33
68
67
69
70
81
SCRLK_LED
26 WIRELESS_EN
33 WLAN_TEST_LED
C359,C362 colse to Pin VDD
SMBD_Therm
SMBC_Therm
40,41 BAT_SDA
40,41 BAT_SCL
26
26
C362
0R2J-L-GP
UMA
31
C359
1 R520
GMCH_BL_ON
C380
C386
GPIO10/LPCPD#
LRESET#
LCLK
LFRAME#
LAD0
LAD1
LAD2
LAD3
SERIRQ
GPIO11/CLKRUN#
KBRST#
GA20
ECSCI#/GPIO54
GPIO65/SMI#
GPIO67/PWUREQ#
C354
124
PLT_RST1#_1
7
2
3
PCLK_KBC
1R3145
2
3
12 LPC_LFRAME#
R3146
120R2J-2-GP 126
1
2
12 LPC_LAD0
120R2J-2-GP
127
12 LPC_LAD1
R187
128
12 LPC_LAD2
1
DY 0R2J-2-GP
12 LPC_LAD3
125
13 INT_SERIRQ
SC4D7P50V2CN-1GP
8
13 PM_CLKRUN#
122
C371
12
KBRCIN#
121
12
KA20GATE
ECSCI#_KBC
1
2PCLK_KBC_RC
29
NV_BL_IN
1 R519
2
9
50 NV_BLON_IN
ECSWI#_KBC 123
DIS 0R2J-L-GP
DY
THERMAL----->
Add VGA Thermal-0410
BATTERY----->
SC4D7U10V5KX-1GP
2
1 OF 2
GPIO41
1
2
BAT_IN#
BAT_IN#
C353
DY
33KR2J-3-GP
SC27P50V2JN-2-GP
DY
40
3D3V_S0
SB
C374
SC15P50V2JN-2-GP
R189 2
1
0R0402-PAD
PLT_RST1#
C368
34,37,43
1
2
DY
3D3V_S0
SC15P50V2JN-2-GP
SC1U16V3ZY-GP
7,13,23,26,46
C363
SCD1U16V2ZY-2GP
SB
C366
3D3V_AUX_S5
2 R184
1
0R0603-PAD
71.00773.00G
FOR KBC DEBUG

R202
KCOL2
KCOL3
0R2J-2-GP
D14
ISP Mode disable
13
ECSCI#_1
ECSCI#_KBC
PCB_VER0
PCB_VER1
2
3
RB731U-2-GP
DY
83.R2002.B8E
ECSWI#
13
2
10KR2J-3-GP
R173
ECSWI#_KBC
10KR2J-3-GP
R176
DY
DY:
AD_OFF
R191
1
2
1KR2J-1-GP
2 EC63
SCD1U50V3ZY-1-GP
PlanarID
(0,0)
SA: 0,0
SB: 0,1
SC: 1,0
RN48
8
7
6
5
R175
10KR2J-3-GP
10KR2J-3-GP
R203
DY
3D3V_S5
DY
SPIDI
3D3V_AUX_S5
R174
1
2
0R2J-2-GP
DY
SRN10KJ-6-GP
DY
RN44
C369 DY
1
2
PCLK_KBC
RSMRST#_KBC
BLON_OUT
AD_OFF
S5_ENABLE_KBC
1
2
3
4
3D3V_S0
SC4D7P50V2CN-1GP
1
2
3
4
PLATFORM_ID
8
7
6
5
SATA_LED# 12,31
WLAN_LED#_MC 26,33
SRN10KJ-6-GP
66.10336.08L
2
2nd = 83.R3004.A8E
Internal KeyBoard Connector
3D3V_AUX_S5
RN47
R412 1
100R2J-2-GP
R414 1
100R2J-2-GP
5V_S0
5V_S0
KCOL16_Q
KCOL17_Q
3
1
43
KCOL0
43
43
43
43
KCOL16_Q
KCOL15
KCOL14
KCOL13
43
43
43
43
KCOL8
KCOL7
KCOL6
KCOL5
KCOL0
KCOL16_Q
KCOL15
KCOL14
KCOL13
KCOL16_Q
R1
43
43
43
43
KCOL4
KCOL3
KCOL2
KCOL1
2EC118 1
SC100P50V2JN-3GP
2EC117
1
SC100P50V2JN-3GP
2EC116
1
DY
SC100P50V2JN-3GP
2EC115
1
DY
SC100P50V2JN-3GP
2
R2
84.00143.G1K
2nd = 84.00143.D1K
43
43
43
43
KROW0
KROW7
KROW6
KROW5
43
43
43
43
KROW4
KROW3
KROW2
KROW1
43
43
43
43
KCOL12
KCOL11
KCOL10
KCOL9
KROW0
KROW7
KROW6
KROW5
2EC114 1
SC100P50V2JN-3GP
2EC113
1
SC100P50V2JN-3GP
2EC112
1
DY
SC100P50V2JN-3GP
2EC111
1
DY
SC100P50V2JN-3GP
KROW4
KROW3
KROW2
KROW1
2EC110 1
SC100P50V2JN-3GP
2EC109
1
SC100P50V2JN-3GP
2EC108
1
DY
SC100P50V2JN-3GP
2EC107
1
DY
SC100P50V2JN-3GP
KCOL12
KCOL11
KCOL10
KCOL9
2EC106 1
SC100P50V2JN-3GP
2EC105
1
SC100P50V2JN-3GP
2EC104
1
DY
SC100P50V2JN-3GP
2EC100
1
DY
SC100P50V2JN-3GP
DY
DY
Q33
3
KCOL17
3D3V_S0
SMBC_Therm 27,50
2EC122 1
SC100P50V2JN-3GP
2EC121
1
SC100P50V2JN-3GP
2EC120
1
DY
SC100P50V2JN-3GP
2EC119
1
DY
SC100P50V2JN-3GP
KCOL4
KCOL3
KCOL2
KCOL1
NOVO_BTN#
KBC_PWRBTN#
BAT_IN#
SRN100KJ-L-GP
3D3V_AUX_S5
DY
DY
KCOL8
KCOL7
KCOL6
KCOL5
8
7
6
5
RN49
SRN4K7J-12-GP
BAT_SCL
BAT_SDA
SMBC_Therm
SMBD_Therm
DY
DY
DTC143ZUB-GP
1
2
3
4
DY
DY
Q31
KCOL16
KCOL17_Q
2EC128 1
SC100P50V2JN-3GP
2EC127 1
DY
SC100P50V2JN-3GP
2EC126 1
DY
SC100P50V2JN-3GP
2EC125
1
SC100P50V2JN-3GP
2EC124
1
DY
SC100P50V2JN-3GP
2EC123
1
DY
SC100P50V2JN-3GP
1
2
3
4
KROW0
KB_LED_2
KCOL2
KCOL4
KCOL7
KCOL8
KCOL6
KCOL3
KCOL12
KCOL13
KCOL14
KCOL11
KCOL10
KCOL15
KROW2
KROW3
KCOL5
KCOL1
KCOL0
KB_LED_1
43
KCOL17_Q
8
7
6
5
KB1
ACES-CON30-1-GP
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
32
KROW4
KROW5
KCOL9
KROW7
KROW6
KROW1
31
1
20.K0320.030
KCOL17_Q
R1
2
R2
DY
DY
DTC143ZUB-GP
84.00143.G1K
2nd = 84.00143.D1K
<Core Design>
DY
DY
43
KB_LED_1
43
KB_LED_2
SMBD_Therm 27,50
Wistron Corporation
Title
KBC WPCE773L
KB_LED_1
Size
Document Number
Custom
KB_LED_2
Date:
Rev
SB
LB46E
Sheet
28
of
53
3D3V_AUX_S5
4
5
6
7
8
RN41
3D3V_AUX_S5
SRN10KJ-6-GP
4
3
2
1
16M Bits
SPI FLASH ROM
ER6
0R0603-PAD
1
2
3
4
SPICS#
VCC
HOLD#
CLK
DIO
8
7
6
5
3D3V_AUX_S5_SPI_ROM
SPI_HOLD#
SPICLK
SPIDO
72.25X16.A01
3
SPI_HOLD#
1
2
SC4D7P50V2CN-1GP
EC59
SC4D7P50V2CN-1GP
DY
EC57
W 25X16AVSSIG-GP
SPIDI
28
DY
EC55
SC4D7P50V2CN-1GP
SPI_W P#
CS#
DO
WP#
GND
28
28
28
SPI_W P#
U40
28
DY
EC58
SC4D7P50V2CN-1GP
2 EC56
SCD1U50V3ZY-1-GP
DY
<Core Design>
Wistron Corporation
Title
Size
Rev
SB
LB46E
A
BIOS
Document Number
Date:
D
Sheet
E
29
of
53
5V_S0
TOUCH PAD
SCD1U10V2KX-4GP
EC27
DY
32,43
32,43
SCD1U10V2KX-4GP
EC28
T/P
TPAD1
DY
ACES-CON6-13-GP
8
6
5
4
3
2
TP_CLK
TP_DATA
TP_LEFT
TP_RIGHT
1
EC131 EC132
EC130
EC129
20.K0320.006
SC100P50V2JN-3GP
2
DY
DY
DY
2ND = 20.K0382.006
4
3
SRN10KJ-5-GP
DY
SC100P50V2JN-3GP
2
RN7
SC100P50V2JN-3GP
2
1
2
SC100P50V2JN-3GP
2
5V_S0
RN8
28
28
TPDATA
TPCLK
1
2
4
3
TP_DATA
TP_CLK
TP_DATA 43
TP_CLK 43
SRN33J-5-GP-U
<Core Design>
A
Wistron Corporation
Title
Touch pad
Size
Document Number
Rev
SB
LB46E
Date:
5
Sheet
1
30
of
53
5V_S0
1
2
PB1
AFTP175
9
KBC_PW RBTN#
AFTE14P-GP
1
2
1
2
R607
100KR2J-1-GP
1
2
3
W IRELESS_BTN#
W IRELESS_BTN# 28
5
SW -SLIDE3-3-GP
EC42
3D3V_S0
SW 1
EC41
SCD1U10V2KX-4GP
AFTP141
AFTE14P-GP
EC40
SCD1U10V2KX-4GP
2ND = 20.K0465.008
EC39
SCD1U10V2KX-4GP
20.K0320.008
C
EC38
SCD1U10V2KX-4GP
ACES-CON8-19-GP
1
AFTE14P-GP
AFTP176
AFTP169
AFTP170
AFTP171
AFTP172
AFTP173
KBC_PW RBTN# 28
NOVO_BTN# 28
SCRLK_LED 28
SATA_LED# 12,28
INDICATE_LED 28
SCD1U10V2KX-4GP
10
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
1
1
1
1
1
KBC_PW RBTN#
NOVO_BTN#
G77
GAP-OPEN
G78
GAP-OPEN
2
3
4
5
6
7
8
KBC_PW RBTN#
NOVO_BTN#
SCRLK_LED
SATA_LED#
INDICATE_LED
AFTE14P-GP
AFTP174
KBC_PW RBTN#
EC45
SCD1U10V2KX-4GP
EC43
SCD1U10V2KX-4GP
Power and LED Board
5V_S5
DY
2
62.40018.491
AFTE14P-GP
AFTP142
C692
SCD1U10V2KX-4GP
2nd = 62.40018.471
<Core Design>
A
Wistron Corporation
Title
Power Board
Size
Rev
SB
LB46E
5
Document Number
Date:
2
Sheet
1
31
of
53
Cover Up Switch
TP_SW _L
TPS1
TP_LEFT
3D3V_AUX_S5
30,43
R667
100R2J-2-GP
HALL1
OUTPUT
SW -TACT-5P-2-GP
62.40009.B21
AFTE14P-GP
AFTP108
LID_CLOSE#_1
VSS
VDD
LID_CLOSE#
100R2F-L1-GP-U
1
1
TP_SW _L 1
R350
74.06781.07B
EM-6781-T30-GP
LID_CLOSE# 28
C491
SCD22U6D3V2KX-1GP
C493
SC1U6D3V2KX-GP
2ND = 74.09132.B7B
TP_SW _R
TPS2
2
5
TP_RIGHT 30,43
R669
100R2J-2-GP
C
4
LID_CLOSE#_1
SW -TACT-5P-2-GP
TP_SW _R 1
AFTE14P-GP
AFTE14P-GP
AFTP106
AFTP111
62.40009.B21
<Core Design>
Wistron Corporation
Title
SWITCHS
Size
5
Document Number
Rev
SB
LB46E
Date:
2
Sheet
1
32
of
53
Q63
28
PW R_LED
LED1
PW R_LED#_Q
R1
R2
A PW R_LED#_R
R632
1
5V_S5
120R2J-2-GP
LED-W -56-GP
83.00191.J70
POWER LED
DTC143ZUB-GP
84.00143.G1K
2nd = 84.00143.D1K
white
Q62
28 DC_BATFULL
R630
1
LED2
CHARGE_LED2#_Q
R1
R2
A CHARGE_LED2#_R
83.00191.J70
CHARGER LED2
DTC143ZUB-GP
84.00143.G1K
2nd = 84.00143.D1K
orange
Q61
28 CHARGE_LED
R629
LED3
CHARGE_LED1#_Q
R1
R2
A CHARGE_LED1#_R
LED-O-16-GP-U
5V_S5
120R2J-2-GP
LED-W -56-GP
5V_S5
CHARGER LED1
59R2F-GP
83.00190.Z70
DTC143ZUB-GP
84.00143.G1K
2nd = 84.00143.D1K
White
R134
Q29
R2
R1
26,28 W LAN_LED#_MC
W LAN_LED#
2W LAN_LED#_R
A
LED-W -56-GP
330R2F-GP
5V_S0
LED4
83.00191.J70
DTA143ZUB-GP
Q27
2N7002-12-GP
DY
84.00143.F1K
EC47
SCD1U50V3ZY-1-GP
G
S
28 W LAN_TEST_LED
84.27002.Y31
Q57
28
TP_LED
LED6
R1
R2
TP_LED#_Q
A TP_LED#_R
LED-W -56-GP
83.00191.J70
DTC143ZUB-GP
R624
1
5V_S0
499R2F-2-GP
TP LED
84.00143.G1K
2nd = 84.00143.D1K
<Core Design>
A
Wistron Corporation
Title
LED
Size
Rev
SB
LB46E
5
Document Number
Date:
2
Sheet
1
33
of
53
Run Power
5V_S5
5V_S0
DY
C269
1
Q13
NDS0610-NL-GP
10KR2J-3-GP
G
R117
100KR2J-1-GP
R120
D9
UDZS9V1B-GP
83.9R103.H3F
3D3V_S0
3D3V_S5
1
2
3
4
U21
S
S
S
G
D
D
D
D
8
7
6
5
AO4468-GP
Z_12V_D4
3D3V_runpwr 2
84.04468.037
84.2N702.A3F
2N7002KDW -GP
Z_12V_D3
2
1
330KR2J-L1-GP
DY
DY
2Z_12V_G3
C278
330KR2J-L1-GP
R109
100R5J-3-GP
SCD22U25V3KX-GP
R115
10KR2J-3-GP
R118
1
AO4468-GP
D
K
3D3V_S0
8
7
6
5
84.04468.037
Z_12V
D
D
D
D
SCD1U25V3KX-GP
RUN_POW ER_ON
R119
1
DCBATOUT
1
2
3
4
U20
S
S
S
G
Q11
2N7002-11-GP
Z_12V_D3
1D5V_S0
1
2
3
4
Q12
1D5V_S3
3
U24
S
S
S
G
D
D
D
D
8
7
6
5
AO4468-GP
84.04468.037
PM_SLP_S3# 13,28,38,39,44
3D3V_S5
SCD1U16V2KX-3GP
C257
1
U17
EMC2102_PW ROK
27 EMC2102_PW ROK
13,28,38,39,44 PM_SLP_S3#
VCC
DY
PW ROK 7,13
GND
74LVC1G08GW -1-GP
73.01G08.L04
2nd = 73.7SZ08.AAH
3rd = 73.01G08.L03
1D05V_S0
R112
2K2R2J-2-GP
DY
C266
1
DY
R114
1KR2J-1-GP
E
H_PW RGD#
KBC_THERMALTRIP# 28
Q9
Q10
MMBT2222A-3-GP
MMBT3904-3-GP
84.02222.V11
2nd = 84.02222.R11
C268
SC2D2U16V3KX-GP
H_PW RGD
4,12
DY
2
SCD1U16V2ZY-2GP
D8
28,37,43 S5_ENABLE
83.00016.K11
3
BAS16-6-GP
2
RSMRST# 27,28
<Core Design>
Wistron Corporation
Title
Size
RUN POWER and 3D3V_AUX_S5

Document Number
Rev
SB
LB46E
Date:
Sheet
34
of
53
CPU_CORE
ISL6266A
Input Power
Output Signal
VID Setting
VID0
VID0(I / 3.3V)
VID1
1D5V_S0
Output Power
1D8V_S3
5V_S5 (6A)
VIN
VIN
1D5V_S0 (2.5A)
1D5V(O)
5V(O)
D
VID1(I / 3.3V)
Input Signal
VID2
PM_SLP_S3#
3D3V_S5 (6A)
S5_ENABLE
VID2(I / 3.3V)
CPUCORE_ON
PGOOD
EN
3D3V(O)
EN0
VID3
VID3(I / 3.3V)
Output Power
5V(O)
VID4
5V_AUX_S5
Output Signal
VID4(I / 3.3V)
VID5
RT9018A
DCBATOUT_51125
VGATE_PWRGD
PGOOD
TPS51125
5V/3D3V
VCC_CORE_PWR(O)
VCC_CORE(Imax=38A) ALW_PWRGD_3V_5V
RT9026
PGOOD
VIN
3D3V(O)
VID5(I / 3.3V)
0D9V_S0
5V_S5
3D3V_AUX_S5
1D8V_S3
VID6
0D9V_S3 (1A)
VLDOIN
VID6(I / 3.3V)
VTT
PM_SLP_S4#
S3
Input Signal
0D9V_S3_1
VTTREF
CPUCORE_ON
S5
EN (I / 3.3V)
C
Voltage Sense
VCC_SENSE
VSEN(I / Vcore)
VSS_SENSE
RGND(I / Vcore)
Input Power
DCBATOUT_6266A
VCC(I)
Charger BQ24745
5V_S0
VCC(I)
Input Signal
3D3V_S0
CHG_ON#
VCC(I)
B
Output Signal
CHGEN#
24750_CELLS
Input Power
AD_IA
SRSET
CELLS
TPS51124
1D8V/1D05V
5V_S5
AC_IN#
ACGOOD#
Output Power
Input Power
Output Power
VDD
DCBATOUT_51124
1D8V (O)
AD+
1D8V_S3 (10A)
ACN
BT+
VOUT (O)
VCC
Input Signal
PM_SLP_S4#
1D05V(O)
VOUT (O)
Adapter
1D05V_S0 (15A)
Input Signal
EN1
Output Signal
AD_IN#
PM_SLP_S3#
A
AD_OFF
EN2
DCBATOUT
<Core Design>
(O)
(I)
Wistron Corporation
CPUCORE_ON
Output Power
Input Power
Output Signal
AD_JK
PGOOD1

VCC(I)
VCC(O)
Title
AD+
Power Sequence Logic
PGOOD2
5V_AUX_S5
Size
B
VCC(I)
Document Number
Date: Monday, October 25, 2010

5
Rev
LB46E
SB
Sheet
1
35
of
53
PM_DPRSLPVR 7,13
2
0R0402-PAD
2 H_VID6
0R0402-PAD
2 H_VID5
0R0402-PAD
2 H_VID4
0R0402-PAD
2 H_VID3
0R0402-PAD
2 H_VID2
0R0402-PAD
2 H_VID1
0R0402-PAD
2 H_VID0
0R0402-PAD
37
C33
1
2
SCD22U10V2KX-1GP
1
2
1
2
1
2
1
2
1
2
1
6266A_UGATE2
TP4107
U6
IRF6725MTRPBF-GP-U
TPAD40-GP
5V_S0
6266A_LGATE2
R25
1
TC3
L-D36UH-1-GP
68.R3610.20A
2nd = 68.R3610.20C
1
TP4104
2
10R2F-L-GP
C31
SC1U25V3KX-1-GP
TPAD40-GP
84.06725.030
TC1
5V_S0
0R2J-2-GP
one phase
2
DY
1
6266A_LGATE2
TP4102
79.33719.L01
79.33719.L01
2nd = 77.C3371.0512nd = 77.C3371.051
TPAD40-GP
R31
1
2
0R0402-PAD
C36
SCD01U25V2KX-3GP
6266A_VSUM
6266A_ISEN2
6266A_ISEN1
Single Phase
R47=1.2K, R63=5.6K,R460=0R
C33=47p, C49=0.033u, C52=0.1u
R27
1
R26
1
R29
1
R28
1
one phase
2 3K65R2F-1-GP
6266A_ISEN2_P2_VCORE
2 10KR2F-2-GP
one phase
2 1R2F-GP
one phase
6266A_ISEN1_P2_VCORE
<Core
Design>
A
2 10KR2F-2-GP
one phase
Wistron Corporation
Title
ISL6266A_CPU_CORE
DY=U7,U28,U29,L9,R62,R56,R42,
R45,R37,R39,R48,C20
R20
1
Size
A3
5
DY
C316
SCD1U50V3KX-GP
VCC_CORE
R162
NTC-10K-26-GP
6266A_VO
C11
L9
1
6266A_VSUM_R_VO
C312
Cyntec 10*10*4
DCR=1.05+-5%mohm, Irating=30A
Isat=60A
6266A_UGATE2
1
2
1
1
26266A_VO
SCD22U10V2KX-1GP
6266A_VO
2
1
R32
11KR2F-L-GP
C43
SCD047U25V3KX-3-GP
84.06721.030
C34
R30
2K61R2F-1-GP
1
2
1
2
C45
SCD22U50V3ZY-1GP
5
4
3
6
5
2
1
U34
IRF6721SPBF-GP-U
C29
C310
One phase-->
C33,C34 are
63.R0034.1DL
6266A_ISEN1
-1
-1
one phase
6266A_VSUM
A
DCBATOUT_6266A
one phase
R156
6266A_BOOT2 1
26266A_BOOT2_R
2D2R2J-GP
ISEN1
ISEN2
23
6266A_ISEN2
24
6266A_VDD
22
VDD
GND
21
VSUM
VIN
6266A_VIN 20
VO
DFB
18
1
6266A_VO
6266A_VSUM 19
6266A_DFB 17
2
1
1
6266A_UGATE2
2 10KR2F-2-GP
one phase
S
S
G
6
5
2
1
28
2 1R2F-GP
1 R34
6266A_PHASE2
10R3F-GP
C41
PHASE2
1 R35
SE330U2VDM-L-GP
6266A_ISEN2
C329
SCD22U25V3KX-GP
SE330U2VDM-L-GP
7
6
2
1
6266A_VO
6266A_PHASE2
R24
C37
one phase
SC2D2U16V3KX-GP
D
D
D
D
29
39
38
VID1
41
40
VID2
VID3
42
VID4
VID5
44
43
VID6
VR_ON
45
46
DPRSTP#
DPRSLPVR
VID0
PGND2
DCBATOUT
SCD01U25V2KX-3GP
6266A_VDIFF13
DROOP
VDIFF
2 10KR2F-2-GP
6266A_LGATE2
SC10U25V6KX-1GP
1 R36
5V_S0
25
SCD33U10V3KX-3GP
2 R22
1
0R0402-PAD
6266A_ISEN1
31
30
NC#25
SC180P50V2JN-1GP
VSS_SENSE
2 3K65R2F-1-GP
PVCC
FB2
R18
POWER SB
3K01R2F-3-GP
1 R33
LGATE2
26
2
R16
1KR2J-1-GP
6266A_VSUM
TP4103
TPAD40-GP
BOOT2
R23
6266A_ LGATE1
TC2
C327
UGATE2
C28
SC330P50V2KX-3GP
5
33
32
FB
COMP
2 R21
1
0R0402-PAD
PGND1
LGATE1
27
C35
SC330P50V2KX-3GP
VCC_SENSE
6266A_VR_ON 1
R144
6266A_D6
1
R143
6266A_D5
1
R139
6266A_D4
1
R138
6266A_D3
1
R146
6266A_D2
1
R142
6266A_D1
1
R137
6266A_D0
1
R136
R147
2
48
VW
DY
PHASE1
TC20
79.33719.L01
79.33719.L01 2nd = 77.C3371.051
2nd = 77.C3371.051
6266A_SOFT
2
1KR2F-3-GP
47
OCSET
1KR2F-3-GP
R15
1
3V3
SOFT
6266A_VDIFF
B
35
34
74.06266.073
NTC
R14
1KR2F-3-GP
one phase
C32
2 6266A_FB2_R 1
2
100R2F-L1-GP-U
SC2200P50V2KX-2GP
UGATE1
SC10U25V6KX-1GP
2
SC270P50V2KX-1GP
ISL6266AHRZ-GP
84.06725.030
TPAD40-GP
SC10U25V6KX-1GP
C24
1
VR_TT#
RTN
6266A_FB2 12
RBIAS
6266A_RTN 15
11
PMON
16266A_DROOP
16
6266A_FB
BOOT1
PSI#
TP4105
R151
6266A_BOOT1 1
2
2D2R2J-GP
6266A_BOOT1_R
1
6266A_UGATE1
6266A_ LGATE1
2
6266A_PHASE1
C321
SCD22U25V3KX-GP
R19
1
2 6266A_COMP_R
97K6R2F-GP
2
10K5R2F-GP
PGOOD
TC4
6266A_ LGATE1 1
POWER SB
36
68.R3610.20A
2nd = 68.R3610.20C
U7
IRF6725MTRPBF-GP-U
D
D
D
D
R17
1
1
R13
2
SC100P50V2JN-3GP
6266A_DPRSTP# 1
2
R140
0R0402-PAD
6266A_DPRSLPVR 2 R145
1 499R2F-2-GP
1
6266A_COMP
10
CLK_EN#
49
GND
6266A_NTC
6
1 R161
26266A_NTC_R1 R155
2
NTC-470K-8-GP
4K02R2F-GP
C328
C325
6266A_SOFT
7
1
2
SCD015U50V3KX-GP
1
2
SCD01U25V2KX-3GP
6266A_VO 1 R157
8
26266A_OCSET
10K5R3F-GP
C22 1
6266A_VW 9
2 SC1000P50V3JN-GP-U
C25
1
1 0R2J-2-GP
2
1
2
1
2
4 CPU_PROCHOT#_R
L-D36UH-1-GP
Id=19.5A
Qg=21.5~33nC,
Rdson=5.5~6.7mohm
SE330U2VDM-L-GP
PSI#
C320
1
SE330U2VDM-L-GP
2 R149
16266A_PSI# 2
0R0402-PAD
3
2 6266A_PMON_R 1
2 6266A_PMON
R150 4K99R2F-L-GP
SCD1U25V3KX-GP
1
26266A_RBIAS4
R152 147KR2F-GP
5
4
C317
SCD1U50V3KX-GP
Vcc_core
Iomax=38A
SE330U2VDM-L-GP
13,27 VGATE_PW RGD
R154
68R2-GP
DY
VCC_CORE
S
S
G
C313
L8
6266A_PHASE1
U5
R148
1K91R2F-1-GP
1D05V_S0
C339
Cyntec 10*10*4
DCR=1.05+-5%mohm, Irating=30A
Isat=60A
6266A_UGATE1
D
D
D
D
6266A_3V3
3D3V_S0
VSEN
SCD1U10V2KX-4GP
79.33719.L01
TPAD40-GP
C393
SC10U25V6KX-1GP
DY
GAP-CLOSE-PW R
TP4106
C314
DY
GAP-CLOSE-PW R
84.06721.030
6266A_UGATE11
G
TC18
SE330U2VDM-L-GP
GAP-CLOSE-PW R
G47
1
2
U38
IRF6721SPBF-GP-U
SC10U25V6KX-1GP
GAP-CLOSE-PW R
G49
1
2
R141
10R3F-GP
5
5
5
5
5
5
5
SC10U25V6KX-1GP
GAP-CLOSE-PW R
G54
1
2
GAP-CLOSE-PW R
G51
1
2
H_VID6
H_VID5
H_VID4
H_VID3
H_VID2
H_VID1
H_VID0
6266A_VSEN14
GAP-CLOSE-PW R
G50
1
2
D
D
D
D
GAP-CLOSE-PW R
G52
1
2
39
3D3V_S0
G48
CPUCORE_ON
G53
7
6
2
1
4,7,12 H_DPRSTP#
5
4
3
DCBATOUT_6266A
DCBATOUT_6266A
DCBATOUT
DCBATOUT_6266A
DCBATOUT
Date:
2
Document Number
Rev
SB
LB46E
Sheet
36
1
of
53
GAP-CLOSE-PW R
G45
1
2
3D3V_PW R
3D3V_S5
G30
1
GAP-CLOSE-PW R
G40
1
2
3
4
GAP-CLOSE-PW R
G44
1
2
1
GAP-CLOSE-PW R
G36
1
2
51125_ENTIP1
Q26
84.2N702.A3F
R268
154KR2F-L-GP
C519
R275
154KR2F-L-GP
2
GAP-CLOSE-PW R
G34
1
2
DY
GAP-CLOSE-PW R
G31
1
2
GAP-CLOSE-PW R
G32
1
2
DCBATOUT
GAP-CLOSE-PW R
GAP-CLOSE-PW R
TC13
ST15U25VDM-1-GP
1
51125_VO1
51125_FB1
TONSEL
GND
25
R261
1
DY
0R2J-2-GP
C524
3D3V_AUX_S5
R281 2
1
0R0402-PAD
R282
2
DY
VREG5
2
1
DY
0R2J-2-GP
SC4D7U10V5KX-1GP
Close to VFB Pin (pin5)
51125_VCLK
5
6
7
8
1
2
R273
0R2J-2-GP
DY
GAP-CLOSE-PW R-3-GP
DY
R458
100KR2F-L1-GP
C518
SC18P50V2JN-1-GP
51125_FB1_R
C283
TC11
R270
30KR2F-GP
64.30025.6DL
SB
DY
1
3D3V_S5
1
5V_AUX_S5
DY
77.C2271.00L
2nd = 77.22271.27L
1 2
TPAD28
G80
R283
51125_VREF
Id=7.7A
Qg=8.5~13nC
Rdson=16.5~21mohm
G39
R276
100KR2J-1-GP
R266
20KR2F-L-GP
DY
GAP-CLOSE-PW R-3-GP
18
G79
VCLK
17
VREG3
SKIPSEL
P2003BEA-GP
51125_ENTIP1
15
74.51125.073
2
1
51125_PGOOD
GND
TPS51125RGER-GP
R264
0R0402-PAD
2
1
23
1
VREF
14
3D3V_AUX_S5
PGOOD
ENTRIP1
51125_SKIPSEL
51125_VREF
ENTRIP2
15V_AUX_S5_51125
51125_FB2_R
C516
DYSC18P50V2JN-1-GP
51125_TONSEL
EN0
Id=7.7A
Qg=8.5~13nC
Rdson=16.5~21mohm
C517
2 51125_EN 13
820KR2F-GP
51125_ENTIP2 6
VFB1
VFB2
VO1
IND-3D3UH-116-GP
3
2
1
VO2
51125_FB2
U29
51125_DRVL1
19
24
DRVL1
DRVL2
12
51125_VO2
51125_DRVL2
5V_PW R
L6
1
5
6
7
8
8
7
6
5
51125_VREF
1 2
R262
0R2J-2-GP
3D3V_AUX_S5
2
51125_LL1
3
2
1
20
D
D
D
D
1 S
2 S
3 S
1
1
16
LL1
LL2
S
S
S
1
R280
SCD22U6D3V2KX-1GP
11
ST220U6D3VDM-15GP
51125_LL2
SCD1U10V2KX-4GP
51125_DRVH1
Iomax=5A
Cyntec 7*7*3
DCR=30mohm, Irating=6A
Isat=13.5A
GAP-CLOSE-PWR-3-GP
21
P2003BEA-GP
DY
R269
10KR2F-2-GP
22
DRVH1
4
P2003BEA-GP
77.C2271.00L
2nd = 77.22271.27L
R265
6K65R2F-GP
VBST1
DRVH2
D
D
D
D
U23
GAP-CLOSE-PWR-3-GP
ST220U6D3VDM-15GP
SCD1U10V2KX-4GP
G42
VBST2
10
3D3V_AUX_S5_5_51125 8
TC8
9
51125_DRVH2
2
IND-3D3UH-116-GP
C529
SCD1U25V3KX-GP
51125_VBST1
SCD1U25V3KX-GP
L15
DY
VIN
1 S
2 S
3 S
51125_VBST2
DY
S
S
S
C528
2
1
DY
C295
Iomax=5A
3D3V_PW R
1
2
1
2
8
7
6
5
D
D
D
D
U47
4
P2003BEA-GP
U28
D
D
D
D
U22
Id=7A
Qg=8.7~13nC
Rdson=23~30mohm
C299
SCD01U50V2KX-1GP
51125_EN
C301
SC10U25V6KX-1GP
Id=7A
Qg=8.7~13nC
Rdson=23~30mohm
DY
DCBATOUT_5V
C533
SC10U25V6KX-1GP
C296
SC10U25V6KX-1GP
DY
SC10U25V6KX-1GP
SCD01U50V2KX-1GP
Cyntec 7*7*3
DCR=30mohm, Irating=6A
Isat=13.5A
C510
DCBATOUT
R457
249KR2F-GP
DY
SCD01U50V2KX-1GP
C298
DCBATOUT_3V
5V_AUX_S5_R_1
GAP-CLOSE-PW R
DY
C521
GAP-CLOSE-PW R
G38
1
2
5V_AUX_S5_R_2
GAP-CLOSE-PW R
G83
1
2
S5_ENABLE 28,34,43
SC18P50V2JN-1-GP
GAP-CLOSE-PW R
G43
1
2
2N7002KDW -GP
SC18P50V2JN-1-GP
DY
GAP-CLOSE-PW R
G12
1
2
G75
1
51125_ENTIP2
GAP-CLOSE-PW R
G10
1
2
79.68612.30L
2nd = 79.68612.L01
GAP-CLOSE-PW R
G41
1
2
DCBATOUT_3V
51125_ENTIP1
28,34,43 S5_ENABLE
GAP-CLOSE-PW R
G35
1
2
2N7002KDW -GP
GAP-CLOSE-PW R
51125_ENTIP2
84.2N702.A3F
RN59
SRN100KJ-6-GP
Q25
GAP-CLOSE-PW R
G11
1
2
DCBATOUT
C287
5V_S5
1
2
1
GAP-CLOSE-PW R
G74
1
2
TC30
SE68U25VM-3-GP
5V_PW R
5V_AUX_S5
G37
GAP-CLOSE-PW R
G46
1
2
DCBATOUT_5V
G73
2
DCBATOUT
S5_ENABLE
C534
SC22U6D3V5MX-2GP
78.22610.51L
<Core Design>
1
0R2J-2-GP
Wistron Corporation
Title
DCDC 5V/3D3V (TPS51125)

Size
Custom
5
Date:
2
Document Number
Rev
SB
LB46E
Sheet
1
37
of
53
SSID = PWR.Plane.Regulator_1p5v0p75v
5V_AUX_S5
13,28,34,39,44
R566
5D1R3J-GP
5V_AUX_S5
13
7 S3_PWRGD
1D5V_EN
620KR2F-GP
11
0D75V_EN 10
23
15
14
NC#12
DH
VTTEN
21 TPS51116_UGT
20 TPS51116_PHS
GAP-CLOSE-PWR
PG5006
2
1
LX
19 TPS51116_LGT
GAP-CLOSE-PWR
PG5008
2
1
VTTIN
2 1M1R2J-GP
PR5014
7,13,28 PM_SLP_S4#
1D5V_EN
2
0R0402-PAD
DY
DL
PC5022
SCD1U10V2KX-4GP
+1.5V_SUS_P
GAP-CLOSE-PWR
PG5003
1
2
GAP-CLOSE-PWR
TPS51116_VDDQSET
5V_AUX_S5
GAP-CLOSE-PWR
PG5009
1
2
S
S
S
1
2
GAP-CLOSE-PWR
PG5011
1
2
PC5007
SC4D7U25V5KX-GP
C695
SCD033U16V3KX-GP
Q54
P0903BK-GP-U
PC5006
SCD1U50V3KX-GP
PC5020
SC1U10V3KX-3GP
DCBATOUT_1D5V
GAP-CLOSE-PWR
PG5012
1
2
84.00903.037
GAP-CLOSE-PWR
PG5019
1
2
TPS51116_UGT
PG5014
2
TPS51116_PHS
Hi
On
On
Lo
Hi
On
On
Off(Hi-Z)
S4/S5
Lo
Lo
Off
Off
Off
TPS51116_VDDQSNS
PR5009
VTTREF and VTT
2.5
VVDDQSNS/2
DDR
V5IN
1.8
VVDDQSNS/2
DDR2
FB Resistors
Adjustable
VVDDQSNS/2
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L

Inductor: 0.56uH PCMC104T-R56MN Cyntec DCR:1.8mohm Isat=25Arms 68.R5610.10D
O/P cap: 330U 2.5V EEFSX0D331ER 9mOhm 3Arms PANASONIC/ 79.33719.L0
H/S: SiS406DN/ POWERPAK-8/ 11.5mOhm/14.5mOhm @4.5Vgs/ 84.00406.037
L/S: SiS402DN/ POWERPAK-8/ 6.4mOhm/8mohm@4.5Vgs/ 84.00402.037
Switching freq-->400KHz
1.5 V < VVDDQ < 3 V
PC5016
SC18P50V2JN-1-GP
Wistron Corporation

Title
TPS51116_+1.5V_S3
Size
Custom
<Core Design>
PR5010
30KR2F-GP
Date:
5
GAP-CLOSE-PWR
NOTE
GND
GAP-CLOSE-PWR
PG5022
1
2
VDDQ (V)
TPS51116_VDDQSET
VDDQSET
DY
30K9R2F-GP
1
2
On
PC5015
SC330P50V3KX-GP
GAP-CLOSE-PWR
PG5021
1
2
PC4511
Hi
S3
DY
S0
TPS51116_PHS_SET
PG5016
GAP-CLOSE-PWR-3-GP
VTT
4
3
2
1
VTTREF
PTC4505
SE330U2VDM-L-GP
VDDR
PR5008
2D2R5F-2-GP
SE330U2VDM-L-GP
S5
PTC4504
DY
84.00460.037
S
S
S
G
S3
Q53
SIR460DP-T1-GE3-GP
GAP-CLOSE-PWR
TPS51116_LGT
State
IND-D56UH-27-GP
C702
SCD1U25V3KX-GP
GAP-CLOSE-PWR
PG5020
1
2
L27
TPS51116_VBST1 1
GAP-CLOSE-PWR
PG5015
1
2
+1.5V_SUS_P
5
6
7
8
PC5011
SC10U6D3V5MX-3GP
1
2
0D75V_S0
SCD1U25V3KX-GP
PC5010
SC10U6D3V5MX-3GP
1
2
0D75V_S0_P
D
D
D
D
PC5009
SC10U6D3V5MX-3GP
1
2
PC5008
SCD1U10V2KX-4GP
3
2
1
GAP-CLOSE-PWR
PG5013
1
2
Iomax=16A
OCP>24A
DY
0R2J-2-GP
D
D
D
D
0D75V_S0_P
DY
DDR_VREF_S3
PR5013
1
2
0R0603-PAD
GAP-CLOSE-PWR
PG5007
1
2
PR5005
PC5005
SC10U25V6KX-1GP
REF
VSSA
74.51116.073
Design Current = 0.7A
VCCA
1TPS51116_REF
25
GND
VTTS
FB
VTT
TPS51116_VDDQSNS
24
DY
GAP-CLOSE-PWR
PG5005
1
2
18
17
VDDQS
PC5004
SC10U25V6KX-1GP
PGND1
PGND1
TON
PGND2
PC5035
SC10U25V6KX-1GP
5
6
7
8
1
TPS51116_TON
1D5V_S3
PG5001
2
TPS51116RGER-GP-U
2 0R2J-2-GP
PC5017
SC1KP50V2KX-1GP
0D75V_S0_P
DCBATOUT_1D5V
PG5002
1
GAP-CLOSE-PWR
PG5004
2
1
DY
2 TPS51116_VBST1
0R3J-0-U-GP
EN/PSV
C685
7 NC#7
SC1U10V3KX-3GP
22 TPS51116_VBST
PGD
+1.5V_SUS_P
DCBATOUT
PR546
BST
PC5001
SCD1U10V2KX-4GP
PD5001
CH551H-30PT-GP
TPS51116_NC#12 12
1 PR5011 2
DY
U52
VDDP
ILIM
VDDP
16
2
PR570
20KR2F-L-GP
DY
1
2
5V_AUX_S5
TPS51116_VDD_R
+1.5V_SUS_P
PR50021
C687
SC1KP50V2KX-1GP
SC1U10V3KX-3GP
C684
DCBATOUT_1D5V
5V_AUX_S5
PR50011
TPS51116_VDD
C682
SC1U10V3KX-3GP
2
1
RT: Non_ASM
TI: ASM
0D75V_EN
0R2J-2-GP
DY
2 0R2J-2-GP
PR5015
1
13KR2F-GP
R559
3D3V_AUX_S5
DY
PR5012 1
PM_SLP_S3#
Document Number
Rev
SB
LB46E
Sheet
1
38
of
53
DCBATOUT
PW R_1D05V_DCBATOUT
PG4501
PG4502
PG4503
PW R_1D05V_DCBATOUT
GAP-CLOSE-PW R-3-GP
1
2
SCD1U25V2KX-GP
1
2
PTC4503
PTC4502
84.00460.037
PR4507
10KR2F-2-GP
2
Id=26.5A
Qg=40.6~61nC,
Rdson=2.6~3.2mohm
PC4509
U27
SIR460DP-T1-GE3-GP
SCD1U25V3KX-GP
PC4501
SE330U2VDM-L-GP
2
IND-D88UH-10-GP
SE330U2VDM-L-GP
PC4505
0920 SB
S
S
S
G
PW R_1D05V_VFB
1
SC1KP50V2KX-1GP
5
6
7
8
3
2
1
TPS51218DSCR-GP-U1
1D05V_S0
L16
5V_S5
PW R_1D05V_LGATE
SC1U10V2KX-1GP
PC4503
SCD1U25V3KX-GP
1
2PW R_1D05V_BOOT_R
2
Iomax=16A
OCP>24A
PR4505
2D2R3J-2-GP
PW R_1D05V_BOOT 1
PW R_1D05V_UGATE
PW R_1D05V_PHASE
D
D
D
D
PR4504
470KR2F-GP
11
10
9
8
7
6
GND
VBST
DRVH
SW
V5IN
DRVL
PGOOD
TRIP
EN
VFB
RF
0R0402-PAD PR4502
1
2
3
4
5
EC4501
5
6
7
8
PM_SLP_S3#
PW R_1D05V_TRIP
PW R_1D05V_EN
PW R_1D05V_VFB
95K3R3F-GP PW R_1D05V_CCM
2
4
3
2
1
PR4501
13,28,34,38,44
MODIFY to Mag. 0.88uH 10*10*4

(68.R8810.10G)
DCR=1.1~13mohm
Idc=20A, Isat=23A
U46
PC4514
10KR2J-3-GP
36 CPUCORE_ON
0920 SB
S
S
S
Id=14.3A
Qg=9.2~14nC
Rdson=11~14mohm
4
PR4512
1
PC4513
SC4D7U25V5KX-GP
3D3V_S0
PC4512
SC4D7U25V5KX-GP
GAP-CLOSE-PW R-3-GP
PC4504
SC4D7U25V5KX-GP
TPS51218 for 1D05V
D
D
D
D
U26
P0903BK-GP-U
SC4D7U25V5KX-GP
PG4504
0920 SB
GAP-CLOSE-PW R-3-GP
D
GAP-CLOSE-PW R-3-GP
PR4508
20K5R2F-GP
Vout=0.704V*(R1+R2)/R2
RT9025 for 1D8V_S0
3D3V_S5
5V_S5
RT9025-25PSP-GP
9025_ADJ
1
74.09025.03D
R511
R489
14K3R2F-GP
36 CPUCORE_ON
C508
C507
GAP-CLOSE-PW R-3-GP
DY
<Core Design>
DY 10KR2F-2-GP
C450
R483
DY
18KR2F-GP
5
6
7
8
NC#5
VOUT
ADJ
GND
SC10U6D3V5MX-3GP
3D3V_S0
G93
1
SC10U6D3V5MX-3GP
C456 DY
SCD1U10V2KX-5GP
VDD
VIN
EN
PGOOD
SC100P50V2JN-3GP
4
3
2
1
GAP-CLOSE-PW R-3-GP
2
1D8V_S0
Vo(cal.)=1.8069V
0R0402-PAD R512
GND
U35
9025_EN
G92
1
1D8V_LDO
1
2
PM_SLP_S3#
C446
SC1U6D3V2KX-GP
13,28,34,38,44
Iomax=0.8A
OCP>1.35A
1
2
C199
SC10U6D3V5MX-3GP
Wistron Corporation
9025_PGOOD

Vo=0.8*((R1+R2)/R2)
0R0402-PAD R510
Title
Size
5
Date:
2
DC/DC_1D05V_TPS51218
Document Number
Rev
LB46E
SA
Sheet
39
of
53
DC1
Adaptor in to generate DCBATOUT
1
AFTE14P-GP
AFTE14P-GP
1
1
AD+
AD_JK
2
3
4
5
6
AFTP3802
AFTP3803
AD+_2
R1
PR3802
100KR2J-1-GP
84.00124.K1K
R2
PDTA124EU-1-GP
AD_OFF
8
7
6
5
PC3802
SC1U50V5ZY-1-GP
PQ3801
28
D
D
D
D
AD_OFF#_JK
PR3804
34K8R2F-1-GP
1
SCD1U50V3ZY-1-GP
2
AFTP3801 AFTE14P-GP
R2
PC3803
PQ3802
AD_DETECT 28
R1
2nd = 20.D0187.106
PU3801
S
S
S
G
TPCC8103-GP
PR3801
200KR2F-L-GP
20.F0735.006
ACES-CON6-3GP
PR3803
200KR2F-L-GP
PC3801
SCD1U50V3ZY-1-GP
8
4
1
2
3
4
PDTC124EU-1-GP
84.00124.H1K
2ND = 84.00124.X1K
BATA_SDA_1 43
BATA_SCL_1 43
BAT_IN#_1 43
BATT_SENSE 41,43
3
BATTERY CONNECTOR
1
2
PC3901
SCD1U50V3KX-GP
BT+
PC3902
SC2200P50V2KX-2GP
41,43 BATT_SENSE
0R0402-PAD PR3901
PRN3901
SRN33J-7-GP
4
3
2
1
28,41 BAT_SCL
28,41 BAT_SDA
28 BAT_IN#
BTY1
8
1
BT+
5
6
7
8
BATA_SCL_1
BATA_SDA_1
BAT_IN#_1
PC3904
2ND = 83.5R603.K3F
3rd = 83.5R603.Q3F
BAV99-8-GP
D3903
1
BAV99-8-GP
DY
DY
1
AFTE14P-GP
AFTP3804
ALP-CON7-21-GP-U
20.81323.007
BAT_SCL
BAT_SDA
BAT_IN#
D3902
PD3901
MMPZ5232BPT-GP-U
SC10P50V2JN-4GP
DY
SC1000P50V3JN-GP-U
83.5R603.D3F
SC10P50V2JN-4GP
PC3903
PC3905
2
3
4
5
6
7
9
D3901
BAV99-8-GP
<Core Design>
Wistron Corporation
3D3V_AUX_KBC

Title
Size
Rev
SB
LB46E
A
AD/BATT CONN
Document Number
Date:
D
Sheet
E
40
of
53
AD+ total power
NEAR
AD+
R1
R2
65w
187k
49.9k
90w
121k
49.9k
AD+ total power

80w
R1
R2
137k
49.9k
U3
BT+
1
2
3
4
C340
2
1BQ24745_CSSP
R2
SCD1U50V3KX-GP
74.24745.073
NC#16
16
VFB
15
C18
C19
C323
SCD1U50V3KX-GP
20100518 WAYNE
BATT_SENSE
BATT_SENSE 40,43
MAX8731A_CSIP
MAX8731A_CSIN
BQ24745RHDR-GP
C375
SCD1U25V2ZY-1GP
C338
SC1U10V3KX-3GP
FBO
EAI
EAO
VREF
CE
GND
GND
6
5
4
3
7
12
84.02003.D37
2
4
C365
2
1
29
1
2
C341
SC56P50V2JN-2GP
BQ24745_EAI
BQ24745_EAO
BQ24745_VREF
BQ24745_CHG_ON
C337
R167
SC2200P50V2KX-2GP
7K5R2F-1-GP
2
1BQ24745_EAO_RC2
1
C318
G55
17
G56
U39
P2003BEA-GP
VICM
R166
1
2BQ24745_FBO
4K7R2J-2-GP
1
2
BQ24745_FBO_RC
R171
1
2
200KR2F-L-GP
NC#14
D01R3721F-GP-U
IND-5D6UH-45-GP
SCD1U50V3KX-GP
18
0920 SB
SC10U25V6KX-1GP
CSOP
CSON
24745_LOW _G
BT+_R
SC10U25V6KX-1GP
PGND
19
SC10U25V6KX-1GP
LGATE
20
SDA
BQ24745_LX1
R160
GAP-CLOSE-PWR-3-GP
C351
SC220P50V2KX-3GP
23
L7
1
2
C372
SCD1U50V3KX-GP
S
S
S
SC150P50V2JN-3GP
PHASE
BT+
24745_HIGH_G
SCL
CHG_AGND
BQ24745_IINP
C336
1
CH520S-30PT-GP
ACOK
GAP-CLOSE-PWR-3-GP
CHG_AGND
AD_IA
2 C367
4
SC1U10V3KX-3GP
D
D
D
D
14
28
24
84.02003.D37
D12
UGATE
2STOP_CHG#
U32
P2003BEA-GP
25
21
83.R0203.08F
2nd = 83.1R003.I8F
C319
SCD1U25V2ZY-1GP
BOOT
VDDP
BQ24745_CSSN
BQ24745_ICOUT 1
PR4012
0R0402-PAD
BQ24745_BST
BQ24745_VDDP
C17
27
26
CSSN
ICOUT
28
3
2
1
CSSP
C331
VDDSMB
CHG_AGND
1 R172
2
0R0201-PAD-GP
C315
28,40 BAT_SDA
0920 SB
10
C358
SC1U10V3KX-3GP
28,40 BAT_SCL
BQ24745_ACOK 13
SCD1U50V3KX-GP
C344
SCD1U50V3KX-GP
CHG_AGND
1 R183
2
0R0201-PAD-GP
DCBATOUT
C350
1
S
S
S
AC_OK
C342
SCD01U50V2KX-1GP
STOP_CHG#
28 STOP_CHG#
5
6
7
8
11
3D3V_AUX_S5
R153
470KR2J-2-GP
PR4009
10KR2F-2-GP
SC10U25V6KX-1GP
ACIN
3D3V_AUX_S5
SC10U25V6KX-1GP
DCIN
PD4002
SMF18A-GP
83.SMF18.AAH
SC10U25V6KX-1GP
22
BQ24745_ACIN
8
7
6
5
84.08103.037
D
D
D
D
BQ24745_DCIN
D
D
D
D
CHG_AGND
ICREF
49K9R2F-L-GP
CHG_AGND
U41
R164
316KR3F-2-GP
C
AC_OK
U31
S
S
S
G
TPCC8103-GP
STOP_CHG#
connects to KBC
3
2
1
1
PR4008
AD+
5
6
7
8
C364
SC1U25V5KX-1GP
1
2
AD+
R1
PR4007
121KR2F-L-GP
83.00400.C1F
2nd = 83.1S400.B2F
1
2
3
4
PC4024
G4
GAP-CLOSE-PWR-3-GP
BQ24745_VREF
GAP-CLOSE-PWR-3-GP
84.2N702.A3F
2nd = 84.DM601.03F
20100518 WAYNE
G3
D13
1SS400GPT-GP
DC_IN_D
Q2
2N7002KDW -GP
R169
49K9R2F-L-GP
D01R3721F-GP-U
0914 SB
1
2
AD+
R12
49K9R2F-L-GP
0914 SB
SCD1U25V2ZY-1GP
C324
SCD1U25V2ZY-1GP
AD+_TO_SYS
AD+_G_2
AD+_G_1
R9
R11
100KR2J-1-GP
TPCC8103-GP
R10
10KR2F-2-GP
DCBATOUT
S
S
S
G
D
D
D
D
8
7
6
5
0R0402-PAD
1
CHG_AGND
R163
CHG_AGND
CHG_AGND
BQ24745_VREF
RN43
3D3V_AUX_S5
8
7
6
5
Q20
AC_OK
CHG_ON#
AC_IN#
BQ24745_CHG_ON
DY
C345
SCD1U10V2KX-4GP
BQ24745_CHG_ON
AC_OK
<Core Design>
A
CHG_ON#
AC_IN#
CHG_ON#
28
AC_IN#
28
Wistron Corporation
SRN100KJ-L-GP
1
2
3
4
84.2N702.A3F
2N7002KDW -GP
C398
SC1U10V3KX-3GP
Title
Size
5
Date:
2
Charger_BQ24745
Document Number
Rev
LB46E
SA
Sheet
41
1
of
53
DCBATOUT
D
1
2
1
2
1
2
1
2
EC133
SCD1U25V2ZY-1GP
EC103
SCD1U25V2ZY-1GP
EC102
SCD1U25V2ZY-1GP
GNDPAD4
GNDPADS197X138-NP
GNDPAD3
GNDPADS197X138-NP
EC101
SCD1U25V2ZY-1GP
EC99
SCD1U25V2ZY-1GP
EC98
SCD1U25V2ZY-1GP
GNDPAD2
GNDPADS197X138-NP
EC97
SCD1U25V2ZY-1GP
EC17
SCD1U25V2ZY-1GP
EC16
SCD1U25V2ZY-1GP
GNDPAD1
GNDPADS197X138-NP
EC95
SCD1U25V2ZY-1GP
EC94
SCD1U25V2ZY-1GP
EC15
SCD1U25V2ZY-1GP
SPRING2
SPRING-12-GP-U1
EC14
SCD1U25V2ZY-1GP
EC92
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SPRING1
SPRING-12-GP-U1
EC91
EC11
SCD1U25V2ZY-1GP
1D05V_S0
EC13
HT8BE75R24-U-45-GP
H9
HT8BE75R24-U-45-GP
H8
H7
HT75X825B9X9R24-S-GP
H6
HT75X825B9X9R24-S-GP
HT8BE75R24-U-45-GP
H5
H25
HOLE315R95-GP
H27
STF217R115H221-GP
STF217R128H83-GP
H22
H26
STF217R115H221-GP
H24
HOLE315R95-GP
H21
HT8BE75R24-U-45-GP
ZZ.00PAD.ZZZ
H4
H3
ZZ.00PAD.ZZZ
H19
HOLE237R95-GP
HOLE276R178-GP
H13
HOLE276R178-GP
HOLE276R178-GP
STF217R128H83-GP
HOLE237R95-GP
H1
ZZ.00PAD.ZZZ
H12
HOLE276R178-GP
H11
H10
ZZ.00PAD.ZZZ
34.41Y19.001
HOLE315X315R91-S1-GP
34.41Y19.001
<Core Design>
Wistron Corporation
Title
Size
Rev
SB
LB46E
5
EMI/Spring/Boss
Document Number
Date:
2
Thursday, December 02, 2010
Sheet
1
42
of
53
Battery
Touch pad
5V_S0
30
30
30,32
30,32
TP_DATA
TP_CLK
TP_RIGHT
TP_LEFT
1
1
1
1
1
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTP109
AFTP105
AFTP110
AFTP114
AFTP113
40,41
40
40
40
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
1
1
1
1
1
1
BATT_SENSE
BATA_SDA_1
BATA_SCL_1
BAT_IN#_1
BT+
BT+
AFTP18
AFTP16
AFTP17
AFTP15
AFTP13
AFTP14
Keyboard
28
28
28
28
KCOL16_Q
KCOL15
KCOL14
KCOL13
1
1
1
1
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTP127
AFTP139
AFTP148
AFTP146
28
28
28
28
KCOL8
KCOL7
KCOL6
KCOL5
1
1
1
1
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTP98
AFTP99
AFTP101
AFTP100
28
28
28
28
KCOL4
KCOL3
KCOL2
KCOL1
1
1
1
1
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTP118
AFTP138
AFTP122
AFTP123
28
28
28
28
KROW0
KROW7
KROW6
KROW5
1
1
1
1
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTP152
AFTP154
AFTP153
AFTP151
28
28
28
28
KROW4
KROW3
KROW2
KROW1
1
1
1
1
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTP94
AFTP95
AFTP92
AFTP97
28
28
28
28
KCOL12
KCOL11
KCOL10
KCOL9
1
1
1
1
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTE14P-GP
AFTP260
AFTP116
AFTP117
AFTP102
28
28
KCOL17_Q
KCOL0
1
1
AFTE14P-GP
AFTE14P-GP
AFTP72
AFTP87
28
28
KB_LED_1
KB_LED_2
1
1
AFTE14P-GP
AFTE14P-GP
AFTP73
AFTP74
Check test point
28,34,37 S5_ENABLE
4,6
H_CPURST#
AFTE14P-GP
AFTP242
AFTE14P-GP
AFTP239
Test Point locate near DIMM Door where can be tested

FAN
27 EMC2102_FAN_TACH
AFTE14P-GP
AFTP187
27 EMC2102_FAN_DRIVE
AFTE14P-GP
AFTP188
Cover Switch
3D3V_AUX_S5
AFTE14P-GP
AFTP240
<Core Design>
A
Wistron Corporation
Title
Size
AFTE test point
Document Number
Rev
SB
LB46E
5
Sheet
43
of
1
53
DCBATOUT
SSID = PWR.Plane.Regulator_GFX
1
2
PWR_VGA_CORE_VOUT
RT8208AGQW-GP
PWR_VGA_CORE_VOUT
DIS
RT8208A:74.08208.073
DIS
PTC9204
DIS
DIS
2
DIS
PTC9203
PTC9202
DIS
84.06725.030
DIS
2
50
PC9208
SCD1U10V2KX-4GP
NVVDD_ALTV1
PWR_VGA_CORE_D1
PWR_VGA_CORE_D0
GAP-CLOSE-PWR-3-GP
PG9205
U56
IRF6725MTRPBF-GP-U
VOUT
SE330U2VDM-L-GP
GND
50
S
S
G
17
EM/DEM
DIS IND-D36UH-19-GP
NVVDD_ALTV0
PWR_VGA_CORE_FB
SE330U2VDM-L-GP
15
7
3
14
5
6
L28
SE330U2VDM-L-GP
8209A_EN/DEM_VGA
G0
FB
G1
D1
D0
+VGA_CORE
PR9203
10R2J-2-GP
PGOOD
CS
13
12
11
8
7
6
2
1
VDD
BOOT
UGATE
PHASE
LGATE
DIS
PC9206
PWR_VGA_CORE_BOOT 1
2PWR_VGA_CORE_BOOT_C 1
SCD1U25V3KX-GP
2D2R3J-2-GP
PWR_VGA_CORE_UGATE
PWR_VGA_CORE_PHASE
PWR_VGA_CORE_LGATE
5
4
3
2
4
10
TON
VDDP
8209A_PGOOD_VGA
PWR_VGA_CORE_CS
16
9
DIS
Design Current = 21.94A

24.14A<OCP< 28.53A
PR9205
182KR2F-GP
D
D
D
D
DIS
1
2
2 PR9201 1
DIS 10R2F-L-GP
PWR_VGA_CORE_VDD
PC9207
SC1U10V2KX-1GP
Vout=0.75V*(R1+R2)/R2
DIS
DIS
7K68R2F-GP
DIS
1
2
SE47U25VM-11-GP
PC9203
SC4D7U25V5KX-GP
U61
PWR_VGA_CORE_TON
SC1U10V2KX-1GP
PR9204
1
DIS
DIS
SC4D7U25V5KX-GP
DIS
TPAD40-GP
PC9201
PR9202
PC9202 PC9205
DIS
SC4D7U25V5KX-GP
84.06721.030
TP9203
79.47612.3FL
DIS
SCD1U25V3KX-GP
PWR_VGA_CORE_UGATE 1
PTC9201
PC9204
D
D
D
D
U60
IRF6721SPBF-GP-U
5V_S5
6
5
2
1
DCBATOUT
TP9201
2
1
DIS
100KR2J-1-GP
PWR_VGA_CORE_EN_R#
DY
CH551H-30PT-GP
DY
DY
PC9211
SCD1U10V2KX-4GP
DY PR9217
PC9209 PC9210
PR9208
10KR2F-2-GP
8209A_EN/DEM_VGA
DY
PM_SLP_S3#
13,28,34,38,39
3D3V_AUX_S5
SC10P50V2JN-4GP
TPAD40-GP
PD9201
0R0402-PAD
2 1KR2J-1-GP
3D3V_S0_NV
TP9202
DIS
VGACORE_VDD_SENSE_1
SC10P50V2JN-4GP
PWR_VGA_CORE_LGATE 1
PR9206 1
PR9211
1
TPAD40-GP
46 VGACORE_VDD_SENSE
+VGA_CORE
PQ9201
DMN66D0LDW-7-GP
DY
PWR_VGA_CORE_FB
45
DIS
1
2
PQ9206_3
8209A_EN/DEM_VGA
41K2R2F-GP
DIS
1GND_SENSE_1
1
2
DGPU_PWROK
1 PR9214
2
0R0201-PAD-GP
DY 100R2J-2-GP
PR9213
PWR_VGA_CORE_D1
PWR_VGA_CORE_D0
DIS
PC9212
SC100P50V2JN-3GP
PR9210
75KR2F-GP
DY
PR9212
10KR2J-3-GP
8209A_PGOOD_VGA
PR9215
PR9209
150KR2F-L-GP
3D3V_S0_NV
PR9216
1
DIS
0R0402-PAD
2
VGACORE_GND_SENSE
46
PR9207
10R2J-2-GP
2
DIS
<Core Design>
Wistron Corporation
Title
Size
5
Date:
2
DC/DC_VGA CORE_RT8208B
Document Number
Rev
LB46E

1
SA
Sheet
44
of
53
Del +3VS to 1.8V Transfer for OP 0119

+3VS to 1.8V Transfer
0R0402-PAD R342
1
I=300mA
DGPU_PWROK_TO1D8V
U63
DGPU_PWROK
44
1
2
+1.5V to FBVDD Transfer
+1.05V to +1.05V_NV Transfer
1D8V_S0_NV = IFPA_IOVDD & IFPB_IOVDD, it

should be the latest ramp up rail.
FBVDD
4.3A SA 0902
U45
1
2
DIS
1D05V_S0_NV
8 D
7 D
6 D
5 D
U48
S
S
S
G
3.6A
1
2
3
4
DY
C747
AO4468-GP
DIS 84.04468.037
2ND = 84.04800.D37
3RD = 84.08061.037
SCD1U25V2ZY-1GP
C728
SC10U6D3V3MX-GP
1D05V_S0
2ND = 84.00610.C31
84.S0610.B31
Q51
RUNON_S
DIS
C729
DY
SCD1U25V2ZY-1GP
DIS
C727
DIS
84.08056.037
RUN_POWER_ON
R493
1
2
3
G
TPCA8056-H-GP
DIS
S
S
S
SCD1U16V2KX-3GP
C726
SC10U6D3V3MX-GP
8 D
7 D
6 D
5 D
1D5V_S3
DIS
C732
SC1U10V3KX-3GP
DIS
74.09091.G3F
DIS
C731
SC1U10V2ZY-GP
C730
G9091-180T11U-GP
DY
3D3V_S0_NV
1D8V_S0_NV
1
2
3
4
5
SC1U10V2ZY-GP
VIN
GND
EN
NC#4
VOUT
NDS0610-NL-GP
S
200KR2J-L1-GP
RUNON_R
DIS
DY
2
DIS
DIS
DIS_EN_1D5_RUN
1 C743
2
R602
330KR2F-L-GP
SCD22U25V3KX-GP
1
2DIS_EN_1D5_RUN_R
R485
330KR2J-L1-GP
R341
DIS
100KR2J-1-GP
0R0402-PAD R486
1
Q47
2N7002A-7-GP
DIS
2
DGPU_PWROK_R
84.2N702.E31
C744
SCD01U16V2KX-3GP
44 DGPU_PWROK
DIS
+3VS to 3.3V_DELAY Transfer

3.3v (580mA)
VDDR3discharge CKT
DIS
R524
3D3V_S0_NV
0R3J-4-GP
B
3D3V_S0
<Core Design>
Wistron Corporation
Title
5
NV power
Size
A2
Document Number
Date:
Rev
SA
LB46E
1
Sheet
45
of
53
71.0N11M.C1U
PEG_TXP14
PEG_TXN14
1
DIS
1
DIS
PEG_TXP15
PEG_TXN15
AG25
AG26
2 C553 SCD1U10V2KX-5GP PEX_TXP15AE25
2 C550 SCD1U10V2KX-5GP PEX_TXN15AE26
AF27
AE27
PEX_RX6
PEX_RX6#
PEX_TX7
PEX_TX7#
PEX_RX7
PEX_RX7#
PEX_TX8
PEX_TX8#
VDD_SENSE
GND_SENSE
PEX_TX9
PEX_TX9#
VDD_SENSE
GND_SENSE
PEX_RX9
PEX_RX9#
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
PEX_TX10
PEX_TX10#
PEX_RX10
PEX_RX10#
PEX_SVDD_3V3
PEX_RX11
PEX_RX11#
120mA
SA 0824
C556
DIS
AG9
C433
AF9
DIS
C495
DIS
DIS
PEX_RX14
PEX_RX14#
DIS
2
1
3D3V_S0_NV
C498
DIS
Uner GPU
B
Near
GPU
C486
Near GPU
1D05V_S0_NV
L23
DIS
1
2
HCB1608KF-181-GP
C485
DIS
PEX_TX15
PEX_TX15#
AG10
C496
PEX_PLLVDD
120mA
PEX_TERMP
1
VGACORE_VDD_SENSE 44
VGACORE_GND_SENSE 44
PEX_TX14
PEX_TX14#
PEX_RX15
PEX_RX15#
DIS
1
0R2J-2-GP
R304
E15
E14
A12
B12
C12
D12
E12
F12
PEX_RX12
PEX_RX12#
PEX_RX13
PEX_RX13#
Under GPU
DY
Uner
GPU
PEX_PLLVDD
DIS
C243
1
2
2
VGACORE_VDD_SENSE 44
VGACORE_GND_SENSE 44
120mA
PEX_TX13
PEX_TX13#
1
2
1
2
1
0R2J-2-GP
R303
W15
W16
PEX_TX12
PEX_TX12#
1
2
1
2
3D3V_S0_NV
PEX_TX11
PEX_TX11#
C241
+VGA_CORE
DY
PEX_RX8
PEX_RX8#
DIS
PEX_TX6
PEX_TX6#
PEX_RX5
PEX_RX5#
DIS
68.00214.051
AG24
AF25
2 C774 SCD1U10V2KX-5GP PEX_TXP14AD23
2 C509 SCD1U10V2KX-5GP PEX_TXN14AD24
PEX_TX5
PEX_TX5#
DIS
C488
DIS
PEX_TERMP
N11M-LP1-S-A2-GP-U
R90
2K49R2F-GP
DIS
DIS
2
7 PEG_TXP15
7 PEG_TXN15
2 C780 SCD1U10V2KX-5GP PEX_TXP13AC22

PEX_RX4
PEX_RX4#
PEG_RXP15
PEG_RXN15
1
DIS
1
DIS
AE24
AF24
PEX_TX4
PEX_TX4#
C267
SC4D7U6D3V3KX-GP
PEG_RXP15
PEG_RXN15
PEG_TXP13
PEG_TXN13
AF22
AE22
2 C512 SCD1U10V2KX-5GP PEX_TXP12AB21
2 C784 SCD1U10V2KX-5GP PEX_TXN12AB22
PEX_RX3
PEX_RX3#
SC4D7U6D3V3KX-GP
PEG_RXP14
PEG_RXN14

2 C768 SCD1U10V2KX-5GP PEX_TXN11AC21
PEX_TX3
PEX_TX3#
DIS
SC1U6D3V2KX-GP
PEG_RXP14
PEG_RXN14
1
DIS
1
DIS
AG21
AG22
PEX_RX2
PEX_RX2#
15690mA
SC4D7U6D3V3KX-GP
PEG_RXP13
PEG_RXN13
PEG_RXP13
PEG_RXN13

PEX_TX2
PEX_TX2#
SCD1U10V2KX-5GP
1
DIS
1
DIS
PEG_TXP12
PEG_TXN12
7 PEG_TXP14
7 PEG_TXN14
7
7
1
DIS
1
DIS
PEG_TXP11
PEG_TXN11
PEG_RXP12
PEG_RXN12
PEG_RXP12
PEG_RXN12
7 PEG_TXP13
7 PEG_TXN13
7
7
1
DIS
1
DIS
DIS
C263
+VGA_CORE
SCD1U10V2KX-5GP
PEG_RXP11
PEG_RXN11
PEG_RXP11
PEG_RXN11
2 C500 SCD1U10V2KX-5GP PEX_TXP9 AB19

2 C783 SCD1U10V2KX-5GP PEX_TXN9 AB20
AE21
AF21
PEG_TXP10
PEG_TXN10
7 PEG_TXP12
7 PEG_TXN12
7
7
1
DIS
1
DIS
DIS
SA-0820
SCD1U10V2KX-5GP
PEG_RXP10
PEG_RXN10
PEG_RXP10
PEG_RXN10
2 C523 SCD1U10V2KX-5GP PEX_TXP8 AC18

AF19
AE19
PEG_TXP9
PEG_TXN9
7 PEG_TXP11
7 PEG_TXN11
7
7
1
DIS
1
DIS
C258
C158
C216
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
DIS
PEG_RXP9
PEG_RXN9
7 PEG_TXP10
7 PEG_TXN10
7
7
AG18
AG19
PEG_TXP8
PEG_TXN8
PEG_RXP9
PEG_RXN9
2 C547 SCD1U10V2KX-5GP PEX_TXP7 AD17

2 C555 SCD1U10V2KX-5GP PEX_TXN7 AD18
PEX_RX1
PEX_RX1#
C482
Near GPU
J10
J12
J13
J9
L9
M11
M17
M9
N11
N12
N13
N14
N15
N16
N17
N19
N9
P11
P12
P13
P14
P15
P16
P17
R11
R12
R13
R14
R15
R16
R17
R9
T11
T17
T9
U19
U9
W10
W12
W13
W18
W19
W9
SCD1U10V2KX-5GP
1
DIS
1
DIS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
PEG_RXP8
PEG_RXN8
PEG_RXP8
PEG_RXN8
2 C775 SCD1U10V2KX-5GP PEX_TXP6 AC16

AE18
AF18
PEG_TXP7
PEG_TXN7
7 PEG_TXP9
7 PEG_TXN9
7
7
1
DIS
1
DIS
DIS
PEG_RXP7
PEG_RXN7
PEG_RXP7
PEG_RXN7

AF16
AE16
PEG_TXP6
PEG_TXN6
7 PEG_TXP8
7 PEG_TXN8
7
7
1
DIS
1
DIS
PEX_TX1
PEX_TX1#
PEG_RXP6
PEG_RXN6
PEG_RXP6
PEG_RXN6

2 C778 SCD1U10V2KX-5GP PEX_TXN4 AC15
AG15
AG16
PEG_TXP5
PEG_TXN5
7 PEG_TXP7
7 PEG_TXN7
7
7
1
DIS
1
DIS
DIS
PEX_RX0
PEX_RX0#
PEG_RXP5
PEG_RXN5
7 PEG_TXP6
7 PEG_TXN6
7
7
AE15
AF15
PEG_TXP4
PEG_TXN4
PEG_RXP5
PEG_RXN5

C238
PEG_RXP4
PEG_RXN4
PEG_RXP4
PEG_RXN4
7 PEG_TXP5
7 PEG_TXN5
7
7
1
DIS
1
DIS
PEG_TXP3
PEG_TXN3
7 PEG_TXP4
7 PEG_TXN4
7
7
AF13
AE13
DIS
PEG_RXP3
PEG_RXN3
PEG_RXP3
PEG_RXN3

DIS
C232
AG12
AG13
1
DIS
1
DIS
PEG_TXP2
PEG_TXN2
7 PEG_TXP3
7 PEG_TXN3
7
7
AE12
AF12
C262
PEG_RXP2
PEG_RXN2
PEG_RXP2
PEG_RXN2
7 PEG_TXP2
7 PEG_TXN2
7
7

2 C548 SCD1U10V2KX-5GP PEX_TXN1 AC12
PEG_TXP1
PEG_TXN1
7 PEG_TXP1
7 PEG_TXN1
7
7
1
DIS
1
DIS
PEG_TXP0
PEG_TXN0
PEX_TX0
PEX_TX0#
PEG_RXP1
PEG_RXN1
DIS
PEX_REFCLK
PEX_REFCLK#
PEG_RXP1
PEG_RXN1
7 PEG_TXP0
7 PEG_TXN0
7
7

C254
SC4D7U10V3KX-GP
PEG_RXP0
PEG_RXN0
1
DIS
1
DIS
DIS
SC1U6D3V2KX-GP
7
7
PEG_RXP0
PEG_RXN0
C233
SC1U6D3V2KX-GP
C236
SCD1U10V2KX-5GP
AB10
AC10
3 CLK_PCIE_PEG
3 CLK_PCIE_PEG#
C249
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
DIS
PEX_RST#
Under GPU
C244
SCD047U16V2KX-1-GP
AD9
DIS
1D05V_S0_NV
SCD1U10V2KX-5GP
PEX_RST#
2
0R0402-PAD-1-GP
PEX_TSTCLK_OUT
PEX_TSTCLK_OUT#
DIS
C150
C151
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
DIS
SCD047U16V2KX-1-GP
1
R75
AF10
AE10
DIS
C554
+VGA_CORE
SCD047U16V2KX-1-GP
7,13,23,26,28 PLT_RST1#
N11M_PEX_TSTCLK_OUT
N11M_PEX_TSTCLK_OUT#
1
1
TP96
TP81
DIS
TPAD14-GP
TPAD14-GP
AB13
AB16
AB17
AB7
AB8
AB9
AC13
AC7
AD6
AE6
AF6
AG6
C148
SA 0822
D
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_CLKREQ#
AE9
1
2
2
1
DIS
2200mA
PEX_CLKREQ
C137
Near GPU
SC1U6D3V2KX-GP
C141
SC1U6D3V2KX-GP
AC9
AD7
AD8
AE7
AF7
AG7
SCD1U10V2KX-5GP
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
R104
10KR2J-3-GP
1D05V_S0_NV
Under GPU
1/12 PCI_EXPRESS
PEX_CLKREQ#
is OD.
SCD1U10V2KX-5GP
DIS
1 OF 12
VGA1A
3D3V_S0_NV
71.0N11M.A0U
<Core Design>
Wistron Corporation
Title
N11M(1/6)_PEG
5
Size
Custom
Document Number
Rev
SA
LB46E
Sheet
1
46
of
53
2 OF 12
VGA1B
2/12 FRAME_BUFFER
FBVDD
FBAD[16..23]
52
FBAD[24..31]
53
FBAD[32..39]
53
53
FBAD[40..47]
FBAD[48..55]
53
FBAD[56..63]
52
52
52
52
53
53
53
53
FBADQM0
FBADQM1
FBADQM2
FBADQM3
FBADQM4
FBADQM5
FBADQM6
FBADQM7
52
52
52
52
53
53
53
53
FBADQSP0
FBADQSP1
FBADQSP2
FBADQSP3
FBADQSP4
FBADQSP5
FBADQSP6
FBADQSP7
52
52
52
52
53
53
53
53
FBADQSN0
FBADQSN1
FBADQSN2
FBADQSN3
FBADQSN4
FBADQSN5
FBADQSN6
FBADQSN7
C26
B19
D19
D23
T24
AA23
AB27
T26
C25
A19
E19
A24
T22
AA24
AA26
T27
D25
A18
E18
B24
R22
Y24
AA27
R27
DIS
DIS
DIS
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
DIS
DIS
C787
DIS
C561
C788
C790 C560
C789
C786
A13
B13
C13
D13
D14
E13
F13
F14
F15
F16
F17
F19
F22
H23
H26
J15
J16
J18
J19
L19
L23
L26
M19
N22
U22
Y22
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
DIS
SC4D7U6D3V3KX-GP
52
1.72A
FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63
SCD047U16V2KX-1-GP
FBAD[8..15]
D22
E24
E22
D24
D26
D27
C27
B27
A21
B21
C21
C19
C18
D18
B18
C16
E21
F21
D20
F20
D17
F18
D16
E16
A22
C24
D21
B22
C22
A25
B25
A26
U24
V24
V23
R24
T23
R23
P24
P22
AC24
AB23
AB24
W24
AA22
W23
W22
V22
AA25
W27
W26
W25
AB25
AB26
AD26
AD27
V25
R25
V26
V27
R26
T25
N25
N26
SCD047U16V2KX-1-GP
FBAD0
FBAD1
FBAD2
FBAD3
FBAD4
FBAD5
FBAD6
FBAD7
FBAD8
FBAD9
FBAD10
FBAD11
FBAD12
FBAD13
FBAD14
FBAD15
FBAD16
FBAD17
FBAD18
FBAD19
FBAD20
FBAD21
FBAD22
FBAD23
FBAD24
FBAD25
FBAD26
FBAD27
FBAD28
FBAD29
FBAD30
FBAD31
FBAD32
FBAD33
FBAD34
FBAD35
FBAD36
FBAD37
FBAD38
FBAD39
FBAD40
FBAD41
FBAD42
FBAD43
FBAD44
FBAD45
FBAD46
FBAD47
FBAD48
FBAD49
FBAD50
FBAD51
FBAD52
FBAD53
FBAD54
FBAD55
FBAD56
FBAD57
FBAD58
FBAD59
FBAD60
FBAD61
FBAD62
FBAD63
SCD047U16V2KX-1-GP
52
FBAD[0..7]
52
RN10
FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7
FBA_CLK0
FBA_CLK0#
FBA_CLK1
FBA_CLK1#
F26
J24
F25
M23
N27
M27
K26
J25
J27
G23
G26
J23
M25
K27
G25
L24
K23
K24
G22
K25
H22
M26
H24
F27
J26
G24
G27
M24
K22
J22
L22
F24
F23
N24
N23
FBA_CMD_0 52
FBA_CMD_1 52,53
FBA_CMD_2 52
FBA_CMD_3 52,53
FBA_CMD_4 53
FBA_CMD_5 53
FBA_CMD_6 53
FBA_CMD_7 53
FBA_CMD_8 53
FBA_CMD_9 52,53
FBA_CMD_10 52,53
FBA_CMD_11 52,53
FBA_CMD_12 52,53
FBA_CMD_13 53
FBA_CMD_14 52,53
FBA_CMD_15 52,53
FBA_CMD_16 52,53
FBA_CMD_17 52,53
FBA_CMD_18 52
FBA_CMD_19 52,53
FBA_CMD_20 52,53
FBA_CMD_21 52,53
FBA_CMD_22 52
FBA_CMD_23 52,53
FBA_CMD_24 52
FBA_CMD_25 52,53
FBA_CMD_26 52,53
FBA_CMD_27 52,53
FBA_CMD_28 53
FBA_CMD_29 52
FBA_CMD_30 52
FBA_CLK0
FBA_CLK0#
FBA_CLK1
FBA_CLK1#
FBA_CMD_18
FBA_CMD_28
FBA_CMD_15
FBA_CMD_7
4
3
2
1
FBA_CMD_30
5
6
7
8
SRN10KJ-6-GP
DIS
R305
2
10KR2J-3-GP
DIS
FBA_CLK0 52
FBA_CLK0# 52
FBA_CLK1 53
FBA_CLK1# 53
FBA_CLK0 and FBA_CLK0_N + FBA_D[31:0]

FBA_CLK1 and FBA_CLK1_N *
FBVDD
FBA_D[63:32]
R311
FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7
FBA_DEBUG/CAS2
FBA_DEBUG
M22
2
10KR2J-3-GP
DIS
FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7
FBVDD
FB_CAL_PD_VDDQ
FB_CAL_PU_GND
0311
FB_CAL_TERM_GND
B15
FBCAL_PD_VDDQ
1
RT1
A15
FBCAL_PU_GND
B16
FBCAL_TERM_GND
FBVDD
2
2
To compute the drive strength of

the frame buffer pads.
40D2R2F-GP
2
60D4R2F-GP
CHECK
40D2R2F-GP
DIS
1
RT2
DIS
1
R454
DIS
Termination Calibration
R580
N10M use 60.4 ohm 64.60R45.6DL
N10P use 40.2 ohm 64.40R25.6DL
1D05V_S0_NV
FB_VREF
FB_DLLAVDD
FB_PLLAVDD
T19
C557
AC19
SCD01U50V2KX-1GP
N11M-LP1-S-A2-GP-U
DIS
DIS
71.0N11M.A0U
DIS
C559
SC4D7U6D3V3KX-GP
DY
A16
DY
C791
FB_PLLAVDD
SC1U6D3V2KX-GP
FB_VREF
R313
1K05R2F-GP
R19
FB_PLLAVDD
DY
R312
1K05R2F-GP
1
2
DIS
FCM1608KF-221T05-GP
L29
68.00217.741
100mA
16~12mils
<Core Design>
Wistron Corporation
Title
52_N11M(2/6)_MEMORY
SA
LB46E
http://mycomp.su - . , ,
.
Size
Custom
Date:
Document Number
Rev
Sheet
1
47
of
53
120mA
1
AG2
DACA_VDD
DACA_VREF
AF1
DACA_VREF
DACA_RSET
AE1
DACA_RSET
C795
R108
DIS 124R2F-U-GP
Set Reference
Current
Set Reference
Current
DACA_HSYNC
DACA_VSYNC
AD2
AD1
3.3V
CRT_HSYNC
CRT_VSYNC
19
19
DACA_RED
AE2
CRT_RED_1 19
DACA_GREEN
AE3
CRT_GREEN_1 19
DACA_BLUE
AD3
CRT_BLUE_1 19
1
2
71.0N11M.A0U
150R2F-1-GP
DIS
DIS
150R2F-1-GP
DIS
R668 R562 R567
N11M-LP1-S-A2-GP-U
150R2F-1-GP
SCD1U10V2KX-5GP
DIS
DACA_VDD
DIS
SC4700P50V2KX-1GP
C792 C794
SC470P50V2KX-3GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC1U6D3V2KX-GP
DIS
SC4D7U6D3V3KX-GP
HCB1608KF-301T20-GP C793DIS C797DIS C796DIS C799DIS C798DIS
DIS
3/12 DACA
3 OF 12
VGA1C
3D3V_S0_NV
L32
DIS
4 OF 12
VGA1D
4/12 DACB
W5
DACB_VDD
R6
DACB_VREF
V6
DACB_RSET
DACB_VDD
R113
10KR2J-3-GP
DIS
DACB_HSYNC
DACB_VSYNC
U6
U4
DACB_RED
T5
DACB_GREEN
T4
DACB_BLUE
R4
N11M-LP1-S-A2-GP-U
DIS
71.0N11M.A0U
<Core Design>
Wistron Corporation

Title
N11M(3/6)_DAC
Size
Custom
Date:
5
Document Number
Rev
SA
LB46E
Sheet
1
48
of
53
LVDS
Display Port
5 OF 12
VGA1E
IFPAB_PLLVDD
IFPAB_RSET
DY
C800
C803
DIS
IFPA_IOVDD
GPU_TXAOUT1- 18
GPU_TXAOUT1+ 18
IFPA_TXD2#
IFPA_TXD2
Y4
W4
GPU_TXAOUT2- 18
GPU_TXAOUT2+ 18
IFPA_TXD3#
IFPA_TXD3
AB5
AB4
TXAOUT3TXAOUT3+
1
1
TP35 TPAD14-GP
TP37 TPAD14-GP
IFPB_TXD4#
IFPB_TXD4
V1
W1
GPU_TXBOUT0- 1
GPU_TXBOUT0+ 1
TP93 TPAD14-GP
TP89 TPAD14-GP
IFPB_TXD5#
IFPB_TXD5
W2
W3
GPU_TXBOUT1- 1
GPU_TXBOUT1+ 1
TP111 TPAD14-GP
TP38 TPAD14-GP
IFPB_TXD6#
IFPB_TXD6
AA3
AA2
GPU_TXBOUT2- 1
GPU_TXBOUT2+ 1
TP82 TPAD14-GP
TP112 TPAD14-GP
IFPB_TXD7#
IFPB_TXD7
AA1
AB1
TXBOUT3TXBOUT3+
TP104 TPAD14-GP
TP103 TPAD14-GP
IFPA_TXC#
IFPA_TXC
AD4
AC4
IFPCD_PLLVDD
IFPD_RSET
220mA
N6
M6
IFPD_PLLVDD
IFPD_RSET
AA4
AA5
B
150mA V3
DIS
V2
150mA
SCD1U10V2KX-5GP
DIS
IFPA_TXD1#
IFPA_TXD1
R74
1KR2F-3-GP
Set Reference
Current
IFPD_AUX_I2CX_SDA#
IFPD_AUX_I2CX_SCL
D4
D3
IFPD_L3#
IFPD_L3
B4
B3
IFPD_L2#
IFPD_L2
C4
C3
IFPD_L1#
IFPD_L1
D5
E4
IFPD_L0#
IFPD_L0
F4
F5
GPIO19
F2
DATA
SCD1U10V2KX-5GP
DIS
C802
SC1U6D3V2KX-GP
C801
GPU_TXAOUT0- 18
GPU_TXAOUT0+ 18
DIS
R300
1KR2F-3-GP
IFPAB_IOVDD
SC4D7U6D3V3KX-GP
68.00143.061
DIS
V4
V5
1D8V_S0_NV
L31
1
2
BLM18PG181SN1D-GP
IFPA_TXD0#
IFPA_TXD0
DIS
AD5
AB6
7/12 IFPD
DIS
IFPAB_PLLVDD
IFPAB_RSET
C805
SC4D7U6D3V3KX-GP
C804
SC1U6D3V2KX-GP
68.00143.061
DIS
1D05V_S0_NV
L22
1
2
BLM18PG181SN1D-GP
7 OF 12
VGA1G
5/12 IFPAB
IFPB_IOVDD
1
1
N11M-LP1-S-A2-GP-U
DIS
GPU_TXACLK- 18
GPU_TXACLK+ 18
71.0N11M.A0U
CLOCK
Display Port
IFPB_TXC#
IFPB_TXC
GPIO0
AB2
AB3
GPU_TXBCLKGPU_TXBCLK+
1
1
TP84 TPAD14-GP
TP83 TPAD14-GP
8/12 IFPE
IFPEF_PLLVDD
N1
N11M-LP1-S-A2-GP-U
DIS
DIS
D7
F8
IFPE_PLLVDD
IFPE_RSET
R76
10KR2J-3-GP
Set Reference
Current
71.0N11M.A0U
8 OF 12
VGA1H
IFPAB_HPD
IFPE_AUX_I2CY_SDA#
IFPE_AUX_I2CY_SCL
G6
F7
6/12 IFPC
IFPE_L3#
IFPE_L3
E7
E6
IFPC_PLLVDD
IFPC_RSET
IFPE_L2#
IFPE_L2
B7
B6
IFPE_L1#
IFPE_L1
A7
A6
IFPE_L0#
IFPE_L0
C6
D6
GPIO15
F3
Display Port
6 OF 12
VGA1F
P6
R5
R676
1KR2F-3-GP
DY
R677
10KR2J-3-GP
IFPCD_PLLVDD
IFPC_RSET
DIS
IFPC_AUX_I2CW_SDA#
IFPC_AUX_I2CW_SCL
G5
G4
IFPC_L3#
IFPC_L3
J4
H4
IFPC_L2#
IFPC_L2
K4
L4
IFPC_L1#
IFPC_L1
M4
M5
IFPC_L0#
IFPC_L0
N4
P4
GPIO1
G1
IFPEF_IOVDD
IFPC_IOVDD
R678
10KR2J-3-GP
IFPE_IOVDD
N11M-LP1-S-A2-GP-U
DIS
DIS
71.0N11M.A0U
DIS
H6
R77
10KR2J-3-GP
J6
IFPC_IOVDD
N11M-LP1-S-A2-GP-U
DIS
71.0N11M.A0U
<Core Design>
Wistron Corporation
Title
N11M(4/6)
Size
Custom
Date:
5
Document Number
Rev
SA
LB46E
Sheet

1
49
of
53
3D3V_S0_NV
RN56
JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_TRST#
AF3
AF4
AG4
AE4
AG3
R2
R3
I2CB_SCL
I2CB_SDA
JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_TRST#
R315
10KR2J-3-GP
DIS
DIS
T6
W6
Y6
AA6
N3
STRAP0
STRAP1
STRAP2
Set reference current

for multilevel straps
STRAP_3V3
F11
3D3V_S0_NV
I2CS_SCL
I2CS_SDA
DBG_DATA0
DBG_DATA1
DBG_DATA2
DBG_DATA3
DBG_DATA4
NV_LCD_BL_PWM
C1
M2
M3
K3
K2
J2
C2
M1
D2
D1
J3
J1
K1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
Thermal
N11M_DBG_DATA0
N11M_DBG_DATA1
N11M_DBG_DATA2
N11M_DBG_DATA3
N11M_DBG_DATA4
ROM_CS#
C7
B9
A9
ROM_SI
ROM_SO
ROM_SCLK
NVVDD_ALTV0
NVVDD_ALTV1
NV_GPIO8
NV_GPIO9
NV_GPIO10
NV_GPIO11
NV_GPIO12
NV_GPIO13
NV_GPIO14
G3
G2
F1
GPIO16
GPIO17
GPIO18
1
1
TP124 TPAD14-GP
1
NV_LCDVDD_ON 18
NV_BLON_IN 28
NVVDD_ALTV0 44
NVVDD_ALTV1 44
SRN2K2J-1-GP
TP133 TPAD14-GP
TP120 TPAD14-GP
TP107 TPAD14-GP
1
RN67
NV_I2CB_SDA
NV_I2CB_SCL
3
4
TP134 TPAD14-GP
TESTMODE
GND
N2
PEX_TESTMODE
AD25
3
4
F6
R460
10KR2J-3-GP
AC6
DIS
DIS
NV_GPIO9 3
NV_GPIO14 4
2
1
N5
N11M-LP1-S-A2-GP-U
RN53
3D3V_S0_NV
NV_LCD_EDID_CLK
NV_LCD_EDID_DAT
GND
3D3V_S0_NV
DIS
RN92
DGPUEVENT# 1
NC#N2
NC#F9
SRN2K2J-1-GP
Debug pin
TP121 TPAD14-GP
TP108 TPAD14-GP
DIS
F9
2
1
HDCP_CLK
1
HDCP_SDA
1
Pull up? SDA
is input
A3
A4
R326
40K2R2F-GP
DIS
3D3V_S0_NV
TP131 TPAD14-GP
TP125
TP106 TPAD14-GP
1
1
1
BUFRST#
R325
40K2R2F-GP
DIS
A10 GPU_ROM_SI
C10 GPU_ROM_SO
C9 GPU_ROM_SCLK
MULTI_STRAP_REF1_GND
3
4
I2CH_SCL
I2CH_SDA
MULTI_STRAP_REF0_GND
STRAP_MIOB F10
2
1
B10 GPU_ROM_CS#
T1
T2
CHECK
1
1
1
1
1
STRAP0
STRAP1
STRAP2
RN13
SMBC_Therm_NV
SMBD_Therm_NV
TP119
TP126
TP128
TP129
TP130
2
1
DIS SRN10KJ-5-GP
CRT_DDCCLK
CRT_DDCDATA
Debug pin
TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP
3
4
18
18
DIS
10/12 MISC
All Other
R314
10KR2J-3-GP
NV_GPIO12
NV_GPIO10
NV_LCD_EDID_CLK
NV_LCD_EDID_DAT
R451
10KR2J-3-GP
10 OF 12
VGA1K
RN52
NV_LCD_EDID_CLK
NV_LCD_EDID_DAT
A2
B1
I2CC_SCL
I2CC_SDA
DIS SRN10KJ-5-GP
CRT_DDCCLK 19
CRT_DDCDATA 19
1
1
1
1
1
CRT_DDCCLK
CRT_DDCDATA
VGA I2C-Compatible
NV_I2CB_SCL
NV_I2CB_SDA
R1
T3
I2CA_SCL
I2CA_SDA
THERMDP
TP85
TP132
TP135
TP137
TP86
THERMDN
TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP
TPAD14-GP
D9
D8
input
3D3V_S0_NV
2
1
9/12 I2C_GPIO_THERM_JTAG
3
4
NV_GPIO11
NV_GPIO8
9 OF 12
VGA1I
2
1
71.0N11M.A0U
DIS SRN10KJ-5-GP
SRN2K2J-1-GP
N11M-LP1-S-A2-GP-U
DIS
GPIO8,9,18 change to TP NV yangbo 0311
DIS
3D3V_S0_NV
3D3V_S0_NV
71.0N11M.A0U
C
R324
10KR2J-3-GP
R317 1
0R2J-2-GP
XTAL_OUTBUFF
XTAL_IN
XTAL_OUT
N11M-LP1-S-A2-GP-U
DIS 71.0N11M.A0U
DIS
VGA_XIN1
XTAL_SSIN
E9
XTALOUTBUFF 1
TP115 TPAD14-GP
D10
when not use

spectrum, pull down
SMBD_Therm 27,28
XTALSSIN D11
R323
0R2J-2-GP
XTALIN
DY
C807
SC15P50V2JN-2-GP
if not use, pull down
DIS1MR2F-GP
4
DIS
DIS
R316
10KR2J-3-GP
E10
DIS
R3144
1
X7
Q17
SMBD_Therm_NV
SP_PLLVDD
DIS
VID_PLLVDD
45mA
XTALOUT
3
2
SMBC_Therm 27,28
DIS
DY
XTAL_SSIN1
L6
PLLVDD
DIS
DIS
K6
R680
10KR2J-3-GP
DIS
C576
DIS
K5
45mA
SMBC_Therm_NV
R217
100KR2J-1-GP
1
2
2N7002KDW-GP
DIS
84.2N702.A3F
DIS
NV_LCDVDD_ON
NV_BLON_IN
4
3
RN91
SRN4K7J-8-GP
SC1U6D3V2KX-GP
C575
SC4D7U6D3V3KX-GP
68.00143.061
SP_PLLVDD
1
2
BLM18PG181SN1D-GP
DIS
60mA
C572
DIS
C571
DIS
L25
2
1D05V_S0_NV
DIS
C574
SCD1U10V2KX-4GP
DIS
VIO_PLLVDD
C573
SCD1U10V2KX-4GP
68.00143.061
R671
10KR2J-3-GP
SC1U6D3V2KX-GP
3D3V_S0_NV
11/12 XTAL_PLL
1
2
BLM18PG181SN1D-GP
DY
R679
10KR2J-3-GP
11 OF 12
VGA1L
DIS
SC4D7U6D3V3KX-GP
12
NVVDD_ALTV0
L24
12
DY
NVVDD_ALTV1
1D05V_S0_NV
R674
10KR2J-3-GP
R672
10KR2J-3-GP
XTALOUT
DIS
C806
SC15P50V2JN-2-GP
78.15034.1FL
STRAP0
STRAP1
STRAP2
XTAL-27MHZ-85-GP
82.30034.641
3D3V_S0_NV
1 R675
DIS R673
2 20KR2F-L-GP
2 34K8R2F-1-GP
GPU_ROM_SI
GPU_ROM_SO
GPU_ROM_SCLK
2 15KR2F-GP
DY
1 RT5
DIS
1
R318
45K3R2F-L-GP
DIS
DY
1 R320
34K8R2F-1-GP
DY
2 RT4
2KR2J-1-GP
R319
3D3V_S0_NV
R322
2 15KR2F-GP
2 15KR2F-GP
DIS
DY
1 R473
10KR2F-2-GP
DY
1
DY
RT3
2
2KR2J-1-GP
2 R475
10KR2F-2-GP
DIS
1
R321
2 20KR2F-L-GP
*VRAM_SAM_HYX
R321=15K FOR HYNIX_H5TQ1G63BFR 512MB

=20K FOR SAMSUNG 512MB
=5K FOR HYNIX_H5TQ1G63DFR 512MB
<Core Design>
Wistron Corporation
Title
N11M(5/6)_MIO/ GPIO
Size
Custom
Date:
5
Document Number
Rev
SA
LB46E
Sheet
1
50
of
53
12 OF 12
VGA1J
12/12 GND_NC
AC11
AC14
AC17
AC2
AC20
AC23
AC26
AC5
AC8
AF11
AF14
AF17
AF2
AF20
AF23
AF26
AF5
AF8
B11
B14
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
B17
B2
B20
B23
B26
B5
B8
E11
E17
E2
E20
E23
E26
E5
E8
H2
H5
J11
J14
J17
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
K19
K9
L11
L12
L13
L14
L15
L16
L17
L2
L5
M12
M13
M14
M15
M16
P19
P2
P23
P26
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
P5
P9
T12
T13
T14
T15
T16
U11
U12
U13
U14
U15
U16
U17
U2
U23
U26
U5
V19
V9
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
W11
W14
W17
Y2
Y23
Y26
Y5
GND
GND
GND
GND
GND
GND
GND
NC#C15
NC#D15
NC#J5
C15
D15
J5
<Core Design>
A
Wistron Corporation
Title
N11M(6/6)_POWER
71.0N11M.A0U
Size
Custom
Document Number
LB46E
http://mycomp.su N11M-LP1-S-A2-GP-U
- . , , Date:

.
Wednesday, November
03, 2010
Sheet
5
DIS
Rev
SA
51
of
1
53
L3
K3
J3
47,53 FBA_CMD_11
47,53 FBA_CMD_10
47,53 FBA_CMD_1
K4W2G1646C-HC11-GP
WE#
CAS#
RAS#
1
2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
G1
F9
E8
E2
D8
D1
B9
B1
G9
C583
DIS
K4W2G1646C-HC11-GP
DIS
1
2
1
2
1
2
1
2
1
2
1
2
DIS
DIS
DIS
C590
DIS
1
2
DIS
C595
DIS
DIS
C589
C581
C594
1
2
C588
DIS
C579
1
2
DIS
C586
DIS
C597
DIS
DIS
DIS
C607
C591
DIS
C596
DIS
C611
C593
FBA_CMD_29 47
FBA_CMD_15 47,53
C612
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
DIS
FBA_CMD_30 47
1
CKE
DMU
DML
1
2
T7
L9
L1
J9
J1
DIS
D3
E7
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
DIS
FBADQM1
FBADQM2
L2
T2
DIS
47
47
CS#
RESET#
DIS
K9
DIS
K1
DIS
C584
SCD1U10V2KX-5GP
FBA_CMD_18
ODT
DIS
C580
SC1U6D3V2KX-GP
47
FBADQSP2 47
FBADQSN2 47
C582
DIS
SCD01U50V2KX-1GP
FBA_CLK0
FBA_CLK0#
DQSL
DQSL#
C585
SCD047U16V2KX-1-GP
47
47
FBADQSP1 47
FBADQSN1 47
C608
SCD1U10V2KX-5GP
WE#
CAS#
RAS#
G1
F9
E8
E2
D8
D1
B9
B1
G9
2 243R2F-2-GP
J7 CK
K7 CK#
C7
B7
F3
G3
C605
SCD01U50V2KX-1GP
DMU
DML
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
1 R467
BA0
BA1
BA2
DQSU
DQSU#
C578
SC1U6D3V2KX-GP
CKE
M2
N8
M3
47,53 FBA_CMD_12
47,53 FBA_CMD_3
47,53 FBA_CMD_27
C587
SCD1U10V2KX-5GP
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC#M7
Per each VRAM chip
SCD047U16V2KX-1-GP
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
FBA_CMD_19
FBA_CMD_25
FBA_CMD_22
FBA_CMD_24
FBA_CMD_0
FBA_CMD_2
FBA_CMD_21
FBA_CMD_16
FBA_CMD_23
FBA_CMD_20
FBA_CMD_17
FBA_CMD_9
FBA_CMD_14
FBA_CMD_26
DIS
SCD1U10V2KX-5GP
T7
L9
L1
J9
J1
47,53
47,53
FBA_CMD_29 47
47
FBA_CMD_15 47,53 47
47
47
47,53
47,53
47,53
47,53
47,53
47,53
47,53
47,53
47
SCD01U50V2KX-1GP
L3
K3
J3
47,53 FBA_CMD_11
47,53 FBA_CMD_10
47,53 FBA_CMD_1
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7
DIS
FBA_CMD_30 47
FBAD[8..15]
SCD1U10V2KX-5GP
D3
E7
FBADQM0
FBADQM3
L2
T2
VREFDQ
VREFCA
ZQ
FBAD13
FBAD10
FBAD15
FBAD9
FBAD14
FBAD8
FBAD12
FBAD11
C613
SC4D7U6D3V3KX-GP
SCD01U50V2KX-1GP
47
47
CK
CK#
CS#
RESET#
1FBA_ZQ1
243R2F-2-GP
H1
M8
L8
D7
C3
C8
C2
A7
A2
B8
A3
FBVDD
SCD047U16V2KX-1-GP
47 FBA_CMD_18
K9
K1
FBADQSP3 47
FBADQSN3 47
FBA_VREF12
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
47
SCD1U10V2KX-5GP
J7
K7
ODT
R462
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
FBAD20
FBAD22
FBAD21
FBAD23
FBAD17
FBAD16
FBAD19
FBAD18
SCD1U10V2KX-5GP
FBA_CLK0
FBA_CLK0#
47
47
BA0
BA1
BA2
DQSL
DQSL#
FBADQSP0 47
FBADQSN0 47
A8
A1
C1
C9
D2
E9
F1
H9
H2
E3
F7
F2
F8
H3
H8
G2
H7
SCD047U16V2KX-1-GP
M2
N8
M3
47,53 FBA_CMD_12
47,53 FBA_CMD_3
47,53 FBA_CMD_27
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC#M7
C7
B7
F3
G3
FBVDD
47
FBAD[16..23]
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
SCD1U10V2KX-5GP
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7
FBA_CMD_19
FBA_CMD_25
FBA_CMD_22
FBA_CMD_24
FBA_CMD_0
FBA_CMD_2
FBA_CMD_21
FBA_CMD_16
FBA_CMD_23
FBA_CMD_20
FBA_CMD_17
FBA_CMD_9
FBA_CMD_14
FBA_CMD_26
DQSU
DQSU#
FBAD[0..7]
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
SC1U6D3V2KX-GP
DIS
243R2F-2-GP
47,53
47,53
47
47
47
47
47,53
47,53
47,53
47,53
47,53
47,53
47,53
47,53
FBAD4
FBAD3
FBAD7
FBAD1
FBAD5
FBAD0
FBAD6
FBAD2
K8
K2
N1
R9
B2
D9
G7
R1
N9
SC1U6D3V2KX-GP
VREFDQ
VREFCA
ZQ
D7
C3
C8
C2
A7
A2
B8
A3
VRAM2
FBVDD
47
SC1U6D3V2KX-GP
FBA_ZQ0
H1
M8
L8
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
FBAD[24..31]
SC1U6D3V2KX-GP
SCD01U50V2KX-1GP
1 FBA_VREF12
FBAD24
FBAD31
FBAD27
FBAD29
FBAD26
FBAD28
FBAD25
FBAD30
SC1U6D3V2KX-GP
R328
DIS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
E3
F7
F2
F8
H3
H8
G2
H7
SC1U6D3V2KX-GP
C577
A8
A1
C1
C9
D2
E9
F1
H9
H2
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
FBVDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VRAM1
K8
K2
N1
R9
B2
D9
G7
R1
N9
FBVDD
DIS
FBVDD
FBVDD
TC12
ST100U6D3VBM-16GP
R461
1K05R2F-GP
DIS
R327
1K05R2F-GP
FBA_VREF12
DY
DIS
C592
SCD01U50V2KX-1GP
DIS
<Core Design>
Wistron Corporation
Title
VRAM(1/4)
Size
Custom
Document Number
Rev

5
SA
LB46E
Sheet
1
52
of
53
VRAM3
FBVDD
FBVDD
C614
2
1 FBA_VREF34
SCD01U50V2KX-1GP
R331
2
1FBA_ZQ2
DIS
47,52 FBA_CMD_19
47,52 FBA_CMD_25
47 FBA_CMD_4
47 FBA_CMD_6
47 FBA_CMD_5
47 FBA_CMD_13
47,52 FBA_CMD_21
47,52 FBA_CMD_16
47,52 FBA_CMD_23
47,52 FBA_CMD_20
47,52 FBA_CMD_17
47,52 FBA_CMD_9
47,52 FBA_CMD_14
47,52 FBA_CMD_26
47,52 FBA_CMD_12
47,52 FBA_CMD_3
47,52 FBA_CMD_27
DIS
47
47
47
243R2F-2-GP
FBA_CMD_19
FBA_CMD_25
FBA_CMD_4
FBA_CMD_6
FBA_CMD_5
FBA_CMD_13
FBA_CMD_21
FBA_CMD_16
FBA_CMD_23
FBA_CMD_20
FBA_CMD_17
FBA_CMD_9
FBA_CMD_14
FBA_CMD_26
FBA_CMD_12
FBA_CMD_3
FBA_CMD_27
243R2F-2-GP
R334
1
2
FBA_CLK1
FBA_CLK1#
FBA_CMD_7
FBA_CMD_7
47
47
K8
K2
N1
R9
B2
D9
G7
R1
N9
A8
A1
C1
C9
D2
E9
F1
H9
H2
DIS
FBADQM7
FBADQM4
FBA_CMD_11
FBA_CMD_10
FBA_CMD_1
47,52 FBA_CMD_11
47,52 FBA_CMD_10
47,52 FBA_CMD_1
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
H1
M8
L8
VREFDQ
VREFCA
ZQ
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC#M7
M2
N8
M3
BA0
BA1
BA2
J7
K7
CK
CK#
K9
FBAD[32..39]
E3
F7
F2
F8
H3
H8
G2
H7
FBAD32
FBAD33
FBAD39
FBAD36
FBAD37
FBAD34
FBAD35
FBAD38
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
FBAD61
FBAD60
FBAD56
FBAD57
FBAD59
FBAD63
FBAD58
FBAD62
DQSU
DQSU#
C7
B7
DQSL
DQSL#
F3
G3
FBADQSP4 47
FBADQSN4 47
ODT
K1
FBA_CMD_28 47
CS#
RESET#
L2
T2
FBA_CMD_8 47
FBA_CMD_15 47,52
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
T7
L9
L1
J9
J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
G1
F9
E8
E2
D8
D1
B9
B1
G9
CKE
D3
E7
DMU
DML
L3
K3
J3
WE#
CAS#
RAS#
FBVDD
47
FBADQSP7 47
FBADQSN7 47
Mode A
0119
VRAM4
FBVDD
47
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
FBAD[56..63]
FBA_VREF34
2 R441
1FBA_ZQ3
243R2F-2-GP
DIS
K8
K2
N1
R9
B2
D9
G7
R1
N9
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
A8
A1
C1
C9
D2
E9
F1
H9
H2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
H1
M8
L8
VREFDQ
VREFCA
ZQ
47,52 FBA_CMD_19
47,52 FBA_CMD_25
47 FBA_CMD_4
47 FBA_CMD_6
47 FBA_CMD_5
47 FBA_CMD_13
47,52 FBA_CMD_21
47,52 FBA_CMD_16
47,52 FBA_CMD_23
47,52 FBA_CMD_20
47,52 FBA_CMD_17
47,52 FBA_CMD_9
47,52 FBA_CMD_14
47,52 FBA_CMD_26
FBA_CMD_19
FBA_CMD_25
FBA_CMD_4
FBA_CMD_6
FBA_CMD_5
FBA_CMD_13
FBA_CMD_21
FBA_CMD_16
FBA_CMD_23
FBA_CMD_20
FBA_CMD_17
FBA_CMD_9
FBA_CMD_14
FBA_CMD_26
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
NC#M7
47,52 FBA_CMD_12
47,52 FBA_CMD_3
47,52 FBA_CMD_27
FBA_CMD_12
FBA_CMD_3
FBA_CMD_27
M2
N8
M3
BA0
BA1
BA2
J7
K7
CK
CK#
47
47
47
47
47
FBA_CLK1
FBA_CLK1#
FBA_CMD_7
FBA_CMD_7
FBADQM6
FBADQM5
47,52 FBA_CMD_11
47,52 FBA_CMD_10
47,52 FBA_CMD_1
FBA_CMD_11
FBA_CMD_10
FBA_CMD_1
K9
CKE
D3
E7
DMU
DML
L3
K3
J3
WE#
CAS#
RAS#
FBAD[40..47]
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
E3
F7
F2
F8
H3
H8
G2
H7
FBAD42
FBAD45
FBAD40
FBAD44
FBAD41
FBAD43
FBAD47
FBAD46
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
FBAD51
FBAD53
FBAD49
FBAD52
FBAD48
FBAD54
FBAD50
FBAD55
DQSU
DQSU#
C7
B7
FBADQSP6 47
FBADQSN6 47
DQSL
DQSL#
F3
G3
FBADQSP5 47
FBADQSN5 47
ODT
K1
FBA_CMD_28 47
CS#
RESET#
L2
T2
FBA_CMD_8 47
FBA_CMD_15 47,52
NC#T7
NC#L9
NC#L1
NC#J9
NC#J1
T7
L9
L1
J9
J1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
G1
F9
E8
E2
D8
D1
B9
B1
G9
47
FBAD[48..55]
47
K4W 2G1646C-HC11-GP
K4W 2G1646C-HC11-GP
DIS
DIS
FBVDD
R330
1K05R2F-GP
FBA_VREF34
R332
1K05R2F-GP
DIS
C615
SCD01U50V2KX-1GP
DIS
DIS
<Core Design>
A
Wistron Corporation
Title
VRAM(2/4)
Size
A3
5
Date:
2
Document Number
Rev
SA
LB46E
Sheet
1
53
of
53

Lenovo B460 Wistron LB46E

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Lenovo B460 Wistron LB46E

Uploaded by

Copyright:

Available Formats

5

Project code: 91.4HK01.A01

LVDS, CRT I/F

DDR Memory I/F

AGTL+ CPU I/F

High Definition Audio

Serial Peripheral I/F

12 USB 2.0/1.1 ports

Matrix Storage Technology(DO)

Active Managemnet Technology(DO)

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

ICH9M Functional Strap Definitions

ICH9M Integrated Pull-up

XOR Chain Entrance/

Allows entrance to XOR Chain testing when TP3

PCIE config1 bit0,

This signal has a weak internal pull-down.

PCIE config2 bit2,

This signal has a weak internal pull-up.

ESI Strap (Server Only)

ICH9 EDS 642879

ESI compatible mode is for server platforms only.

The pull-up or pull-down active when configured for native

Boot BIOS Destination

Controllable via Boot BIOS Destination bit

Integrated TPM Enable,

Sample low: the Integrated TPM will be disabled.

PCI Express Lane

Signal has weak internal pull-up. Sets bit 27

If sampled high, the system is strapped to the

This signal should not be pull low unless using

XOR Chain Entrance.

Sampled low:the Flash Descriptor Security will be

PCIE Graphics Lane

0 = Reverse Lanes,15->0,14->1 ect..

PCIE Loopback enable

DMI Termination Voltage, The signal is required to be low for desktop

Montevina Platform Design guide 22339

Cantiga chipset and ICH9M I/O controller

FSB Dynamic ODT

0 = Dynamic ODT Disabled

DMI Lane Reversal

Digital Display Port

0 = Only Digital Display Port

Local Flat Panel

1= LFP Card Present; PCIE disabled

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Pull high PCLKCLK4

ICS9LPRS365BKLFT setting table

0 = Overclocking of CPU and SRC Allowed

3.3V PCI clock output

0 = Pin24 as SRC-1, Pin25 as SRC-1#, Pin20 as DOT96, Pin21 as DOT96#

SEL2 SEL1 SEL0

Monday, December 27, 2010

Follow Demo Circuit

Net "TEST4" as short as possible,

All place within 2" to CPU

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

Monday, December 27, 2010

layout note: "1D5V_VCCA_S0"

VCCSENSE and VSSSENSE lines

Monday, December 27, 2010

H_SWING routing Trace width and