Switching Circuits & Logic Design

Sequential Circuit Design

Professor Chien-Mo James Li
Graduate Institute of Electronics Engineering
National Taiwan University
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Objective of this Chapter

Learn how to design a sequential circuit

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Flow of Design a Sequential Ckt.

specification
Ch 14
State graph
State Table

Ch 15
Ch 12

Ch 13

Ch 16

K-map
FF, Comb Logic
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Outline

Summary of Design Procedure for Sequential Circuits.

Design Example-Code Converter.
Design of Iterative Circuits.
Design of Sequential Circuits Using ROMs and PLAs.

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Design Procedure for Seq. Ckt.

1.
2.
3.
4.
5.
6.

Determine state graph and state table

Reduce state table
State Assignment
Transition table
Next-state map input Map, output map
Equations and circuits

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Design Example Code Converter

Convert BCD code to Excess-3 code

Table 1-2
Add 3 to input sequence

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Step 1. State table

X

Input

Output

(BCD)

(excess-3)

t3

t2

t1

t0

t3

t2

t1

t0

Tab 16.1
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Step 1. State table

State graph

LSB first, MSB last

Fig. 16-1
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Step 2. Reduce states

time

Input
sequence
received

Present
state

Next state

Table 16-2

Present
output(Z)

X=0

X=1

X=0

X=1

t0

reset

t1

00

01

10

11

000

001

010

011

100

101

110

111

t2

t3

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Step 2. Reduce states

Time

Present
state

Next stat
X=0

X=1

Present
output(Z)
X=0
X=1

t0

t1

t2

t3

Table 16-3
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Step 3. Assign states

Figure 16-2
Adjacent states

(B,C) (D,E) (H,M)

(A,B,E,M) (C,D,H)

Fig. 16-2

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Step 4. Transition Table

Figure 16-2 (b)
Q1+Q2+ Q3+

Q1

Q2

Q3

X=0

X=1

X=0

X=1

100

101

111

110

110

110

011

011

011

010

000

000

000

xxx

xxx

xxx

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Step 5. 6. Maps and Equations

Figure 16-3

Fig. 16-3
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Done!
Figure 16-4

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Question!
Q: Why output Z is not delayed?
A: Because excess-3 code = BCD code + 3

Not delay is needed from LSB to MSB

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Food for Thought

Q: what happens if we input MSB first?
Q: what should we do if we want to design a BCD to 6-3-1-1
converter?
Table 1-2

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Outline

Summary of Design Procedure for Sequential Circuits.

Design Example-Code Converter.
Design of Iterative Circuits.
Design of Sequential Circuits Using ROMs and PLAs.

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17

Iterative Circuits
Definition

An iterative circuit consist of a number of identical cells

interconnected in a regular manner
Example
A parallel adder consists of many full adders

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Unilateral Iterative Circuit

Linear array of combinational cells with signals between traveling in
only one direction
Figure 16-5
X = inputs
Z = outputs
a = states

Fig. 16-5

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Seq. Ckt. v.s. Iterative Circuits

Sequential circuits

Serial input, serial output

Iterative Circuits

Parallel input. Parallel output

Design of iterative circuits is very similar to design of sequential

circuits
Comparison
Iterative circuits receives inputs sequence in SPACE
Sequential circuits receives input sequence in TIME

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Design Example Comparator

Specification

Input two n-bit numbers X and Y

Determine if X=Y or X>Y or X<Y?

Two possible designs

Iterative circuit
Sequential circuit

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Iterative Comparator
MSB in the left; LSB in the right
Input X, Y; output Z
Think of ai and bi as states
LSB

MSB

PS

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State Table for Comparator

TABLE 16-4

S0 : X=Y
S1: X>Y
S2 :X<Y
PS
Si

NS
Si+1

Output

XiYi
00

01

11

10

Z1

Z2

Z3

X=Y

S0

S0

S2

S0

S1

X>Y

S1

S1

S1

S1

S1

X<Y

S2

S2

S2

S2

S2

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Transition Table
Table 16-5
PS

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NS
ai+1bi+1

outputs

aibi

xiyi=00

01

11

10

Z1

Z2

Z3

00

00

10

00

01

01

01

01

01

01

10

10

10

10

10

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Next-State Map
Although there is not real next state

Think of ai+1 as next state of ai

Fig. 16-7

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Next-State Circuit
one Cell i only

Think of ai+1 as next state of ai

Fig. 16-7

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Output Circuit
Fig. 16-8

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Whole Iterative Comparator

Many next-state cells connected together

Followed by one output cell

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Sequential Design
Use 2FF to store states
Fig. 16-9

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Food for Thought

Which comparator is better?

Sequential circuit or
Iterative circuit?

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Outline

Summary of Design Procedure for Sequential Circuits.

Design Example-Code Converter.
Design of Iterative Circuits.
Design of Sequential Circuits Using ROMs and PLAs

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Design Seq. Ckt. Using ROM

Use ROM to implement comb. logic
If m inputs, k state variables (using D-FF), and n outputs

Need m+k input, n+K output ROM

Why?

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Design Example
Same BCD to excess-3 Code converter
State table

Table 16-6(a)
Transition table
Table 16-6(b)

Truth Table

Table 16-6 (c)

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Design Example
Table 16-6 (a)
Present
state

Next
state
X=0

X=1

X=0

X=1

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output (Z)

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Design Example
Table 16-6 (b)
Q1+Q2+Q3+

Q1 Q2 Q3

X=0

X=1

X=0

X=1

000

001

010

001

011

100

010

100

100

011

101

101

100

101

110

101

000

000

110

000

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Design Example
Table 16-6 (c)

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Q1

Q2

Q3

D1

D2

D3

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Implementation Using ROM

Fig 16-10

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Final Notice on ROM-based Design

Use D-FF is preferable to JK FFs

Because JK-FF has two inputs that require a larger ROM

Use straight state assignment is ok, no optimal assignment needed

Because area of ROM is the same regardless of the complexity of

logic
e.g. If you memorize the whole 9x9 multiplication table, you do
not need any computation

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Design Using PLA

Same code converter
Equations:

16-1

Table 16-7

Q1

Q2

Q3

D1

D2

D3

Notice: state assignment does mater

Straight assignment: 13 product terms

Better assignment: 7 product terms
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PAL with feedback

Q+ = D = ABQ+ABQ
Useful for sequential ckt.

Fig 16-11
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Food for Thought

Which comparator is better?

Sequential circuit or
Iterative circuit?

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Next Time

ch 9 Multiplexers Decoders and PLD

ch 11 Latches and FF
ch 12 Registers and Counters
ch 13 Analysis of Clock Sequential Ckts
ch 14 Derivation of State Graphs and
Tables
ch 16 Sequential Ckt Design
ch 18 Ckts for Arith. Operations
final exam

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