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A programmable logic device or PLD is an electronic component used to build
reconfigurable digital circuits. Unlike a logic gate, which has a fixed function, a PLD has an
undefined function at the time of manufacture. Before the PLD can be used in a circuit it
must be programmed, that is, reconfigured. Other names you might encounter for this class of
device are Programmable Logic Array (PLA), Programmable Array Logic (PAL), and
Generic Array Logic (GAL).

Inside each PLD is a set of fully connected macrocells. These macrocells are typically
comprised of some amount of combinatorial logic (AND and OR gates, for example) and a
flip-flop. In other words, a small Boolean logic equation can be built within each macrocell.
This equation will combine the state of some number of binary inputs into a binary output
and, if necessary, store that output in the flip-flop until the next clock edge. Of course, the
particulars of the available logic gates and flip-flops are specific to each manufacturer and
product family. But the general idea is always the same.

Because these chips are pretty small, they don't have much relevance to the remainder of this
discussion. But you do need to understand the origin of programmable logic chips before we
can go on to talk about the larger devices. Hardware designs for these simple PLDs are
generally written in languages like ABEL or PALASM (the hardware equivalents of
assembly) or drawn with the help of a schematic capture tool.

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Before PLDs were invented, read-only memory (ROM) chips were used to create arbitrary
combinational logic functions of a number of inputs. Consider a ROM with µ inputs (the
address lines) and outputs (the data lines). When used as a memory, the ROM contains 2µ
words of bits each. Now imagine that the inputs are driven not by an µ-bit address, but by
µ independent logic signals. Theoretically, there are 2µ possible Boolean functions of these
µ signals, but the structure of the ROM allows just 2 of these functions to be produced at the
output pins. The ROM therefore becomes equivalent to separate logic circuits, each of
which generates a chosen function of the µ inputs.

The advantage of using a ROM in this way is that any conceivable function of the µ inputs
can be made to appear at any of the outputs, making this the most general-purpose
combinatorial logic device available. Also, PROMs (programmable ROMs), EPROMs
(ultraviolet-erasable PROMs) and EEPROMs (electrically erasable PROMs) are available
that can be programmed using a standard PROM programmer without requiring specialised
hardware or software. However, there are several disadvantages:

jc they are usually much slower than dedicated logic circuits,

jc they cannot necessarily provide safe "covers" for asynchronous logic transitions so
the PROM's outputs may glitch as the inputs switch,
jc they consume more power, and
jc because only a small fraction of their capacity is used in any one application, they
often make an inefficient use of space.

Since most ROMs do not have input or output registers, they cannot be used stand-alone for
sequential logic. An external TTL register was often used for sequential designs such as state
machines. Common EPROMs, for example the 2716, are still sometimes used in this way by
hobby circuit designers, who often have some lying around. This use is sometimes called a
'poor man's PAL'.

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A programmable logic array (PLA) is a programmable device used to implement

combinational logic circuits. The PLA has a set of programmable AND gate planes, which
link to a set of programmable OR gate planes, which can then be conditionally complemented
to produce an output. This layout allows for a large number of logic functions to be
synthesized in the sum of products (and sometimes product of sums) canonical forms.

One application of a PLA is to implement the control over a datapath. It defines various states
in an instruction set, and produces the next state (by conditional branching). [eg. if the
machine is in state 2, and will go to state 4 if the instruction contains an immediate field; then
the PLA should define the actions of the control in state 2, will set the next state to be 4 if the
instruction contains an immediate field, and will define the actions of the control in state 4].
Programmable Logic Arrays should correspond to a state diagram for the system.

Other commonly used programmable logic devices are PAL, CPLD and FPGA.

Note that the use of the word "Programmable" does not indicate that all PLAs are field-
programmable; in fact many are mask-programmed during manufacture in the same manner
as a mask ROM. This is particularly true of PLAs that are embedded in more complex and
numerous integrated circuits such as microprocessors. PLAs that can be programmed after
manufacture are called FPLA (Field-programmable PLA).

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The term Programmable Array Logic (PAL) is used to describe a family of programmable
logic device semiconductors used to implement logic functions in digital circuits introduced
by Monolithic Memories, Inc. (MMI) in March 1978.[1]

PAL devices consisted of a small PROM (programmable read-only memory) core and
additional output logic used to implement particular desired logic functions with few
components.

Using specialized machines, PAL devices were "field-programmable". Each PAL device was
"one-time programmable" (OTP), meaning that it could not be updated and reused after its
initial programming. (MMI also offered a similar family called HAL, or "hard array logic",
which were like PAL devices except that they were mask-programmed at the factory.)

The programmable logic plane is a programmable read-only memory (PROM) array that
allows the signals present on the devices pins (or the logical complements of those signals) to
be routed to an output logic macrocell.

PAL devices have arrays of transistor cells arranged in a "fixed-OR, programmable-AND"

plane used to implement "sum-of-products" binary logic equations for each of the outputs in
terms of the inputs and either synchronous or asynchronous feedback from the outputs.

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The GAL22V10, at 4ns maximum propagation delay time, combines a high performance
CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest
performance available of any 22V10 device on the market. CMOS circuitry allows the
GAL22V10 to consume much less power when compared to bipolar 22V10 devices. E2
technology offers high speed (<100ms) erase times, providing the ability to reprogram or
reconfigure the device quickly and efficiently. The generic architecture provides maximum
design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the
user. The GAL22V10 is fully function/fuse map/parametric compatible with standard bipolar
and CMOS 22V10 devices. Unique test circuitry and reprogrammable cells allow complete

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AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor
delivers 100% field programmability and functionality of all GAL products. In addition, 100
erase/write cycles and data retention in excess of 20 years are specified.

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The GAL22V10 has a variable number of product terms per OLMC. Of the ten available
OLMCs, two OLMCs have access to eight product terms (pins 14 and 23, DIP pinout), two
have ten product terms (pins 15 and 22), two have twelve product terms (pins 16 and 21), two
have fourteen product terms (pins 17 and 20), and two OLMCs have sixteen product terms
(pins 18 and 19). In addition to the product terms available for logic, each OLMC has an
additional product-term dedicated to output enable control. The output polarity of each
OLMC can be individually programmed to be true or inverting, in either combinatorial or
registered mode. This allows each output to be individually configured as either active high
or active low.
The GAL22V10 has a product term for Asynchronous Reset (AR) and a product term for
Synchronous Preset (SP). These two product terms are common to all registered OLMCs.
The Asynchronous Reset sets all registers to zero any time this dedicated product term is
asserted. The Synchronous Preset sets all registers to a logic one on the rising edge of the
next clock pulse after this product term is asserted.
NOTE: The AR and SP product terms will force the Q output of the flip-flop into the same
state regardless of the polarity of the output. Therefore, a reset operation, which sets the
register output to a zero, may result in either a high or low at the output pin, depending on the
pin polarity chosen.

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Each of the Macrocells of the GAL22V10 has two primary functional modes: registered, and
combinatorial I/O. The modes and the output polarity are set by two bits (SO and S1), which
are normally controlled by the logic compiler. Each of these two primary modes, and the bit
settings required to enable them, are described below and on the following page.

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In registered mode the output pin associated with an individual OLMC is driven by the Q
output of that OLMC¶s D-type flip-flop. Logic polarity of the output signal at the pin may be
selected by specifying that the output buffer drive either true (active high) or inverted (active
low). Output tri-state control is available as an individual product-term for each OLMC, and
can therefore be defined by a logic equation. The D flip-flop¶s /Q output is fed back into the
AND array, with both the true and complement of the feedback available as inputs to the
AND array.
NOTE: In registered mode, the feedback is from the /Q output of the register, and not from
the pin; therefore, a pin defined as registered is an output only, and cannot be used for
dynamic I/O, as can the combinatorial pins.



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In combinatorial mode the pin associated with an individual OLMC is driven by the output of
the sum term gate. Logic polarity of the output signal at the pin may be selected by specifying
that the output buffer drive either true (active high) or inverted (active low). Output tri-state
control is available as an individual product-term for each output, and may be individually set
by the compiler as either ³on´ (dedicated output), ³off´ (dedicated input), or ³product-term
driven´ (dynamic I/O). Feedback into the AND array is from the pin side of the output enable
buffer. Both polarities (true and inverted) of the pin are fed back into the AND array.

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Fig:- Functional block diagram

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The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance
CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest
speed performance available in the PLD market. High speed erase times (%100ms) allow the
devices to be reprogrammed quickly and efficiently. The generic architecture provides
maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be
configured by the user. An important subset of the many architecture configurations possible
with the GAL16V8 are the PAL architectures listed in the table of the macrocell description
section. GAL16V8 devices are capable of emulating any of these PAL architectures with full
function/fuse map/parametric compatibility. Unique test circuitry and reprogrammable cells
allow complete AC, DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers 100% field programmability and functionality of all GAL products.
In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.

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The following discussion pertains to configuring the output logic macrocell. It should be
noted that actual implementation is accomplished by development software/hardware and is
completely transparent to the user. There are three global OLMC configuration modes
possible: ()*, )*+, and *(**. Details of each of these modes are illustrated in
the following pages. Two global bits, SYN and AC0, control the mode configuration for all
macrocells. The XOR bit of each macrocell controls the polarity of the output in any of the
three modes, while the AC1 bit of each of the macrocells controls the input/output
configuration. These two global and 16 individual architecture bits define all possible
configurations in a GAL16V8. The information given on these architecture bits is only to
give a better understanding of the device. Compiler software will transparently set these
architecture bits from the pin definitions, so the user should not need to directly manipulate
these architecture bits. The following is a list of the PAL architectures that the GAL16V8 can
emulate. It also shows the OLMC mode under which the GAL16V8 emulates the PAL
architecture.

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In the Registered mode, macrocells are configured as dedicated registered outputs or as I/O
functions. Architecture configurations available in this mode are similar to the common 16R8
and 16RP4 devices with various permutations of polarity, I/O and register placement. All
registered macrocells share common clock and output enable control pins. Any macrocell can
be configured as registered or I/O. Up to eight registers or up to eight I/O's are possible in this
mode. Dedicated input or output functions can be implemented as subsets of the I/O function.
Registered outputs have eight product terms per output. I/O's have seven product terms per
output.






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In the Complex mode, macrocells are configured as output only or I/O functions.
Architecture configurations available in this mode are similar to the common 16L8 and 16P8
devices with programmable polarity in each macrocell. Up to six I/O's are possible in this
mode. Dedicated inputs or outputs can be implemented as subsets of the I/O function. The
two outer most macrocells (pins 12 & 19) do not have input capability. Designs requiring
eight I/O's can be implemented in the Registered mode. All macrocells have seven product
terms per output. One product term is used for programmable output enable control. Pins 1
and 11 are always available as data inputs into the AND array.

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In the Simple mode, macrocells are configured as dedicated inputs or as dedicated, always
active, combinatorial outputs. Architecture configurations available in this mode are similar
to the common 10L8 and 12P6 devices with many permutations of generic output polarity or
input choices. All outputs in the simple mode have a maximum of eight product terms that
can control the logic. In addition, each output has programmable polarity. Pins 1 and 11 are
always available as data inputs into the AND array. The center two macrocells (pins 15 & 16)
cannot be used as input or I/O pins, and are only available as dedicated outputs.

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As chip densities increased, it was natural for the PLD manufacturers to evolve their products
into larger (logically, but not necessarily physically) parts called Complex Programmable
Logic Devices (CPLDs). For most practical purposes, CPLDs can be thought of as multiple
PLDs (plus some programmable interconnect) in a single chip. The larger size of a CPLD
allows you to implement either more logic equations or a more complicated design. In fact,
these chips are large enough to replace dozens of those pesky 7400-series parts.

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Figure 1 contains a block diagram of a hypothetical CPLD. Each of the four logic blocks
shown there is the equivalent of one PLD. However, in an actual CPLD there may be more
(or less) than four logic blocks. I've just drawn it that way for simplicity. Note also that these
logic blocks are themselves comprised of macrocells and interconnect wiring, just like an
ordinary PLD.

Unlike the programmable interconnect within a PLD, the switch matrix within a CPLD may
or may not be fully connected. In other words, some of the theoretically possible connections
between logic block outputs and inputs may not actually be supported within a given CPLD.
The effect of this is most often to make 100% utilization of the macrocells very difficult to
achieve. Some hardware designs simply won't fit within a given CPLD, even though there are
sufficient logic gates and flip-flops available.

Because CPLDs can hold larger designs than PLDs, their potential uses are more varied.
They are still sometimes used for simple applications like address decoding, but more often
contain high-performance control-logic or complex finite state machines. At the high-end (in
terms of numbers of gates), there is also a lot of overlap in potential applications with
FPGAs. Traditionally, CPLDs have been chosen over FPGAs whenever high-performance

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logic is required. Because of its less flexible internal architecture, the delay through a CPLD
(measured in nanoseconds) is more predictable and usually shorter.

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The XC9500 CPLD family provides advanced in-system programming and test capabilities
for high performance, general purpose logic integration. All devices are in-system
programmable for a minimum of 10,000 program/erase cycles. Extensive IEEE 1149.1
(JTAG) boundary-scan support is also included on all family members.
The XC9500 architectural features address the requirements of in-system programmability.
Enhanced pin-locking capability avoids costly board rework. An expanded JTAG instruction
set allows version control of programming patterns and in-system debugging. In-system
programming throughout the full device operating range and a minimum of 10,000
program/erase cycles provide worry-free reconfigurations and system field upgrades.
Advanced system features include output slew rate control and user-programmable ground
pins to help reduce system noise. I/Os may be configured for 3.3V or 5V operation. All
outputs provide 24 mA drive.

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Each XC9500 device is a subsystem consisting of multiple Function Blocks (FBs) and I/O
Blocks (IOBs) fully interconnected by the Fast CONNECTΠswitch matrix. The IOB
provides buffering for device inputs and outputs. Each FB provides programmable logic
capability with 36 inputs and 18 outputs. The Fast CONNECT switch matrix connects all FB
outputs and input signals to the FB inputs. For each FB, 12 to 18 outputs (depending on
package pin-count) and associated output enable signals drive directly to the IOBs.

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Each Function Block, as shown in Figure 2, is comprised of 18 independent macrocells, each

capable of implementing a combinatorial or registered function. The FB also receives global
clock, output enable, and set/reset signals. The FB generates 18 outputs that drive the Fast
CONNECT switch matrix. These 18 outputs and their corresponding output enable signals
also drive the IOB. Logic within the FB is implemented using a sum-of-products
representation. Thirty-six inputs provide 72 true and complement signals into the
programmable AND-array to form 90 product terms. Any number of these product terms, up
to the 90 available, can be allocated to each macrocell by the product term allocator. Each FB
(except for the XC9536) supports local feedback paths that allow any number of FB outputs
to drive into its own programmable AND-array without going outside the FB. These paths are
used for creating very fast counters and state machines where all state registers are within the
same FB.

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Each XC9500 macrocell may be individually configured for a combinatorial or registered
function. The macrocell and associated FB logic is shown in Figure 3. Five direct product
terms from the AND-array are available for use as primary data inputs (to the OR and XOR
gates) to implement combinatorial functions, or as control inputs including clock, set/reset,
and output enable. The product term allocator associated with each macrocell selects how the
five direct terms are used. The macrocell register can be configured as a D-type or T-type
flip-flop, or it may be bypassed for combinatorial operation. Each register supports both
asynchronous set and reset operations. During power-up, all user registers are initialized to
the user-defined preload state (default to 0 if unspecified).

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The product term allocator controls how the five direct product terms are assigned to each
macrocell. For example, all five direct terms can drive the OR function as shown in Figure 5.
The product term allocator can re-assign other product terms within the FB to increase the
logic capacity of a macrocell beyond five direct terms. Any macrocell requiring additional
product terms can access uncommitted product terms in other macrocells within the FB. Up
to 15 product terms can be available to a single macrocell with only a small incremental delay
of TPTA, as shown in Figure 6. Note that the incremental delay affects only the product
terms in other macrocells. The timing of the direct product terms is not changed. The product
term allocator can re-assign product terms from any macrocell within the FB by combining
partial sums of products over several macrocells, as shown in Figure 7. In this example, the
incremental delay is only 2*TPTA. All 90 product terms are available to any macrocell, with
a maximum incremental delay of 8*TPTA.

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The Fast CONNECT switch matrix connects signals to the FB inputs, as shown in Figure 9.
All IOB outputs (corresponding to user pin inputs) and all FB outputs drive the Fast
CONNECT matrix. Any of these (up to a FB fan-in limit of 36) may be selected, through user
programming, to drive each FB with a uniform delay. The Fast CONNECT switch matrix is
capable of combining multiple internal connections into a single wired-AND output before
driving the destination FB. This provides additional logic capability and increases the
effective logic fan-in of the destination FB without any additional timing delay. This
capability is available for internal connections originating from FB outputs only. It is
automatically invoked by the development software where applicable.

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The I/O Block (IOB) interfaces between the internal logic and the device user I/O pins. Each
IOB includes an input buffer, output driver, output enable selection multiplexer, and user
programmable ground control. See Figure 10 for details. The input buffer is compatible with
standard 5V CMOS, 5V TTL, and 3.3V signal levels. The input buffer uses the internal 5V
voltage supply (VCCINT) to ensure that the input thresholds are constant and do not vary
with the VCCIO voltage. The output enable may be generated from one of four options: a
product term signal from the macrocell, any of the global OE signals, always [1], or always
[0]. There are two global output enables for devices with up to 144 macrocells, and four
global output enables for the rest of the devices. Both polarities of any of the global 3-state
control (GTS) pins may be used within the device.. Each output has independent slew rate
control. Output edge rates may be slowed down to reduce system noise (with an additional
time delay of TSLEW) through programming. See Figure 11. Each IOB provides user
programmable ground pin capability. This allows device I/O pins to be configured as
additional ground pins. By tying strategically located programmable ground pins to the
external ground connection, system noise generated from large numbers of simultaneous
switching outputs may be reduced. A control pull-up resistor (typically 10K ohms) is attached
to each device I/O pin to prevent them from floating when the device is not in normal user
operation. This resistor is active during device programming mode and system power-up. It is
also activated for an erased device. The resistor is deactivated during normal operation. The
output driver is capable of supplying 24 mA output drive. All output drivers in the device
may be configured for either 5V TTL levels or 3.3V levels by connecting the device output
voltage supply (VCCIO) to a 5V or 3.3V voltage supply. Figure 12 shows how the XC9500
device can be used in 5V only and mixed 3.3V/5V systems.

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