US006721207B2

(12) United States Patent

(10) Patent N0.:

(45) Date of Patent:

Tsujikawa et al.

(56)

(54) NON-VOLATILE MEMORY SYSTEM

US 6,721,207 B2
*Apr. 13, 2004

References Cited

INCLUDING A CONTROL DEVICE TO

U.S. PATENT DOCUMENTS

CONTROL WRITING, READING AND

STORAGE AND OUTPUT OPERATIONS OF
NON-VOLATILE DEVICES INCLUDING
MEMORY CELLS AND DATA LATCHES

5,570,315 A
5,602,789 A

5,761,122 A
5,768,191 A

(75) Inventors: Tetsuya Tsujikawa, Hamura (JP);

5,870,218 A
5,982,667 A

Atsushi Nozoe, Hino (JP); Michitaro

Kanamitsu, Ome (JP); Shoji Kubono,

Akishima (JP); Eiji Yamamoto,

4/2001 Sato et al.

5/2001

JP
JP

(JP); Hitachi ULSI Systems Co., Ltd.,

U.S.C. 154(b) by 0 days.

(21) Appl. No.: 10/211,342

Aug. 5, 2002
(22) Filed:
Prior Publication Data
(65)

11, 2001, now Pat. No. 6,507,520, which is a continuation of

application No. 09/539,633, ?led on Mar. 30, 2000, now Pat.
No. 6,233,174, which is a continuation of application No.
09/250,157, ?led on Feb. 16, 1999, now Pat. No. 6,046,936.

(51)
(52)
(58)

Primary ExaminerHoai Ho
(74) Attorney, Agent, or FirmAntonelli, Terry, Stout &
Kraus, LLP

ABSTRACT

device and non-volatile memory devices, each including

Continuation of application No. 10/011,723, ?led on Dec.

Foreign Application Priority Data

(JP)

Flash MemoryMultiLevel Memory, US Makers Set

About Technological Development Precedent and Bring to
the Commercial Stage in 1995, Getting Over Reliability,

A non-volatile memory system is provided with a control

Related US. Application Data

Feb. 16, 1998

5/1987
11/1997

OTHER PUBLICATIONS

(57)

US 2002/0191459 A1 Dec. 19, 2002

(30)

62-099996
9297996

(with English translation).

This patent is subject to a terminal dis

claimer.

(63)

McGoldrick et al. ..... .. 711/103

FOREIGN PATENT DOCUMENTS

Tokyo (JP)
Subject to any disclaimer, the term of this
patent is extended or adjusted under 35

365/185.21

2/1999 Jyouno et al. ....... .. 365/18503

11/1999 Jyouno et al. ....... .. 365/185.22

6,226,708 B1

(JP)

Notice:

6/1998 Nakamura et al.

6/1998 ch01 et al.

6,222,763 B1

Kodaira (JP); Ken Matsubara, Ome

(73) Assignees: Renesas Technology Corp., Tokyo

10/1996 Tanaka et al. ....... .. 365/185.22

2/1997 Endoh et al. ........ .. 365/185.03

........................................... .. 10-32776

Int. Cl.7 .............................................. .. G51C 16/04

US. Cl. ............................ .. 365/185.28; 365/185.29
Field of Search ..................... .. 365/185.28, 185.29,

memory cells and data latches. The control device supplies

commands to the non-volatile memory devices, including a
write command, and ?rst and second read commands. When
the control device supplies the write command with write
address information and data for storing in the non-volatile
memory device, it stores the data to the data latches and then
to the memory cells, and then veri?es storage. When the
control device supplies the ?rst read command with read
address information, the nonvolatile memory device reads
data stored in the memory cells to the data latches and then
outputs the data in the data latches to the control device.
When the control device supplies the second read command,
the non-volatile memory device outputs data in the data
latches to the control device.

4 Claims, 57 Drawing Sheets

365/18501

MEMORY MAIv
DATA LATCH
CIRCUIT
SENSE LATCH
CRCUW

5* L
MODE CONIROL CWT/UH
STATUS REGISIHJ

U.S. Patent

Apr. 13, 2004

Sheet 1 0f 57

3 4

US 6,721,207 B2

f3
MEMORY MAT,

DATA LATCH

ADDREss
BUFFER

ADDRESS
DECODER

CIRCUIT,
SENSE LATCH
CIRCUIT
I

7\

17

I/OOII?
I MULTI
V07

PLEXER-

*7 INPUTS

16 (Ff-3%)
21

1' DRTA )

BUFFER

R/Bb

\11

2' COUNTER v12

CEb

18

2O

CONIAFEOL
S
BUFFER +MODE CONTROL CIRCUIT
,

gggggcmcm sTATUs REGISTER I

M;

Y ADDRESS 7

SIGN

BUFFER

F DEcoDER .

3g;S0

Y ADDREss

N L

x2:

I YAR(RATEDIRDUTT/
0 UTPUT
Y

3%?

~"

Q _ ______A,)\_/5
r13

180

* INTERNAL POWER

21

5f+

SUPPLY CIRCUlT
,_

U.S. Patent

Apr. 13, 2004

US 6,721,207 B2

Sheet 2 0f 57

CONTROL GATE
POTENTIAL

FIG. 2

/CG

CONTROL GATE

FG

INTERLAYER
INSULATING FILM

SOURCE
POTENTIAL

S\ *

J DRAIN

FLOATING GATE

POTENTIAL

TUNNEL OXIDE FILM

SOURCE

I DRAIN _/0

MEMORY WELL

WELL POTENTIAL

sue

MODE

FIRST
COMMAND

SECOND
COMMAND

READ

OUR

NO NEED

RECOVERY
READ

01H

NO NEED

EHASE

20H

BOH

PROGRAM

TFR

40H

ADDITIONAL
PROGRAM
RETRY
PROGRAM
PARTIAL
ERASE

0H

40H

IAH

NO NEED

2FH

BOH

REWRITE

11H

40H

U.S. Patent

Apr. 13, 2004

Sheet 3 0f 57

US 6,721,207 B2

FIG. 4
TITLE

DEFINITION

1/07 Ready/IE?

VOH=Ready VOL"=Busy

I/O6 Reserved
[/05 Erase Check

VoH"=Fai| VOL:Pass

1/04 Program Check VOH"=FaIl VOL"=Pass

[/03 Reserved
I/O2 Reserved
I/ O1

Reserved

[/00 Reserved

STATUS REGISTER

U.S. Patent

Apr. 13, 2004

US 6,721,207 B2

Sheet 5 0f 57

FIG. 6
PROGRAM
DATA

DLL

DLR

DOA OD

11

VWV3
VH3 ------------ -

VH2 ------------

vm

-- ---------- -

VWE2

VWV2
VWE1
VWV1
VWDS

OV

MEMORY CELL
NUMBER

U.S. Patent

Apr. 13, 2004

Sheet 6 0f 57

US 6,721,207 B2

FIG. 8
-17v

SELECTED

wORD LINE

----------

SEOTOR
BATCH
ERASE

0V

5 +111
P11 j=
-----------

(1 WORD ERASE
AT SAME TIME)

&

&
0v

IN

NON-SELECTED
WORD LINE

IN

SELECTED

WORD LINE

---------

WRITE EvERY
BIT

0v

(1 WORD WRITE
AT SAME TIME)

NONSELECTED
wORD LINE

J:

W
SELECTED

W
NON-SELECTED

BIT LINE

BIT LINE

OPERATION VOLTAGE

FIG. 9
WHITE

Case1

(1)

Case2

Case3

(3)

Case4

(3)

CaSeS

(2)

(3)

(31 (HT (1)

I I I
ERASING STATE

I II

U.S. Patent

Apr. 13, 2004

Sheet 8 0f 57

US 6,721,207 B2

FIG. 1 1
AND TYPE
MEMORY MAT

M1
l

/ SOURCE LINE

SDI BIT LINE

(CONTROL GATE) FIJI [

WL (WORD LINE)

1|

j.

WL (WORD LINE)

SUB-BIT LINE

'l;_ ._ ;.j>'/
/\/MC

mv/
i

_T_

{MC

g)

klzqvMc AL-LI SUB-BIT LINE

l

WL (WORD LINE)

11/ MC

farm

SSi (sOuRcE LINE

CONTROL GATE)

MC\

wORO
WORD LINE

WORO LINE

WORO LINE MCf

1 /\/M2

ILL

BIT LINE

NEARIIOTFIIFTMAT

__

01

BIT LINE

SOURCE LINE

u-"

A\_/MC

AVMC

'

BIT LINE

BIT LINE

U.S. Patent

Apr. 13, 2004

Sheet 9 0f 57

US 6,721,207 B2

DiNOR TYPE

MEMORY MAT

>-SOURCE LINE

WORD LINE

\_,MC

WORD LINE
WORD LINE

Hp/MC

WORD NE

SUB-BIT LINE
.5

FF
5 '

WORD LINE

.:

_j

\\_M_(_;--.

SELECTED GATE-

_j

4| \MC

____ _-__I

BIT LINE

BIT UNE

NAND TYPE

MEMORY MAT
sOuRcE LINE

r1

CONTROL GATE

---- --

ME"

SOURCE LINE

2]

WORD LINE -#/::i .... --_.__ WMC

WORD LINE

II

..... ..__D|

WORD LlNE-

----- --___|| WMC

WORD LINE-

\ M-_-___I|
'

WORD LINE ~7

12/ MC
I

BIT LINE

____ .____" \\_MC

.... -.

OONTROL GATE

.,_5

BIT LINE

BIT LINE

U.S. Patent

Apr. 13, 2004

HiCFI TYPE
MEMORY MAT

BIT LINE

SOURCE LINE

CONTROL GATE

Sheet 10 0f 57

"Jab

T|| MC

WORD LINE

SUB-SOURCE
LINE
\<~

SOURCE LINE

TLII

II_

II'TF"

rJl MC

l
Fur/MC

US 6,721,207 B2

,7

WORD LINE

Ii

MC

ITLI.

BIT LINE

CONTROL GATE

r71

SUB-BIT MM??WORD LINE

IL_

TTLI
5% Q

___

._

__

MC5"

BIT LINE

{MC

MC5H'TT

BIT LINE BIT LINE

LL

AMC
BIT LINE

U.S. Patent

Apr. 13, 2004

FETCH FIRST COMMAND

Sheet 11 0f 57

5'81

US 6,721,207 B2

'

FETCH SECTOR ADDRESS FSQ

TS
'01-

FETCH PROGRAM DATA

53

FETCH SECOND COMMAND

84

LATCH '01" DATA

5 PROGRAM '00- DATA

5
5 (SEE FIG 23)
=

PROGRAMING 5
OPERATION -;
:

:
VERIFY vwv3
FAIL;
g
?
I
-_,-._PP_S_S_ ________________ _.
T52

'

LATCH '00" DATA

11' WORD
?lswwgggcm

FAIL
T84

________________________ _'

PROGRAM *oo- DATA

ERRATIC/

PROGRAMING
OPERATION

T53
"0'

PROGRAMING
OPERATION

OISTURB
DETECTION
OPERATION

LATCH '10 DATA

P OGRAM "1()' DATA

SET PASS FLAG

TO STATUS

55? REGISTER
I

SET FAIL FLAG

,38
TO STATUS
I

REGISTER
I

( END TOTO) CENDINGI)

PROGRAM FLOW (CASE 1)

U.S. Patent

Apr. 13, 2004

Sheet 12 0f 57

FIG. 17
Vth
VWV3

> "01"
---------------- __

> "H"
BIT NUMBER
"01" PROGRAM DATA

FIG. 18
Vlh 1

> ~01
WW2

BIT NUMBER

7190i EBQQBAM DATA

US 6,721,207 B2

U.S. Patent

Apr. 13, 2004

Sheet 13 0f 57

FIG. 19

BlT NUMBER
"10" PROGRAM DATA

FIG. 20
V

asm

VWD
0v

,7
_

mun?l"1.M0_m

>
BIT NUMBER

MQ/DISTURB
DETECTION OPERATON

US 6,721,207 B2

U.S. Patent

Apr. 13, 2004

Sheet 14 0f 57

US 6,721,207 B2

FIG. 21
DATA LATCH PROCESS

CALCULATION CONTENT
(SENSE LATCH DATA OF
SELECTED MAT SIDE)

'01- PROGRAM DATA

A+

'00" PROGRAM DATA

A+B

'10" PROGRAM DATA

5+8

"0o" ERRATIC DETECTION DATA

A+B_

"10" ERRATIC DETECTION DATA

A .

'11" DIsTuRB DETECTION DATA

A - B

A: UPPER DlGlT DATA

BILOWER DIGIT DATA

FIG. 22
UPIIXDER LOIENER A+B' A+B K+B m A-' A-B
DIGIT
0

DIGIT
1

'I

U.S. Patent

Apr. 13, 2004

Sheet 15 0f 57

US 6,721,207 B2

START '01" PROGRAMING

OPERATION

5 S101

?
-

I
EXECUTE DATA LATCH

PROcEss

-_

8'11 APPLY "o1" PROGRAMING

BIAS VOLTAGE
7

S121

EXECUTE PROGRAM
VERIFY vwvs
813
ALL

JUDGIEIAENT
PASS

END "01" PROGRAMING)

OPERATION
sTART "I0" ERRATIO

DETECTION

II
EXECUTE DATA LATCH

S201

5
E

PROCESS

I
E

I
5211

EXECUTE ERRATIO
VERIFY VWE1

522

\-

ALL

\\

FAIL

JUDGMENT

PASS

END "10" ERRATID

DETECTION

l
' _

-__l

U.S. Patent

Apr. 13, 2004

Sheet 17 0f 57

US 6,721,207 B2

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U.S. Patent

Apr. 13, 2004

Sheet 18 0f 57

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US 6,721,207 B2

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U.S. Patent

Apr. 13, 2004

Sheet 19 0f 57

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