US006504764B2

(12) United States Patent

(10) Patent N0.:

(45) Date of Patent:

Tsujikawa et al.

(56)

(54) NON-VOLATILE MEMORY DEVICE

U.S. PATENT DOCUMENTS

Atsushi Nozoe, Hino (JP); Michitaro

5,570,315
5,602,789
5,768,191
5,870,218

Kanamitsu, Ome (JP); Shoji Kubono,

Akishima (JP); Eiji Yamamoto,
Kodaira (JP); Ken Matsubara, Ome

(JP)
(73) Assignee: Hitachi, Ltd., Tokyo (JP)
Notice:

*Jan. 7, 2003

References Cited

(75) Inventors: Tetsuya Tsujikawa, Hamura (JP);

(*)

US 6,504,764 B2

A
A
A
A

10/1996
2/1997
6/1998
2/1999

Tanaka et al.
Endoh et al.
(31101 et al.
Jyouno et al.

5,910,918 A

6/1999

5,917,756 A
6,064,606 A

*
*

6/1999 Imamiya et al. ..... .. 365/185.17

5/2000 Kuroda et al. ............ .. 365/200

6,222,763 B1

Subject to any disclaimer, the term of this

patent is extended or adjusted under 35

Hirano ................ .. 365/18516

4/2001 Sato et al.

FOREIGN PATENT DOCUMENTS

JP

U.S.C. 154(b) by 0 days.

9297996

11/1997

OTHER PUBLICATIONS

This patent is subject to a terminal dis

claimer.

Flash MernoryMultiLevel Memory US Makers Set

About Technological Development Precedent and Bring to
the Commerical Stage in 1995, Getting Over Reliability,

(21) Appl. No.: 09/985,116

Nov. 1, 2001
(22) Filed:
Prior Publication Data
(65)

(with English Translation).

* cited by examiner

Primary ExaminerHoai Ho
(74) Attorney, Agent, or FirmAntonelli, Terry, Stout &
Kraus, LLP

US 2002/0027807 A1 Mar. 7, 2002

Related US. Application Data

(63)

(57)

A non-volatile memory device having a plurality of memory

Continuation of application No. 09/820,906, ?led on Mar.

cells and a control circuit. The control circuit receives

30, 2001, now Pat. No. 6,320,793, which is a continuation

of application No. 09/539,633, ?led on Mar. 30, 2000, now

operation commands from outside the device and controls

the operation of the device according to the commands. The
commands include read commands and write commands. In

Pat. No. 6,233,174, which is a continuation of application

No. 09/250,157, ?led on Feb. 16, 1999, now Pat. No.

6,046,936.

(30)
(51)
(52)
(58)

a read command, the control circuit reads data in the

memory cells and outputs it. In a write command, the control
circuit controls the inputting of data to data latch circuits and
then to memory cells. The control circuit provides status
information indicating whether the writing of data is a

Foreign Application Priority Data

Feb. 16, 1998

ABSTRACT

(JP) ........................................... .. 10-32776

Int. Cl.7 .............................................. .. G11C 16/04

US. Cl. ............... ..
365/185.28; 365/185.22
Field of Search ..................... .. 365/185.28, 185.22,

success or a failure.

11 Claims, 57 Drawing Sheets

365/18501

,6

f3
MEMORY MAT,

ADDRESS

ADDRESS

BUFFER

05000511
+

M 2

17
V00

[/07

INPUT

DATA LATCH
0100011,
SENSE LATCH
016000

x
DATA

21

/ 13

2 Y GATE

$15

.1 - CONTROL L ARRAY cmcun ,_ OUTPUT

BUFFER

C|HCU|T

Y ADDRESS

R/Bb

BUFFER

DECODER
\

V06

2 |Y ADDRESS

V55

LOUNTER

CED

OEb

\ 12

(8

WEb

,,

REsslcJ v

MODE CONTROL cmcun _ INTERNAL POWER

CD51,

5110i
1156mm
S

19

180

,i,

2.

11

SUPPLY 010000
t

21
I

17.

U.S. Patent

Jan. 7, 2003

US 6,504,764 B2

Sheet 1 0f 57

FIG. 1
8

{1

MEMORY MAT,
X

DATA LATCH

ADDRESS

ADDRESS

cIRcuIT,

DDEEER

DEcoDER

SENSE LATCH
CIRCUIT

(t/""S""~> <f__" ,i7\_/5

\ N
[/07 I l MULT|_

R/Bb

PIExER :

BUFFER

CIRCUIT

Y ADDRESS

I" DECODER \

2 Y ADDRESS _

V85 1::

CEb

f5

3' |NPUT LEQKXTROL 1% ARRAY C|RCUIT _> OUTPUT

Vcc

OED

E couIITER

I8

CONTROL

BUFFER

11

\42

520

WEb
REgg

SIGNAL
BUFFER + MDDE CONTROL DIRDIIIT

,NTERNAL POWER

CDEb

CIRCUIT

SUPPLY CIRCUIT

>

-* STATUS REG|STER

>

,5

19

180

U.S. Patent

Jan. 7, 2003

US 6,504,764 B2

Sheet 2 0f 57

CONTROL GATE
POTENTIAL

FIG. 2

L/

CONTROL GATE

INTERLAYER
INSULATING FILM

SOURCE
POTENTIAL

S\ -

CG

JFG

DRAIN
POTENTIAL

FLOATING GATE
TUNNEL OXIDE FILM

SOURCE

DRAIN

MEMORY WELL

5
wELL POTENTIAL

SUB

MODE

FIRST
COMMAND

SECOND
COMMAND

READ

OUR

NO NEED

RECOVERY
READ

OIH

NO NEED

ERAsE

20H

BOH

PROGRAM

IFH

40H

10

40

ADDITIONAL
PROGRAM
RETRY
PROGRAM
PARTIAL
ERASE

IAH

NO NEED

2FH

BOH

REwRITE

IIR

40H

JD

U.S. Patent

Jan. 7, 2003

Sheet 3 0f 57

US 6,504,764 B2

FIG. 4
TITLE
I/O7

Ready/m

DEFINITION
VOH ": Ready VOL ":Busy

I/O6 Reserved
[/05

Erase Check

VOH "= Fail VOL ": Pass

1/04

Program Check

VOH ": Fail VOL "= Pass

[/03 Reserved

1/02 Reserved
1/01 Reserved

I/OO Reserved
STATUS REGISTER

U.S. Patent

Jan. 7, 2003

Sheet 5 0f 57

US 6,504,764 B2

FIG. 6
B$ERAM 41/00

DLL

DLR

O1

00

1O

VH3 --------VWE2

----------------- i,

\\ 001!

VH2 ____________ _, vwvz >

VWE1

VH1 iiiiiiiiiiii v,

---------------- _

vwv1 > 0
VWDS >

H ,,

OV
MEMORY CELL
NUMBER

U.S. Patent

Jan. 7, 2003

-17v

Sheet 6 6f 57

US 6,504,764 B2

SELECT

WORD L

TOR
BATCH
35

i PH
----------PL ;,

0V

(1 WORD ERASE
AT SAME TIME)

i
W

SELECT
------------------- ~~

WRITE EVERY
BIT

NON-SELECTED
WORD LINE

0v

WORD

N~SELECTED
RD LINE

(I WORD WRITE
AT SAME TIME)
ECTED
LINE

6V
NONSELECTED
BIT LINE

OPERATION VOLTAGE

FIG. 9
WRITE

CaseI

Case2

(1)

(3)

(2)

(2)

CaseS

(3)

Case4

Cases

(2)

(3)

(2) I (I) I

(1) I

(31) (It) I I I I] (if) HG?)

ERASING STATE

U.S. Patent

Jan. 7, 2003

Sheet 8 0f 57

US 6,504,764 B2

11
AND TYPE
MEMORY MAT
,

SDI (BIT LINE

OONTROL GATE)

jIII

WL (wORO LINE)

M1

[MI
I].
_

SUB-BIT LINE

L/ML

a
JEEP

SUB-BIT LINE

//

i.

__T_ /

i.

II

[if

SSI (SOURCE LINE

CONTROL GATE)

[MC

g)

n f/MC

WL (WORO LINE)

SOURCE LINE

J:

WL (WORO LINE)

LL:

BIT LINE

BIT LINE

FIG. 12
NOR TYPE
MEMORY MAT

SOURCE LINE

MC

WORD LINE
WORD LINE

WORD LINE
WORD LINE

II
II

MCI BIT LINE

I
I

I : /'\ L / MC

I
I

I
BIT LINE

U.S. Patent

Jan. 7, 2003

Sheet 9 0f 57

US 6,504,764 B2

FIG. 13
DiNOR WPE

MEMORY MAT
>SOURCE LINE

W 0 DH D L W E
w

0 Dn RD LI E
m

WORD LINE

SELECTED GATE

SUB-BIT LINE

ERNIE:

BIT LINE

FIG. 14
NAND TYPE
MEMORY MAT
SOURCE LINE

SOURCE LINE
CONTROL GATE

I
I

fJ/W?"

WORD LINE

I: rL/MC

WORD LINE

II

II

II

WORD LINE

II

II

I
I

WORD LINE

WORD LINE
BIT LINE
CONTROL GATE

| rv/MC

":3
I

BIT LINE

BIT LINE

U.S. Patent

Jan. 7, 2003

HICR TYPE
MEMORY MAT
BIT LINE

Sheet 10 0f 57

SOURCE LINE
'

CONTROL GATE FIJI MC

IEF

sOuROE LINE
'

wORO LINE
l1 l
SUB-SOURCE
, I_I FY r/MC
LINE
\\-R_
WORD LINE

SUB-BIT
WORD LINE
BIT LINE

CONTROL GATE

US 6,504,764 B2

'

WEI MC
l
LIT)

IEF
l
1'1.
/
MC

_I_

:L

L
Big
i 5

IvIO 5 Ir

BIT LINE

ILL

K MC

MC 5 ,[

BIT LINE BIT LINE

II_L

'

aMO
BIT LINE

U.S. Patent

Jan. 7, 2003

T5
I01.
PROGRAMING
OPERATION

Sheet 11 0f 57

US 6,504,764 B2

2 (SEE FIG. 23)

'

' I

"II" WORD
DISTURB DETECTION
VWDS ?
T82

FAIL
T84

__________________________ ,_

'01"
PROGRAMING
OPERATION

T53
'0"

PROGRAMING
OPERATION

ERRATIC/
DISTURB
DETECTION
OPERATION

"00" ERRATIC
DETECTION
VWE2 ?

LATCH "IO" DATA

PROGRAM 10 DATA

PASS

SET PASS FLAG

SET FAIL FLAG

T0 STATIIS

T0 STATUS

A REGISTER

REGISTER

( END (OK) ) Q ENDING) )

PROGRAM FLOW (CASE 1)

S8
f

U.S. Patent

Jan. 7, 2003

Sheet 12 0f 57

FIG. 17
Vth

> "01"

vwvs ~~~~~~~~~~~~~~~~ -

>
BIT NUMBER
"01" PROGRAM DATA

FIG. 18
Vth

W > 00

0V

BIT NUMBER
"00" PROGRAM DATA

US 6,504,764 B2

U.S. Patent

Jan. 7, 2003

Sheet 13 0f 57

FIG. 19
A

Vth

> "01"
> "00"

W >*

"11..

0V
BIT NUMBER
"10" PROGRAM DATA

FIG. 20

VWE2
VWE1
VWDS ----------------- E

> "11"
BlT NUMBER

w
DETECTION OPERATION

US 6,504,764 B2

U.S. Patent

Jan. 7, 2003

Sheet 14 0f 57

US 6,504,764 B2

FIG. 21
CALCULATION CONTENT
(SENSE LATCH DATA OF

DATA LATCH PROCESS

SELECTED MAT SIDE)

"01 PROGRAM DATA

Mg

"00" PROGRAM DATA

A+B

"10" PROGRAM DATA

3+8

"00" ERRATIC DETECTION DATA

A+B

"10" ERRATIC DETECTION DATA

A . 5

"II" DISTuRR DETECTION DATA

A - B

A: UPPER DIGIT DATA

8 I LOWER DIGIT DATA

FIG. 22
uPIER LOEVER A+ A+B AIR E5 Ag A.B
DIGIT

DIGIT

U.S. Patent

Jan. 7, 2003

Sheet 15 0f 57

US 6,504,764 B2

FIG. 23
E

START "01" PROGRAMING

OPERATION

S1072

EXECUTE OATA LATCH

PROCESS

-=~
V

APPLY "01" PROGRAMING

BIAS VOLTAGE

5 312?

EXECUTE PROORAII/I
vERIEY vwva
S13
ALL

JUDGMENT

FAIL

PASS

END "01" PROORAMINO

OPERATION

FIG. 24 I ---------------------------------------------------- _,
E

START "10" ERRATIC

( DETECTION
I

5 520?

5
.

EXECUTE DATA LATCH

PROCESS

I
92 T2

EXECUTE ERRATIC

VERIFY vwEI

END "10 ERRATIC

DETECTION

U.S. Patent

Jan. 7, 2003

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