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    This document summarizes a homework assignment that involves: 1) Performing a breakeven analysis between a Xilinx FPGA and AMI gate array to determine the quantity at which it is cheaper to switch to the gate array. The breakeven point is found to be 430 chips for 1k quantity and 859 chips for 50k quantity. 2) Drawing the transistor level design of a 2-input NAND gate and verifying its truth table. 3) Calculating the current required to drive a 1.25 GHz prescaler off-chip with a given capacitance and signal swing. The required current is found to be 22.8 mA.

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    ECE510 HW

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    This document summarizes a homework assignment that involves: 1) Performing a breakeven analysis between a Xilinx FPGA and AMI gate array to determine the quantity at which it is cheaper to switch to the gate array. The breakeven point is found to be 430 chips for 1k quantity and 859 chips for 50k quantity. 2) Drawing the transistor level design of a 2-input NAND gate and verifying its truth table. 3) Calculating the current required to drive a 1.25 GHz prescaler off-chip with a given capacitance and signal swing. The required current is found to be 22.8 mA.

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    © All Rights Reserved
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    104 views2 pages

    HW4

    Uploaded by

    saliya_kumara
    This document summarizes a homework assignment that involves: 1) Performing a breakeven analysis between a Xilinx FPGA and AMI gate array to determine the quantity at which it is cheaper to switch to the gate array. The breakeven point is found to be 430 chips for 1k quantity and 859 chips for 50k quantity. 2) Drawing the transistor level design of a 2-input NAND gate and verifying its truth table. 3) Calculating the current required to drive a 1.25 GHz prescaler off-chip with a given capacitance and signal swing. The required current is found to be 22.8 mA.

    Copyright:

    © All Rights Reserved
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    of 2

    ECE 510 Computer Design

    Homework #4
    Saliya Kumara K. (1773937)

    Replacing a FPGA with a Gate Array


    1. Breakeven analysis example between a Xilinx FPGA and an AMI Semiconductor gate array:
    The Xilinx XCV200 is a 236,000 gate FPGA that costs $139* @ in qty = 50K and $278 @ in qty = 1K.
    Find the breakeven point (# of units) to move to the X2P528 gate array from AMI Semiconductor
    (0.15um process). The AMI charge per gate array is $40* @ in qty = 50K and $80 @ in qty=1K with
    an NRE charge of $85K. Hint: Start with the lower unit #s 1st (1K qty).
    For 1k Qty,
    = +
    =
    = . =

    For 50k Qty,


    = +
    =
    = . =

    Therefore, the breakeven point is 430 chips for 1k Qty, and 859 chips for 50k Qty.
    2. Show the CMOS transistor level design for a 2-input NAND gate. Verify Truth Table

    A
    1
    1
    0
    0

    B
    1
    0
    1
    0

    Out
    0
    1
    1
    1

    3. Find the current required for an output buffer to drive a 1.25 GHz prescaler off-chip with a 5 Vpp
    swing and 0.9 pF of parasitic capacitance from an oscilloscope.

    = . , =

    = =
    =
    =
    .
    =

    = .

    = . = .

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