static void mdlOutputs(SimStruct *S, int_T tid)

{
InputRealPtrsType uPtrs = ssGetInputPortRealSignalPtrs(S,0);
real_T

*y = ssGetOutputPortRealSignal(S,0);

real_T Ua,Ub,absUa,absUb,Umc,Uu,Uv,Uw,d1,d2,dz,D,S1,S2,S3,S4,S5,S6,Ts;
/*******************************************************************
********/
/* (*uPtrs[0])==Ua ; (*uPtrs[1])==Ub ; (*uPtrs[2])== Umc *uPtrs[3])==D */
/*********************************************************************
******/
Ua=(*uPtrs[0]);
Ub=(*uPtrs[1]);
Umc=(*uPtrs[2]);
D=(*uPtrs[3]); // duty cycle of shoot - through state
Ts=1;
/* Calculates asbsolute of voltage anphal */
if(Ua>=0)
absUa=Ua;
else
absUa=-Ua;
if(absUa>0.67*Umc)
absUa=0.67*Umc; /*Limiting*/
/* Calculates asbsolute of voltage betta */
if(Ub>=0)
absUb=Ub;
else
absUb=-Ub;
if(absUb>0.67*Umc)

absUb=0.67*Umc;
// Calculates phase-neutral voltage
Uu=Ua;
Uv=-0.5*Ua+sqrt(3)*Ub/2;
Uw=-0.5*Ua-sqrt(3)*Ub/2;
if(Uu>=Uv)
{
if (Uv>=Uw)
{
//sector 1
d1=(1.5*Ua-sqrt(3)*Ub/2)/Umc;
d2=(sqrt(3)*Ub)/Umc;
dz=1-d1-d2;
// calculate upper
S1= Ts*(dz/4-D/12);
S3= Ts*(dz/4+d1/2+D/12);
S5= Ts*(dz/4+d1/2+d2/2+D/4);
// calculate lower (must invert logic state)
S4= Ts*(dz/4-D/4);
S6= Ts*(dz/4+d1/2-D/12);
S2= Ts*(dz/4+d1/2+d2/2+D/12);
}
else if (Uw>=Uu)
{
//sector 5
d1=(-1.5*Ua-sqrt(3)*Ub/2)/Umc;
d2=(1.5*Ua-sqrt(3)*Ub/2)/Umc;

dz=1-d1-d2;
// calculate upper
S1= Ts*(dz/4+d1/2+D/12);
S3= Ts*(dz/4+d1/2+d2/2+D/4);
S5= Ts*(dz/4-D/12);
// calculate lower (must invert logic state)
S4= Ts*(dz/4+d1/2-D/12);
S6= Ts*(dz/4+d1/2+d2/2+D/12);
S2= Ts*(dz/4-D/4);
}
else
{
//sector 6
d1=(1.5*Ua+sqrt(3)*Ub/2)/Umc;
d2=(-sqrt(3)*Ub)/Umc;
dz=1-d1-d2;
// calculate upper
S1= Ts*(dz/4-D/12);
S3= Ts*(dz/4+d1/2+d2/2+D/4);
S5= Ts*(dz/4+d1/2+D/12);
// calculate lower (must invert logic state)
S4= Ts*(dz/4-D/4);
S6= Ts*(dz/4+d1/2+d2/2+D/12);
S2= Ts*(dz/4+d1/2-D/12);
}
}
else

{
if(Uv<Uw)
{
//sector 4
d1=(-sqrt(3)*Ub)/Umc;
d2=(-1.5*Ua+sqrt(3)*Ub/2)/Umc;
dz=1-d1-d2;
// calculate upper
S1= Ts*(dz/4+d1/2+d2/2+D/4);
S3= Ts*(dz/4+d1/2+D/12);
S5= Ts*(dz/4-D/12);
// calculate lower (must invert logic state)
S4= Ts*(dz/4+d1/2+d2/2+D/12);
S6= Ts*(dz/4+d1/2-D/12);
S2= Ts*(dz/4-D/4);
}
else if (Uw<Uu)
{
//sector 2
d1=(-1.5*Ua+sqrt(3)*Ub/2)/Umc;
d2=(1.5*Ua+sqrt(3)*Ub/2)/Umc;
dz=1-d1-d2;
// calculate upper
S1= Ts*(dz/4+d1/2+D/12);
S3= Ts*(dz/4-D/12);
S5= Ts*(dz/4+d1/2+d2/2+D/4);
// calculate lower (must invert logic state)

S4= Ts*(dz/4+d1/2-D/12);
S6= Ts*(dz/4-D/4);
S2= Ts*(dz/4+d1/2+d2/2+D/12);
}
else
{
//sector 3
d1=(sqrt(3)*Ub)/Umc;
d2=(-1.5*Ua-sqrt(3)*Ub/2)/Umc;
dz=1-d1-d2;
// calculate upper
S1= Ts*(dz/4+d1/2+d2/2+D/4);
S3= Ts*(dz/4-D/12);
S5= Ts*(dz/4+d1/2+D/12);
// calculate lower (must invert logic state)
S4= Ts*(dz/4+d1/2+d2/2+D/12);
S6= Ts*(dz/4-D/4);
S2= Ts*(dz/4+d1/2-D/12);
}
}
y[0]=2*S1/Ts;
y[1]=2*S3/Ts;
y[2]=2*S5/Ts;
y[3]=2*S4/Ts;
y[4]=2*S6/Ts;
y[5]=2*S2/Ts;
}