2.

ENTITY DESIGN VHDL2

1. ENTITY ======================
library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity AOI is
port (A, B, C, D: in STD_LOGIC;
F: out STD_LOGIC);
end AOI;

architecture V1 of AOI is
begin
F <= not((A and B) or (C and D));
end V1;

2. SIGNAL ---------------------------------------
architecture V2 of AOI is
signal AB, CD, O: STD_LOGIC;
begin
AB <= A and B after 2 NS;
CD <= C and D after 2 NS;
O <= AB or CD after 2 NS;
F <= not O after 1 NS;
end V2;

3. COMPONENT =================
library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity MUX2 is
port (SEL, A, B: in STD_LOGIC;
F: out STD_LOGIC);
end MUX2;

architecture STRUCTURE of MUX2 is

component INV
port (A: in STD_LOGIC;
F: out STD_LOGIC);
end component;

component AOI
port (A, B, C, D: in STD_LOGIC;
F: out STD_LOGIC);
end component;

signal SELB: STD_LOGIC;

begin
G1: INV port map(SEL, SELB);
G2: AOI port map(SEL, A, SELB, B, F);
end STRUCTURE;

4. --------------------------------------------------
G1: entity WORK.INV(ARCH)
port map (SEL, SELB);
G2: entity WORK.AOI(V2)
port map (SEL, A, SELB, B, F);

vhdl_ex 1
5. TEST BENCHES ===============
library IEEE;
use IEEE.STD_LOGIC_1164.all;
(or use WORK.all;)

entity TEST_MUX4 is
end; -- empty entity !

architecture BENCH of TEST_MUX4 is

component MUX4
port (SEL: in STD_LOGIC_VECTOR(1 downto 0);
A, B, C, D: in STD_LOGIC;
F: out STD_LOGIC);
end component;

signal SEL: STD_LOGIC_VECTOR(1 downto 0);

signal A, B, C, D, F: STD_LOGIC;

begin
SEL <= "00",
"01" after 30 NS,
"10" after 60 NS, "11" after 90 NS,
"XX" after 120 NS, "00" after 130 NS;
A <= 'X',
'0' after 10 NS,
'1' after 20 NS;
B <= 'X',
'0' after 40 NS,
'1' after 50 NS;
C <= 'X',
'0' after 70 NS,
'1' after 80 NS;
D <= 'X',
'0' after 100 NS,
'1' after 110 NS;
...
M: MUX4 port map(SEL, A, B, C, D, F);

end BENCH;

configuration CFG_MUX4 of TEST_MUX4 is

for BENCH
end for;
end CFG_MUX4;

vhdl_ex 2
3. PROCESS & SYNCHRONISATION VHDL3

1. PROCESS ====================
architecture V3 of AOI is

signal AB, CD, O: STD_LOGIC;

begin
process (A, B, C, D) -- sensitivity list !
begin
AB <= A and B after 2 NS;
CD <= C and D after 2 NS;
end process;

process (AB, CD) -- procese concurente !

begin
O <= AB or CD after 2 NS;
end process;

process (O)
begin
F <= not O after 1 NS;
end process;

end V3;

2. SENSITIVITY LIST ------------------------

(P2: ) process (SEL, A, B, C)
begin
if SEL = '1' then
OP <= A and MASK;
else
OP <= B;
end if;
end process (P2);

3. WAIT ------------------------------------------
Stimulus: process
begin
Reset <= '0';
wait for 50 NS;
Reset <= '1';
wait;
end process;

4. TEST VECTORS ---------------------------

TestVectors: process
begin
A <= "0000";
B <= "0000";
wait for 10 NS;
A <= "1111";
wait for 10 NS;
B <= "1111";
wait for 10 NS;
A <= "0101";
B <= "1010";
wait;
end process;

vhdl_ex 3
5. EVENTS -------------------------------------
process (A, B, S, T) -- delta delay !
begin
S <= A nand B after 2 NS;
T <= not S;
F <= T after 1 NS;
end process;

6. --------------------------------------------------
Feedback: process (S, R, Q, QB) -- RS
begin
Q <= S nand QB;
QB <= R nand Q;
end process;

vhdl_ex 4
4. SEQUENCIAL STATES VHDL4

1. VARIABLE -----------------------------------
process (A, B, C)
variable V: Std_logic; -- local !

begin
V := A nand B;
V := V nor C;
F <= not V;
end process;

2. SIGNAL / VARIABLE ----------------------

architecture ...
signal F: Std_logic; -- global !

begin
process (A, B, C)
variable V: Std_logic; -- local !
begin
V := A nand B;
V := V nor C;
F <= not V;
end process;

process (F)
begin
...
end process;
...

3. IF / ELSE  MUX --------------------------

if C1 = '0' then
V := A;
else
V := B;
end if;

4. ---------------------------------------------------
if C2 = '1' and C3 = '1' then
V := not V;
end if;

5. ----------------------------------------------------
process (C1, C2, C3, A, B)
variable V: Std_logic;
begin
if C1 = '0' then
V := A;
else
V := B;
end if;

if C2 = '1' and C3 = '1' then

V := not V;
end if;

F <= V;
end process;

vhdl_ex 5
6. NESTED IF ----------------------------------
process (C0, C1, C2, A, B, C, D)

begin
if C0 = '1' then
F <= A;
else
if C1 = '1' then
F <= B;
else
if C2 = '1' then
F <= C;
else
F <= D;
end if;
end if;
end if;
end process;

7. ELSIF -----------------------------------------
process (C0, C1, C2, A, B, C, D)

begin
if C0 = '1' then
F <= A;
elsif C1 = '1' then
F <= B;
elsif C2 = '1' then
F <= C;
else
F <= D;
end if;
end process;

8. INCOMPLET ASIGN ----------------------

process (Enable, Data) -- transparent latch !

begin
if Enable = '1' then
Q <= Data;
end if;
end process;

9. CASE ------------------------------------------
case SEL is
when "00" => -- nu elemente comune !
F <= A;
when "01" =>
F <= B;
when "10" =>
F <= C;
when "11" =>
F <= D;
when others =>
F <= 'X';
end case;

vhdl_ex 6
10. OR COND ---------------------------------
case ADDRESS is
when 16 | 20 | 24 | 28 =>
A <= '1';
B <= '1';
when others =>
end case;

11. DOMAIN COND --------------------------

case ADDRESS is
when 0 to 7 =>
A <= '1';
when 8 to 15 =>
B <= '1';
when 16 | 20 | 24 | 28 =>
A <= '1';
B <= '1';
when others =>
null;
end case;

12. COMPARISON IF- CASE ---------------

if SEL(1) = '1' then -- IF priority !
F <= A;
elsif SEL(0) = '1' then
F <= B;
else
F <= C;
end if;

13. -------------------------------------------------
case SEL is -- CASE paralel test !
when "10" =>
F <= A;
when "11" =>
F <= A;
when "01" =>
F <= B;
when others =>
F <= C;
end case;

14. ------------------------------------------------
if SEL = "00" then -- No FPGA !
F <= A;
elsif SEL = "01" then
F <= B;
elsif SEL = "10" then
F <= C;
else
F <= D;
end if;

vhdl_ex 7
15. -------------------------------------------------
case SEL is
when "00" =>
F <= A;
when "01" =>
F <= B;
when "10" =>
F <= C;
when others =>
F <= D;
end case;

16. FOR LOOPS ------------------------------

for I in 0 to 3 loop -- [Lab:] for Loop_par in Range loop
F(I) <= A(I) and B(3-I);
V := V xor A(I);
end loop; -- end loop [Lab];
-----------------------------------------------------

for I in 3 downto 0 loop -- descendent range

F(I) <= A(I) and B(3-I);
V := V xor A(I);
end loop;

17. ------------------------------------------------
process (A, B)
variable I: Std_logic;
...
begin

for I in 0 to 3 loop -- I local !

F(I) <= A(I) and B(3-I);
V := V xor A(I);
end loop;

I := not I;
end process;

18. MULTIPLE COPY -------------------------

process (A, B)
variable V: Std_logic;

begin
V := '0';

for I in 0 to 3 loop
F(I) <= A(I) and B(3-I);
V := V xor A(I);
end loop;

G <= V;
end process;

vhdl_ex 8
19. LOOP ---------------------------------------
loop
...
exit;
...
exit when CONDITION;
...
end loop;

20. EXIT Label WHEN -----------------------

L1: for I in 0 to 7 loop
L2: for J in 0 to 7 loop
C := C + 1;
exit L2 when A(J) = B(I); -- label shows which loop exit !
exit L1 when B(C) = 'U';
end loop L2;
end loop L1;

21. ----------------------------------------------
Main: for I in 0 to 15 loop
...
next Main when Reset = '0'; -- jmp to begin !
...
end loop Main;

22. TEST BENCH CLOCK -------------------

ClockGenerator_1: process

begin
for I in 1 to 1000 loop -- eqv: while NOW < 15 US
Clock <= '0';
wait for 5 NS;
Clock <= '1';
wait for 10 NS;
end loop;

wait;
end process ClockGenerator_1;

23. ----------------------------------------------
ClockGenerator_3: process

begin
loop
Clock <= '0';
wait for 5 NS;
Clock <= '1';
wait for 10 NS;
exit when NOW >= 15 US;
end loop;

wait;
end process ClockGenerator_3;

vhdl_ex 9
24. -----------------------------------------------
process (A, B, C, D) -- priority coder ?
variable V: Std_logic_vector(3 downto 0);

begin
V(3) := A;
V(2) := B;
V(1) := C;
V(0) := D;
F <= 0;

for I in 0 to 3 loop
if V(I) = '1' then
F <= I;
exit;
end if;
end loop;

end process;

25. ------------------------------------------------
architecture V2 of AOI is
signal AB, CD, O: STD_LOGIC;

begin
AB <= A and B after 2 NS; -- event asign !
CD <= C and D after 2 NS;
O <= AB or CD after 2 NS;
F <= not O after 1 NS;
end V2;

26. -----------------------------------------------
process (A, B)

begin
AB <= A and B after 2 NS;
end process;

vhdl_ex 10
5. TYPES VHDL5

1. ENUMERATION TYPE --------------------

architecture V1 of Ent is
type Opcode is (Add, Neg, Load,
Store, Jmp, Halt);
signal S: Opcode;

begin
C1: Reg port map (..., S, ...);
C2: Ctl port map (..., S, ...);
end;

2. LOGIC TYPE --------------------------------

type BOOLEAN is (FALSE, TRUE);
type BIT is ('0', '1');
3. --------------------------------------------------
type STD_ULOGIC is
('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-'); -- X, 0, 1 – strong; W, L, H - weak

4. --------------------------------------------------
case IP is
when "00" =>
OP <= "0--1"; -- ‘-‘ (don’t care); optimization for outputs !
when "01" =>
OP <= "1-0-";
when "10" =>
OP <= "--10";
when others =>
OP <= "101-";
end case;

5. ---------------------------------------------------
case IP is
when "0--" => -- ‘-‘ no for inputs; exclusive inputs in case !
OP <= "00";
when "10-" =>
OP <= "01";
when "1-1" =>
OP <= "10";
when others =>
OP <= "11";
end case;

6. 3 STATE DRIVER --------------------------

signal BUSS: STD_LOGIC;

Tri1: process (ENB1, D1) -- 3 state driver

begin
if ENB1 = '1' then
BUSS <= D1;
else
BUSS <= 'Z'
end if;
end process;

Tri2: process (ENB2, D2)

…
end process;

vhdl_ex 11
7. RESOLVED ---------------------------------
function RESOLVED
(S: STD_ULOGIC_VECTOR)
return STD_ULOGIC;

subtype STD_LOGIC is -- ex.: …

RESOLVED STD_ULOGIC;

signal BUSS: STD_LOGIC;

8. INITIAL VALUES ----------------------------

signal CLOCK, RESET: STD_LOGIC; -- ‘U’ - implicit
variable V: STD_LOGIC_VECTOR(0 to 1); -- “UU”

9. ---------------------------------------------------
type Opcode is (Add, Neg, Load,
Store, Jmp, Halt);
signal S: Opcode := Halt; -- := initialisation - explicit
------------------------------------------------------
variable
V: Std_logic_vector(0 to 1) := "00";

10. CONSTATES ------------------------------

constant Active: Std_logic := '0'; -- := expression;
constant SIZE: INTEGER := 16;
constant
ZERO: STD_LOGIC_VECTOR := "0000"; -- range from initial value !

11. CONCATENARE --------------------------

signal
A, B: STD_LOGIC_VECTOR(7 downto 0);
signal
F: STD_LOGIC_VECTOR(15 downto 0);

F <= A & B; -- concat. vectors

F(15) <= A(7); F(8) <= A(0);
F(7) <= B(7); F(0) <= B(0);

12. -------------------------------------------------
signal A, B, C: STD_LOGIC;
signal F: STD_LOGIC_VECTOR(3 downto 0);

F(3 downto 0) <= (A & B) & C; -- F(3) = A; F(2) = B; F(1) = C; F(0) no chg

13. SHIFT & ROTATE -------------------- -- shift logic:sll, srl; arithm: sla, sra; rotate: rol, ror
signal

Reg: STD_LOGIC_VECTOR(7 downto 0);

Reg <= Reg(6 downto 0) & ‘0’; -- shift left eqv. Reg <= Reg sll 1;
Reg <= Reg(6 downto 0) & Reg(7); -- rotate left eqv. Reg <= Reg rol 1;

vhdl_ex 12
14. OVERLOADING --------------------------
library IEEE, COMPASS_LIB;
use IEEE.STD_LOGIC_1164.all;
use COMPASS_LIB.COMPASS.all; -- op ‘+’ – def. implicit for sum integer
not for sum vector !
entity ADDER is
port(A, B: in
STD_LOGIC_VECTOR(7 downto 0);
SUM: out
STD_LOGIC_VECTOR(7 downto 0));
end;

architecture A1 of ADDER is

begin
SUM <= A + B; -- ok sum vector !
end;

15. -------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all; -- sum +

entity ADDER is
port(A, B: in UNSIGNED(7 downto 0);
SUM: out UNSIGNED(7 downto 0));
end;

architecture A1 of ADDER is

begin
SUM <= A + B; -- ok sum vector !
end;

16. CONVERSION FUNCT ------------------

use IEEE.NUMERIC_STD.all;
...
signal A: Unsigned(7 downto 0);
signal F: Unsigned(2 downto 0);
...
Priority_encoder: process (A) -- Priority encoder
begin
F <= "000";
for I in 7 downto 0 loop -- I integer
if A(I) = '1' then
F <= To_unsigned(I, 3); -- ok; F <= I; illegal asign (vector – int)
exit; -- explicit conversion funct
end if;
end loop;
end process;

17. -----------------------------------------------
use IEEE.NUMERIC_STD.all;
...
signal A: Unsigned(7 downto 0);
signal S: Unsigned(2 downto 0);
signal G: Std_logic;
...
Mux: G <= A(To_integer(S)); -- A(I), I – integer; explicit conversion funct

vhdl_ex 13
6. CLOCKS & REGISTERS VHDL6

1. --------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity LATCH is
port (ENB, D: in STD_LOGIC;
Q: out STD_LOGIC);
end;

architecture BEHAVIOUR of LATCH is

begin
process (ENB, D)
begin
if ENB = '1' then
Q <= D;
end if;
end process;
end;

2. ---------------------------------------------------
process (Clock)
begin
if Clock'EVENT and Clock = '1' then
Q <= D;
…
end if;
end process;

3. ---------------------------------------------------
process (Clock)
begin
if RISING_EDGE(Clock) then
Q <= D;
end if;
end process;

4. ---------------------------------------------------
...
signal Count :
STD_LOGIC_VECTOR(7 downto 0);

begin
process (Clock, Reset)
begin
if Reset = '0' then
Count <= "00000000";
elsif RISING_EDGE(Clock) then
if Load = '1' then
Count <= Data;
else
Count <= Count + '1';
end if;
end if;
end process;

vhdl_ex 14
5. ---------------------------------------------------
architecture A1 of Block1 is
...
component GlobalResetBuffer
port (Pin: out Std_logic);
end component;

signal Reset: Std_logic;

begin
G: GlobalResetBuffer
port map (Reset);

process (Clock, Reset)

begin
if Reset = '0' then
Q <= '0';
elsif RISING_EDGE(Clock) then
Q <= Data;
end if;
end process;

6. ---------------------------------------------------
process (Clock)
begin
if RISING_EDGE(Clock) then
if Reset = '1' then
Q <= '0';
elsif Enable = '1' then
Q <= Data;
end if;
end if;
end process;

7. ---------------------------------------------------
process (Clock)
begin
if RISING_EDGE(Clock) then
if Enable = '1' then
if Reset = '1' then
Q <= '0';
else
Q <= Data;
end if;
end if;
end if;
end process;

8. ---------------------------------------------------
Another_Flipflop: process
begin
wait until Clock = '1';
if Reset = '1' then
Q <= '0';
else
Q <= D;
end if;
end process;

vhdl_ex 15
9. ---------------------------------------------------
Another_Flipflop: process
begin
wait until RISING_EDGE(Clock);

if Reset = '1' then

Q <= '0';
else
Q <= D;
end if;
end process;

10. ---------------------------------------------------
T1: process (All_Inputs)
begin

... Pure combinational logic

end process;

11. ---------------------------------------------------
T2: process (All_Inputs)
begin
if Enable = '1' then

... Transparent latches + logic

end if;
end process;

12. ---------------------------------------------------
T3: process (Clock)
begin
if RISING_EDGE(Clock) then

... Flipflops + logic

end if;
end process;

13. ---------------------------------------------------
T4: process
begin
wait until RISING_EDGE(Clock);

... Flipflops + logic

end process;

14. ---------------------------------------------------
T5: process (Clock, Reset)
begin
if Reset = '0' then
... Asynchronous actions

elsif RISING_EDGE(Clock) then

... Flipflops + logic

end if;
end process;

vhdl_ex 16
15. ---------------------------------------------------
signal Acc, Delta:
... STD_LOGIC_VECTOR(11 downto 0);

process
variable Up: STD_LOGIC;
variable nextA:
STD_LOGIC_VECTOR(11 downto 0);
begin
wait until RISING_EDGE(Clock);

if Up = '1' then
nextA := Acc + Delta;
if nextA >= Max then
Up := '0';
end if;
else
nextA := Acc - Delta;
if nextA < 0 then
Up := '1';
end if;
end if;

Acc <= nextA;

end process;

16. ---------------------------------------------------
signal Reg: STD_LOGIC;
...
AND_REG: process
variable V: STD_LOGIC;
begin
wait until RISING_EDGE(Clock);

V := '1';
for I in 0 to 7 loop
V := V and Input(I);
end loop;

Reg <= V;
end process;

17. ---------------------------------------------------
Counter: process
variable Count:
STD_LOGIC_VECTOR(7 downto 0);
begin
wait until RISING_EDGE(Clock);

if Reset = '0' then

Count := "00000000";
else
Count := Count + '1';
end if;

Output <= Count(7);

end process;

vhdl_ex 17
18. ---------------------------------------------------
process
begin
wait until RISING_EDGE(Clock);
Q <= Data;
QB <= not Data;
end process;

19. ---------------------------------------------------
process
begin
wait until RISING_EDGE(Clock);
Q <= Data;
end process;

QB <= not Q;

20. ---------------------------------------------------
port (...UpOut: out STD_LOGIC);
...
process
begin
wait until RISING_EDGE(Clock);

if UpOut = '1' then

...
UpOut <= '0';
else
...
UpOut <= '1';
end if;
end process;

21. ---------------------------------------------------
port (...UpOut: out STD_LOGIC);
...
process
variable Up: STD_LOGIC;
begin
wait until RISING_EDGE(Clock);

if Up = '1' then
...
Up := '0';
else
...
Up := '1';
end if;

UpOut <= Up;

end process;

vhdl_ex 18
22. ---------------------------------------------------
port (... UpOut: out STD_LOGIC);
...
signal Up: STD_LOGIC;
...
begin
process
begin
wait until RISING_EDGE(Clock);

if Up = '1' then
...
Up <= '0';
else
...
Up <= '1';
end if;
end process;

UpOut <= Up;

23. ---------------------------------------------------
port (...UpOut: buffer STD_LOGIC);
...
process
begin
wait until RISING_EDGE(Clock);

if UpOut = '1' then

...
UpOut <= '0';
else
...
UpOut <= '1';
end if;
end process;

vhdl_ex 19
7. FINITE STATE MACHINES VHDL7

1. --------------------------------------------------
library IEEE;
use IEEE.Std_logic_1164.all;

entity FSM is
port (Clock, Reset: in Std_logic;
F, G: out Std_logic);
end;

architecture Explicit of FSM is

begin
process
...
begin
wait until RISING_EDGE(Clock);
…
end process;
end;

2. ---------------------------------------------------
architecture Explicit of FSM is

begin
process
type StateType is (Idle, Start, Stop, Clear);
variable State: StateType;
begin
wait until RISING_EDGE(Clock);

if Reset = '1' then

State := Idle; F <= '0'; G <= '1';
else
case State is
when Idle => State := Start; G <= '0';
when Start => State := Stop;
when Stop => State := Clear; F <= '1';
when Clear => State := Idle; F <= '0';G <= '1';
end case;
end if;
end process;
end;

vhdl_ex 20
3. ---------------------------------------------------
architecture SeparateDecoding of FSM is
type StateType is (Idle, Start, Stop, Clear);
signal State: StateType;

begin
Change_state: process
begin
wait until RISING_EDGE(Clock);

if State = Clear or Reset = '1' then

State <= Idle;
elsif State = Idle then State <= Start;
elsif State = Start then State <= Stop;
else State <= Clear;
end if;
end process;

Output: process (State)

begin
F <= '0'; G <= '0';
if State = Clear then F <= '1';
elsif State = Idle then G <= '1';
end if;
end process;
end;

4. --------------------------------------------------
architecture RegistersPlusLogic of FSM is
type StateType is (Idle, Start, Stop, Clear);
signal State, NextState: StateType;

begin
Registers: process
begin
wait until RISING_EDGE(Clock);

if Reset = '0' then

State <= Idle;
else
State <= NextState;
end if;
end process;

C_logic: process (State)

begin
if State = Clear then NextState <= Idle;
F <= '1';
elsif State = Idle then NextState <= Start;
G <= '1';
elsif State = Start then NextState <= Stop;
else NextState <= Clear;
end if;
end process;
end;

vhdl_ex 21
5. --------------------------------------------------
architecture NoDecoding of AnotherFSM is
constant Idle: STD_LOGIC_VECTOR := "11";
constant Start: STD_LOGIC_VECTOR := "01";
constant Stop: STD_LOGIC_VECTOR := "10";
constant Clear: STD_LOGIC_VECTOR := "00";
signal State: STD_LOGIC_VECTOR(1 downto 0);

begin
process
begin
wait until RISING_EDGE(Clock);

if Reset = '0' then State <= Idle;

else
case State is
when Idle => State <= Start;
when Start => State <= Stop;
when Stop => State <= Clear;
when Clear => State <= Idle;
when others => State <= Idle;
end case;
end if;
end process;

P <= State(1);
Q <= State(0);
end;

6. --------------------------------------------------
type StateType is
(Idle, Start, Stop, Clear);
signal State: StateType;

-- Synthesis tool specific attribute...

attribute ENUM_ENCODING: STRING;

attribute ENUM_ENCODING of StateType:
type is "000 100 010 001";

7. ---------------------------------------------------
type StateType is
(One, Two, Three, Four, Five);
signal State: StateType;

8. ---------------------------------------------------
type StateType is
(One, Two, Three, Four, Five,
Dummy1, Dummy2, Dummy3);

9. ---------------------------------------------------
signal Count:
STD_LOGIC_VECTOR(3 downto 0);
...
if Count = "1001" then
Count <= "0000";
else
Count <= Count + '1';
end if;

vhdl_ex 22