1

uFBN Base Tiansceivei Implementation

Release 1
Bocumentation
































Technische Universitt Dresden
Vodafone Chair Mobile Communications Systems
D-01062 Dresden


2




































Bocument title uFBN Base Tiansceivei Implementation Release 1 Documentation
Bate 31.03.2014
Authoi Ainoa Navaiio Caluevilla
Contiibutois Nicola Nichailow, Ivan Simes uaspai, Naximilian Natthe,
Bi. Luciano Nenues, Bi. Anuieas Festag
Contact Email: Sgtestbeuifn.et.tuuiesuen.ue




3

Table of Contents
Table of Figures ...................................................................................................................................... 4
List of Tables ........................................................................................................................................... 4
Acronyms and Symbols ........................................................................................................................... 5
Summary ................................................................................................................................................. 6
License .................................................................................................................................................... 6
1 Motivation for GFDM ..................................................................................................................... 7
2 GFDM Transceiver Implementation Model .................................................................................... 8
2.1 Low Complexity Transmitter .................................................................................................. 8
2.1.1 Mathematical Model ........................................................................................................ 8
2.1.2 Implementation Model .................................................................................................... 9
2.2 Low Complexity Receiver ..................................................................................................... 10
2.2.1 Mathematical Model ...................................................................................................... 10
2.2.2 Implementation Model .................................................................................................. 10
3 LabVIEW Implementation ............................................................................................................ 11
3.1 Hardware Setup ..................................................................................................................... 11
3.2 Software Setup ...................................................................................................................... 11
3.3 Project Structure .................................................................................................................... 12
3.4 GFDM Transmitter ................................................................................................................ 15
3.4.1 Functionality .................................................................................................................. 15
3.4.2 Configuration (Host vi) ................................................................................................. 17
3.4.2.1 Top Level vi .............................................................................................................. 17
3.4.2.2 GUI ............................................................................................................................ 18
3.4.2.3 Top Level vi .............................................................................................................. 19
3.5 GFDM Receiver .................................................................................................................... 24
3.5.1 Functionality .................................................................................................................. 24
3.5.2 Configuration (Host vi) ................................................................................................. 24
3.5.2.1 Top Level vi .............................................................................................................. 24
3.5.2.2 GUI ............................................................................................................................ 25
3.5.3 FPGA vi ......................................................................................................................... 25
3.5.3.1 Top level vi ................................................................................................................ 25
4 References ..................................................................................................................................... 31



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Table of Figures
Figure 1: Hardware structure of the low complexity GFDM transmitter. ............................................... 9
Figure 2: Hardware structure of the low complexity GFDM receiver. ................................................. 10
Figure 3: NI PXI hardware setup. ......................................................................................................... 11
Figure 4: Overview software components displayed by NI MAX. ....................................................... 12
Figure 5: Folder structure of the GFDM LabVIEW project .................................................................. 12
Figure 6: GFDM transceiver project explorer overview. ...................................................................... 14
Figure 7: GFDM frame structure used in the basic implementation. .................................................... 15
Figure 8: Overview block diagram implementation basic GFDM transmitter. ..................................... 16
Figure 9: Overview GUI GFDM transmitter. ........................................................................................ 17
Figure 10: Data generation and filtering in frequency domain in the GFDM transmitter. .................... 19
Figure 11: GFDM block windowing in time domain in the GFDM transmitter. .................................. 21
Figure 12: Overview GUI GFDM receiver. .......................................................................................... 24
Figure 13: Overview block diagram of the GFDM receiver implementation. ...................................... 26
Figure 14: Block diagram for timing synchronization based on autocorrelation of the CP. ................. 27

List of Tables
Table 1: List of files required for the GFDM transmitter. ..................................................................... 13
Table 2: List of files required for the GFDM receiver. ......................................................................... 13
Table 3: Input parameters range for GFDM transmitter........................................................................ 18
Table 4: Verified modes for the GFDM transceiver.............................................................................. 18
Table 5: Input parameters range for GFDM receiver ............................................................................ 25



5
Acronyms and Symbols



Acronym Description
5GNOW 5
th
Generation Non-Orthogonal Waveforms for Asynchronous Signaling
ADC Analog Digital Converter
CoMP Coordinated Multipoint
CP Cyclic Prefix
DAC Digital Analog Converter
DFT Discrete Fourier Transform
F.D. Frequency Domain
FPGA Field Programmable Gate Array
FFT Fast Fourier Transform
GFDM Generalized Frequency Division Multiplexing
GUI Graphical User Interface
IDFT Inverse Discrete Fourier Transform
IFFT Inverse Fast Fourier Transform
LTE Long Term Evolution
LUT Look Up Table
M2M Machine to Machine
MAC Medium Access Control
MIMO Multiple Input Multiple Output
MTC Machine Type Communication
NI National Instruments
OFDM Orthogonal Frequency Division Multiplexing
PHY Physical Layer
PXI PCI eXtensions for Instrumentation
QAM Quadrature Amplitude Modulation
RF
RRC
Radio Frequency
Root-Raised-Cosine
SNR Signal-to-Noise Ratio
VI Virtual Instrument
T.D. Time Domain
Symbol Description
K Number of subcarriers
L Upsampling factor of pulse shaping filter
M Number of time domain slots or symbols
N Upsampling factor at output of transmitter


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Summary
This document describes the base implementation of the GFDM wireless transceiver chain. It covers
the implementation model of the GFDM transmitter and receiver, the hardware setup and software
installation and an overview of the GFDM transmitter and receiver implementation in NI LabVIEW
software.
The work is based on National Instruments (NI) hardware and software. The reader is expected to
have experiences with the NI LabVIEW software and to be familiar with the NI PXI hardware
platform.
The implementation described in the present document has been created as part of the NI Lead User
Program and the research project 5GNOW 5th Generation Non-Orthogonal Waveforms for
Asynchronous Signalling supported by the European commission in the 7th framework program
[5][6].

License
Copyright 2014 Vodafone Chair Mobile Communications Systems, TU Dresden

This documentation is part of GFDM Base Transceiver Implementation
GFDM Base Transceiver Implementation is free software: you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the Free Software Foundation,
either version 3 of the License, or (at your option) any later version.
GFDM Base Transceiver Implementation is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License along with GFDM Base
Transceiver Implementation. If not, see http://www.gnu.org/licenses/.




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1 Motivation for GFDM
Generalized frequency division multiplexing (GFDM) is a new physical layer modulation scheme for
wireless communication systems. It has been proposed as an alternative to Orthogonal Frequency
Division Multiplexing (OFDM) and as a candidate waveform to replace OFDM in future 5G cellular
systems [4]. GFDM aims at compensating for several shortcomings of OFDM, including strong
energy leakage, strict synchronization requirement and high peak-to-average power ratio.
From a high level perspective, GFDM builds on the OFDM concept, but adds signal processing to
both the transmit and receive chain in order to improve operational performance. For instance, by
effectively applying pulse shaping filters to each individual subcarrier, the out-of-band radiation can
be reduced and the efficiency of the power amplifier can be increased.
Further benefits of GFDM are:
- Filtering subcarriers allows the out of band radiation to be much lower than that of traditional
OFDM,
- Flexible frame structure of M time slots per K subcarriers,
- Ability to engineer waveform properties in both time and frequency through filtering and
windowing,
- Efficient use of a single cyclic prefix and/or suffix for multiple subsymbol blocks,
- Low complexity equalization in frequency domain,
- Applicable to framed and burst applications,
- Suitable for embedded training sequences defined in time or frequency domain.



8
2 GFDM Transceiver Implementation Model
This section provides the mathematical background that leads to the implemented GFDM transceiver.
More details on the theory behind GFDM as well as various other representations of the transmitter
and the receiver can be found in [1] and [2].
2.1 Low Complexity Transmitter
2.1.1 Mathematical Model
The GFDM multicarrier signal is built with K active subcarriers and M active time slots. Each
subcarrier is pulse shaped with a transmitter filter and modulated with a subcarrier frequency. Each
symbol is sampled N K times leading to a total of MN samples per subcarrier, which is necessary in
order to satisfy the Nyquist criterion. The transmit data signal is obtained through superposition of the
filtered data symbols of all subcarriers and time slots

1 1
2
Tx
0 0
[ ] [ ] ( [ ]mod )
k
M K
j n
N
k
m k
x n d m g n mN NM e
t

= =
=
, (1)
where [ ]
k
d m are complex valued data symbols,
Tx
( [ ]mod ) g n mN NM is a circular pulse shaping
filter based on a prototype filter [ ]
Tx
g n and
2
n
j k
N
e
t
denotes subcarrier up-conversion. Note that the
filter response is cyclic with an interval of MN samples, and can be also written as a circular
convolution operation. In time domain the number of complex valued multiplications necessary to
produce this result is
2
GFDM
C NKM = . From a hardware perspective, a straightforward
implementation of the model described in (1) is not suitable for practical uses.
The solution comes from reformulating the GFDM transmitter into a form that is similar to the well-
known IFFT/FFT approach used in OFDM:
| |
2
Tx
[ ] [ ] [ ] [ ]
j n
N
NM k NM N
k
M
k m
NM
x n IDFT d m n mN DFT g n e DFT DFT
t
o
| | (
(
=
|
(
(
|

\ .

(2)
where DFT
NM
is the NM-point discrete Fourier transform and IDFT
NM
represents the corresponding
inverse operation.
Now the left side product [ ) ] [ ] (
NM k
m FT d n D mN o represents the Fourier transform of the up-
sampled data symbols. Up-sampling in time domain leads to a spectrum repetition pattern of the
samples in frequency domain. Thus the result can be equally produced by copying the values of the
( [ ) ]
M k
DFT d m M point DFT, instead of actually performing arithmetic operations necessary for an
NM point DFT. As the DFT is an operation with periodic inputs and periodic outputs, it is possible to
achieve further computational savings when the periodicity of the time domain signal is maintained
during the filtering operation. In that case the pulse shaping filter from eq. (1) turns into a regular
multiplication in frequency domain in eq. (2).
Also, since the aim of pulse shaping is to keep out-of-band radiation minimal, the utilized pulse may
turn out to be sparse in frequency domain, i.e. many of the coefficients can be zero and thus
multiplications do not need to be carried out. Consequently, in general, the filter pulse spans over only
its immediately neighboring subcarriers in frequency domain. This derives from the fact that,


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depending on the roll-off factor, a bandwidth of an ideal RRC pulse is between 1/T and 2/T, where T
is the duration of each time slot.
Lastly, the DFT of a sinusoid corresponds to Dirac impulse in frequency domain and the convolution
with it results in a simple position shift. Consequently, the subcarrier up-conversion can be
implemented by realigning the samples in frequency domain. The operations listed above lead to the
following implementation model.
2.1.2 Implementation Model
The operations can basically be executed in a pipeline structure that sequentially processes N chunks
of M samples, processing and combining them in a tapped delay line. Figure 1 illustrates how a set of
3 subcarriers (labeled as waveforms M1 to M3) can be processed in a sequential manner.

Figuie 1: Baiuwaie stiuctuie of the low complexity uFBN tiansmittei.
The M-points spectrum of the subcarriers data is repeated and shaped by the coefficients of the
transmitter. The 2-stage pipeline structure performs the filtering process per subcarrier in the
frequency domain, by separating the filter into two parts. In the first stage of the pipeline, the current
active subcarrier, k, is filtered by the first half of the pulse shape, by means of doing an M-point
complex multiplication. In parallel the previous (k-1)
th
subcarrier is filtered with the second half of the
pulse shape. The filter coefficients of the pulse are saved in look up-tables (LUTs) for both filter
halves. In the sequence both sequences will be added to build the overlapped half spectrum of the k
th

subcarrier with the (k-1)
th
active subcarrier. Non-active subcarriers are basically obtained by nulling
the data in the input.
By using this structure, the output of the adder represents the natural order of the modulated
subcarriers in the spectrum. The expected hardware costs for implementing the oversampling, filtering
process and up-conversion to the subcarrier frequency is 2 parallel structures of M-point complex
multiplications, M-point delay memory chains and M-point complex additions.
Doing this process for K subcarriers, at the output of the adder a KM-point sequence in frequency
domain is set up. In the next step this sequence will be transformed into the time domain by an IFFT
of NM points.


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2.2 Low Complexity Receiver
2.2.1 Mathematical Model
The approach is similar to the transmitter. The matched filtered version of the GFDM receiver follows
the structure of the GFDM transmitter. For a received signal y[n], the data on the k-th subcarrier can
be obtained according to
| |
2

[ ] [ ] [ ]
k
j n
N
k NM NM Rx NM
n mN
d m I n e DFT DFT g D y n FT
t
=
( (
=
( (
(

, (3)
under the assumption of perfect synchronization and equalization. Again, the operations are performed
in frequency domain. In (3), | | [ ]
NM
D T y n F denotes the discrete Fourier transform of the received
samples and
2
[ ]
k
j n
N
NM Rx
n D e FT g
t (
(

is the discrete Fourier transform of the frequency shifted
version of the receiver matched filter. Finally, the outcome of the IDFT is decimated, in order to get
the data symbols

[ ]
k
d m .
2.2.2 Implementation Model
Based on the equations above, the block diagram in Figure 2 is developed by using the same
simplifications as in the transmitter. Again, only adjacent subcarriers are considered to overlap. The
transmitter receives M input symbols per subcarrier based on sequential samples and a domain
conversion is obtained by reusing a single DFT component. The spectrum repetition basically consists
of a memory block of M positions. The pulse shaping process is performed using a single multiplier
with coefficients provided by LUTs. Each LUT contains half of the transfer function of the filter,
denoted by falling and rising edge. The up-conversion of the pulse shaped subcarriers is naturally
obtained with the sequential sum of the samples in transmitter chain and finally converted to time
domain by employing an inverse DFT with H points.

Figuie 2: Baiuwaie stiuctuie of the low complexity uFBN ieceivei.


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3 LabVIEW Implementation
3.1 Hardware Setup
The hardware platform for running the GFDM transceiver chain is shown in Figure 3. It consists of
two NI PXI chassis 1082 with the following plug-in hardware modules each:
- NI-8133 embedded controller running Microsoft Windows and LabVIEW 2012.
- NI-7965R FPGA module,
- NI-5791 RF adapter module.

Figuie S: NI PXI haiuwaie setup.
3.2 Software Setup
For running the demonstration, a PXI with the NI-8133 embedded controller running National
Instruments, Microsoft Windows 7 (32 bits) Factory Image 1.2.2f0 and LabVIEW 2012 are required.
It is necessary to install the driver for the NI-5791. If it is required to compile the VHDL code for
software execution in another FPGA module, then additional toolkits, as presented in Figure 4, need to
be installed as well.



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Figuie 4: 0veiview softwaie components uisplayeu by NI NAX.
3.3 Project Structure
The LabVIEW project called GFDM_Transceiver must be unzipped and copied to the hard disk in the
both PXIs. Some required configuration files are inside the project under the folder UserData. Copy its
content to C:\UserData before running the demonstration.

Figure 5: Folder structure of the GFDM LabVIEW project.
Figure 5 depicts the folder structure of the LabVIEW Project. The top level folders are listed below:
- FPGA: required FPGA VIs for the GFDM transmitter.
o FFT_xilinx: IP integration node support files.
- FPGA Bit files: FPGA bit files for both transmitter and receiver.
- FPGA2: required FPGA VIs for the GFDM receiver.
o gfdm_rx2: IP integration node support files.
- Gui_backgrounds: background .png files for the Host or GUI VIs.
- RT: host vis for both transmitter and receiver.


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SubVIs_5791: required subvis to configure the RF module 5791.
Table 1 lists the required configuration files for the GFDM transmitter, while Table 2 shows the
necessary files to execute the GFDM receiver.
Table 1: List of files iequiieu foi the uFBN tiansmittei.
Required files for GFDM transmitter
I_preamble_data32x8_1.txt
Q_preamble_data32x8_1.txt
I_preamble_data64x8_1.txt
Q_preamble_data64x8_1.txt
I_preamble_data128x8_1.txt
Q_preamble_data128x8_1.txt
I_preamble_data256x8_1.txt
Q_preamble_data256x8_1.txt
I_preambleSym_resampler_32x8.txt
Q_preambleSym_resampler_32x8.txt
I_preambleSym_resampler_64x8.txt
Q_preambleSym_resampler_64x8.txt
I_preambleSym_resampler_128x8.txt
Q_preambleSym_resampler_128x8.txt
I_preambleSym_resampler_256x8.txt
Q_preambleSym_resampler_256x8.txt
carrier_selector_32.txt
carrier_selector_64.txt
carrier_selector_128.txt
carrier_selector_256.txt
I_window_32x8.txt
Q_window_32x8.txt
I_window_64x8.txt
Q_window_64x8.txt
I_window_128x8.txt
Q_window_128x8.txt
I_window_256x8.txt
Q_window_256x8.txt
filter_re0.txt
filter_im.txt

Table 2 List of files iequiieu foi the uFBN ieceivei.
Required files for GFDM receiver
filter_re0.txt
filter_im.txt
I_pre_inv_32x8_1.txt
Q_pre_inv_32x8_1.txt
I_pre_inv_64x8_1.txt
Q_pre_inv_64x8_1.txt
I_pre_inv_128x8_1.txt
Q_pre_inv_128x8_1.txt
I_pre_inv_256x8_1.txt
Q_pre_inv_256x8_1.txt



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Figure 6 depicts the project structure that can be seen by opening the project file
GFDM_Transceiver.lvproj.

Figuie 6: uFBN tiansceivei pioject exploiei oveiview.
Two FPGA target devices are attached in the project. The first one is used for the transmitter and the
second for the receiver. These FPGA targets are configured as FPGA reference RIO3 and RIO2,
respectively. It is important to observe how the FPGA modules are connected to the PXI by having a
look at the NI MAX parameter and adapt the FPGA ref on the host VI, if necessary.
The main transmitter VIs are listed below:
- Host (top level) VI: RT_GFDM_TX.vi required to execute the GFDM transmitter,
- FPGA VI: gfdm_tx_configurableFFT.vi,
- Bit file: gfdm_tx_configurableFFT_1903.lvbitx.
The main receiver VIs are listed below:
- Host (top level) VI: RT_GFDM_RX.vi required to execute the GFDM receiver,
- FGPA VI: gfdm_rx.vi,
- Bit file: gfdm_rx_1903.lvbitx.


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3.4 GFDM Transmitter
3.4.1 Functionality
The transmitter generates a stream of GFDM blocks for different number of subcarriers (K) and
number of sub-symbols per subcarrier (M). The use of pulse shaping filters for this type of modulation
is allowed through a flexible interface between the Host computer and the FPGA which concede the
possibility to load dynamically different types of filters. This kind of filtering process can be applied
both at sub-subcarrier level and at GFDM frame level (windowing in time domain). An adjustable
occupancy of the spectrum through the used carrier pattern on-run-time parameter makes its use
attractive for testing this new modulation scheme in scenarios where coexistence with other legacy
systems must be proved. The use of cyclic prefix samples to combat multipath and for synchronization
objectives at the receiver side was implemented. As a result, the following frame structure is sent
(Figure 7):

Figuie 7: uFBN fiame stiuctuie useu in the basic implementation.
The cyclic prefix samples are used for synchronization at the receiver by performing an
autocorrelation algorithm. The preamble sequence is GFDM modulated and it is known at the receiver
so that it is easy to estimate the channel. In order to distinguish the autocorrelation peaks of the
preamble and the data, they are sent with half of the power, respectively.
In the Figure 8 an overview of the implemented features in the basic GFDM transmitter represented.




16


Figuie 8: 0veiview block uiagiam implementation basic uFBN tiansmittei.
In the next section a detailed explanation of the individual blocks is presented.


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3.4.2 Configuration (Host vi)
3.4.2.1 Top Level vi
In the top level vi, the GFDM transmitter can be configured. For starting the GFDM transmitter press
Run.

Figuie 9: 0veiview u0I uFBN tiansmittei.
After pressing the button Configuration settings a popup window appears with information about how
to configure the demonstration. After this, another popup window with the configuration of the GFDM
transmitter is shown. The configuration is divided in two parts: the basic mode, which is
recommended for the default demonstration mode, and the advanced mode, where it is possible to
change more parameters. In the basic mode, the following default parameters are configured:
M: Number the sub-symbols per subcarrier,
K: Number of subcarriers,
Output power: At the transmitter side, we choose the maximum power, 20 dBm,
Carrier frequency: from 200 MHz to 4.4 GHz,
Operation mode:
Fixed Preamble & Data (FPGA): In this mode, a fixed pattern of preamble and data
are passed into an FPGA memory and will be modulated by the GFDM chain in the
FPGA,
Arbitrary Preamble & Random Data: In this mode, it is possible to pre-compute an
arbitrary preamble and introduce it directly to the fractional re-sampler loop. As a data
block, random QAM symbols will be generated in the FPGA and modulated by the
GFDM chain,
Fixed Preamble & Random Data: In this mode, a fixed pattern of preamble is loaded
into an FPGA memory and modulated by the GFDM chain. The data is randomly
generated in the FPGA and as well modulated by the GFDM structure.


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Table 3: Input parameters range for GFDM transmitter
Parameter Range Default value
M 8128
1
8
K 8(2048/M)
1
256
Output power -100dBm...20dBm
2
20dBm
Carrier frequency 200MHz4.4GHz 2.437GHz
1
Please note that only the combinations for K and M as listed in Table 4 are supported by the available configuration files.
Other combinations are possible but new configuration files (for data, preamble and filter coefficients) have to be generated.
2
The lower limit is only assumed, since it is not documented in the hardware specification of NI-5791.

Table 4 lists the modes that were verified in the chain.
Table 4: veiifieu moues foi the uFBN tiansceivei.
KxM Setup Transmission mode
32x8 Fixed Preamble & Data (FPGA)
32x8 Arbitrary Preamble & Random Data
32x8 Fixed Preamble & Random Data
64x8 Fixed Preamble & Data (FPGA)
64x8 Arbitrary Preamble & Random Data
64x8 Fixed Preamble & Random Data
128x8 Fixed Preamble & Data (FPGA)
128x8 Arbitrary Preamble & Random Data
128x8 Fixed Preamble & Random Data
256x8 Fixed Preamble & Data (FPGA)
256x8 Arbitrary Preamble & Random Data
256x8 Fixed Preamble & Random Data

3.4.2.2 GUI
The GUI is organized as follows.
In the left part, the configuration button with an overview table about the configured parameters is
located. On the left-bottom part three interacting buttons are available:
Bypass filtering in the time domain: It is possible to bypass the windowing process in time
domain for controlling out of band leakage in case of transmission of cyclic prefix samples.
First symbol zero: In this version this button is disabled but it can be used to null the first sub-
symbol for all subcarriers, which has the effect to create soft transitions between concatenated
GFDM blocks in the case of transmission without cyclic prefix.
Stop: To stop the application.
On the right part, some graphs indicators are shown:
Power spectrum: Power spectrum of the transmitted signal.
Carrier selector buttons: For turning on/off subcarriers in the transmitted spectrum. It is
possible to turn off all subcarriers (empty button), to turn on all subcarriers (full button), to
have a random pattern of sent subcarriers (random button). For loading the chosen pattern
press Load carrier Selector button.


19
FPGA throughput: It is a measurement of the throughput at the output of the IFFT in the
FPGA (number IQ symbols per second).
GFDM symbol in time domain: Representation in time domain of the sent data.
Pulse shaping filter: Current pulse shaping filter at subcarrier level.
Rate: Configuration of the sampling rate for the GFDM time domain signal. It directly
corresponds to the required bandwidth of the transmitted signal, if all subcarriers are occupied.
FPGA vis
3.4.2.3 Top Level vi
The top level vi is organized in different timed loop structures described in the following section.
Every timed loop consists of different functional blocks and sub vis. For the sake of clarity a different
format is used to indicated timed loops, functional blocks and sub vis. Note that the names of the
loops and functional blocks are annotated in the block diagrams of the top-level VI and can thus
directly be related.
Signal Processing in frequency domain loop (100 MHz):
The GFDM multicarrier signal is built with K active subcarriers and M active time slots. For
every subcarrier modulated QAM symbols are generated and then transformed into the
frequency domain by a Fast Fourier Transform of M points. Each sub-carrier is pulse shaped
with a transmitter filter.
As an input data for the GFDM transmitter, three different modes are supported:
Pattern IQ: In this mode a pattern of modulated IQ samples are written in a file that
will be load in the host vi and downloaded to a memory on the FPGA.
Random IQ: The FPGA generates random bits that will be mapped into QAM
symbols.
Hybrid mode: It is a mixture of both pattern IQ and random mode, alternating
between adjacent GFDM symbols.

Figuie 1u: Bata geneiation anu filteiing in fiequency uomain in the uFBN tiansmittei.
Subvis and functional blocks:
Symbol generator functional block:
It generates random bits that will be mapped into 4QAM, 16QAM, 64QAM symbols.
Input parameters:
- PN Config: Configuration for the random bit generator,
- Constellation: Type of constellation (4QAM, 16QAM, 64QAM),


20
- Loop Size (K*M) Pre: Number of samples to be read in the case of sending data from
the memory LUT IQ,
- Loop Size (K*M) Data: Number of samples to be generated by the QAM generator,
- Random input data: This signal is asserted for generating random QAM symbols as
input data for the transmitter chain. If it is false, data from the memory LUT IQ data
will be transmit,
- Hybrid mode: If this signal is true, both random data from the QAM generator and
data from the memory LUT IQ will be sent through the GFDM chain. If this is false,
the parameter Random input data indicates the type of source data for the GFMD
chain.
Output parameters:
- Modulated QAM symbols.

FFT (M) vi:
It performs an M-point direct Fourier Transform of the input data by using the Xilinx IP core.
The core is configured in streaming mode and with scaled fixed point option for the arithmetic
operations. Clock enable signaling is activated to stop the core in case of underflow at the
input FIFO.
Input parameters:
- Start: FFT start signal which is asserted to begin the data loading and transform
calculation,
- Real input: In phase component of the input signal,
- Imaginary input: In quadrature component of the input signal,
- CE: Clock enable to start/stop the core,
- Forward or inverse FFT: Control signal that indicates if a forward FFT or an
inverse FFT is performed (fwd_inv),
- Setup WE: Asserts the FFT signals nfft_we and fwd_inv_we, which are write enable
signals for nfft and fwd_inv respectively.
- NIfft: Number of FFT samples (nfft)
Output parameters:
- Real Output: In phase component of the output signal,
- Imaginary Output: In quadrature component of the output signal,
- DV: Indicates a valid output data,
- Ready for data: This signal is high during the load operation of the input data.

Filtering frequency domain vi:
It performs the 2-stage pipeline structure for the filtering of the GFDM subcarriers. It is based
on two complex high throughput multipliers, two high throughputs adders, a discrete delay
chain and two look up tables for the filter coefficients.
Input parameters:
- Done fft: For debugging purposes,
- I: In phase component of the input signal,
- Q: In quadrature component of the input signal,
- DV fft: Indicates a valid input data,
- M-1: Length of the delay chain.
Output parameters:
- IQ: Concatenated I(upper I16) and Q(lowerI16) samples as an U32 value,


21
- Output valid: Indicates a valid output data.

Signal Processing in time domain loop (100 MHz):
Up to this point the GFDM spectrum was build. An inverse Fourier transform of KxM
samples is required to transform the signal into the time domain. In order to prevent inter-
symbol interference after the IFFT, cyclic prefix samples are introduced. This can produce
some discontinuities between concatenated GFDM blocks which lead to high out of band
leakage spectrum. For improving this, a windowing of the whole GFDM block is applied in
time domain. The hardware structure is the same like the one for the subcarrier filtering,
described in the previous section. It is possible to bypass this process.



Figuie 11: uFBN block winuowing in time uomain in the uFBN tiansmittei.
Subvis and functional blocks:
IFFT vi:
It performs a KxM-point inverse Fourier Transform of the input data by using the Xilinx IP
core. The core is configured in streaming mode and with run-time adjusted scaling (block
floating-point) for the arithmetic operations. Clock enable signaling is activated to stop the
core in case of underflow at the input FIFO.
Input parameters:
- NIfft: Number of FFT samples (nfft),
- IQ Input: Concatenated I(upper I16) and Q( lower I16) samples as an U32 value,
- Start: FFT start signal which is asserted to begin the data loading and transform
calculation,
- CE: Clock enable signal to start/stop the core,
- Forward or Inverse FFT: control signal that indicates if a forward FFT or an inverse
FFT is performed (fwd_inv),
- Setup WE: asserts the FFT signals nfft_we and fwd_inv_we which are write enable
signals for nfft and fwd_inv respectively.
Output parameters:


22
- Real Output: In phase component of the output signal,
- Imaginary Output: In quadrature component of the output signal,
- DV: Indicates a valid output data,
- Ready for data: This signal is high during the load operation of the input data,
- Blk_exp: The amount of scaling applied by the core. (0utput 2
BIk_cxp
).

FFT shift vi:
It rearranges the output of the iFFT by moving the zero-frequency component to the center of
the array. It is applied at the output of the iFFT (i.e., in the time domain) by negating every
second sample in the array. This equivalent method is better suited for realization in hardware.
Input parameters:
- I: In phase component of the input signal,
- Q: In quadrature component of the input signal,
- DV ifft in: Indicates a valid input data.
Output parameters:
- IQ: Concatenated I(upper I16) and Q( lower I16) samples as an U32 value,
- DV ifft out: Indicates a valid output data.

Windowing in time domain vi:
It performs a windowing over the whole GFDM block including the cyclic prefix samples.
This vi has a similar structure like the filtering vi in frequency domain explained in the
previous section. A slight difference can be found in the realization of the discrete delay chain.
In this case a block RAM memory was used with different pointer address for writing and
reading data.
Input parameters:
- K*M+CP: Length of the window,
- Done: ifft signal for debugging purposes,
- IQ: Concatenated I(upper I16) and Q(lower I16) samples as an U32 value,
- Dv ifft: Indicates a valid input data,
- Edone: ifft signal for debugging purposes,
- notStopRFD: ifft signal for controlling address counter of the filter coefficients LUT.
Output parameters:
- Edone delayed: For debugging purposes,
- I: In phase component of the output signal,
- Q: In quadrature component of the output signal,
- OV: Indicates a valid output data.
Debug Interface vi:
This vi writes samples to an internal memory on the FPGA that will be later read by a Host
DMA FIFO.
Input parameters:
- Dump start: It is asserted to start the vi,
- Synch event: This signal synchronizes the input stream that will be written in the
memory to allow a block-wise transfer to the Host, i.e., always beginning with first
sample of a block,
- I: In phase component of the input signal,
- Q: In quadrature component of the input signal,
- DV: Indicates a valid input data,


23
- Source: Indicates the intermediate memory on the FPGA, where the data will be
stored.
Output parameters:
- Stop: Indicates when the vi has finished writing samples on the memory.

Multiplexing different data sources at the input of the fractional re-sampler loop
(100 MHz):
Similar to the three supported modes as input data for the GFDM transmitter, three modes are
supported here as input data for the fractional re-sampler:
IQ from FPGA: In this case the input at the re-sampler is the GFDM signal generated
in the FPGA (explained in the previous section),
IQ from external: A GFDM block defined in time domain is written directly through
the host into an FPGA memory. This is useful and flexible for introducing different
preamble schemes in the transmission, for channel estimation and synchronization
purposes,
Hybrid mode which is a combination of both modes.

Rate conversion loop (130 MHz):
In this loop the rate of the input data is converted to 130 MHz rate for the DAC by using the
fractional interpolator from the NI-5791 library. Additionally the IQ impairments are
compensated with a vi from the library.

5791 Configuration loop (40 MHz):
This is the standard configuration of the RF front end.

Config interface from host to FPGA loop (100 MHz):
This loop is used for configuring look up tables on the FGPA.

Debug interface from FPGA to host:
It passes data from the FPGA to the host via DMAs for debugging purposes.
Adjust gain control capabilities take place in the configuration vi from the library of the NI-5791 at the
host, by adjusting an input/output (rx/tx) power in the host vi.



24
3.5 GFDM Receiver
3.5.1 Functionality
The GFDM receiver prototype demodulates a stream of GFDM blocks for different configurations of
subcarriers (K) and sub-symbols per subcarrier (M). A non-synchronized scenario of both TX and RX
PXIs is allowed by utilizing a closed-loop tracking mechanism for timing synchronization of GFDM
blocks based on the autocorrelation of the cyclic prefix. For compensating the frequency mismatch of
the local oscillator of the RF frontend, a carrier frequency offset compensation process was
implemented. Basic pilot-based channel estimation over the GFDM spectrum is performed using a
known preamble and residual time offsets are corrected by a plain one-tap frequency domain phase
equalizer. A matched filter approach considering a null roll-off factor is implemented for
demodulating the GFDM sub-carriers. Overlapping between sub-carriers may occur if the roll-off is
increased in the GFDM transmitter. This leads to side effects of inter-carrier interference that needs to
be removed on the receiver side [2]. The latter feature is not implemented in the current version of the
software.
Figure 12 shows the GUI of the basic GFDM receiver.
3.5.2 Configuration (Host vi)
3.5.2.1 Top Level vi
In the top level vi, the configuration of the GFDM receiver takes place. For starting the transmitter
press Run..

Figuie 12: 0veiview u0I uFBN ieceivei.
By pressing the button Settings Configuration a popup window will appear with some information
about how to configure the demonstration. After this, another popup window with the configuration of
the GFDM receiver is shown. The following parameters can be configured


25
M: number the sub-symbols per subcarrier.
K: number of subcarriers
Reference input power: expected power level at the input of the receiver.
Carrier frequency from 200 MHz to 4.4 GHz.
Sampling rate: configuration of the sampling rate for the GFDM time domain signal.
Table 5: Input parameters range for GFDM receiver
Parameter Range Default value
M 8128
1
8
K 8(2048/M)
1
256
Output power -100dBm...20dBm
2
-5dBm
Carrier frequency 200MHz4.4GHz 2.437GHz
1
Please note that only the combinations listed in Table 4 are officially supported for K and M. Other combinations are
possible but new configuration files (for data, preamble and filter coefficients) have to be generated.
2
The lower limit is only assumed, since it is not documented in the hardware specification of NI-5791.

3.5.2.2 GUI
The GUI is organized as follows:
In the left part, the configuration button with an overview table about the configured parameters is
located. On the left-bottom part two interacting buttons are available:
Time tracking enable: This signal is asserted to activate the time tracking control loop for
compensating sampling clock deviations between the transmitter and receiver clocks.
Integer CFO (half subcarrier offset): adjustment (coarse) integer carrier frequency offset.
Stop: To stop the application.
On the right part, some graphs indicators are shown:
Received time domain signal: Received signal at the output of the rate conversion vi,
CP autocorrelation peak index: To track the timing of the received stream,
CP autocorrelation peak magnitude: Magnitude of the timing peak,
Channel magnitude: Estimated magnitude of the channel after re-modulation with the inverse
of the preamble sequence,
Channel phase: Estimated phase of the channel after re-modulation with the inverse of the
preamble sequence,
Un-equalized IQ: Un-equalized received IQ samples,
Channel Phase Equalizer: Equalized IQ samples after applying a channel phase equalizer on
the FPGA,
3.5.3 FPGA vi
3.5.3.1 Top level vi
The top level vi is organized in different timed loop structures described in the following section. Each
timed loop consists of different functional blocks and sub vis. For the sake of clarity a different
format is used in the following to indicated timed loops, functional blocks and sub vis.
Main signal processing loop (100 MHz): This loop contains the whole demodulation of the
received GFDM samples, organized in the following functional block or subvis:


26
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Figuie 1S: 0veiview block uiagiam of the uFBN ieceivei implementation.


27
Timing Synchronization vi:
This vi estimates the symbol arrival time of the GFMD stream. It is based on the
autocorrelation of the cyclic prefix samples of the GFDM block. It operates in a searching
window of 2x(KxM + CP) samples as it is intended to detected two peaks, one from the
preamble block and one from the data block. To be able to differentiate both peaks in the
searching window, the preamble block is sent with half the power of the data. For improving
results an averaging over 5 symbols takes place. The hardware implementation of the block
looks like this:


Figuie 14: Block uiagiam foi timing synchionization baseu on autocoiielation of the CP.
Time Tracking vi:
This vi is intended to extract the synchronized data of the main stream and track the signal
against sampling clock deviations. The data is cut in the middle of the cyclic prefix in order to
be more robust against inaccuracies of the timing synch and inter-symbol interference. This
function generates a flag for distinguishing between data and preamble GFDM symbols.
Input parameters:
- 2(KxM + CP): Searching window length for estimating the time arrival of the data,
- Time tracking enable: This signal is asserted to activate the timing tracking,
- Autocorr Idx: Index to start cutting the signal, that points to the beginning of the data
symbol,
- DV: Indicates valid data at the input,
- CP/2: Half of the cyclic prefix length,
- NIfft: Number of FFT samples,
- CP length: Number of cyclic prefix samples.
Output parameters:
- State out: For debugging purposes,
- Counter for CFO out: Counter for calculating the phase increment in the CFO
compensation vi,
- Pre/Data flag out: For distinguish between data and preamble. 0 for preamble symbol,
1 for data symbol,l
- IQ: Concatenated I(upper I16) and Q(lower I16) samples as an U32 value,
- IQ Vld: Indicates valid data at the output.

CFO calculation vi:
The (fine) fractional carrier frequency offset is estimated based on the angle information of the
autocorrelation peak. This is calculated by using the Xilinx Cordic IP. The lock-in range of the
fine CFO estimation is [-n, , +n], i.e., half of the sub carrier spacing.
It is possible to adjust (coarse) integer carrier frequency offsets externally with the input
subcarrier half offset.
Input parameters:


28
- Subcarrier half offset: To adjust integer carrier frequency offsets from external. A
value of 2 means one subcarrier,
- IQ: Input concatenated I(upper I16) and Q(lower I16) samples as an U32 value, which
is the peak value of the autocorrelation function,
- Input valid: Indicates valid data at the IQ input,
- Bypass frequency offset: To bypass this processing.
Output parameters:
- Phase_out cordic: Output from the Cordic function in fixed point format,
- Frequency offset: CFO to be applied in the compensation function,
- DV: Indicates a valid output.

CFO compensation vi:
This function compensates the calculated phase rotation, caused by the CFO, at the IQ
samples of the GFDM time-domain signal. This is done by a Xilinx Cordic IP.
Input parameters:
- Frequency offset: Phase offset to be compensated,
- -log2(K*M)-1: Required scaling factor for the input frequency offset,
- Input IQ: Concatenated I(upper I16) and Q( lowerI16) samples as an U32 value,
- Input valid: Indicates a valid data in the input.
Output parameters:
- Input valid delayed: For debugging purposes,
- Phase in Cordic: For debugging purposes,
- Input valid delayed: For debugging purposes,
- I: In phase component of the compensated signal,
- Q: In quadrature component of the compensated signal,
- DV: Indicates a valid output data.

FFT shift vi:
It rearranges the output of the iFFT by moving the zero-frequency component to the middle
(center?) of the array.
Input parameters:
- IQ: Concatenated I(upper I16) and Q(lower I16) samples as an U32 value,
- Input valid: Indicates a valid input data.
Output parameters:
- IQ: Concatenated I(upper I16) and Q(lower I16) samples as an U32 value.

FFT (KxM):
It performs a KxM-point direct Fourier Transform of the input data by using the Xilinx IP
core.
Input parameters:
- NIfft: Number of FFT samples (nfft),
- IQ Input: Non-concatenated I(upper I16) and Q(lower I16) samples as an U32 value,
- Start: FFT start signal, which is asserted to begin the data loading and transform
calculation,
- CE: Clock enables start/stop of the core,
- Forward or Inverse FFT: Control signal that indicates if a forward FFT or an inverse
FFT is performed (fwd_inv),


29
- Setup WE: Asserts the FFT signals nfft_we and fwd_inv_we, which are write enable
signals for nfft and fwd_inv respectively.
Output parameters:
- Real Output: In phase component of the output signal,
- Imaginary Output: In quadrature component of the output signal,
- DV: Indicates a valid output data,
- Ready for data: This signal is high during the load operation,
- Blk_exp: The amount of scaling applied by the core, (0utput 2
BIk_cxp
).

Channel estimation functional block:
This block estimates the channel by re-modulating the received preamble symbol. In the
memory Preamble_inv, the inverse of the send preamble at the transmitter is stored. By
multiplying both sequences, the inverse of the preamble and the received preamble, an
estimation of the channel is obtained.
Channel phase equalization functional block:
This block implements a one-tap frequency domain equalizer by using the phase of the
estimated effective channel. This phase is easily shifted back with high throughput complex
multiplier.
Cut used carriers vi (simplified matched filtering):
This vi extracts the vector of samples that are passed to the iFFT. Currently, this is
implemented as a simplified matched filter. Instead of performing the iFFT on 2xM points and
then decimating the resulting signal by 2, this block extracts the M points at the center of the
subcarrier and passes them directly to a M-point iFFT. This will not maximize the SNR but it
is a good approximation for the matched filter.
Input parameters:
- Lower limit: Index of the first used subcarrier calculated as:
Iowcr limit = FirstCorricr H +
M
2
+ 1 ,
- Upper limit: Index of the last used carrier calculated as:
uppcr limit = Iowcr limit + uscJCorricrs H ,
- IQ in: Concatenated I(upper I16) and Q(lower I16) samples as an U32 value,
- DV: Indicates a valid input data,
- NIfft: Number of FFT samples.
Output parameters:
- IQ out: Concatenated I(upper I16) and Q(lower I16) samples as an U32 value,
- DV out: Indicates a valid output data.

iFFT(M) vi:
It performs a sub-carrier-wise M-point inverse Fourier transform for all used sub-carriers.
Input parameters:
- Start: FFT start signal which is asserted to begin the data loading and transform
calculation,
- Real input: In phase component of the input signal,
- Imaginary input: In quadrature component of the input signal,
- CE: Clock enable to start/stop the core,
- Forward or inverse FFT: Control signal that indicates if a forward FFT or an inverse
FFT is performed, (fwd_inv),


30
- Setup WE: Asserts the FFT signals nfft_we and fwd_inv_we, which are write enable
signals for nfft and fwd_inv respectively,
- NIfft: Number of FFT samples (nfft),
Output parameters:
- Real Output: In phase component of the output signal,
- Imaginary Output: In quadrature component of the output signal,
- DV: Indicates a valid output data,
- Ready for data: This signal is high during the load operation,

Rate Conversion loop (130 MHz):
In this loop the rate of the input data is converted from 130 MHz (ADC clock) to the
transmitter sampling rate, by using the fractional interpolator from the NI-5791 library.
Additionally the IQ impairments are compensated with a vi from the library.

Config interface from host to FPGA loop (100 MHz):
The loop is responsible for configuring look up tables on the FGPA.

5791 Configuration loop (40 MHz):
This contains the standard configuration of the RF front end.



31
4 References
[1] N. Michailow, I. Gaspar, S. Krone, M. Lentmaier and G. Fettweis, Generalized Frequency
Division Multiplexing: Analysis of an Alternative Multi-Carrier Technique for Next Generation
Cellular Systems, in Proceedings of the 9th International Symposium on Wireless Communication
Systems (ISWCS'12), Paris, France, August 2012.
[2] I. Gaspar, N. Michailow, A. Navarro, E. Ohlmer, S. Krone, and G. Fettweis, Low Complexity
GFDM Receiver Based On Sparse Frequency Domain Processing, in Proc. 77th IEEE Vehicular
Technology Conference, VTC Spring 2013, Dresden, Germany, June 2013.
[3] National Instrument, NI FlexRIO FPGA Module Installation Guide and Specifications,
Available on-line. Accessed on March 2014, URL: http://www.ni.com/pdf/manuals/373047b.pdf.
[4] N. Michailow, M. Matth, I. Simes Gaspar, A. Navarro Caldevilla, L. Leonel Mendes, A. Festag,
G. Fettweis: Generalized Frequency Division Multiplexing for 5th Generation Cellular Networks,
to appear in IEEE Transaction on Communications, 2014, DOI: 10.1109/TCOMM.2014.2345566,
URL: https://mns.ifn.et.tu-dresden.de/Lists/nPublications/Attachments/985/gfdm-tcom-accepted.pdf.
[5] M. Kasparick, et al. 5GNOW: Non-Orthogonal, Asynchronous Waveforms for Future Mobile
Applications, IEEE Communications Magazine, vol. 52, no. 2, pp. 97105, February 2014.
[6] 5GNOW Project: URL http://www.5gnow.eu

Further references can be found at https://mns.ifn.et.tu-dresden.de or http://www.vodafone-chair.com.